Multipath phase shift PWM synchronous optimization system and method based on FPGA architecture

Abstract

The invention provides a multi-path phase shift PWM synchronous optimization system and method based on an FPGA architecture, and relates to the technical field of power electronics, and the optimization system comprises a synchronous logic reconstruction unit which is used for generating corresponding reconstructed synchronous data according to a synchronous demodulation signal and each channel parameter when the synchronous demodulation signal is received; the time base management unit is used for acquiring counting parameters of the time base counters corresponding to the channels and generating triangular carriers of the channels according to the counting parameters and the corresponding reconstructed synchronous data; the PWM comparison generation unit is used for acquiring an external modulation wave signal and generating a phase-shift PWM wave corresponding to each channel according to the external modulation wave signal, the reconstructed synchronous data and each triangular carrier wave; according to the invention, on the basis of deep fusion of the global synchronization signal and each channel parameter, a high-precision synchronization reference with a flexibly reconfigurable phase is generated, so that multiple paths of PWM waves with extremely high synchronization consistency and nanosecond-level precise phase shift are generated in parallel.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically, to a multi-channel phase-shifting PWM synchronous optimization system and method based on FPGA architecture. Background Technology

[0002] In the field of power electronics, multi-channel phase-shifting PWM technology is widely used in scenarios such as motor drive, grid-connected inverter, and multi-module parallel DC-DC conversion. Its core requirement is to achieve accurate synchronization and stable phase shifting of multiple PWM signals in order to avoid harmonic interference and circulating current generation, and ensure the efficient and reliable operation of the system.

[0003] However, existing technical solutions have significant limitations: when using microcontrollers (MCUs) or digital signal processors (DSPs), their synchronization mechanisms rely on software and internal buses, making them susceptible to interrupt responses and instruction cycles. This results in microsecond-level synchronization errors and jitter between channels, and insufficient real-time performance and flexibility in phase-shift control. While traditional FPGA implementations utilize parallelism to generate multiple PWM channels, their synchronization mechanisms are often coarse-grained, making it difficult to compensate for inherent delays between channels, and prone to pulse disturbances during dynamic phase shifting. These shortcomings collectively lead to deficiencies in synchronization accuracy, phase control flexibility, and system reliability in multi-channel PWM systems, limiting their performance in high-end applications. Summary of the Invention

[0004] The problem solved by this invention is one or more of the problems of the prior art described above.

[0005] To address the aforementioned problems, this invention provides a multi-channel phase-shifting PWM synchronization optimization system and method based on an FPGA architecture.

[0006] In a first aspect, the present invention provides a multi-channel phase-shifting PWM synchronous optimization system based on an FPGA architecture, comprising: The synchronous logic reconstruction unit is used to generate corresponding reconstructed synchronous data based on the synchronous demodulation signal and the parameters of each channel when a synchronous demodulation signal is received. The time base management unit is used to obtain the counting parameters of the time base counters corresponding to each channel, and generate the triangular carrier of each channel based on the counting parameters and the corresponding reconstructed synchronization data. The PWM comparison generation unit is used to acquire the external modulation wave signal and generate the phase-shifted PWM wave corresponding to each channel based on the external modulation wave signal, the reconstructed synchronization data and each triangular carrier.

[0007] Optionally, the reconstructed synchronization data includes a synchronization signal and a synchronization enable signal; the synchronization logic reconstructing unit is specifically used for: Based on the phase-time mapping algorithm, the synchronization delay time of each channel is determined according to the parameters of each channel; Based on each synchronization delay time, generate the corresponding time base counter's safety window monitoring start time data, and determine the corresponding safety window threshold data; Based on the safety window monitoring start time data and the corresponding safety window threshold data, the safety window decision process is executed, generating synchronization signals and synchronization enable signals for each channel respectively.

[0008] Optionally, the safety window decision process includes: Based on the safety window monitoring start time data and the corresponding safety window threshold data, the safety window monitoring of the corresponding channel is started; When the security window monitoring of the target channel is initiated, the current count data of the time base counter of the target channel is received; The current count data is compared with the safety window threshold data to obtain the comparison result; Based on the comparison results and the synchronous demodulation signal, the synchronization signal and synchronization enable signal of the target channel are generated synchronously.

[0009] Optionally, based on the comparison result and the synchronous demodulation signal, a synchronization signal and a synchronization enable signal for the target channel are generated synchronously, including: When the current count data is less than or equal to the safety threshold, the time base counter of the target channel is determined to have entered the safety range; Based on the timing reference of the synchronous demodulation signal, the synchronization signal of the target channel is generated, and the corresponding synchronization enable signal is generated synchronously.

[0010] Optionally, the channel parameters include a preset phase difference, a triangular carrier period, and a delay compensation amount; based on a phase-time mapping algorithm, the synchronization delay time of each channel is determined according to the channel parameters, including: Using Equation 1, the synchronization delay time of each channel is determined based on the parameters of each channel; Equation 1 is: ; in, Let n be the synchronization delay time of the nth channel. The preset phase difference for the nth channel. For the triangular carrier period, This is the amount of delay compensation.

[0011] Optionally, the PWM comparison generation unit includes multiple PWM comparators, each corresponding to a channel, and each PWM comparator processes the signal generation logic for the corresponding channel.

[0012] Optionally, the PWM comparator is specifically used for: When the corresponding synchronization enable signal is received, the synchronization enable signal is judged. When the synchronization enable signal is low, compare the external modulation wave signal with the corresponding triangular carrier wave. When the external modulation wave signal is greater than or equal to the triangular carrier wave, the phase-shifted PWM wave is output at a high level. When the external modulation wave signal is less than the triangular carrier wave, the phase-shifted PWM wave is output at a low level.

[0013] Optionally, the PWM comparator is also used to lock the PWM output state when the synchronization enable signal is high.

[0014] Optionally, the counting parameters include a preset initial count value. The time base counter is used to immediately stop the current counting and reset to the corresponding preset initial count value when the synchronization signal of each corresponding channel is received.

[0015] Secondly, this invention provides a multi-channel phase-shift PWM synchronization optimization method based on an FPGA architecture, applied to the aforementioned multi-channel phase-shift PWM synchronization optimization system based on an FPGA architecture. The multi-channel phase-shift PWM synchronization optimization method based on an FPGA architecture includes: When a synchronous demodulation signal is received, the corresponding reconstructed synchronous data is generated based on the synchronous demodulation signal and the parameters of each channel. Obtain the counting parameters of the time base counter corresponding to each channel, and generate the triangular carrier of each channel based on each counting parameter and the corresponding reconstructed synchronization data; The external modulation wave signal is acquired, and the phase-shifted PWM wave corresponding to each channel is generated based on the external modulation wave signal, the reconstructed synchronization data, and each triangular carrier wave.

[0016] The beneficial effects of the multi-channel phase-shifting PWM synchronization optimization system and method based on FPGA architecture of the present invention are: By constructing a collaborative architecture of a synchronous logic reconfiguration unit, a timing management unit, and a PWM comparison generation unit, fully digital multi-channel phase-shifting PWM control is achieved at the FPGA hardware level. Its core advantages lie in: generating a high-precision synchronization reference with flexible phase reconfigurability based on the deep integration of the global synchronization signal and the parameters of each channel, thereby generating multiple PWM waves in parallel with extremely high synchronization consistency and nanosecond-level precise phase shifting. This not only fundamentally eliminates the timing jitter and delay differences between multiple channels in traditional solutions, ensuring the continuity and integrity of the output waveform and system reliability, but also effectively smooths the total current ripple and reduces the equivalent switching frequency and electromagnetic interference level by actively staggering the switching times of each channel through independent reconfigured synchronization data. Ultimately, this system achieves highly integrated control of synchronization, phase shifting, and modulation on a single chip, possessing excellent real-time performance, modular scalability, and superior cost-effectiveness, making it particularly suitable for advanced industrial and communication applications with stringent requirements for multi-channel PWM timing. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a multi-channel phase-shifting PWM synchronous optimization system based on an FPGA architecture according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a triangular carrier synchronization based on the zero point according to an embodiment of the present invention; Figure 3 This is a schematic diagram of intermediate value triangular carrier synchronization according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a phase-delay synchronization according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a multi-channel phase-shifting PWM synchronous optimization system based on an FPGA architecture according to an embodiment of the present invention; Figure 6 This is a flowchart illustrating a multi-channel phase-shifting PWM synchronization optimization method based on an FPGA architecture according to an embodiment of the present invention. Detailed Implementation

[0018] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Although some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the accompanying drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0019] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0020] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to"; the term "based on" means "at least partially based on"; the term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments"; and the term "optionally" means "optional embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first," "second," etc., mentioned in this invention are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0021] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0022] The names of the messages or information exchanged between the multiple devices in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0023] In related technologies, existing systems suffer from insufficient module coordination. The synchronization triggering, carrier generation, and PWM comparison stages lack effective linkage mechanisms. This either relies on additional high-precision analog devices to improve performance, leading to high hardware costs and integration difficulties, or simplifies the design at the expense of synchronization accuracy and waveform quality, making it difficult to balance high performance and engineering feasibility. Furthermore, some solutions exhibit poor channel adaptability; modifying phase-shifting parameters or expanding the number of channels requires redesigning the hardware circuit, extending product iteration cycles and failing to meet the rapid adaptation needs of diverse scenarios. These problems severely restrict the application of multi-channel phase-shifting PWM technology in high-power, high-precision power electronic systems, necessitating an optimized synchronization optimization solution with improved architecture, stable performance, and flexible adaptability.

[0024] To address the problems existing in the aforementioned related technologies, embodiments of the present invention provide a multi-channel phase-shifting PWM synchronization optimization system and method based on FPGA architecture.

[0025] like Figure 1 As shown in the figure, an embodiment of the present invention provides a multi-channel phase-shifting PWM synchronization optimization system based on an FPGA architecture, comprising: The synchronous logic reconstruction unit is used to generate corresponding reconstructed synchronous data based on the synchronous demodulation signal and the parameters of each channel when a synchronous demodulation signal is received.

[0026] Specifically, the external synchronization signal generator inputs a short pulse synchronization signal to the FPGA through a high-speed serial interface module. This module must first complete the signal demodulation to ensure that the FPGA can accurately identify the reference synchronization trigger command, i.e., the synchronization demodulation signal, and transmit it to the synchronization logic reconstruction unit.

[0027] The synchronization logic reconfiguration unit is the core scheduling module of the multi-channel phase-shifted PWM synchronization optimization system. Its core function is to coordinate the processing of the global synchronization reference and the differentiated requirements of each channel. When a pre-processed synchronization demodulation signal (a globally unified synchronization trigger reference) is received, this unit calls the system's preset parameters for each channel (including phase shift configuration, carrier-related parameters, etc.) and, through its built-in signal reconfiguration logic, transforms the single global synchronization reference into reconfigured synchronization data adapted to each channel. This process does not rely on external additional devices; it only uses the FPGA's internal logic to achieve personalized adaptation of the synchronization signal. This ensures that the reconfigured synchronization data inherits the consistency of the global synchronization reference while matching the specific working requirements of the corresponding channel, providing a precise synchronization control basis for subsequent triangular carrier generation and PWM signal output.

[0028] The synchronous logic reconfiguration unit effectively solves the problems of low synchronization accuracy and waveform distortion caused by a single synchronization pulse adapting to all channels in traditional global synchronization schemes by converting a single global synchronization demodulation signal into reconfigured synchronization data specific to each channel. This ensures the uniformity of the synchronization reference for multiple channels and the personalized adaptation to channel requirements. Based on the internal logic of the FPGA, signal reconfiguration is achieved without the need for additional high-precision synchronization devices, improving the flexibility of synchronization control while reducing hardware costs and integration difficulty. Furthermore, the unit's signal reconfiguration mechanism avoids inter-channel synchronization interference, ensuring that each channel achieves precise synchronization according to its own parameters. This significantly improves the phase coordination stability of multiple phase-shifted PWM signals, providing a core guarantee for the reliable operation of high-power, high-precision power electronic systems.

[0029] The time base management unit is used to obtain the counting parameters of the time base counters corresponding to each channel, and generate the triangular carriers of each channel based on the counting parameters and the corresponding reconstructed synchronization data.

[0030] Specifically, the time base management unit is the core module for generating triangular carriers, responsible for providing a dedicated and stable carrier reference for each channel. This unit first acquires the preset counting parameters of the time base counters for each channel (including core configurations such as counter operating range and initial start value), and receives the channel-specific reconstructed synchronization data output by the synchronization logic reconstructing unit in real time. Using the FPGA high-frequency system clock as a unified timing reference, the time base management unit drives the time base counters of each channel to count cyclically according to a preset rule. Simultaneously, based on the control instructions of the reconstructed synchronization data, it precisely controls the counting start / stop and state reset of the counters, ensuring that the counters always operate stably within the appropriate timing interval. Finally, through the linear counting process of the counters, it directly generates the triangular carriers required by each channel that meet the phase shift requirements. The generated distortion-free triangular carriers are strictly aligned with the timing of the reconstructed synchronization data of the corresponding channel, providing a high-quality carrier signal for subsequent PWM comparisons.

[0031] The time base management unit ensures that the generation of triangular carriers in each channel follows a unified timing reference and meets specific phase shift requirements through coordinated control of counting parameters and reconstructed synchronization data. This effectively avoids the frequency offset and phase drift problems that easily occur in traditional multi-channel carrier generation. Its triangular carrier generation mechanism based on the time base counter eliminates the need for complex analog circuits, resulting in low waveform distortion and high stability, laying the foundation for high-precision PWM signal generation. At the same time, the unit achieves precise control of the counter through reconstructed synchronization data, avoiding invalid disturbances during the counting process, ensuring the continuity and integrity of the triangular carriers, thereby reducing PWM output glitches and distortions, improving the operational reliability of the entire power electronic system, and achieving fully digital control based on the FPGA architecture, simplifying the hardware structure and reducing debugging difficulty and maintenance costs.

[0032] The PWM comparison generation unit is used to acquire the external modulation wave signal and generate the phase-shifted PWM wave corresponding to each channel based on the external modulation wave signal, the reconstructed synchronization data and each triangular carrier.

[0033] Specifically, the PWM comparison generation unit is the final generation module of the phase-shifted PWM wave, responsible for converting the system control requirements and carrier reference into digital switching signals that can drive power devices. This unit first acquires external modulation wave signals reflecting the system output requirements (such as the target voltage signal for motor drive or the grid-connected waveform signal of the inverter system), and simultaneously receives the dedicated triangular carrier waves for each channel output by the time base management unit, as well as the reconstructed synchronization data generated by the synchronization logic reconstruction unit. Using the FPGA high-frequency system clock as a unified timing reference, the modulation wave signals and triangular carrier waves are synchronously sampled and preprocessed to ensure signal timing alignment and no delay deviation. Subsequently, combined with the control logic of the reconstructed synchronization data, the preprocessed modulation wave signals and the corresponding channel's triangular carrier waves are compared in real time. Based on the comparison results, high and low level signals are output, ultimately generating phase-shifted PWM waves for each channel that meet the preset phase-shift requirements. Furthermore, the timing of the output PWM waves is strictly consistent with the synchronization reference, directly adapting to the driving requirements of power devices.

[0034] The PWM comparator generation unit integrates external modulation signals, reconstructed synchronization data, and triangular carrier waves for collaborative processing. This ensures that the generation of phase-shifted PWM waves accurately responds to system control requirements while strictly adhering to synchronization references and phase shift requirements, effectively solving the timing misalignment and phase deviation problems that easily occur in traditional PWM generation. Based on fully digital comparator logic, it achieves signal computation, exhibiting stronger anti-interference capabilities and higher stability compared to analog comparator circuits. It avoids PWM output distortion caused by environmental fluctuations, ensuring the consistency and accuracy of multiple phase-shifted PWM waves. Simultaneously, through the collaborative control of reconstructed synchronization data, this unit avoids glitches and abrupt changes in the output signal during synchronization while ensuring PWM wave phase shift accuracy, improving the stability and safety of power device operation. Furthermore, the overall modular design, based on an FPGA architecture, eliminates the need for additional complex auxiliary circuits, simplifying the system integration process and enhancing adaptability to different application scenarios. This provides crucial support for the efficient and reliable operation of power electronic systems.

[0035] In this embodiment, a fully digital multi-channel phase-shift PWM control is achieved at the FPGA hardware level by constructing a collaborative architecture of a synchronization logic reconfiguration unit, a timing management unit, and a PWM comparison generation unit. Its core advantages are: based on the deep integration of the global synchronization signal and the parameters of each channel, a high-precision synchronization reference with flexible phase reconfigurability is generated, thereby generating multiple PWM waves in parallel with extremely high synchronization consistency and nanosecond-level precise phase shifting. This not only fundamentally eliminates the timing jitter and delay differences between multiple channels in traditional solutions, ensuring the continuity and integrity of the output waveform and system reliability, but also effectively smooths the total current ripple and reduces the equivalent switching frequency and electromagnetic interference level by actively staggering the switching times of each channel through independent reconfigured synchronization data. Ultimately, this system achieves highly integrated control of synchronization, phase shifting, and modulation with a single chip, possessing excellent real-time performance, modular expansion capabilities, and superior cost-effectiveness, making it particularly suitable for advanced industrial and communication applications with stringent requirements for multi-channel PWM timing.

[0036] Optionally, the reconstructed synchronization data includes a synchronization signal and a synchronization enable signal; the synchronization logic reconstructing unit is specifically used for: Based on the phase-time mapping algorithm, the synchronization delay time of each channel is determined according to the parameters of each channel; Based on each synchronization delay time, generate the corresponding time base counter's safety window monitoring start time data, and determine the corresponding safety window threshold data; Based on the safety window monitoring start time data and the corresponding safety window threshold data, the safety window decision process is executed, generating synchronization signals and synchronization enable signals for each channel respectively.

[0037] Optionally, the safety window decision process includes: Based on the safety window monitoring start time data and the corresponding safety window threshold data, the safety window monitoring of the corresponding channel is started; When the security window monitoring of the target channel is initiated, the current count data of the time base counter of the target channel is received; The current count data is compared with the safety window threshold data to obtain the comparison result; Based on the comparison results and the synchronous demodulation signal, the synchronization signal and synchronization enable signal of the target channel are generated synchronously.

[0038] Optionally, based on the comparison result and the synchronous demodulation signal, a synchronization signal and a synchronization enable signal for the target channel are generated synchronously, including: When the current count data is less than or equal to the safety threshold, the time base counter of the target channel is determined to have entered the safety range; Based on the timing reference of the synchronous demodulation signal, the synchronization signal of the target channel is generated, and the corresponding synchronization enable signal is generated synchronously.

[0039] Optionally, the channel parameters include a preset phase difference, a triangular carrier period, and a delay compensation amount; based on a phase-time mapping algorithm, the synchronization delay time of each channel is determined according to the channel parameters, including: Using Equation 1, the synchronization delay time of each channel is determined based on the parameters of each channel; Equation 1 is: ; in, Let n be the synchronization delay time of the nth channel. The preset phase difference for the nth channel. For the triangular carrier period, This is the amount of delay compensation.

[0040] Specifically, in a typical three-phase power system, the phase differences between the phases are 0°, 120°, and 240°, respectively. Then, the count value of the time base counter in channel 1 (phase 0°) at the initial phase point... The count values ​​for the other two phases (two channels) are as follows: ; ;in This is the maximum value of the counter.

[0041] Each carrier (triangular carrier) of the time base counter and the corresponding modulation setpoint signal The external modulated wave signal is compared in real time in a digital comparator (PWM comparator): ; Global synchronization pulse at Forcibly resetting all counters at any time has different effects on time-base counters with different initial phases. For example... Figure 2 As shown, a schematic diagram of triangular carrier synchronization near zero point; in Figure 2 In the middle, the synchronization signal received by the zero-phase counter is near zero. At this time, the counter will reset its count to zero, which has almost no impact on the comparison of the current modulation wave, and the output of the PWM comparator is normal. Figure 2 Mid-triangular carrier (carrier counting): from 0 to N max The system uses a cyclic counting pattern (→0) to form a triangular waveform with periods Tcarrier1 and Tcarrier2 (the actual periods are the same; only the markings distinguish adjacent periods). The modulation wave is a dashed line intersecting the triangular carrier wave, representing the voltage / current command signal required by the system. Synchronization trigger (tsync): When the triangular carrier wave counts to near 0 (zero point), a synchronization signal is triggered, resetting the triangular carrier wave and restarting the count from 0. PWM output: When the modulation wave amplitude is greater than the triangular carrier wave amplitude, the output is high; otherwise, it is low. Because the synchronization reset occurs near zero point, the linear change of the triangular carrier wave is not interrupted, resulting in a continuous and distortion-free duty cycle for the PWM output, and a complete waveform.

[0042] And such Figure 3 The diagram illustrates the intermediate-value triangular carrier synchronization strategy, highlighting its inherent flaws. When the triangular carrier undergoes a synchronization reset at a non-zero point (e.g., 1 / 3Nmax), it disrupts the normal triangular carrier generation process, leading to a series of problems. Specifically, the triangular carrier, with an initial phase of 120°, begins cyclic counting from 1 / 3Nmax. When the synchronization signal tsync is triggered, the triangular carrier is forcibly reset at a non-zero point, causing a mid-value jump in the count. Although the intersection logic between the modulation wave and the triangular carrier remains unchanged, the abnormal reset timing disrupts the original comparison sequence, resulting in a sudden change in the comparison result between the modulation wave and the triangular carrier. Ultimately, this causes a duty cycle error in the PWM output (manifested as an abnormally narrow pulse in the PWM level). Mathematically, this forced reset introduces a duty cycle error in the nth phase. Its magnitude deviates from the count value at reset. These periodic duty cycle errors manifest as specific harmonics in the output spectrum, increasing the total harmonic distortion (THD) of the system and limiting system performance improvement. In other words, this distortion not only causes power device malfunctions but also generates specific harmonics in the output spectrum. This figure, by illustrating the drawbacks of non-zero-point synchronization, conversely demonstrates the necessity of this invention to perform synchronization only within a safe window near zero.

[0043] To overcome this technical bottleneck, this embodiment implements an innovative synchronous logic architecture within the FPGA chip. The core of this architecture is the synchronous logic reconfiguration unit, which changes the traditional processing method for synchronous signals. When an external reference synchronization signal is input to the FPGA through a high-speed serial interface, it is not simply distributed but undergoes a sophisticated signal processing procedure. The synchronous logic unit first reads the preset phase difference data for each channel, and then calculates the precise delay time corresponding to each channel using a phase-time mapping algorithm.

[0044] Specifically, the core of the synchronization logic reconfiguration unit is to transform a single global synchronization reference into channel-specific synchronization data, which is implemented entirely based on FPGA digital logic. For example, its implementation steps are as follows: Step 1, Parameter Preset and Initialization: The synchronous logic reconfiguration unit first loads the preset channel parameters and global configuration parameters to complete the initialization: channel-specific parameters: preset phase difference (e.g., three-phase system channel 1: 0°, channel 2: 120°, channel 3: 240°), delay compensation amount (e.g., uniformly set to 10ns to offset the internal logic delay of the FPGA). Global parameters: triangular carrier period (e.g., 20μs, corresponding to a switching frequency of 50kHz), safety window threshold δ (e.g., 2, meaning the safety range is [-2, +2]), FPGA high-frequency system clock (e.g., 100MHz, period 10ns); initialization action: store the parameters in the internal register, start the synchronous demodulation signal receiving port, and wait for global synchronization trigger.

[0045] Step 2: Receive the synchronization demodulation signal and lock the reference timing: After the external synchronization signal is demodulated by the high-speed serial interface module, the synchronization logic reconstruction unit detects the synchronization demodulated signal (such as a 10ns wide high-level pulse) and immediately executes: Timing Locking: The rising edge of the synchronous demodulation signal is used as the global reference time. Start the internal timer (10ns precision), and the delay calculation for all subsequent channels will be based on this timer. Starting point; Signal verification: The validity of the signal is confirmed by two consecutive samples (filtering out glitches and noise below 1ns) to avoid false triggering.

[0046] Step 3, calculate the synchronization delay time of each channel: Based on the phase-time mapping algorithm, the preset parameters from step 1 are called, and the synchronization delay time of each channel is calculated using Equation 1: For example, channel 1 ( ): ; For example, channel 2 ( ): ; For example, channel 3 ( ): ; The calculation results are stored in the corresponding channel's delay register, serving as the trigger condition for starting security window monitoring.

[0047] Step 4: Start monitoring of the safety windows in each channel at different times: The synchronous logic reconfiguration unit is based on the synchronization delay time of each channel. ,exist Safety window monitoring for the corresponding channel is activated at specific times: For example: The time interval is 100μs. Channel 1 starts monitoring at 100μs + 10ns = 100.01μs, Channel 2 starts monitoring at 100μs + 6.676μs = 106.676μs, and Channel 3 starts monitoring at 100μs + 13.343μs = 113.343μs. Monitoring Action: Real-time acquisition of the current count value of the target channel time base counter (acquiring once every 10ns), and calculation of the absolute value of the count value. (Current count data).

[0048] Step 5, Safety Window Decision and Synchronization Data Generation: For the collected and the corresponding safety window threshold (For example Perform real-time comparison and execute the decision logic: like (e.g., channel 2 count value is 3) ): Continue data acquisition without generating a synchronization signal; like (e.g., channel 2 count value is 1) ): Continue collecting data, determine if it has entered a safe zone, and immediately generate two types of synchronization data; the two types of synchronization data include a synchronization signal: a high-level pulse for 2 clock cycles (20ns), used to trigger the time base counter reset, such as channel 2; and a synchronization enable signal: a high-level pulse, such as 20ns, that is perfectly aligned with the timing of the synchronization signal, used to control the PWM comparator corresponding to channel 2 to lock the output; The two types of synchronization data are directed to the time base management unit and PWM comparison generation unit of the corresponding channel to complete the generation of synchronization data for that channel.

[0049] Step 6: Loop and wait for the next synchronization demodulation signal: After the synchronous data of each channel is generated in a single round, the synchronous logic reconstruction unit resets the internal timer, returns to step 2, waits for the next synchronous demodulation signal to be triggered, and repeats the above process to achieve periodic synchronization optimization.

[0050] The synchronous logic reconfiguration unit achieves precise adaptation between the global synchronization benchmark and the personalized needs of each channel through a closed-loop implementation step of parameter presetting, benchmark locking, time-division delay calculation, safety window monitoring, and synchronization data generation. This effectively solves the phase drift and waveform distortion problems caused by a single pulse triggering all channels in traditional synchronization schemes. Based on standardized formulas, it calculates the synchronization delay time and combines it with a time-division monitoring mechanism to ensure that the synchronization timing of each channel strictly matches the preset phase difference. Synchronization data is generated only in the disturbance-free safety range near zero, completely avoiding the PWM output glitches and power device mis-conduction risks caused by mid-counting reset. At the same time, it is implemented entirely using FPGA digital logic, with flexible parameter configuration (phase difference, carrier period, etc. can be modified through registers). No additional high-precision analog devices are required. While improving the synchronization accuracy and system stability of multi-channel phase-shifted PWM, it reduces hardware costs and integration difficulty, making it suitable for diverse high-power application scenarios such as motor drives and grid-connected inverters.

[0051] The entire process relies on FPGA-based digital logic, offering highly flexible and dynamic parameter configuration capabilities. Core parameters such as phase difference and carrier period are stored in the FPGA's internal registers, requiring no hardware modifications. Simply write new values ​​to the registers using debugging tools to quickly switch between different phase shift angles (e.g., from a three-phase 120° interval to a five-phase 72° interval) and carrier frequencies (e.g., from 50kHz to 100kHz). It even supports dynamic online configuration during system operation. For example, in motor drive scenarios, the carrier period can be finely adjusted in real time according to changes in load torque to optimize switching losses, or in grid-connected inverter scenarios, the phase difference can be dynamically calibrated according to grid frequency fluctuations to ensure that grid-connected current harmonics always meet standards. This flexible parameter configuration method eliminates the cumbersome process of replacing hardware components in traditional analog solutions and avoids the inefficient operation of recompiling and burning programs in some digital solutions. While improving the synchronization accuracy and system stability of multi-channel phase-shifting PWM, it eliminates the need for additional high-precision analog devices, significantly reducing hardware costs and integration difficulty. It can be seamlessly adapted to diverse high-power application scenarios such as motor drive, grid-connected inverter, and multi-module parallel DC-DC conversion, significantly shortening the product's scenario adaptation cycle.

[0052] In some embodiments, the external dynamic configuration of parameters such as the safety window decision threshold and preset phase difference can be achieved through the process of "external signal input - register buffer - logic adaptation", as detailed below: This embodiment can receive parameter signals from external control devices (such as host computers and PLCs) through the FPGA's external communication interface (such as SPI, UART, Ethernet interface), realizing the external input and dynamic updating of core parameters. The process is as follows: External input and parsing of parameter signals: The external control device encapsulates parameters such as the safety window decision threshold, preset phase difference, triangular carrier period, and delay compensation amount into digital signals according to a preset communication protocol (such as SPI frame format) and sends them to the FPGA's communication interface; the communication parsing module inside the FPGA verifies and decodes the received signals and extracts the values ​​of each parameter (such as parsing the 16-bit digital signal into "safety window threshold = 2" and "preset phase difference = 120°").

[0053] Parameter caching and validity verification: The parsed parameters are written into the "parameter configuration register group" inside the FPGA (different parameters correspond to different register addresses), and at the same time, the validity verification logic is triggered - such as verifying whether the triangular carrier period is within the range supported by the FPGA system clock, and whether the safety window threshold is less than 5% of the maximum value of the counter. If the parameter is invalid, the original register value is maintained and an error signal is fed back to ensure stable system operation.

[0054] Parameter adaptation of logic modules: Each functional unit reads the latest value from the parameter configuration register in real time and automatically adapts its working logic accordingly. The synchronous logic reconstruction unit reads the "preset phase difference" and "delay compensation amount" to update the calculation results of the synchronization delay time; it also reads the "safety window decision threshold" to adjust the comparison conditions for safety window monitoring. The time base management unit reads the "triangular carrier cycle" and updates the maximum value and counting frequency of the time base counter; Online activation and status feedback: After the parameters are updated, there is no need to restart the system. Each unit will automatically run according to the new parameters in the next synchronization cycle. At the same time, the FPGA will send a "parameters have taken effect" status signal to the external device through the communication interface, thus completing the entire configuration process.

[0055] This method of external input parameters allows the FPGA-based multi-channel phase-shifting PWM synchronous optimization system to quickly adapt to the needs of different application scenarios (such as adjusting the preset phase difference to 120° in motor drive scenarios and adjusting the triangular carrier period to 20μs in grid-connected inverter scenarios) without modifying the hardware or reprogramming the program. It even supports dynamic optimization of parameters based on external conditions such as load and power grid during operation, which greatly improves the system's versatility and scenario adaptability.

[0056] Optionally, the PWM comparison generation unit includes multiple PWM comparators, each corresponding to a channel, and each PWM comparator processes the signal generation logic for the corresponding channel.

[0057] Optionally, the PWM comparator is specifically used for: When the corresponding synchronization enable signal is received, the synchronization enable signal is judged. When the synchronization enable signal is low, compare the external modulation wave signal with the corresponding triangular carrier wave. When the external modulation wave signal is greater than or equal to the triangular carrier wave, the phase-shifted PWM wave is output at a high level. When the external modulation wave signal is less than the triangular carrier wave, the phase-shifted PWM wave is output at a low level.

[0058] Optionally, the PWM comparator is also used to lock the PWM output state when the synchronization enable signal is high.

[0059] Optionally, the counting parameters include a preset initial count value. The time base counter is used to immediately stop the current counting and reset to the corresponding preset initial count value when the synchronization signal of each corresponding channel is received.

[0060] Specifically, the PWM comparison generation unit uses a channel-specific PWM comparator as its core. Through a closed-loop process of signal preprocessing, timing alignment, dynamic comparison, and output stabilization, it generates phase-shifted PWM waves for each channel. The specific implementation steps are as follows: (Taking a PWM comparator with one channel as an example, multiple channels are executed in parallel, with completely identical logic): First, the PWM comparator generation unit loads the preset configuration: clearly defining the channel number, signal sampling period (synchronized with the FPGA high-frequency system clock, such as a 10ns sampling period corresponding to a 100MHz clock), and output level standard (such as 0V / 15V for IGBT driver adaptation) for each PWM comparator; simultaneously, the signal receiving port is activated to acquire three types of input signals: ① external modulation wave signal (such as the target voltage digital signal for motor drive, with a quantization range of 0~2000); ② channel-specific triangular carrier wave output by the time base management unit (such as the carrier wave of a 120° phase-shifted channel, with a count value range of 667~2000~667); ③ channel-specific reconstructed synchronization data (including synchronization enable signal) output by the synchronization logic reconstruction unit.

[0061] The PWM comparison generation unit distributes the above three types of input signals to the corresponding PWM comparators according to the principle of one comparator per channel. Each comparator works independently and processes in parallel to avoid signal interference between channels. The unit level is only responsible for signal distribution, global timing calibration and anomaly monitoring (such as signal loss alarm), and does not participate in the specific comparison calculation.

[0062] Implementation steps of a single-channel PWM comparator: Input signal preprocessing: Triangular carrier preprocessing: Receive digital triangular carrier signals and eliminate the internal transmission delay of the FPGA (delayed by 1 clock cycle) through a level 1 buffer register to ensure that the carrier signal is stable and jitter-free; Modulation wave preprocessing: If the modulation wave is an analog signal (e.g., 0~3.3V), it is quantized into a digital quantity consistent with the triangular carrier (e.g., 3.3V corresponds to 2000) through the FPGA's built-in ADC module; if it is a digital signal, level matching is directly performed (e.g., a 16-bit signal is truncated to 11 bits to align with the carrier quantization range), and transmission delay is eliminated through a synchronization buffer. Synchronization enable signal preprocessing: The synchronization enable signal is sampled twice consecutively (it is considered valid only if a high level is sampled for two consecutive clock cycles), and spike noise below 1ns is filtered to avoid false triggering.

[0063] Using the FPGA high-frequency system clock (100MHz, 10ns) as a unified reference, the PWM comparator synchronously samples the pre-processed triangular carrier wave, modulation wave, and synchronization enable signal: the current values ​​of the three types of signals are collected simultaneously every 10ns and stored in the internal sampling register to ensure that the comparison operation is based on the signal data at the same time and avoids comparison errors caused by timing misalignment (such as using the value at time t for the carrier wave and the value at time t+10ns for the modulation wave).

[0064] Dynamic processing based on the synchronization enable signal executes different processing logic according to the level state of the synchronization enable signal: When the synchronization enable signal is high (during synchronization reset, such as 20ns): ① Latch output state: Immediately write the last valid comparison result (high level / low level) before reset to the output latch register. For example: before reset, the modulation wave = 1000, the carrier = 0, and the comparison result is high level, then latch the high level. ② Prohibit jump transitions: Cut off the transmission path of the real-time comparison result to the output terminal, and only allow the fixed value of the latch register to be output to avoid sudden changes in the comparison result caused by carrier reset (such as level fluctuations caused by the carrier jumping from 0 to 667).

[0065] When the synchronization enable signal is low (during normal operation): ① Unlock Output: Clear the output latch register and restore the transmission path of the real-time comparison result; ② Real-time comparison operation: The current sampled value is compared according to the rule that a high level is output when the modulating wave is greater than or equal to the triangular carrier wave, and a low level is output when the modulating wave is less than or equal to the triangular carrier wave. For example: Carrier increment stage (667→2000): Modulation wave = 1000, output high level when carrier = 800 (800≤1000), output low level when carrier = 1200 (1200>1000); Carrier decrement phase (2000→667): When carrier = 1500 (1500>1000), output low level; when carrier = 900 (900≤1000), output high level. ③ Output update: The output level is updated every 10ns based on the comparison result to ensure that the duty cycle of the PWM wave accurately responds to the modulation wave requirements.

[0066] The original level signal output by the comparator needs to be post-processed to adapt to the power devices: anti-jitter filtering: maintain the logic filtering for one clock cycle to remove instantaneous glitches caused by comparison errors (such as level jumps within 10ns are judged as noise and the original level is maintained); level conversion: convert the 0V / 1.8V level inside the FPGA to the 0V / 15V drive level compatible with the power devices; drive enhancement: enhance the signal drive capability through the IO buffer to ensure that the PWM wave remains stable and attenuated after long-distance transmission, and is finally output to the gate drive circuit of IGBT / MOSFET.

[0067] Cyclic execution and synchronous linkage: The above steps are executed cyclically with a 10ns sampling period, while responding in real time to changes in the level of the synchronization enable signal: When the synchronization enable signal becomes high again, the output logic is repeatedly latched; when it is low, real-time comparison is maintained to achieve timing linkage with the synchronization logic reconstruction unit and the time base management unit.

[0068] The PWM comparison generation unit and PWM comparator employ a refined implementation process involving preprocessing, timing alignment, dynamic comparison, and output stabilization to ensure that the generation of phase-shifted PWM waves accurately responds to system control requirements while strictly avoiding output disturbances caused by synchronous reset. The parallel design of the single-channel independent comparator avoids inter-channel interference, the timing alignment mechanism solves the duty cycle error caused by signal delay in traditional comparator circuits, and the latching logic linked to the synchronous enable signal completely eliminates level erroneous transitions during reset, effectively reducing the risk of mis-enabling of power devices and PWM output glitches. Based on fully digital logic implementation, it has stronger resistance to temperature and voltage interference and higher waveform stability compared to analog comparator circuits. Furthermore, the post-processing steps such as level conversion and drive enhancement are directly adapted to the requirements of power devices, simplifying the system integration process. At the same time, parameters such as sampling period, output level, and comparison rules can be flexibly adjusted through FPGA configuration to adapt to different application scenarios such as motor drive and grid-connected inverter. This improves the generation accuracy of multi-channel phase-shifted PWM signals and the reliability of system operation while reducing hardware costs and debugging difficulty.

[0069] Optionally, the time base management unit includes multiple time base management modules, each corresponding to a channel, and each time base management module processes the triangular carrier generation logic of the corresponding channel.

[0070] Specifically, the time base management unit adopts a distributed architecture with one dedicated time base management module per channel. Each time base management module is independently responsible for generating the triangular carrier for its corresponding channel, ensuring both personalized adaptation of each channel's carrier and collaborative synchronization through a global timing reference. The specific process is as follows: The time base management unit first completes global initialization, and then assigns a unique configuration to each time base management module: clearly defining the channel number corresponding to each time base management module (e.g., module 1 is bound to channel 1, module 2 is bound to channel 2) to ensure directional signal transmission; and setting the preset channel-specific counting parameters (maximum counter value). Initial channel count value Globally shared parameters (FPGA high-frequency system clock period, triangular carrier period) Write to the internal register of the corresponding module; For example: Time base management module 2 corresponding to channel 2 (preset phase difference 120°) loads... , =667 (calculated from 120° / 360°×2000), system clock period 10ns. ; Activate the communication interfaces between each module and the synchronous logic reconstruction unit and PWM comparison generation unit to ensure bidirectional transmission of synchronous data and carrier signals.

[0071] Each time base management module monitors the signal output of the synchronization logic reconstruction unit in real time and only receives the reconstructed synchronization data (channel-specific synchronization signal + synchronization enable signal) of its own bound channel: The module has built-in channel identification logic, which only responds to synchronization data that carries its own channel number, filters synchronization signals from other channels, and avoids cross-channel interference. Using the FPGA high-frequency system clock as a reference, the received synchronization signal is sampled and calibrated (e.g., the signal level is confirmed for two consecutive clock cycles) to eliminate timing deviations caused by transmission delay and ensure accurate triggering of synchronization commands.

[0072] Each time base management module has a built-in independent time base counter that counts cyclically according to preset rules and responds to control commands of the synchronization signal: Normal counting phase: When no synchronization signal is triggered, the counter is driven by the system clock and counts linearly in a cycle according to the pattern of initial count value → maximum counter value → initial count value; For example, the counter in module 2 starts from 667, increments by 1 every 10ns, then decrements in the opposite direction after reaching 2000, and increments again after dropping to 667, forming a triangular carrier counting waveform with a period of 20μs. Synchronous Reset Phase: Upon receiving the synchronization signal (high-level pulse) from the synchronization logic reconstruction unit, the counter immediately stops its current counting action and resets to the initial count value C_init_n of the channel within one clock cycle, then resumes normal cyclic counting. The reset action is performed only when the synchronization signal is triggered, and strictly adheres to the premise that the safety window has been reached (the synchronization signal is only generated when the counter count value falls within [-δ, +δ]), ensuring that the carrier waveform is unbroken after the reset. Figure 4 As shown, a schematic diagram of phase-delay synchronization is presented. Figure 4 This demonstrates two triangular carrier waves (wave a and wave b) with the same frequency but a phase difference. Specifically, the multi-channel phase-shifted PWM synchronization optimization system based on the FPGA architecture in this embodiment does not provide a single global synchronization moment for them, but instead generates a synchronization pulse for each carrier near the zero-crossing moment of its own phase's corresponding counter (i.e., within the safety window). Figure 4 (These are labeled tsync1 and tsync2). This phase-separated synchronization method, triggered within a safe window, avoids forced resets during the middle of the counter count, thus preventing PWM output distortion caused by carrier waveform breaks, such as... Figure 3 The anomalies shown by traditional Chinese methods.

[0073] The time base management module directly converts the real-time count value of the counter into a digital triangular carrier signal and completes the signal adaptation output: the count value of the counter itself corresponds to the amplitude quantization value of the triangular carrier, the count increment phase corresponds to the rising edge of the carrier, and the count decrement phase corresponds to the falling edge of the carrier. No additional waveform synthesis logic is required, and the digital carrier signal is directly output. The module's built-in buffer register eliminates count jitter, enhances signal driving capability, and ensures that the carrier signal is transmitted to the PWM comparison generation unit without distortion or attenuation. Each module only outputs the generated triangular carrier signal to the PWM comparator of the corresponding channel, realizing a one-to-one signal link of "module-channel-PWM comparator".

[0074] The global control logic of the time base management unit performs unified monitoring and coordination of all time base management modules: All modules share the same FPGA system clock, ensuring that the periods of the triangular carrier waves in each channel are strictly consistent (all are...). Phase difference is achieved solely through the difference in initial count values; The system collects the counter status of each module in real time (such as whether the counter overflows or whether the synchronization signal responds normally). If an abnormality is detected (such as counter overflow), a global alarm is immediately triggered and the corresponding module is reset to ensure stable system operation. When it is necessary to adjust global parameters such as the triangular carrier period, the time base management unit synchronously issues update commands to all modules to ensure the consistency of parameters in each channel, eliminating the need to debug individual modules separately.

[0075] In some specific embodiments, such as Figure 5 The diagram shows a multi-channel phase-shifted PWM synchronization optimization system based on an FPGA architecture. It illustrates the complete process from global synchronization signal input to multi-channel PWM signal output to the power unit. The core is the distortion-free generation of multi-channel phase-shifted PWM signals through time-division synchronization logic. The time base management unit includes two channels of time base management modules (Time Base Management Module 1 and Time Base Management Module 2, corresponding to phase 1 and phase 2 respectively). The PWM comparison unit includes two channels of PWM comparators (PWM Comparator 1 and PWM Comparator 2).

[0076] Global synchronization signal and high-speed serial interface: The global synchronization signal is an externally input reference synchronization trigger signal used to unify the synchronization reference of multiple PWM channels.

[0077] The high-speed serial interface is responsible for receiving the global synchronization signal and demodulating it (such as removing noise and restoring the valid synchronization command), and then transmitting the demodulated signal (synchronization demodulation signal) to the synchronization logic reconstruction unit.

[0078] As the core of global synchronization scheduling, the synchronous logic reconfiguration unit receives the demodulated signal from the high-speed serial interface, combines it with the preset phase difference parameters of each channel, generates the reconfigured synchronization signal (including the synchronization signal and the synchronization enable signal), and sends synchronization control commands to the PWM comparators and time base management modules of different channels in a time-division manner to achieve time-division safe synchronization (avoiding waveform distortion caused by simultaneous reset of multiple channels).

[0079] Time base management modules (phase 1, phase 2): Each time base management module corresponds to one PWM channel (e.g., phase 1 corresponds to channel 1, phase 2 corresponds to channel 2), and its core function is to generate triangular carrier waves. The internal time base counter is the triangular carrier generation engine, driven by the FPGA's high-frequency system clock, operating in 0→N mode. max →0 linear counting (N) max (The value of the counter is the maximum value), generating a digital triangular carrier signal (e.g., phase 1 generates the triangular carrier of channel 1, and phase 2 generates the triangular carrier of channel 2). The triangular carrier signal is output to the corresponding PWM comparator (e.g., the triangular carrier of phase 1 of the time base management module is transmitted to PWM comparator 1, and phase 2 is transmitted to PWM comparator 2).

[0080] PWM comparators (PWM comparator 1, PWM comparator 2): Each comparator corresponds to one PWM channel and receives three types of input signals: the triangular carrier wave output by the time base management module; the externally input modulated wave signal (reflecting the system's demand for output voltage / current, such as the target voltage signal for motor drive); and the reconstructed synchronization data output by the synchronization logic reconfiguration unit (used to trigger the synchronous reset of the triangular carrier wave).

[0081] The comparator outputs a high level when the modulated wave signal is greater than or equal to the triangular carrier wave, and outputs a low level otherwise. This generates a PWM signal, which is then transmitted to the corresponding power unit (such as a power module or inverter unit) to achieve switching control of the power devices.

[0082] The time base counter is the core subunit of the time base management module, and its function is to generate digital triangular carrier waves. It is driven by the FPGA's high-frequency system clock (e.g., 100MHz, timing resolution 10ns) and counts linearly from 0 to the maximum value N. max Then from N max The counter decreases linearly back to 0, repeating cyclically to form a triangular digital count value, i.e., a triangular carrier. Simultaneously, it receives the reconstructed synchronization signal from the synchronization logic reconstruction unit, resetting to the preset initial count value at a safe moment (within a safe window where the counter value is close to 0), ensuring the triangular carrier phase is accurate and distortion-free.

[0083] In summary, this system achieves distortion-free generation of multi-channel phase-shifted PWM through the coordinated generation of triangular carrier waves by a time-base counter, modulation by a PWM comparator, and time-division synchronization by a synchronous logic reconfiguration unit. It is suitable for high-power power electronics scenarios with multiple power modules in parallel (such as motor drives and grid-connected inverters).

[0084] like Figure 6 As shown in the figure, an embodiment of the present invention provides a multi-channel phase-shift PWM synchronization optimization method based on FPGA architecture, which is applied to the aforementioned multi-channel phase-shift PWM synchronization optimization system based on FPGA architecture. The multi-channel phase-shift PWM synchronization optimization method based on FPGA architecture includes: When a synchronous demodulation signal is received, corresponding reconstructed synchronous data is generated based on the synchronous demodulation signal and the parameters of each channel. Obtain the counting parameters of the time base counter corresponding to each channel, and generate the triangular carrier of each channel based on the counting parameters and the corresponding reconstructed synchronization data; An external modulation wave signal is acquired, and a phase-shifted PWM wave corresponding to each channel is generated based on the external modulation wave signal, the reconstructed synchronization data, and each of the triangular carrier waves.

[0085] The FPGA-based multi-channel phase-shift PWM synchronization optimization method in this embodiment has the same advantages over existing technologies as the FPGA-based multi-channel phase-shift PWM synchronization optimization system described above, and will not be repeated here.

[0086] While the present invention has been disclosed above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and all such changes and modifications will fall within the scope of protection of the present invention.

Claims

1. A multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture, characterized in that, include: The synchronous logic reconstruction unit is used to generate corresponding reconstructed synchronous data based on the synchronous demodulation signal and the parameters of each channel when a synchronous demodulation signal is received. The time base management unit is used to obtain the counting parameters of the time base counters corresponding to each channel, and generate triangular carriers for each channel based on the counting parameters and the corresponding reconstructed synchronization data. The PWM comparison generation unit is used to acquire the external modulation wave signal and generate the phase-shifted PWM wave corresponding to each channel based on the external modulation wave signal, the reconstructed synchronization data and each of the triangular carrier waves.

2. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 1, characterized in that, The reconstructed synchronization data includes a synchronization signal and a synchronization enable signal; the synchronization logic reconstruction unit is specifically used for: Based on the phase-time mapping algorithm, the synchronization delay time of each channel is determined according to the parameters of each channel. Based on the synchronization delay time, generate the corresponding safety window monitoring start time data for the time base counter, and determine the corresponding safety window threshold data; Based on the security window monitoring start time data and the corresponding security window threshold data, a security window decision process is executed to generate the synchronization signal and the synchronization enable signal for each of the channels.

3. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 2, characterized in that, The safety window decision process includes: Based on the safety window monitoring start time data and the corresponding safety window threshold data, start the safety window monitoring for the corresponding channel; When the security window monitoring of the target channel is activated, the current count data of the time base counter of the target channel is received; The current count data is compared with the safety window threshold data to obtain the comparison result; Based on the comparison result and the synchronous demodulation signal, the synchronization signal and the synchronization enable signal of the target channel are generated synchronously.

4. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 3, characterized in that, The step of synchronously generating the synchronization signal and the synchronization enable signal of the target channel based on the comparison result and the synchronization demodulation signal includes: When the current count data is less than or equal to the safety threshold, it is determined that the time base counter of the target channel has entered the safe range; Based on the timing reference of the synchronous demodulation signal, the synchronization signal of the target channel is generated, and the corresponding synchronization enable signal is generated synchronously.

5. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 2, characterized in that, The channel parameters include a preset phase difference, a triangular carrier period, and a delay compensation amount; the step of determining the synchronization delay time of each channel based on the phase-time mapping algorithm according to each channel parameter includes: The synchronization delay time of each channel is determined according to the parameters of each channel using Equation 1. Wherein, Equation 1 is: ； in, Let n be the synchronization delay time of the nth channel. The preset phase difference for the nth channel. The period of the triangular carrier wave is... This is the amount of delay compensation.

6. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 2, characterized in that, The PWM comparison generation unit includes multiple PWM comparators, each corresponding to one of the channels, and each PWM comparator processes the signal generation logic of the corresponding channel.

7. The multi-channel phase-shifting PWM synchronous optimization system based on FPGA architecture according to claim 6, characterized in that, The PWM comparator is specifically used for: When the corresponding synchronization enable signal is received, the synchronization enable signal is judged. When the synchronization enable signal is low, the external modulation wave signal is compared with the corresponding triangular carrier wave. When the external modulation wave signal is greater than or equal to the triangular carrier wave, the phase-shifted PWM wave is output at a high level; When the external modulation wave signal is less than the triangular carrier wave, the phase-shifted PWM wave is output at a low level.

8. The multi-channel phase-shifted PWM synchronous optimization system based on FPGA architecture according to claim 6, characterized in that, The PWM comparator is also used to lock the PWM output state when the synchronization enable signal is high.

9. The multi-channel phase-shifted PWM synchronous optimization system based on FPGA architecture according to claim 2, characterized in that, The counting parameters include a preset initial count value. When the synchronization signal corresponding to each channel is received, the time base counter immediately stops counting and resets to the corresponding preset initial count value.

10. A multi-channel phase-shifted PWM synchronization optimization method based on FPGA architecture, characterized in that, The method for multi-channel phase-shifting PWM synchronization optimization based on FPGA architecture, as described in any one of claims 1 to 9, comprises: When a synchronous demodulation signal is received, corresponding reconstructed synchronous data is generated based on the synchronous demodulation signal and the parameters of each channel. Obtain the counting parameters of the time base counter corresponding to each channel, and generate the triangular carrier of each channel based on the counting parameters and the corresponding reconstructed synchronization data; An external modulation wave signal is acquired, and a phase-shifted PWM wave corresponding to each channel is generated based on the external modulation wave signal, the reconstructed synchronization data, and each of the triangular carrier waves.

Images