Signal self-correlation detection FPGA (Field Programmable Gate Array) architecture

Abstract

The invention discloses a signal self-correlation detection FPGA architecture, and relates to the technical field of signal processing. According to the invention, a storage module is formed by two dual-port RAMs with the maximum sliding window size, update items are sequentially stored according to an address sequence through a first dual-port RAM, and the update items are products of signal data and conjugates of signal data before a preset time delay of the update items; sequentially storing the accumulated sum of the current update item and the previous update item according to the address sequence through a second dual-port RAM, wherein the total accumulated item number is equal to the address; and on the basis of this, according to the size of the sliding window, obtaining an update item discarded after the sliding window from the first dual-port RAM in real time, and obtaining a historical accumulation item corresponding to the current sliding window from the second dual-port RAM, thereby calculating an autocorrelation function value of the signal under the preset time delay in the current sliding window. The self-correlation detection FPGA architecture supports dynamic window adjustment and can adapt to different signal scenes.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and in particular to an FPGA architecture for autocorrelation detection of signals. Background Technology

[0002] Currently, in the field of signal processing, the autocorrelation function is often used to analyze the periodicity and noise characteristics of signals, especially suitable for extracting weak signals from strong noise. For example, in deep space communication or underwater wireless communication, signals are very weak after long-distance attenuation and must be recovered from complex channel noise. Autocorrelation algorithms can be used for analysis in this case. Correlation refers to the relationship between two deterministic signals or two random signals. By statistically analyzing the patterns of stationary random signals, their correlation function is often deterministic. The autocorrelation function measures the similarity of a signal to itself at different points in time. In signal processing, it is often used to analyze the periodicity, noise characteristics, and system response characteristics of signals. Autocorrelation detection utilizes the good time correlation of signals and the lack of correlation or partial correlation of noise within a short period of time. It leverages the principle that noise does not accumulate while the signal is accumulated, thus extracting signals submerged in noise.

[0003] In existing technologies, autocorrelation detection methods work by calculating the similarity (i.e., the autocorrelation function) between a signal and itself at different time delays. Mathematically, this involves multiplying the signal by a time-shifted conjugate signal and accumulating the product within a sliding window. When the delay is exactly an integer multiple of the signal period, the signal waveform perfectly aligns with the conjugate signal, producing a strong peak. For noise, due to its randomness, the autocorrelation value approaches zero regardless of the delay. Therefore, by calculating the autocorrelation function on a signal mixed with noise, noise can be effectively suppressed, revealing hidden periodic peaks, thereby determining the presence and period of weak signals.

[0004] However, when implementing autocorrelation detection algorithms in hardware, existing technologies have a fixed window size, which lacks flexibility and limits the scope of application. Summary of the Invention

[0005] Therefore, it is necessary to provide an FPGA architecture for signal autocorrelation detection to address the aforementioned technical problems.

[0006] The present invention adopts the following technical solution: The present invention provides an autocorrelation detection device for a signal, comprising: a conjugate module, a calculation module, and a storage module; The storage module includes two dual-port RAMs, each the size of the maximum window of the sliding window. When the first dual-port RAM stores data in address order up to the maximum address, it returns to the starting address to continue storing. The input terminal of the calculation module is connected to the output terminal of the conjugate module, the output terminal of the first dual-port RAM, and the output terminal of the second dual-port RAM, respectively. The output terminal of the calculation module is connected to the input terminal of the first dual-port RAM and the input terminal of the second dual-port RAM, respectively. The input of the conjugate module receives the current signal data and is used to determine the conjugate of the current signal data; The first dual-port RAM is used to store update items sequentially in address order; the update item is the product of the conjugate of the current signal data and its signal data before the preset time delay. The second dual-port RAM is used to store the current update item and the sum of the previous update items in address order, wherein the total number of accumulated items is equal to the number of addresses; The input terminal of the calculation module receives the signal data before the preset time delay, and obtains the conjugate of the current signal data from the conjugate module to calculate the current update item, and stores it into the first dual-port RAM in address order; it obtains the update item discarded after the sliding window from the first dual-port RAM, and obtains the historical sum at the address with the same size as the sliding window from the second dual-port RAM, so as to determine the autocorrelation function value of the signal under the preset time delay in the current sliding window based on the difference between the historical sum and the discarded update item and the sum with the current update item, and stores it in the second dual-port RAM address corresponding to the size of the sliding window.

[0007] Optionally, the calculation module includes a multiplier and an adder; Starting from the moment the current signal data is acquired at the input moment, the conjugate module is called at the first delay moment to obtain the conjugate of the signal data before the preset delay of the current signal data; At the second delay time, the multiplier is invoked to determine the current update term based on the current signal data and the conjugate of the signal data before the preset delay of the current signal data. At the third delay time, the update item discarded after the sliding window in the first dual-port RAM is read, the historical sum at the address with the same size as the sliding window in the second dual-port RAM is read, and the adder is called to determine the autocorrelation function value of the signal under the preset time delay in the current sliding window based on the difference between the historical sum and the discarded update item and the sum with the current update item.

[0008] Optionally, it also includes: a LUT lookup table; the lookup table records the mapping relationship between different autocorrelation function values ​​within a preset range and the result obtained by taking the logarithm of the autocorrelation function values ​​after mapping them to the target range via Sigmoid; The storage module also includes a third RAM. After the calculation module determines the autocorrelation function value of the signal under the preset time delay within the current sliding window, it performs a mapping lookup based on the autocorrelation function value through a LUT lookup table and stores the lookup result into the third RAM for autocorrelation detection.

[0009] The above-mentioned at least one technical solution adopted in this invention can achieve the following beneficial effects: In the FPGA architecture for autocorrelation detection of signals in this invention, a storage module is formed using two dual-port RAMs of the maximum window size of two sliding windows. The first dual-port RAM stores update items sequentially by address; each update item is the product of the conjugate of the current signal data and the signal data before a preset time delay. The second dual-port RAM stores the current update item and the sum of previous update items sequentially by address, where the total number of accumulated items at each address is equal to the address itself. Based on this, when determining the autocorrelation function value according to the recursive formula of the autocorrelation algorithm, the calculation module can, in real time, retrieve the update items discarded after the sliding window from the first dual-port RAM and the historical accumulated items corresponding to the current sliding window from the second dual-port RAM, based on the size of the sliding window, thereby calculating the autocorrelation function value of the signal within the current sliding window at the preset time delay. This FPGA architecture for autocorrelation detection supports dynamic window adjustment, adapting to different signal scenarios. Furthermore, the RAM-based storage module implementation optimizes resource utilization in the autocorrelation detection FPGA architecture. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0011] Figure 1 A schematic diagram of an autocorrelation detection device for a signal provided by the present invention; Figure 2 A schematic diagram of a detection system based on FPGA provided by the present invention; Figure 3 This invention provides a schematic diagram of dynamically adjustable N values; Figure 4 A schematic diagram of a barrel-type RAM provided by the present invention; Figure 5 A schematic diagram of a delay control circuit provided by the present invention; Figure 6 This is a schematic diagram illustrating an increase in data bit width obtained from a different data input method provided by the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0013] The technical solutions provided by the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0014] The complex autocorrelation function is a complex function used to describe the result of convolving a signal with itself, representing the similarity of signals along the time axis. In the time domain, the autocorrelation function of a discrete complex signal is expressed as shown in equation (1):

[0015] (1) In the non-cooperative approach, since there is no prior knowledge of the signal, signal detection is performed by utilizing the different correlation characteristics of the signal and noise. To simplify the computation, instead of correlating the entire data, a depth of [insert depth here] is allocated based on the received signal. The sampling window is slid across the entire data stream (i.e., a sliding window) for point-by-point detection, with each detection point performing... Autocorrelation calculation of points.

[0016] First, an autocorrelation operation is performed on the receiver signal. Because the detected signal... It is real-time updated streaming data, with new data constantly arriving, and the sliding window length is... The current window data is Furthermore, the data is a complex signal, and its autocorrelation function is expressed as shown in equation (2).

[0017] , (2) In the formula, This refers to the window size. Arbitrary time delay indicates the detected signal Its own delay Similarity measure after each sample. Input signal Delay The conjugate of each sample.

[0018] When new data Upon arrival, the window slides and discards. The new calculation window is The new window Calculation formula and The relationships between them are shown in equations (3) and (4), respectively.

[0019] (3) (4) More generally, each time new data arrives, the window slides, the old data leaves the storage area, and the new data becomes... The old data is The sliding window recursive formula for real-time data updates is shown in equation (5).

[0020] (5) in, It is the autocorrelation of the current window. The updated autocorrelation. As can be seen from equation (5), each sliding window autocorrelation operation only requires one complex multiplication and two complex additions.

[0021] Based on the above-mentioned sliding window autocorrelation operation, this invention provides an FPGA architecture for signal autocorrelation detection, such as... Figure 1 As shown.

[0022] Figure 1 The present invention provides a schematic diagram of an FPGA-based detection system, comprising: a conjugate module, a computing module, and a storage module.

[0023] The storage module includes two dual-port RAMs, each the size of the maximum sliding window. The first dual-port RAM stores data in address order until the maximum address is reached, then returns to the starting address to continue storing.

[0024] The input terminal of the calculation module is connected to the output terminal of the conjugate module, the output terminal of the first dual-port RAM, and the output terminal of the second dual-port RAM, respectively. The output terminal of the calculation module is connected to the input terminal of the first dual-port RAM and the input terminal of the second dual-port RAM, respectively.

[0025] The input of the conjugate module receives signal data and is used to determine the conjugate of the signal data.

[0026] The first dual-port RAM is used to store update items sequentially in address order; the update item is the product of signal data and the conjugate of the signal data before its preset time delay.

[0027] The second dual-port RAM is used to store the current update item and the sum of the previous update items in the sliding window in address order, wherein the total number of accumulated items at each address is equal to the address.

[0028] The input terminal of the calculation module receives the current signal data and obtains the conjugate of the signal data before the preset time delay of the current signal data from the conjugate module to determine the current update item, and stores it into the first dual-port RAM in address order; it obtains the update item discarded after the sliding window from the first dual-port RAM, and obtains the historical accumulated sum at the address with the same size as the sliding window from the second dual-port RAM, so as to determine the autocorrelation function value of the signal under the preset time delay within the current sliding window based on the difference between the historical accumulated sum and the discarded update item and the sum with the current update item, and stores it into the second dual-port RAM address corresponding to the size of the sliding window.

[0029] As a programmable logic device, FPGA has advantages such as strong parallel processing capability, high flexibility, and low power consumption, and is widely used in the field of high-speed signal processing. Equation (5) can be completed efficiently and quickly using FPGA. The system design and implementation based on FPGA is the core part of this invention. Its purpose is to transform the autocorrelation broadband weak pulse signal detection algorithm into a hardware-implementable digital system. In the system architecture design, it is first necessary to clarify the overall functional module division of the system, and combine the parallel computing capability of FPGA to optimize the data flow and control logic between modules in order to improve the real-time performance and detection performance of the system.

[0030] The autocorrelation operation module is the core of the entire system. When implemented on the FPGA, a sliding window autocorrelation recursive algorithm is used. In order to make the algorithm more universal and meet more complex target signal conditions, the number of autocorrelation window points is designed to be dynamically adjustable.

[0031] However, the challenges faced in hardware implementation include limited trigger resources, excessive latency, and increased data bit width. FPGAs used for real-time signal processing utilize a large number of trigger resources. Therefore, in sliding window operations involving high-point multiplication and accumulation of large bit-width data, a barrel-type RAM circuit was designed to reduce the use of trigger resources, using conventional memory instead of triggers to implement the shift register.

[0032] Considering the advantages of parallel computing on FPGAs, a pipelined architecture is adopted to implement sliding window autocorrelation recursion. The signal is divided into multiple windows for parallel computation, and an area-for-speed approach is used to calculate the autocorrelation coefficients simultaneously through multiple paths. Meanwhile, the multiplication-accumulation operations in binary systems significantly increase the number of bits and the complexity of hardware implementation. Therefore, in the implementation, the amplitude value of the obtained conventional autocorrelation function is first mapped to a specific range using the Sigmoid function, and then its output is converted into a logarithmic domain representation, with the quantization bit width of this logarithmic domain representation adjustable.

[0033] Figure 2 This is a schematic diagram of a detection system based on FPGA implemented in this invention, as shown below. Figure 2The entire FPGA implementation shown first receives front-end serial real-time data, obtains its conjugate complex signal, and then feeds the current signal data and the conjugate of the signal data before the preset delay of the current signal data into the multiplier to obtain... The product of, and then using the result from the previous time step. Subtract discarded update items In addition to the current update items get However, there are four challenges here.

[0034] First, based on the previous analysis, in order to achieve better adaptability, it is necessary to... The value can be adjusted in real time, and the host computer will update it in real time. Value transmission requires that the FPGA not only be able to dynamically adjust The value must be considered, while ensuring a sufficiently short switching time to reduce various delays during implementation. Therefore, FPGA implementation must take into account... The value can be dynamically adjusted.

[0035] At the same time, to meet real-time requirements, the switching time and other delays must be minimized. Taking a value of 512 as an example, when the amplitude value is recorded using 12 bits of data, the autocorrelation value after multiplication, accumulation, and sliding windowing operations (considering positive and negative values) requires approximately 35 bits of data. Since many subsequent signal processing algorithms are needed, increasing the bit width leads to excessive system resource consumption. Meanwhile... When the value is dynamically adjusted, For 2 and When the value is 512, the effective data bit width varies considerably. Therefore, it is necessary to consider how to reduce the data bit width.

[0036] In actual implementation, three strategies were designed to address the challenges. Firstly, a bucket-based RAM was designed to implement the recursive variables required for sliding window recursion accumulation. The bucket-based RAM corresponding to the point of maximum autocorrelation effectively solved the problem. The purpose of dynamic value adjustment is to simultaneously fix the dynamic switching duration, ensuring that the switching duration is the same for each time. Secondly, a pipelined pattern is designed, combined with autocorrelation sliding window operations; actual measurements show that the latency can be controlled within 4 clock cycles. Thirdly, the sigmoid function is used, combined with a lookup table, to transform the amplitude of the autocorrelation function value into the logarithmic domain. This nonlinear characteristic compresses extreme values ​​and enhances the discriminative power of the intermediate range, achieving both high dynamic range compression and preservation of key information while optimizing hardware resource usage.

[0037] In real-time systems, data arrives in real time. Each time new data enters, the window slides, old data leaves the storage area, and new data... for Right now Real-time data values, while older data... That is, the data leaving the storage area is Time-bound. Then The sliding window recursive formula for real-time data updates is shown in equation (6). It is the autocorrelation function value of the current window. This is the updated autocorrelation function value.

[0038] (6) Therefore, when When the value is dynamically adjusted, the recursive formula shows that the following values ​​need to be dynamically adjusted: and initial value of . As shown in Equation 7.

[0039] (7) While multi-tap shift registers or FIFOs can conventionally be used to implement this sliding window operation, FPGAs used for signal processing typically experience resource constraints in terms of computation and configurable logic block (CLB) resources due to high demand, while memory resources are relatively abundant. Taking Xlinix devices as an example, they can implement arbitrary logic functions such as look-up tables (LUTs) for AND, OR, NOT, XOR, etc., and flip-flops (FFs) for storing states and implementing timing logic. These two types of resources are extremely scarce because signal processing timing and operations frequently require them. Conversely, look-up tables (LUTRAMs) for implementing logic functions with memory capabilities and block RAM (BRAMs) for implementing large-capacity memory are relatively plentiful. Shift registers are implemented using look-up tables (LUTs), but FPGAs used for signal processing have relatively scarce LUT resources, while LUTRAM and BRAM resources are abundant.

[0040] However, the FIFO dynamic storage area cannot achieve fast... Dynamic value switching requires a warm-start time. To address this issue, this invention prioritizes the use of dual-port RAM in its implementation. , and Dynamic adjustments.

[0041] In its implementation, this invention designs a barrel-type RAM structure as follows: Figure 3 As shown in the figure. The size of the storage area in the figure is... That is, the maximum window size of the sliding window. Time data and The data is stored in the same address, that is, the data It stores data cyclically. Bucket RAM consists of two parts: a standard dual-port RAM and an address calculation disk.

[0042] The design uses two values ​​with the maximum value. The design uses a barrel-shaped RAM module of a certain size to perform the aforementioned sliding window autocorrelation operation. The entire design is as follows: Figure 4 As shown. When the incoming data is The first memory contains respectively Each product term, from address 0 to address 1. The specific items stored separately are , The second storage area stores the cumulative sum of the current product terms. For example, the address of the current storage area... The first storage area contains [the item] at this location. The value is stored in the second memory, which contains the value before the current time. The sum of the products is The value stored at addresses 0 and 1 is 0.

[0043] The input and output addresses of the first memory area are obtained using equation (8). Represents the address of the first memory input data, representing The address where the data to be stored needs to be stored; the data arriving at this time is... The stored data is .and This represents the address of the data output from the first memory, and this memory area stores... The implementation of delayed shift storage of data using standard dual-port RAM has been completed.

[0044] (8) The second memory is mainly for solving The value is dynamically adjusted, while the duration of the dynamic switching is fixed so that the switching duration is the same each time. For example... Figure 4 As shown, where The calculation is shown in equation (8), representing The address where the data to be stored needs to be stored; the data to be stored at this time is... That is, the previous data The summation of conjugate multiplications. The data arriving at this point is... If at this time The value is dynamically adjusted to This means that sliding window operation It needs to be changed to the initial value ,Right now forward The summation of conjugate multiplications. It can be calculated by the following formula (9). , , For the address of the second storage area ( ), and The value stored internally.

[0045] (9) Therefore, the switching time depends only on the read speed of the memory area, which is typically one clock cycle. The design of the bucket RAM fully considers the characteristics of FPGA resources used for signal processing, maximizing resource utilization and minimizing latency.

[0046] Regarding delay control, although in the above Figure 3 The design in the middle can effectively solve The issue is that the value is dynamically adjusted, but if the design is unreasonable, it can cause the entire system switching time to reach its maximum. When the value is dynamically adjusted too quickly, it causes the system to have excessively long latency, which fails to meet the real-time requirements.

[0047] Figure 5 This is a schematic diagram of a delay control circuit implementation in this invention. This invention uses a pipelined approach to complete the entire correlation operation. When the current signal data arrives in real time at the input moment, each time new data enters, at the first delay moment, the conjugate module is called to obtain the conjugate of the signal data before the preset delay of the current signal data. At the second delay moment, the multiplier is called to determine the current update term based on the current signal data and the conjugate of the signal data before the preset delay of the current signal data. At the third delay moment, the update terms discarded after the sliding window in the first dual-port RAM are read, and the historical accumulated sum at the address with the same size as the sliding window in the second dual-port RAM is read. An adder is then called to determine the autocorrelation function value of the signal within the preset delay in the current sliding window based on the difference between the historical accumulated sum and the discarded update terms, and the sum with the current update term. Continuing with k=1 as an example, the multiplication result obtained at the second delay moment is added to the historical accumulated result, and then subtracted. With this design, the delay of the entire autocorrelation calculation is the sum of 3 clock cycles and the multiplier output delay.

[0048] To reduce the bit width, in one or more embodiments of the present invention, the FPGA architecture for signal autocorrelation detection may further include a LUT lookup table; the lookup table records the mapping relationship between different autocorrelation function values ​​within a preset range and the result obtained by taking the logarithm of the autocorrelation function values ​​after mapping them to the target range via Sigmoid.

[0049] The storage module also includes a third RAM. After the calculation module determines the autocorrelation function value of the signal under the preset time delay within the current sliding window, it performs a mapping lookup based on the autocorrelation function value through a LUT lookup table and stores the lookup result into the third RAM for autocorrelation detection or other downstream applications.

[0050] Figure 6 This is a schematic diagram illustrating the increased data bit width obtained from a different data input method in this invention. Figure 6 The horizontal axis of the left-hand graph represents the sampling points, and the vertical axis represents the magnitude before autocorrelation (12 bits). Figure 6 In the right-hand graph, the horizontal axis represents the sampling points, and the vertical axis represents the magnitude after autocorrelation. The N value in the graph is 512. The example in the graph shows that when the amplitude value uses approximately 12 bits of data (less than 4096), the autocorrelation value after 512-bit multiplication, accumulation, and sliding window operations increases to 10. 8 Approximately 30 bits of data are required for recording, increasing the data width by 18 bits. If the input information bit width increases while the output signal also needs to provide phase information, the required bit width will increase even more. Therefore, in the design and implementation, the autocorrelation result is converted to the logarithmic domain using the sigmoid function and a lookup table.

[0051] The normal amplitude value is first mapped to a specific range using the Sigmoid function, and then its output is converted into a logarithmic field representation. The quantization bit width of this logarithmic field representation is adjustable, and a LUT lookup table is used to implement it.

[0052] The magnitude of the autocorrelation function value may be distributed over a wide dynamic range. Direct processing or quantization can easily lead to a loss of precision due to extreme values. The sigmoid function can map the magnitude value to the (0,1) interval, compressing extreme values ​​and enhancing the distinguishability of the intermediate range through nonlinear characteristics. Logarithmic domain transformation further compresses the high dynamic range, converting multiplicative relationships into additive relationships while retaining key relative magnitude information. Logarithmic domain quantization is naturally suitable for representing wide dynamic range signals with a smaller bit width. The adjustable bit width allows for a flexible trade-off between precision and cost depending on the scenario: use a high bit width in high-precision stages and a low bit width in resource-constrained or non-critical paths, adapting to the computing power limitations of different hardware platforms (FPGA / ASIC).

[0053] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0054] The same techniques and theories of this invention can be readily applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. Similarly, the theories of this invention are applicable to ASIC design.

[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this invention.

Claims

1. An FPGA architecture for autocorrelation detection of a signal, characterized in that, include: Conjugate module, computation module, and storage module; The storage module includes two dual-port RAMs, each the size of the maximum window of the sliding window. When the first dual-port RAM stores data in address order up to the maximum address, it returns to the starting address to continue storing. The input terminal of the calculation module is connected to the output terminal of the conjugate module, the output terminal of the first dual-port RAM, and the output terminal of the second dual-port RAM, respectively. The output terminal of the calculation module is connected to the input terminal of the first dual-port RAM and the input terminal of the second dual-port RAM, respectively. The input terminal of the conjugation module receives signal data and is used to determine the conjugation of the signal data; The first dual-port RAM is used to store update items sequentially in address order; the update item is the product of signal data and the conjugate of the signal data before its preset time delay; The second dual-port RAM is used to store the current update item and the sum of the previous update items in the sliding window in address order, wherein the total number of accumulated items at each address is equal to the address; The input terminal of the calculation module receives the current signal data and obtains the conjugate of the signal data before the preset time delay of the current signal data from the conjugate module to determine the current update item, and stores it into the first dual-port RAM in address order; it obtains the update item discarded after the sliding window from the first dual-port RAM, and obtains the historical accumulated sum at the address with the same size as the sliding window from the second dual-port RAM, so as to determine the autocorrelation function value of the signal under the preset time delay within the current sliding window based on the difference between the historical accumulated sum and the discarded update item and the sum with the current update item, and stores it into the second dual-port RAM address corresponding to the size of the sliding window.

2. The FPGA architecture for autocorrelation detection of signals as described in claim 1, characterized in that, The computing module includes a multiplier and an adder; Starting from the moment the current signal data is acquired at the input moment, the conjugate module is called at the first delay moment to obtain the conjugate of the signal data before the preset delay of the current signal data; At the second delay time, the multiplier is invoked to determine the current update term based on the current signal data and the conjugate of the signal data before the preset delay of the current signal data. At the third delay time, the update item discarded after the sliding window in the first dual-port RAM is read, the historical sum at the address with the same size as the sliding window in the second dual-port RAM is read, and the adder is called to determine the autocorrelation function value of the signal under the preset time delay in the current sliding window based on the difference between the historical sum and the discarded update item and the sum with the current update item.

3. The FPGA architecture for signal autocorrelation detection as described in claim 1, characterized in that, Also includes: LUT lookup table; the lookup table records the mapping relationship between different autocorrelation function values ​​within a preset range and the result obtained by taking the logarithm of the autocorrelation function values ​​after mapping them to the target range via Sigmoid; The storage module also includes a third RAM. After the calculation module determines the autocorrelation function value of the signal under the preset time delay within the current sliding window, it performs a mapping lookup based on the autocorrelation function value through a LUT lookup table and stores the lookup result into the third RAM for autocorrelation detection.

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