High negative voltage conversion circuit

Abstract

The invention relates to a high negative voltage conversion circuit which comprises a PMOS (P-channel Metal Oxide Semiconductor) tube S1, an NMOS (N-channel Metal Oxide Semiconductor) tube S2, an inductor L, a resistor RDCR, a resistor RESR, a resistor RL, a resistor Rf1, a resistor Rf2, a capacitor COUT, an error amplifier with a compensation network, a clock and ramp signal generator OSC, a comparator COMP1, a logic circuit and dead zone module and a level shifter. The logic circuit and dead zone module comprises a driving circuit PDRI for driving the PMOS tube S1 and a driving circuit NDRI for driving the NMOS tube S2; according to the negative voltage topology circuit, positive voltage can be greatly converted into negative voltage, the use scene of a negative voltage chip is greatly increased, and the reliability and safety of a negative voltage power management chip are improved. On the basis of the 5MHZ frequency, the size of an inductor is reduced, a loop is controlled in a PWM control mode, compared with a self-adaptive guide control mode, the circuit does not need to use a high-performance comparator, and more area is generally saved when a logic and timing circuit is used compared with a high-power analog circuit which is directly used.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion, and in particular to a high negative voltage conversion circuit. Background Art

[0002] Negative voltage ICs are integrated circuits based on DC-DC conversion technology, used to convert positive input voltage into negative output voltage. They are widely used in electronic systems requiring negative voltage power supply, such as analog circuits, sensors, communications equipment, and industrial control. Their core technologies include switching power supply topologies (such as flyback, Cuk, and SEPIC), high-efficiency switching components (such as MOSFETs), PWM control, and highly integrated design. These enable high efficiency, a wide input voltage range, and a compact circuit layout, while also integrating overvoltage, overcurrent, and overtemperature protection. Component selection, heat dissipation, and EMI suppression are key design considerations. While negative voltage ICs offer advantages such as high efficiency, stability, and adaptability, they can also be complex and costly. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high negative voltage conversion circuit to overcome the deficiencies in the above-mentioned prior art.

[0004] The technical solution of the present invention to solve the above technical problems is as follows: A high negative voltage conversion circuit includes a PMOS tube S1, an NMOS tube S2, an inductor L, a resistor R DCR , resistor R ESR , resistor R L , resistor R f1 , resistor R f2 , capacitor C OUT , an error amplifier with a compensation network, a clock and ramp signal generator OSC, a comparator COMP1, a logic circuit and a dead zone module, and a level converter Levelshift; the logic circuit and the dead zone module include a driving circuit P_DRI for driving the PMOS tube S1 and a driving circuit N_DRI for driving the NMOS tube S2;

[0005] The source of the PMOS tube S1 is connected to the input terminal V in The drain of the PMOS tube S1 is connected to the first end of the inductor L and the drain of the NMOS tube S2, and the second end of the inductor L is connected to the resistor R DCR The first end of the resistor R DCR The second end is connected to the resistor R ESR The first end of the resistor R L The first end of the resistor R f1 The first end and GND, the resistor R ESR The second terminal is connected to the capacitor C OUTThe source of the NMOS tube S2 is connected to the capacitor C OUT The second end of the resistor R L The second end of the resistor R f2 The first terminal and the output terminal V out , the resistor R f1 The second terminal is connected to the R f2 The second end of the resistor R f1 and the R f2 The feedback signal V obtained after voltage division fb The first terminal of the error amplifier is connected to the reference voltage V REF ;

[0006] The error signal V at the third terminal of the error amplifier C Connect the first terminal of the comparator COMP1, the ramp signal V of the clock and ramp signal generator OSC RAMP The generating terminal is connected to the second terminal of the comparator COMP1, the third terminal of the comparator COMP1 is connected to the first terminal of the logic circuit and the dead zone module, and the clock signal CLK of the OSC is generated and connected to the second terminal of the logic circuit and the dead zone module; the third terminal and the fourth terminal of the logic circuit and the dead zone module are respectively connected to the first terminal and the second terminal of the level converter Levelshift through the driving circuit P_DRI and the driving circuit N_DRI, the third terminal of the level converter Levelshift is connected to the gate of the PMOS tube S1, and the fourth terminal of the level converter is connected to the gate of the NMOS tube S2.

[0007] The beneficial effects of the present invention are: the present invention can provide a high-voltage negative voltage power supply for the subsequent circuit, and the error amplifier with a compensation network amplifies the feedback signal V of the power stage. fb and compare it with the ramp signal V AMP The comparison generates a pulse signal for controlling the switch, and the control signal passes through the drive circuit to drive the power tube and switch tube of the power stage.

[0008] The negative voltage topology circuit of the present invention can realize a large-scale positive voltage to negative voltage conversion, greatly expands the application scenarios of the negative voltage chip, and improves the reliability and safety of the negative voltage power management chip.

[0009] The present invention is based on a 5 MHz frequency, reduces the size of the inductor, and adopts a PWM control loop. Compared with the adaptive conduction control method, the circuit does not require a high-performance comparator. The use of logic and timing circuits usually saves more area than directly using high-power analog circuits (such as linear comparators and constant current sources).

[0010] On the basis of the above technical solution, the present invention can also be improved as follows.

[0011] Furthermore, it also includes a bandgap reference circuit Bandgap, a reference voltage V REF Generated by the bandgap reference circuit Bandgap.

[0012] Furthermore, the bandgap reference circuit Bandgap includes a Zener diode ZD, a resistor RA, a resistor Ra, a resistor Rb, a capacitor Cc, an operational amplifier AMP, a filter capacitor Ca, a filter capacitor Cb, an NMOS transistor MN, an NMOS transistor MB, an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor NM10, an NMOS transistor NM11, an NMOS transistor NM12, a PMOS transistor NM8, a PMOS transistor NM9, a PMOS transistor NM5, a PMOS transistor NM3, a PMOS transistor NM1, a PMOS transistor NM4, a PMOS transistor NM2, a PMOS transistor NM13, a PMOS transistor NM14, a PMOS transistor NM15, a PMOS transistor NM16, a PNP transistor Q1, a PNP transistor Q2, and a PNP transistor Q3;

[0013] The negative terminal of the voltage zener diode ZD is connected to the first terminal of the resistor RA, the drain of the NMOS transistor NM10, the gate of the NMOS transistor NM10, the first terminal of the filter capacitor Ca, and the gate of the NMOS transistor MN. The second terminal of the resistor RA is connected to the drain of the NMOS transistor MN.

[0014] The source of the NMOS transistor NM10 is connected to the drain of the NMOS transistor NM11 and the gate of the NMOS transistor NM11, the source of the NMOS transistor NM11 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM12, and the source of the NMOS transistor MN is connected to the first end of the filter capacitor Cb;

[0015] The second end of the filter capacitor Cb is connected to the source of the PMOS transistor NM8, the source of the PMOS transistor NM3, the source of the PMOS transistor NM4, the source of the PMOS transistor NM13, and the source of the PMOS transistor NM14;

[0016] The gate of the PMOS transistor NM8 is connected to the drain of the PMOS transistor NM8 and the source of the PMOS transistor NM9. The gate of the PMOS transistor NM9 is connected to the drain of the PMOS transistor NM9 and the source of the PMOS transistor NM5. The gate of the PMOS transistor NM5 is connected to the gate of the NMOS transistor NM6. The drain of the PMOS transistor NM5 is connected to the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM7.

[0017] The gate of the PMOS transistor NM3 is connected to the gate of the PMOS transistor NM4, the first terminal of the operational amplifier AMP, and the drain of the NMOS transistor NM7; the drain of the PMOS transistor NM3 is connected to the source of the PMOS transistor NM1; the drain of the PMOS transistor NM1 is connected to the gate of the PMOS transistor NM1, the gate of the PMOS transistor NM2, the second terminal of the operational amplifier AMP, and the emitter of the PNP-type transistor Q1; the drain of the PMOS transistor NM4 is connected to the source of the PMOS transistor NM2; the drain of the PMOS transistor NM2 is connected to the third terminal of the operational amplifier AMP and the first terminal of the resistor Ra; the second terminal of the resistor Ra is connected to the emitter of the PNP-type transistor Q2;

[0018] The drain of the PMOS transistor NM13 is connected to the source of the PMOS transistor NM15, the drain of the PMOS transistor NM15 is connected to the drain of the NMOS transistor MB, the drain of the PMOS transistor NM14 is connected to the source of the PMOS transistor NM16, the drain of the PMOS transistor NM16 is connected to the first end of the resistor Rb and the first end of the capacitor Cc, and the second end of the resistor Rb is connected to the emitter of the PNP transistor Q3;

[0019] The positive terminal of the diode ZD is connected to the source of the NMOS transistor NM12, the second terminal of the filter capacitor Ca, the source of the NMOS transistor NM6, the source of the NMOS transistor NM7, the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2, the gate of the NMOS transistor MB, the source of the NMOS transistor MB, the collector of the PNP transistor Q3, the base of the PNP transistor Q3, and the second terminal of the capacitor Cc;

[0020] The drain of the PMOS transistor NM16 , the first end of the capacitor Cc, the first end of the resistor Rb, the gate of the PMOS transistor NM5 , and the gate of the NMOS transistor NM6 are connected to the error amplifier.

[0021] Furthermore, it also includes a protection module Protect and a soft start circuit Softstart. The protection module Protect is connected to the logic circuit and the fifth end of the dead zone module; the Bandgap circuit is electrically connected to the error amplifier through the soft start circuit Softstart.

[0022] Furthermore, a 5V pre-stabilization circuit is included. The VDD end of the pre-stabilization circuit is connected to the source of the PMOS tube S1, and the VDD5V terminal of the pre-stabilization circuit is connected to the resistor R DCR The second end of the resistor R ESR The first end of the resistor R L The first end of the resistor R f1 and GND.

[0023] Furthermore, it also includes a zero-crossing detection module ZCD, and the logic circuit and dead zone module also include an AND gate circuit AND, a single pulse trigger One-Shot1, a single pulse trigger One-Shot2 and an RS trigger;

[0024] The first end of the zero-crossing detection module ZCD is connected to the SW point, the second end of the zero-crossing detection module ZCD is connected to the output signal P_DRV of the drive circuit P_DRI, the third end of the zero-crossing detection module ZCD is connected to the first input end of the AND gate circuit AND, the output end of the AND gate circuit AND is connected to the first end of the single-pulse trigger One-Shot1, the second end of the single-pulse trigger One-Shot1 is connected to the S end of the RS trigger, the R end of the RS trigger is connected to the first end of the single-pulse trigger One-Shot2, the second end of the single-pulse trigger One-Shot2 is connected to the output signal P_DRV of the drive circuit P_DRI, the Q end of the RS trigger is connected to the first end of the drive circuit N_DRI, the second and third ends of the drive circuit N_DRI are the output signal N_DRV, and the delay signal N_DRV_Delay of the output signal N_DRV of the fourth end of the drive circuit N_DRI is connected to the second input end of the AND gate circuit AND.

[0025] Furthermore, the clock and ramp signal generator OSC includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a filter capacitor C1, a filter capacitor C2, a storage capacitor C3, a comparator COMP2, a comparator COMP3, A1, an inverter INV1, an inverter INV2, a NAND gate NAND1, a NAND gate NAND2, an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M5, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M12, and a PMOS transistor M4;

[0026] A first end of the resistor R3 is connected to a first end of the resistor R1 and the drain of the NMOS transistor M11. A second end of the resistor R1 is connected to a drain of the NMOS transistor M10, a gate of the NMOS transistor M10, a first end of the filter capacitor C1, and a gate of the NMOS transistor M11. A source of the NMOS transistor M11 is connected to a first end of the filter capacitor C2.

[0027] The second end of the resistor R3 is connected to the first end of A1 and the first end of the resistor R4. The source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M9 and the gate of the NMOS transistor M9. The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M8. The source of the NMOS transistor M8 is connected to the second end of the filter capacitor C1, the second end of the resistor R4, the first end of the resistor R2, the source of the NMOS transistor M3, the source of the NMOS transistor M2, the first end of the energy storage capacitor C3, and the source of the NMOS transistor M1.

[0028] The second end of the filter capacitor C2 is connected to the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M12, and the source of the PMOS transistor M4. The drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M6, the gate of the PMOS transistor M7, and the drain of the NMOS transistor M5. The gate of the NMOS transistor M5 is connected to the third end of A1. The second end of A1 is connected to the second end of the resistor R2 and the source of the NMOS transistor M5.

[0029] The drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M3, the drain of the NMOS transistor M3, and the gate of the NMOS transistor M2. The drain of the PMOS transistor M12 is connected to the gate of the PMOS transistor M12, the gate of the PMOS transistor M4, and the drain of the NMOS transistor M2. The drain of the PMOS transistor M4, the second end of the energy storage capacitor C3, the drain of the NMOS transistor M1, the first end of the comparator COMP2, and the second end of the comparator COMP3 are all connected to the second end of the comparator COMP1.

[0030] A third terminal of the comparator COMP2 is connected to the input terminal of the inverter INV1, an output terminal of the inverter INV1 is connected to the first input terminal of the NAND gate NAND1, a third terminal of the comparator COMP3 is connected to the input terminal of the inverter INV2, and an output terminal of the inverter INV2 is connected to the second input terminal of the NAND gate NAND2;

[0031] The output of NAND gate NAND2 is connected to the second input of NAND gate NAND1. The output of NAND gate NAND1, the first input of NAND gate NAND2 and the gate of NMOS transistor M1 are connected to the logic circuit and the second end of the dead zone module. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is the overall circuit diagram of the present invention;

[0033] Figure 2 The circuit diagram of the clock and ramp signal generator OSC of the present invention is as follows;

[0034] Figure 3 A circuit diagram of a bandgap reference circuit of the present invention;

[0035] Figure 4 A circuit diagram of the zero-crossing detection module ZCD output to the logic circuit and the dead zone module of the present invention;

[0036] Figure 5 This is a circuit diagram of the prior art topology of the present invention. DETAILED DESCRIPTION

[0037] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0038] like Figures 1 to 5 As shown in Example 1, a high negative voltage conversion circuit includes a PMOS tube S1, an NMOS tube S2, an inductor L, and a resistor R DCR , resistor R ESR , resistor R L , resistor R f1 , resistor R f2 , capacitor C OUT , an error amplifier with a compensation network, a clock and ramp signal generator OSC, a comparator COMP1, a logic circuit and a dead zone module, and a level converter Levelshift; the logic circuit and the dead zone module include a drive circuit P_DRI for driving the PMOS tube S1 and a drive circuit N_DRI for driving the NMOS tube S2;

[0039] The source of PMOS tube S1 is connected to the input terminal V in The drain of the PMOS tube S1 is connected to the first end of the inductor L and the drain of the NMOS tube S2, and the second end of the inductor L is connected to the resistor R DCR The first end of the resistor R DCR The second terminal resistor R ESR The first end of the resistor R L The first end of the resistor R f1 The first end and GND, resistor R ESR The second terminal capacitor C OUT The first end of the NMOS tube S2 is connected to the capacitor C OUT The second end of the resistor R L The second end of the resistor R f2 The first terminal and the output terminal V out , resistor R f1 The second terminal is connected to R f2 The second end of the resistor R f1 and R f2 The feedback signal V obtained after voltage division fb Connect to the first terminal of the error amplifier, and the second terminal of the error amplifier is connected to the reference voltage V REF ;

[0040] The error signal V at the third terminal of the error amplifier C Connect the first terminal of comparator COMP1, the ramp signal V of clock and ramp signal generator OSC RAMP The second end of the comparator COMP1 is generated and terminated, the third end of the comparator COMP1 is connected to the first end of the logic circuit and the dead zone module, and the clock signal CLK of the OSC is generated and terminated to the second end of the logic circuit and the dead zone module; the third end and the fourth end of the logic circuit and the dead zone module are connected to the first end and the second end of the level converter Levelshift through the drive circuit P_DRI and the drive circuit N_DRI respectively, the third end of the level converter Levelshift is connected to the gate of the PMOS tube S1, and the fourth end of the level converter is connected to the gate of the NMOS tube S2.

[0041] The present invention can provide a high-voltage negative voltage power supply for the subsequent circuit, and the error amplifier with a compensation network amplifies the feedback signal V of the power stage. fb and compare it with the ramp signal V AMP The comparison generates a pulse signal for controlling the switch, and the control signal passes through the drive circuit to drive the power tube and switch tube of the power stage.

[0042] The negative voltage topology circuit of the present invention can realize a large-scale positive voltage to negative voltage conversion, greatly expands the application scenarios of the negative voltage chip, and improves the reliability and safety of the negative voltage power management chip.

[0043] The present invention is based on a 5 MHz frequency, reduces the size of the inductor, and adopts a PWM control loop. Compared with the adaptive conduction control method, the circuit does not require a high-performance comparator. The use of logic and timing circuits usually saves more area than directly using high-power analog circuits (such as linear comparators and constant current sources).

[0044] Example 2: This example is a further improvement on Example 1, and its details are as follows:

[0045] It also includes a bandgap reference circuit Bandgap, a reference voltage V REF Generated by the bandgap reference circuit Bandgap.

[0046] Example 3: This example is a further improvement on Example 2, and its details are as follows:

[0047] The bandgap reference circuit Bandgap includes a Zener diode ZD, a resistor RA, a resistor Ra, a resistor Rb, a capacitor Cc, an operational amplifier AMP, a filter capacitor Ca, a filter capacitor Cb, an NMOS transistor MN, an NMOS transistor MB, an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor NM10, an NMOS transistor NM11, an NMOS transistor NM12, a PMOS transistor NM8, a PMOS transistor NM9, a PMOS transistor NM5, a PMOS transistor NM3, a PMOS transistor NM1, a PMOS transistor NM4, a PMOS transistor NM2, a PMOS transistor NM13, a PMOS transistor NM14, a PMOS transistor NM15, a PMOS transistor NM16, a PNP transistor Q1, a PNP transistor Q2, and a PNP transistor Q3;

[0048] The negative terminal of the voltage zener diode ZD is connected to the first terminal of the resistor RA, the drain of the NMOS transistor NM10, the gate of the NMOS transistor NM10, the first terminal of the filter capacitor Ca, and the gate of the NMOS transistor MN. The second terminal of the resistor RA is connected to the drain of the NMOS transistor MN.

[0049] The source of the NMOS transistor NM10 is connected to the drain of the NMOS transistor NM11 and the gate of the NMOS transistor NM11, the source of the NMOS transistor NM11 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM12, and the source of the NMOS transistor MN is connected to the first end of the filter capacitor Cb;

[0050] The second end of the filter capacitor Cb is connected to the source of the PMOS transistor NM8, the source of the PMOS transistor NM3, the source of the PMOS transistor NM4, the source of the PMOS transistor NM13, and the source of the PMOS transistor NM14;

[0051] The gate of the PMOS transistor NM8 is connected to the drain of the PMOS transistor NM8 and the source of the PMOS transistor NM9. The gate of the PMOS transistor NM9 is connected to the drain of the PMOS transistor NM9 and the source of the PMOS transistor NM5. The gate of the PMOS transistor NM5 is connected to the gate of the NMOS transistor NM6. The drain of the PMOS transistor NM5 is connected to the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM7.

[0052] The gate of PMOS transistor NM3 is connected to the gate of PMOS transistor NM4, the first terminal of operational amplifier AMP, and the drain of NMOS transistor NM7. The drain of PMOS transistor NM3 is connected to the source of PMOS transistor NM1. The drain of PMOS transistor NM1 is connected to the gate of PMOS transistor NM1, the gate of PMOS transistor NM2, the second terminal of operational amplifier AMP, and the emitter of PNP transistor Q1. The drain of PMOS transistor NM4 is connected to the source of PMOS transistor NM2. The drain of PMOS transistor NM2 is connected to the third terminal of operational amplifier AMP and the first terminal of resistor Ra. The second terminal of resistor Ra is connected to the emitter of PNP transistor Q2;

[0053] The drain of PMOS transistor NM13 is connected to the source of PMOS transistor NM15. The drain of PMOS transistor NM15 is connected to the drain of NMOS transistor MB. The drain of PMOS transistor NM14 is connected to the source of PMOS transistor NM16. The drain of PMOS transistor NM16 is connected to the first terminal of resistor Rb and the first terminal of capacitor Cc. The second terminal of resistor Rb is connected to the emitter of PNP transistor Q3;

[0054] The positive terminal of diode ZD is connected to the source of NMOS transistor NM12, the second terminal of filter capacitor Ca, the source of NMOS transistor NM6, the source of NMOS transistor NM7, the collector of PNP transistor Q1, the base of PNP transistor Q1, the base of PNP transistor Q2, the collector of PNP transistor Q2, the gate of NMOS transistor MB, the source of NMOS transistor MB, the collector of PNP transistor Q3, the base of PNP transistor Q3, and the second terminal of capacitor Cc;

[0055] The drain of PMOS transistor NM16, the first terminal of capacitor Cc, the first terminal of resistor Rb, the gate of PMOS transistor NM5, and the gate of NMOS transistor NM6 are connected to an error amplifier.

[0056] When the loop is working, a precise bandgap reference voltage can improve the stability of the loop. The bandgap reference (Bandgap) is as Figure 3 shown. Due to the existence of various capacitive paths, the power supply sensitivity of the circuit generally increases at high frequencies. For this reason, the power supply voltage VDDL of the core circuit is often locally generated and has low sensitivity. The working principle of the circuit that generates VDDL is as follows: The three diodes ZD connected in the diode connection mode of NM10, NM11, and NM12 provide the gate voltages of three overdrive voltages for MN. The gate and drain of MN are connected in parallel with RA, VG < VD, and MN is in the saturation region. According to the MOS square law, when I MNWhen constant (the sum of the VDDL branch currents in the subsequent stages, with the design current allocated based on power consumption), VDDL can be adjusted based on the W / L ratio of the MN. Because the MN is in the saturation region and the drain current is constant, if the channel length modulation effect is ignored, changes in VDD, i.e., changes in the voltage at the D-terminal of the NM, will not affect the S-terminal of the MN, and VDDL will not be affected by VDD fluctuations. However, in practice, the channel length modulation effect cannot be ignored, so the MN must use a long-channel device. VDD / R is approximately the current in the left branch, and VDD / R is in the uA range, so the value of R1 may be close to 1M ohm or several M ohms.

[0057] VDDL supplies power to the Bandgap core circuit, draws out the PTAT current and superimposes it on Q3 to obtain a reference voltage with a temperature coefficient of 0. REF =[VT*ln(n) / Ra]*Rb+VBE3, where n is I Q1 / I Q3 .

[0058] Example 4: This example is a further improvement on Example 3, and its details are as follows:

[0059] The circuit also includes a protection module (Protect) and a soft-start circuit (Softstart). The protection module is connected to the logic circuit and the fifth terminal of the dead-band module. The bandgap circuit is electrically connected to the error amplifier via the soft-start circuit. By providing the protection module, this circuit ensures safe chip operation. The soft-start module of the present invention has a slow power-up speed and includes a soft-start circuit with a 1ms delay. This circuit gradually increases the output voltage after system startup or recovery from a short circuit, effectively avoiding the high current surge at startup and protecting the load and power supply. The soft-start circuit is controlled by an AND gate using multiple logic signals, allowing the system to restart only when all conditions are met.

[0060] A soft-start circuit gradually increases the output voltage from 0 to the target value by controlling the current source or voltage ramp rate (e.g., through an RC delay network), avoiding current surges caused by sudden power-up. In this circuit, a soft-start restarts from 0 after each short-circuit is cleared, ensuring a low-current startup and protecting both the load and the power supply.

[0061] In addition, in the discontinuous protection mode, a high current is not continuously output when a short circuit occurs, thereby reducing the need to drive a high-power MOSFET, thereby reducing the size of the current sampling and power management modules.

[0062] In addition, when the power supply is just turned on, VX and VY are zero, the input differential pair of the op amp may be turned off, and the NM1, NM2, NM3, and NM4 loops allow zero current state, so a startup mechanism is needed to avoid this state. As shown in the figure, when the power is just turned on, V REF is 0, NM7 is turned on, NM3 and NM4 are turned on. At the same time, V ref Negative feedback back to the NM3 gate is beneficial to V ref stability.

[0063] In addition, the soft start module Softstart and the protection module Protect in the circuit share some logic and trigger modules, reducing the area of ​​repeated design.

[0064] Example 5: This example is a further improvement on Example 1, and its details are as follows:

[0065] It also includes a 5V pre-stabilization circuit. The VDD end of the pre-stabilization circuit is connected to the source of the PMOS tube S1, and the VDD5V terminal of the pre-stabilization circuit is connected to the resistor R DCR The second end of the resistor R ESR The first end of the resistor R L The first end of the resistor R f1 and GND.

[0066] In the traditional topology, a voltage source is added to the input and output to clamp the input and output to the power supply voltage. The input will be more Vdd than the output. For the topology diagram of the existing technology, see Figure 5 Under this clamping condition, the output reaches 40V through PWM loop control. out Relative to GND, it is 45V. In practice, this topology achieves a voltage conversion from 45V to 40V. out By swapping the GND pin with the 5V pin, a 5V to -40V conversion is achieved. Compared to a buckboost converter, which directly generates a negative voltage output, it requires an inverting amplifier to regulate the loop. Inverting amplifiers are not only expensive but also complex to design. This topology design method greatly simplifies the design of the negative voltage chip, while also reducing power consumption and improving efficiency.

[0067] In addition, V in Compared with V OUT The potential difference between them is 45V. A pre-stabilization circuit is designed to generate a 5V low voltage to power other modules. The appropriate voltage threshold can not only simplify the circuit design, but also reduce power consumption and improve efficiency.

[0068] Example 6: This example is a further improvement on Example 1, and its details are as follows:

[0069] It also includes a zero-crossing detection module ZCD, and the logic circuit and dead zone module also include an AND gate circuit AND, a single pulse trigger One-Shot1, a single pulse trigger One-Shot2 and an RS trigger;

[0070] The first end of the zero-crossing detection module ZCD is connected to the SW point, the second end of the zero-crossing detection module ZCD is connected to the output signal P_DRV of the drive circuit P_DRI, the third end of the zero-crossing detection module ZCD is connected to the first input end of the AND gate circuit AND, the output end of the AND gate circuit AND is connected to the first end of the single-pulse trigger One-Shot1, the second end of the single-pulse trigger One-Shot1 is connected to the S end of the RS trigger, the R end of the RS trigger is connected to the first end of the single-pulse trigger One-Shot2, the second end of the single-pulse trigger One-Shot2 is connected to the output signal P_DRV of the drive circuit P_DRI, the Q end of the RS trigger is connected to the first end of the drive circuit N_DRI, the second and third ends of the drive circuit N_DRI are the output signal N_DRV, and the delay signal N_DRV_Delay of the output signal N_DRV of the fourth end of the drive circuit N_DRI is connected to the second input end of the AND gate circuit AND.

[0071] In the stage where S1 is turned off and S2 is turned on, since the topology adopts synchronous control, when S2 is turned on, the current can flow through the NMOS tube in the reverse direction. At this time, the NMOS can be turned off to improve efficiency. When the reverse flow is about to occur, the voltage at the SW point is 0, so the zero-crossing detection is designed to detect the voltage change at this point, and then generate a logic control signal to the logic circuit to turn off the NMOS tube. Figure 4 As shown, it is an anti-backflow current mechanism including ZCD. In the full cycle of the drive signal P_DRV of the PMOS tube S1, the backflow current is detected by the zero-crossing detection module ZCD. Once the voltage of SW is detected to be 0, a valid level will be generated. The backflow current will only be generated when the NMOS is turned on, so it passes through a logic AND gate to shield the NMOS shutdown part. One-Shot is a monostable trigger. As long as a valid level is detected (unstable state), a narrow pulse will be generated and then restored to a steady state. The generation of the valid level further controls the drive circuit of the NMOS, making N_DRV a low level (i.e., turning off the NMOS tube to prevent reverse current from passing through). At the same time, a recovery logic signal is also required to make the NMOS work normally. This recovery signal is generated by P_DRV. When the ZCD generates a valid level, this level must pass through the subsequent logic circuit, so there will inevitably be a certain delay, resulting in inaccurate detection. Therefore, the N_DRV_Delay (N_DRV delay) signal is used to delay and eliminate jitter.

[0072] Example 7: This example is a further improvement on Example 1, and its details are as follows:

[0073] The clock and ramp signal generator OSC includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a filter capacitor C1, a filter capacitor C2, a storage capacitor C3, a comparator COMP2, a comparator COMP3, A1, an inverter INV1, an inverter INV2, a NAND gate NAND1, a NAND gate NAND2, an NMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M5, an NMOS transistor M8, an NMOS transistor M9, an NMOS transistor M10, an NMOS transistor M11, a PMOS transistor M6, a PMOS transistor M7, a PMOS transistor M12, and a PMOS transistor M4;

[0074] A first end of the resistor R3 is connected to a first end of the resistor R1 and the drain of the NMOS transistor M11. A second end of the resistor R1 is connected to a drain of the NMOS transistor M10, a gate of the NMOS transistor M10, a first end of the filter capacitor C1, and a gate of the NMOS transistor M11. A source of the NMOS transistor M11 is connected to a first end of the filter capacitor C2.

[0075] The second end of the resistor R3 is connected to the first end of A1 and the first end of the resistor R4. The source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M9 and the gate of the NMOS transistor M9. The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M8. The source of the NMOS transistor M8 is connected to the second end of the filter capacitor C1, the second end of the resistor R4, the first end of the resistor R2, the source of the NMOS transistor M3, the source of the NMOS transistor M2, the first end of the energy storage capacitor C3, and the source of the NMOS transistor M1.

[0076] The second end of the filter capacitor C2 is connected to the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M12, and the source of the PMOS transistor M4. The drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M6, the gate of the PMOS transistor M7, and the drain of the NMOS transistor M5. The gate of the NMOS transistor M5 is connected to the third end of A1. The second end of A1 is connected to the second end of the resistor R2 and the source of the NMOS transistor M5.

[0077] The drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M3, the drain of the NMOS transistor M3, and the gate of the NMOS transistor M2. The drain of the PMOS transistor M12 is connected to the gate of the PMOS transistor M12, the gate of the PMOS transistor M4, and the drain of the NMOS transistor M2. The drain of the PMOS transistor M4, the second end of the energy storage capacitor C3, the drain of the NMOS transistor M1, the first end of the comparator COMP2, and the second end of the comparator COMP3 are all connected to the second end of the comparator COMP1.

[0078] A third terminal of the comparator COMP2 is connected to the input terminal of the inverter INV1, an output terminal of the inverter INV1 is connected to the first input terminal of the NAND gate NAND1, a third terminal of the comparator COMP3 is connected to the input terminal of the inverter INV2, and an output terminal of the inverter INV2 is connected to the second input terminal of the NAND gate NAND2;

[0079] The output of NAND gate NAND2 is connected to the second input of NAND gate NAND1. The output of NAND gate NAND1, the first input of NAND gate NAND2 and the gate of NMOS transistor M1 are connected to the logic circuit and the second end of the dead zone module.

[0080] like Figure 2 As shown, VDDH is clamped by three diodes to reduce the voltage domain, avoiding unnecessary power consumption. A1 and M2 form a gain-boosting technology to generate bias current. Ideally, the current generated by M2 is [(R4 / R3+R4)×VDDH] / R2, providing current bias for the subsequent circuit. C1, C2, and C3 are all MOS tubes used as capacitors, of which C1 and C2 are used as pre-regulatory filter capacitors, and C3 is an energy storage capacitor. When the current charges C3, V RAMP The voltage rises linearly until it reaches VH, CLK generates a high level to open M1, and M1 acts as a current discharge branch; similarly, after M1 is opened, V RAMP The voltage drops linearly until it drops to VL, and CLK generates a low level, causing the current to recharge C3. This circuit can also generate V RAMP and CLK, and the rise time (low level) and fall time (high level) are related to the charging and discharging of the capacitor and the delay of the logic gate.

[0081] The specific working scheme of the present invention is as follows:

[0082] Open loop working conditions:

[0083] 1. When S1 is turned on and S2 is turned off, V in The inductor is charged to GND, and the inductor current increases linearly

[0084] 2. When S1 is turned off and S2 is turned on, the inductor L discharges, the current of the inductor L decreases, and the voltage across the inductor L is reversed, so at this time the current flows through the capacitor C OUT , for capacitor C OUT Charging, the potential decreases in the direction of current flow, so we get V out Negative pressure drop.

[0085] 3. Without considering the conduction loss, when the inductor L is charged, the voltage drop across it is V in When the inductor L discharges, the voltage drop across it is V OUTAccording to the volt-second balance principle of the inductor L, the conversion ratio M = -D / (1-D), where D is the duty cycle control signal, that is, V RAMP and V C The resulting signals are compared.

[0086] 4. Because the voltage drop across S2 is at least 40V, in specific implementation, high-voltage MOS tubes are used in this topology to avoid breakdown.

[0087] Loop control:

[0088] 1. The feedback resistor is divided to obtain V fb Signal, V fb Signal and V REF The signal is error amplified to generate a V C signal, when V OUT When there is a fluctuation in the change, this fluctuation is reflected in V fb In, recorded in V C signal, generated by OSC V RAMP The signal is compared to generate a signal D that controls the duty cycle change, and then the gates of the two MOS tubes are adjusted and controlled by the driving circuit and the level shift circuit to make V OUT Back to normal.

[0089] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A high negative voltage conversion circuit, characterized in that: Including PMOS tube S1, NMOS tube S2, inductor L, resistor R DCR , resistor R ESR , resistor R L , resistor R f1 , resistor R f2 , capacitor C OUT , an error amplifier with a compensation network, a clock and ramp signal generator OSC, a comparator COMP1, a logic circuit and a dead zone module, and a level converter Levelshift; the logic circuit and the dead zone module include a driving circuit P_DRI for driving the PMOS tube S1 and a driving circuit N_DRI for driving the NMOS tube S2; The source of the PMOS tube S1 is connected to the input terminal V in The drain of the PMOS tube S1 is connected to the first end of the inductor L and the drain of the NMOS tube S2, and the second end of the inductor L is connected to the resistor R DCR The first end of the resistor R DCR The second end is connected to the resistor R ESR The first end of the resistor R L The first end of the resistor R f1 The first end and GND, the resistor R ESR The second terminal is connected to the capacitor C OUT The source of the NMOS tube S2 is connected to the capacitor C OUT The second end of the resistor R L The second end of the resistor R f2 The first terminal and the output terminal V out , the resistor R f1 The second terminal is connected to the R f2 The second end of the resistor R f1 and the R f2 The feedback signal V obtained after voltage division fb The first terminal of the error amplifier is connected to the reference voltage V REF ; The error signal V at the third terminal of the error amplifier C Connect the first terminal of the comparator COMP1, the ramp signal V of the clock and ramp signal generator OSC RAMP The generating terminal is connected to the second terminal of the comparator COMP1, the third terminal of the comparator COMP1 is connected to the first terminal of the logic circuit and the dead zone module, and the clock signal CLK of the OSC is generated and connected to the second terminal of the logic circuit and the dead zone module; the third terminal and the fourth terminal of the logic circuit and the dead zone module are respectively connected to the first terminal and the second terminal of the level converter Levelshift through the driving circuit P_DRI and the driving circuit N_DRI, the third terminal of the level converter Levelshift is connected to the gate of the PMOS tube S1, and the fourth terminal of the level converter is connected to the gate of the NMOS tube S2.

2. A high negative voltage conversion circuit according to claim 1, characterized in that: It also includes a bandgap reference circuit Bandgap, the reference voltage V REF Generated by the bandgap reference circuit Bandgap.

3. The high negative voltage conversion circuit according to claim 2, characterized in that: The bandgap reference circuit Bandgap includes a voltage stabilizing diode ZD, a resistor RA, a resistor Ra, a resistor Rb, a capacitor Cc, an operational amplifier AMP, a filter capacitor Ca, a filter capacitor Cb, an NMOS transistor MN, an NMOS transistor MB, an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor NM10, an NMOS transistor NM11, an NMOS transistor NM12, a PMOS transistor NM8, a PMOS transistor NM9, a PMOS transistor NM5, a PMOS transistor NM3, a PMOS transistor NM1, a PMOS transistor NM4, a PMOS transistor NM2, a PMOS transistor NM13, a PMOS transistor NM14, a PMOS transistor NM15, a PMOS transistor NM16, a PNP transistor Q1, a PNP transistor Q2, and a PNP transistor Q3; The negative terminal of the voltage stabilizing diode ZD is connected to the first terminal of the resistor RA, the drain of the NMOS transistor NM10, the gate of the NMOS transistor NM10, the first terminal of the filter capacitor Ca, and the gate of the NMOS transistor MN. The second terminal of the resistor RA is connected to the drain of the NMOS transistor MN. The source of the NMOS transistor NM10 is connected to the drain of the NMOS transistor NM11 and the gate of the NMOS transistor NM11, the source of the NMOS transistor NM11 is connected to the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM12, and the source of the NMOS transistor MN is connected to the first end of the filter capacitor Cb; The second end of the filter capacitor Cb is connected to the source of the PMOS transistor NM8, the source of the PMOS transistor NM3, the source of the PMOS transistor NM4, the source of the PMOS transistor NM13, and the source of the PMOS transistor NM14; The gate of the PMOS transistor NM8 is connected to the drain of the PMOS transistor NM8 and the source of the PMOS transistor NM9, the gate of the PMOS transistor NM9 is connected to the drain of the PMOS transistor NM9 and the source of the PMOS transistor NM5, the gate of the PMOS transistor NM5 is connected to the gate of the NMOS transistor NM6, and the drain of the PMOS transistor NM5 is connected to the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM7; The gate of the PMOS transistor NM3 is connected to the gate of the PMOS transistor NM4, the first end of the operational amplifier AMP, and the drain of the NMOS transistor NM7; the drain of the PMOS transistor NM3 is connected to the source of the PMOS transistor NM1; the drain of the PMOS transistor NM1 is connected to the gate of the PMOS transistor NM1, the gate of the PMOS transistor NM2, the second end of the operational amplifier AMP, and the emitter of the PNP-type transistor Q1; the drain of the PMOS transistor NM4 is connected to the source of the PMOS transistor NM2; the drain of the PMOS transistor NM2 is connected to the third end of the operational amplifier AMP and the first end of the resistor Ra; the second end of the resistor Ra is connected to the emitter of the PNP-type transistor Q2; The drain of the PMOS transistor NM13 is connected to the source of the PMOS transistor NM15, the drain of the PMOS transistor NM15 is connected to the drain of the NMOS transistor MB, the drain of the PMOS transistor NM14 is connected to the source of the PMOS transistor NM16, the drain of the PMOS transistor NM16 is connected to the first end of the resistor Rb and the first end of the capacitor Cc, and the second end of the resistor Rb is connected to the emitter of the PNP transistor Q3; The positive terminal of the diode ZD is connected to the source of the NMOS transistor NM12, the second terminal of the filter capacitor Ca, the source of the NMOS transistor NM6, the source of the NMOS transistor NM7, the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2, the gate of the NMOS transistor MB, the source of the NMOS transistor MB, the collector of the PNP transistor Q3, the base of the PNP transistor Q3 and the second terminal of the capacitor Cc; The drain of the PMOS transistor NM16 , the first end of the capacitor Cc, the first end of the resistor Rb, the gate of the PMOS transistor NM5 , and the gate of the NMOS transistor NM6 are connected to the error amplifier.

4. The high negative voltage conversion circuit according to claim 3, characterized in that: It also includes a protection module Protect and a soft start circuit Softstart, wherein the protection module Protect is connected to the logic circuit and the fifth end of the dead zone module; the Bandgap circuit is electrically connected to the error amplifier through the soft start circuit Softstart.

5. The high negative voltage conversion circuit according to claim 1, characterized in that: It also includes a 5V pre-stabilizing circuit, the VDD end of the pre-stabilizing circuit is connected to the source of the PMOS tube S1, and the VDD5V end of the pre-stabilizing circuit is connected to the resistor R DCR The second end of the resistor R ESR The first end of the resistor R L The first end of the resistor R f1 and GND.

6. The high negative voltage conversion circuit according to claim 1, characterized in that: It also includes a zero-crossing detection module ZCD, and the logic circuit and dead zone module also include an AND gate circuit AND, a single pulse trigger One-Shot1, a single pulse trigger One-Shot2 and an RS trigger; The first end of the zero-crossing detection module ZCD is connected to the SW point, the second end of the zero-crossing detection module ZCD is connected to the output signal P_DRV of the drive circuit P_DRI, the third end of the zero-crossing detection module ZCD is connected to the first input end of the AND gate circuit AND, the output end of the AND gate circuit AND is connected to the first end of the single-pulse trigger One-Shot1, the second end of the single-pulse trigger One-Shot1 is connected to the S end of the RS trigger, the R end of the RS trigger is connected to the first end of the single-pulse trigger One-Shot2, the second end of the single-pulse trigger One-Shot2 is connected to the output signal P_DRV of the drive circuit P_DRI, the Q end of the RS trigger is connected to the first end of the drive circuit N_DRI, the second and third ends of the drive circuit N_DRI are the output signal N_DRV, and the delay signal N_DRV_Delay of the output signal N_DRV of the fourth end of the drive circuit N_DRI is connected to the second input end of the AND gate circuit AND.

7. The high negative voltage conversion circuit according to claim 1, characterized in that: The clock and ramp signal generator OSC includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a filter capacitor C1, a filter capacitor C2, a storage capacitor C3, a comparator COMP2, a comparator COMP3, A1, an inverter INV1, an inverter INV2, a NAND gate NAND1, a NAND gate NAND2, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M5, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, a PMOS tube M6, a PMOS tube M7, a PMOS tube M12, and a PMOS tube M4; The first end of the resistor R3 is connected to the first end of the resistor R1 and the drain of the NMOS transistor M11. The second end of the resistor R1 is connected to the drain of the NMOS transistor M10, the gate of the NMOS transistor M10, the first end of the filter capacitor C1, and the gate of the NMOS transistor M11. The source of the NMOS transistor M11 is connected to the first end of the filter capacitor C2. The second end of the resistor R3 is connected to the first end of A1 and the first end of the resistor R4, the source of the NMOS transistor M10 is connected to the drain of the NMOS transistor M9 and the gate of the NMOS transistor M9, the source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M8 and the gate of the NMOS transistor M8, and the source of the NMOS transistor M8 is connected to the second end of the filter capacitor C1, the second end of the resistor R4, the first end of the resistor R2, the source of the NMOS transistor M3, the source of the NMOS transistor M2, the first end of the energy storage capacitor C3, and the source of the NMOS transistor M1; The second end of the filter capacitor C2 is connected to the source of the PMOS transistor M6, the source of the PMOS transistor M7, the source of the PMOS transistor M12, and the source of the PMOS transistor M4; the drain of the PMOS transistor M6 is connected to the gate of the PMOS transistor M6, the gate of the PMOS transistor M7, and the drain of the NMOS transistor M5; the gate of the NMOS transistor M5 is connected to the third end of A1; and the second end of A1 is connected to the second end of the resistor R2 and the source of the NMOS transistor M5; The drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M3, the drain of the NMOS transistor M3, and the gate of the NMOS transistor M2; the drain of the PMOS transistor M12 is connected to the gate of the PMOS transistor M12, the gate of the PMOS transistor M4, and the drain of the NMOS transistor M2; the drain of the PMOS transistor M4, the second end of the energy storage capacitor C3, the drain of the NMOS transistor M1, the first end of the comparator COMP2, and the second end of the comparator COMP3 are all connected to the second end of the comparator COMP1; The third terminal of the comparator COMP2 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the first input terminal of the NAND gate NAND1, the third terminal of the comparator COMP3 is connected to the input terminal of the inverter INV2, and the output terminal of the inverter INV2 is connected to the second input terminal of the NAND gate NAND2; The output end of the NAND gate NAND2 is connected to the second input end of the NAND gate NAND1. The output end of the NAND gate NAND1, the first input end of the NAND gate NAND2 and the gate of the NMOS tube M1 are connected to the second end of the logic circuit and the dead zone module.

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