Relaxation oscillator, clock circuit and electronic system

Abstract

The invention provides a relaxation oscillator, a clock circuit and an electronic system, and the relaxation oscillator comprises a charging and discharging module which comprises a first charging and discharging unit and a second charging and discharging unit, is controlled by two groups of control signals, generates a first ramp signal and a second ramp signal through periodic charging and discharging of a capacitor, and alternately outputs the first ramp signal and the second ramp signal as oscillation signals; the voltage average feedback module is used for sampling the oscillation signal and comparing the oscillation signal with a reference signal to generate a feedback signal; the comparison module is used for carrying out periodic input switching on the received oscillation signal, the feedback signal and the reference ground signal through two groups of control signals, and comparing the input signals to generate a first trigger signal and a second trigger signal; the latch module generates a first clock signal and a second clock signal based on the first trigger signal and the second trigger signal; and the control module generates two groups of control signals based on the first and second clock signals. According to the relaxation oscillator, the problem that the oscillation frequency is easily affected due to the fact that an existing relaxation oscillator is out of order is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a relaxation oscillator, a clock circuit and an electronic system. Background Art

[0002] As a key clock source in analog integrated circuits, relaxation oscillators (LOs) are widely used in Internet of Things (IoT) sensors, biomedical chips, energy harvesting systems, and digital circuit clock generation due to their ease of integration, stable structure, and low power consumption. In recent years, research on relaxation oscillators has focused on low-power design, process variation (PVT) optimization, and high-frequency stability enhancement, achieving promising results. However, despite these advances, current relaxation oscillator designs still face the following technical bottlenecks.

[0003] 1) Temperature and power supply voltage sensitivity

[0004] The oscillation frequency of traditional RC charge-discharge relaxation oscillators is significantly affected by temperature variations (typical temperature coefficient >500ppm / °C), and power supply voltage fluctuations can cause frequency drift (for example, a supply voltage change of 1.8V±10% results in a frequency shift of >8%). Existing compensation solutions, such as using PTAT current sources or applying trimming circuits, require additional circuit modules, resulting in increased chip area and power consumption.

[0005] 2) Impact of Comparator Offset on Center Frequency

[0006] The comparator's input offset voltage (approximately 1mV to 10mV) directly introduces errors in the charge and discharge thresholds, resulting in center frequency deviation (measured impacts can reach ±12%). Existing offset cancellation techniques (such as auto-zeroing or chopper stabilization) require complex timing control, resulting in extended startup times (>10μs) and the introduction of additional noise.

[0007] 3) Insufficient startup reliability

[0008] Most designs rely on external reset signals or initial charging circuits, which are prone to startup failure in low-voltage / low-temperature environments (measured failure probability >5%). In addition, the traditional SR latch startup structure has a race risk. That is, when there is a delay inside the latch, it is prone to state uncertainty or metastable state, which leads to an imbalance in the duty cycle of the output oscillation waveform.

[0009] In addition, the impact of technical defects on practical applications cannot be ignored. The above problems lead to limited performance of existing relaxation oscillators in the following scenarios (for example, energy harvesting systems, high-precision sensor interfaces and deep submicron process nodes), and their improvement solutions have certain limitations; for example, in some digital calibration technologies, a high-frequency reference clock needs to be introduced, which conflicts with the original low-power design goal; the cost of some adaptive bias compensation is the need to increase static power consumption by at least 15% and cannot dynamically respond to rapid PVT changes.

[0010] Based on the current state of research, it can be seen that relaxation oscillators still face numerous key technical challenges in their core structural design. These challenges not only concern their fundamental operating principles and architectural optimization, but also the varying performance requirements imposed on oscillators by different application scenarios. Therefore, overcoming these bottlenecks within the existing technological framework while balancing various performance indicators remains a core issue in current relaxation oscillator research.

[0011] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0012] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a relaxation oscillator, a clock circuit and an electronic system for solving the problem that the existing relaxation oscillator is easily affected by the oscillation frequency due to the presence of comparative imbalance.

[0013] To achieve the above-mentioned and other related purposes, the present invention provides a relaxation oscillator, comprising:

[0014] The charging and discharging module includes a first charging and discharging unit and a second charging and discharging unit, which are controlled by two sets of control signals and generate a first ramp signal and a second ramp signal respectively by periodically charging and discharging the capacitor and output them alternately as oscillation signals;

[0015] a voltage average feedback module, receiving an oscillation signal, and generating a feedback signal by sampling the oscillation signal and comparing the sample with a reference signal;

[0016] a comparison module, receiving an oscillation signal, a feedback signal, and a reference ground signal, performing periodic input switching on the received signals through two sets of control signals, and generating a first trigger signal and a second trigger signal by comparing the input signals;

[0017] a latch module, receiving a first trigger signal and a second trigger signal, and generating a first clock signal and a second clock signal based on the first trigger signal and the second trigger signal;

[0018] The control module receives a first clock signal and a second clock signal, and generates two groups of control signals based on the first clock signal and the second clock signal.

[0019] Optionally, the first charge and discharge unit includes a first current source, a first capacitor, a first MOS transistor, a second MOS transistor, and a third MOS transistor, wherein: an output end of the first current source is connected to the source of the first MOS transistor, a gate of the first MOS transistor receives a first control signal, a drain of the first MOS transistor is connected to an upper plate of the first capacitor, a drain of the second MOS transistor, and a drain of the third MOS transistor, a lower plate of the first capacitor is connected to a reference ground, a gate of the second MOS transistor receives an inverted signal of the second control signal, a source of the second MOS transistor is connected to the reference ground, a gate of the third MOS transistor receives an inverted signal of the first control signal, and a source of the third MOS transistor outputs the first ramp signal as the oscillation signal;

[0020] The second charge and discharge unit includes a second current source, a second capacitor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, wherein: the output end of the second current source is connected to the source of the fourth MOS transistor, the gate of the fourth MOS transistor receives the second control signal, the drain of the fourth MOS transistor is connected to the upper plate of the second capacitor, the drain of the fifth MOS transistor, and the drain of the sixth MOS transistor, the lower plate of the second capacitor is connected to the reference ground, the gate of the fifth MOS transistor receives the inverted signal of the first control signal, the source of the fifth MOS transistor is connected to the reference ground, the gate of the sixth MOS transistor receives the inverted signal of the second control signal, and the source of the sixth MOS transistor outputs the second ramp signal as the oscillation signal.

[0021] Optionally, the current values ​​of the first current source and the second current source are equal, the capacitance values ​​of the first capacitor and the second capacitor are equal, and the first current source and the second current source are implemented by a current mirror.

[0022] Optionally, the voltage average feedback module includes an integrating amplifier, a resistor and a third capacitor, wherein: the first end of the resistor receives the oscillation signal, the second end of the resistor is connected to the first input end of the integrating amplifier and the upper plate of the third capacitor, the second input end of the integrating amplifier receives the reference signal, and the output end of the integrating amplifier is connected to the lower plate of the third capacitor and outputs the feedback signal.

[0023] Optionally, the comparison module includes:

[0024] A switch unit receives an oscillation signal, a feedback signal, and a reference ground signal, performs periodic input switching on the received signals through two sets of control signals, and generates two sets of input signals in each input switching;

[0025] a first comparing unit, receiving a first group of input signals, and generating the first trigger signal by comparing two input signals in the first group of input signals;

[0026] The second comparison unit receives a second group of input signals and generates the second trigger signal by comparing two input signals in the second group of input signals.

[0027] Optionally, the latch module includes:

[0028] a latch unit, receiving a first trigger signal and a second trigger signal, and generating the first clock signal and the second clock signal based on the first trigger signal and the second trigger signal;

[0029] Alternatively, the latch module further comprises: a starting unit and / or a feeding unit;

[0030] The starting unit controls the latch unit to start oscillation based on the starting signal;

[0031] The feed unit includes a first feed part and a second feed part, and performs pre-charging control through two control signals to reduce signal transmission delay.

[0032] Optionally, the latch unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, wherein: the source of the seventh MOS transistor and the source of the eighth MOS transistor are connected to the power supply voltage, the gate of the seventh MOS transistor and the gate of the ninth MOS transistor receive the first trigger signal, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the drain of the ninth MOS transistor and outputs the first clock signal, the gate of the eighth MOS transistor is connected to the gate of the tenth MOS transistor, the source of the ninth MOS transistor is connected to the drain of the tenth MOS transistor, and the source of the tenth MOS transistor is connected to the reference MOSFET. According to the present invention, the source of the eleventh MOS transistor and the source of the twelfth MOS transistor are connected to the power supply voltage, the gate of the eleventh MOS transistor and the gate of the thirteenth MOS transistor receive the second trigger signal, the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor and the drain of the thirteenth MOS transistor and outputs the second clock signal, the gate of the twelfth MOS transistor is connected to the gate of the fourteenth MOS transistor, the source of the thirteenth MOS transistor is connected to the drain of the fourteenth MOS transistor, and the source of the fourteenth MOS transistor is connected to the reference ground, wherein the gate of the tenth MOS transistor is further connected to the drain of the twelfth MOS transistor, and the gate of the fourteenth MOS transistor is further connected to the drain of the eighth MOS transistor.

[0033] Optionally, when the latch module includes a startup unit, the startup unit includes a first inverter, a second inverter, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor, wherein: an input end of the first inverter receives a startup signal and is connected to the gate of the fifteenth MOS transistor and the gate of the sixteenth MOS transistor, an output end of the first inverter is connected to the input end of the second inverter, an output end of the second inverter is connected to the gate of the seventeenth MOS transistor and the gate of the eighteenth MOS transistor, the fifteenth MOS transistor is connected in parallel between the source and drain of the eighth MOS transistor, the sixteenth MOS transistor is connected in series between the source of the ninth MOS transistor and the drain of the tenth MOS transistor, the seventeenth MOS transistor is connected in parallel between the source and drain of the twelfth MOS transistor, and the eighteenth MOS transistor is connected in series between the source of the thirteenth MOS transistor and the drain of the fourteenth MOS transistor.

[0034] Optionally, when the latch module includes a feed unit, the first feed portion includes a nineteenth MOS transistor, wherein: a gate of the nineteenth MOS transistor receives the second control signal, a source of the nineteenth MOS transistor is connected to a reference ground, and a drain of the nineteenth MOS transistor is connected to the source of the ninth MOS transistor;

[0035] The second feed portion includes a twentieth MOS transistor, wherein: a gate of the twentieth MOS transistor receives a first control signal, a source of the twentieth MOS transistor is connected to a reference ground, and a drain of the twentieth MOS transistor is connected to the source of the thirteenth MOS transistor.

[0036] Optionally, the control module includes a third inverter and a fourth inverter, wherein: the input end of the third inverter receives the first clock signal and outputs a first control signal, the output end of the third inverter outputs an inverted signal of the first control signal, the input end of the fourth inverter receives the second clock signal and outputs a second control signal, and the output end of the fourth inverter outputs an inverted signal of the second control signal.

[0037] The present invention further provides a clock circuit, comprising: a relaxation oscillator as described in any one of the above.

[0038] The present invention further provides an electronic system, comprising: the clock circuit as described above.

[0039] As described above, the relaxation oscillator, clock circuit and electronic system of the present invention, through the design of the charging and discharging module, the voltage average feedback module, the comparison module, the latch module and the control module, propose a symmetrical oscillator architecture that can autonomously generate a clock signal, with high temperature stability and strong robustness; through the design of the comparison module with the input switch switching function, dynamic offset elimination can be achieved without external clock intervention, without the need for complex timing control, which is conducive to shortening the startup time and will not introduce additional noise; through the design of the latch module with the feed function, the signal transmission delay of the latch module can be effectively reduced, and the startup reliability is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Shown is a structural schematic diagram of a relaxation oscillator in an embodiment of the present invention.

[0041] Figure 2 Shown is a structural schematic diagram of a latch module in an embodiment of the present invention.

[0042] Figure 3 FIG. 2 shows another structural diagram of a latch module according to an embodiment of the present invention.

[0043] Figure 4 FIG. 2 shows another structural diagram of a latch module according to an embodiment of the present invention.

[0044] Figure 5 FIG. 2 is another structural diagram of a latch module according to an embodiment of the present invention.

[0045] Figure 6Shown is a waveform diagram of an oscillation signal obtained by simulation of a relaxation oscillator in an embodiment of the present invention.

[0046] Figure 7 It is a schematic diagram showing the oscillation frequencies of the relaxation oscillator obtained through simulation at different temperatures in an embodiment of the present invention.

[0047] Figure 8 Shown is a structural schematic diagram of a clock circuit in an embodiment of the present invention.

[0048] Figure 9 Shown is a structural schematic diagram of an electronic system in an embodiment of the present invention.

[0049] Component number description

[0050] 1 Electronic system

[0051] 10 Clock Circuit

[0052] 100 Relaxation Oscillator

[0053] 110 charging and discharging module

[0054] 111 First charge and discharge unit

[0055] 112 Second charge and discharge unit

[0056] 120 Voltage average feedback module

[0057] 130 comparison unit

[0058] 131 switch unit

[0059] 132 First comparison unit

[0060] 133 Second comparison unit

[0061] 140 latch module

[0062] 141 latch unit

[0063] 142 Starter Unit

[0064] 143 Feed Unit

[0065] 143a First feeder

[0066] 143b Second feeder

[0067] 150 control module DETAILED DESCRIPTION

[0068] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0069] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0070] like Figure 1 As shown, this embodiment provides a relaxation oscillator 100 , which includes a charge and discharge module 110 , a voltage average feedback module 120 , a comparison module 130 , a latch module 140 and a control module 150 .

[0071] The charge-discharge module 110 includes a first charge-discharge unit 111 and a second charge-discharge unit 112, which are controlled by two sets of control signals (for example, a first control signal and its inverted signal, and a second control signal and its inverted signal). The first ramp signal VC1 and the second ramp signal VC2 are generated by periodically charging and discharging the capacitors and are alternately output as the oscillation signal VOSC.

[0072] In one example, Figure 1 As shown, the first charge and discharge unit 111 includes a first current source IREF1, a first capacitor C1, a first MOS transistor M1, a second MOS transistor M2, and a third MOS transistor M3. The output end of the first current source IREF1 is connected to the source of the first MOS transistor M1, the gate of the first MOS transistor M1 receives the first control signal F1, the drain of the first MOS transistor M1 is connected to the upper plate of the first capacitor C1, the drain of the second MOS transistor M2, and the drain of the third MOS transistor M3, the lower plate of the first capacitor C1 is connected to the reference ground, the gate of the second MOS transistor M2 receives the inverted signal F2N of the second control signal, the source of the second MOS transistor M2 is connected to the reference ground, the gate of the third MOS transistor M3 receives the inverted signal F1N of the first control signal, and the source of the third MOS transistor M3 outputs the first ramp signal VC1 as the oscillation signal VOSC.

[0073] The second charge-discharge unit 112 includes a second current source IREF2, a second capacitor C2, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6. The output end of the second current source IREF2 is connected to the source of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 receives the second control signal F2, the drain of the fourth MOS transistor M4 is connected to the upper plate of the second capacitor C2, the drain of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6, the lower plate of the second capacitor C2 is connected to the reference ground, the gate of the fifth MOS transistor M5 receives the inverted signal F1N of the first control signal, the source of the fifth MOS transistor M5 is connected to the reference ground, the gate of the sixth MOS transistor M6 receives the inverted signal F2N of the second control signal, and the source of the sixth MOS transistor M6 outputs the second ramp signal VC2 as the oscillation signal VOSC.

[0074] In the two charge-discharge units described above, the current values ​​of the first current source IREF1 and the second current source IREF2 are equal, and the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are equal, so that the duty cycle of the clock signal is ideally 50%. In practical applications, the first current source IREF1 and the second current source IREF2 are typically designed as adjustable current sources to facilitate adjusting the design current values ​​according to specific needs. In one specific embodiment, the first current source IREF1 and the second current source IREF2 are implemented via current mirrors. In addition, the first MOS transistor M1 and the fourth MOS transistor M4 are of the same device type, namely, PMOS transistors, and the second MOS transistor M2, the third MOS transistor M3, the fifth MOS transistor M5, and the sixth MOS transistor M6 are of the same device type, namely, NMOS transistors. In this example, the two charge-discharge units have the same structure and are symmetrically arranged on both sides of the voltage averaging feedback module 120, which helps enhance the robustness of the relaxation oscillator 100.

[0075] In the two charge-discharge units of this example, two sets of control signals are used to control the on / off states of the first MOS transistor M1 to the sixth MOS transistor M6 to periodically charge and discharge the first capacitor C1 and the second capacitor C2, respectively, thereby periodically and alternately outputting the first ramp signal VC1 and the second ramp signal VC2. Specifically, the following is a flowchart:

[0076] In the first half of the oscillation cycle, the first control signal F1 is at a high level, the second control signal F2 is at a low level, the inverted signal F1N of the first control signal is at a low level, and the inverted signal F2N of the second control signal is at a high level, then:

[0077] In the first charge-discharge unit 111, the first MOS transistor M1 and the third MOS transistor M3 are turned off, and the second MOS transistor M2 is turned on. The first capacitor C1 is discharged through the second MOS transistor M2. In the second charge-discharge unit 112, the fourth MOS transistor M4 and the sixth MOS transistor M6 are turned on, and the fifth MOS transistor M5 is turned off. The second capacitor C2 is charged through the second current source IREF2. The top plate voltage of the second capacitor C2 (i.e., the second ramp signal VC2) starts from 0 and increases at a slope of IREF / C2. Because the sixth MOS transistor M6 is turned on, the oscillation signal VOSC is equal to the second ramp signal VC2, i.e., VOSC=VC2.

[0078] In the second half of the oscillation cycle, the first control signal F1 is at a low level, the second control signal F2 is at a high level, the inverted signal F1N of the first control signal is at a high level, and the inverted signal F2N of the second control signal is at a low level, then:

[0079] In the second charge-discharge unit 112, the fourth MOS transistor M4 and the sixth MOS transistor M6 are turned off, and the fifth MOS transistor M5 is turned on. The second capacitor C2 is discharged through the fifth MOS transistor M5. In the first charge-discharge unit 111, the first MOS transistor M1 and the third MOS transistor M3 are turned on, and the second MOS transistor M2 is turned off. The first capacitor C1 is charged through the first current source IREF1. The top plate voltage of the first capacitor C1 (i.e., the first ramp signal VC1) starts from 0 and increases at a slope of IREF1 / C1. Because the third MOS transistor M3 is turned on, the oscillation signal VOSC is equal to the first ramp signal VC1, i.e., VOSC=VC1.

[0080] The voltage average feedback module 120 receives the oscillation signal VOSC, samples the oscillation signal VOSC, and compares it with the reference signal VREF to generate the feedback signal VC. Specifically, the voltage average feedback module 120 implements signal sampling by integrating the oscillation signal VOSC over time.

[0081] In one example, Figure 1 As shown, the voltage average feedback module 120 includes an integrating amplifier INTA, a resistor R, and a third capacitor C3. A first end of the resistor R receives the oscillation signal VOSC, a second end of the resistor R is connected to a first input end (e.g., a non-inverting input end) of the integrating amplifier INTA and the upper plate of the third capacitor C3, a second input end (e.g., an inverting input end) of the integrating amplifier INTA receives a reference signal VREF, and an output end of the integrating amplifier INTA is connected to the lower plate of the third capacitor C3 and outputs a feedback signal VC.

[0082] In the voltage average feedback module 120 of this example, the value of the oscillation signal VOSC integrated over time is always equal to the reference signal VREF, satisfying the formula Where T is the oscillation period, VOSC is the oscillation signal, and VREF is the reference signal. Feedback signal VC is generated by real-time feedback adjustment of the oscillation signal VOSC to dynamically adjust the signal level connected to comparison module 130, thereby reducing the impact of comparison module 130 delay and ambient temperature, and maintaining a stable oscillation period.

[0083] The comparison module 130 receives the oscillation signal VOSC, the feedback signal VC, and the reference ground signal GND, performs periodic input switching on the three received signals through two sets of control signals, and generates a first trigger signal and a second trigger signal by comparing the input signals; by adjusting the signal input to the comparator input terminal through periodic input switching, it can dynamically eliminate the influence of comparison offset on the oscillation frequency.

[0084] In one example, Figure 1 As shown, the comparison module 130 includes a switch unit 131 , a first comparison unit 132 and a second comparison unit 133 . The symmetrical design of the two comparison units is beneficial to enhancing the robustness of the relaxation oscillator 100 .

[0085] The switching unit 131 receives the oscillation signal VOSC, the feedback signal VC, and the reference ground signal GND, and periodically switches the three received signals through two sets of control signals. In each input switching, two sets of input signals are generated to be input into the two comparison units respectively. The switching frequency of the switching unit 131 is 2N times the output clock frequency of the relaxation oscillator 100 to ensure that the switching is synchronized with the charging and discharging of the capacitor, where N is a natural number greater than or equal to 1.

[0086] The switching unit 131 includes three input terminals and four output terminals. The three input terminals are respectively denoted as a first input terminal, a second input terminal and a third input terminal, and respectively receive the feedback signal VC, the oscillation signal VOSC and the reference ground signal GND. The four output terminals are respectively denoted as a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. The first output terminal and the second output terminal are correspondingly connected to the two input terminals of the first comparison unit 132 for providing a first group of input signals (including the first input signal A1 and the second input signal A2). The third output terminal and the fourth output terminal are correspondingly connected to the two input terminals of the second comparison unit 133 for providing a second group of input signals (including the third input signal A3 and the fourth input signal A4).

[0087] In the first half of the oscillation cycle, the first control signal F1 is at a high level, the second control signal F2 is at a low level, the inverted signal F1N of the first control signal is at a low level, and the inverted signal F2N of the second control signal is at a high level, then:

[0088] By switching the switch, the first output terminal is connected to the second input terminal, the second output terminal is connected to the third input terminal, the third output terminal is connected to the second input terminal, and the fourth output terminal is connected to the first input terminal. At this time, the first input signal A1 is the oscillation signal VOSC, that is, A1=VOSC, the second input signal A2 is the reference ground signal, that is, A2=GND, the third input signal A3 is the oscillation signal VOSC, that is, A3=VOSC, and the fourth input signal A4 is the feedback signal VC, that is, A4=VC;

[0089] In the second half of the oscillation cycle, the first control signal F1 is at a low level, the second control signal F2 is at a high level, the inverted signal F1N of the first control signal is at a high level, and the inverted signal F2N of the second control signal is at a low level, then:

[0090] Through switch switching, the first output end is connected to the first input end, the second output end is connected to the second input end, the third output end is connected to the third input end, and the fourth output end is connected to the second input end. At this time, the first input signal A1 is the feedback signal VC, that is, A1=VC, the second input signal A2 is the oscillation signal VOSC, that is, A2=VOSC, the third input signal A3 is the reference ground signal, that is, A3=GND, and the fourth input signal A4 is the oscillation signal VOSC, that is, A4=VOSC.

[0091] The first comparison unit 132 receives a first set of input signals and generates a first trigger signal by comparing two input signals in the first set of input signals. Figure 1 As shown, the first comparison unit 132 is implemented by a first comparator CMP1, wherein a first input terminal (e.g., a non-inverting input terminal) of the first comparator CMP1 receives a first input signal A1, a second input terminal (e.g., an inverting input terminal) of the first comparator CMP1 receives a second input signal A2, and an output terminal of the first comparator CMP1 generates a first trigger signal.

[0092] In the first half of the oscillation period, the first input signal A1 is the oscillation signal VOSC, and the second input signal A2 is the reference ground signal, that is, A1=VOSC, A2=GND, then: the first comparator CMP1 outputs a high level, at this time, the first trigger signal is a high level; in the second half of the oscillation period, the first input signal A1 is the feedback signal VC, and the second input signal A2 is the oscillation signal VOSC, that is, A1=VC, A2=VOSC, then: the first comparator CMP1 outputs a low level, at this time, the first trigger signal is a low level.

[0093] The second comparison unit 133 receives the second set of input signals and generates a second trigger signal by comparing two input signals in the second set of input signals. Figure 1 As shown, the second comparison unit 133 is implemented by a second comparator CMP2, wherein a first input terminal (e.g., a non-inverting input terminal) of the second comparator CMP2 receives a fourth input signal A4, a second input terminal (e.g., an inverting input terminal) of the second comparator CMP2 receives a third input signal A3, and an output terminal of the second comparator CMP2 generates a second trigger signal.

[0094] In the first half of the oscillation period, the third input signal A3 is the oscillation signal VOSC, and the fourth input signal A4 is the feedback signal VC, that is, A3=VOSC, A4=VC, then: the second comparator CMP2 outputs a low level, at this time, the second trigger signal is a low level; in the second half of the oscillation period, the third input signal A3 is the reference ground signal, and the fourth input signal A4 is the oscillation signal VOSC, that is, A3=GND, A4=VOSC, then: the second comparator CMP2 outputs a high level, at this time, the second trigger signal is a high level.

[0095] Of course, in other examples, it is also feasible for the comparison module 130 to generate two trigger signals by only performing a comparison operation of one comparison unit, but this does not enhance the robustness of the relaxation oscillator 100. In this case, the comparison module 130 includes a switch unit, a first comparison unit, and a fifth inverter.

[0096] The switch unit receives the oscillation signal VOSC, the feedback signal VC and the reference ground signal GND, performs periodic input switching on the three received signals through two groups of control signals, and generates a group of input signals in each input switching.

[0097] The switch switching unit includes three input terminals and two output terminals. The three input terminals are respectively denoted as a first input terminal, a second input terminal and a third input terminal, and respectively receive a feedback signal VC, an oscillation signal VOSC and a reference ground signal GND. The two output terminals are respectively denoted as a first output terminal and a second output terminal, wherein the first output terminal and the second output terminal are correspondingly connected to the two input terminals of the first comparison unit, for providing a set of input signals (including a first input signal A1 and a second input signal A2).

[0098] In the first half of the oscillation period, the first control signal F1 is at a high level, the second control signal F2 is at a low level, the inverted signal F1N of the first control signal is at a low level, and the inverted signal F2N of the second control signal is at a high level. Then: by switching the switch, the first output terminal is connected to the second input terminal, and the second output terminal is connected to the third input terminal. At this time, the first input signal A1 is the oscillation signal VOSC, that is, A1=VOSC, and the second input signal A2 is the reference ground signal, that is, A2=GND;

[0099] In the second half of the oscillation period, the first control signal F1 is at a low level, the second control signal F2 is at a high level, the inverted signal F1N of the first control signal is at a high level, and the inverted signal F2N of the second control signal is at a low level. Then: through switch switching, the first output end is connected to the first input end, and the second output end is connected to the second input end. At this time, the first input signal A1 is the feedback signal VC, that is, A1=VC, and the second input signal A2 is the oscillation signal VOSC, that is, A2=VOSC.

[0100] The first comparison unit receives the set of input signals and generates a first trigger signal by comparing two input signals in the set of input signals; the fifth inverter generates a second trigger signal by inverting the first trigger signal output by the first comparison unit. In a specific embodiment, the first comparison unit is implemented by a first comparator, wherein a first input terminal (e.g., a non-inverting input terminal) of the first comparator receives a first input signal A1, a second input terminal (e.g., an inverting input terminal) of the first comparator receives a second input signal A2, and an output terminal of the first comparator generates the first trigger signal.

[0101] In the first half of the oscillation period, the first input signal A1 is the oscillation signal VOSC, and the second input signal A2 is the reference ground signal, that is, A1=VOSC, A2=GND, then: the first comparator outputs a high level, at this time, the first trigger signal is a high level, and the second trigger signal is a low level; in the second half of the oscillation period, the first input signal A1 is the feedback signal VC, and the second input signal A2 is the oscillation signal VOSC, that is, A1=VC, A2=VOSC, then: the first comparator outputs a low level, at this time, the first trigger signal is a low level, and the second trigger signal is a high level.

[0102] The latch module 140 receives the first trigger signal and the second trigger signal, and generates the first clock signal and the second clock signal based on the first trigger signal and the second trigger signal.

[0103] In one example, Figure 2 As shown, the latch module 140 includes a latch unit 141, which receives a first trigger signal and a second trigger signal, and generates a first clock signal and a second clock signal based on the first trigger signal and the second trigger signal. Specifically, the latch unit 141 is implemented using an SR latch structure; in a specific embodiment, the latch unit 141 includes a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14. Among them:

[0104] The source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are connected to the power supply voltage. The gate of the seventh MOS transistor M7 and the gate of the ninth MOS transistor M9 are connected to each other as the set end S of the latch unit 141 and receive the first trigger signal. The drain of the seventh MOS transistor M7 is connected to the drain of the eighth MOS transistor M8 and the drain of the ninth MOS transistor M9 and serves as the first output end Q of the latch unit 141 to output the first clock signal. The gate of the eighth MOS transistor M8 is connected to the gate of the tenth MOS transistor M10. The source of the ninth MOS transistor M9 is connected to the drain of the tenth MOS transistor M10. The source of the tenth MOS transistor M10 is connected to the reference ground. The source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12 are connected to the power supply voltage. The gate of the eleventh MOS transistor M11 and the gate of the thirteenth MOS transistor M12 are connected to the power supply voltage. The gates of the MOS transistors M13 are connected to each other to serve as the reset terminal R of the latch unit 141 and receive the second trigger signal. The drain of the eleventh MOS transistor M11 is connected to the drain of the twelfth MOS transistor M12 and the drain of the thirteenth MOS transistor M13 and serves as the second output terminal QN of the latch unit 141 to output the second clock signal. The gate of the twelfth MOS transistor M12 is connected to the gate of the fourteenth MOS transistor M14. The source of the thirteenth MOS transistor M13 is connected to the drain of the fourteenth MOS transistor M14. The source of the fourteenth MOS transistor M14 is connected to the reference ground. The gate of the tenth MOS transistor M10 is also connected to the drain of the twelfth MOS transistor M12 to be connected to the second output terminal QN. The gate of the fourteenth MOS transistor M14 is also connected to the drain of the eighth MOS transistor M8 to be connected to the first output terminal Q.

[0105] In this embodiment, the seventh MOS transistor M7, the eighth MOS transistor M8, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 are of the same device type, namely, PMOS transistors, and the ninth MOS transistor M9, the tenth MOS transistor M10, the thirteenth MOS transistor M13, and the fourteenth MOS transistor M14 are of the same device type, namely, NMOS transistors. The seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, and the tenth MOS transistor M10 form a first NAND gate, and the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, and the fourteenth MOS transistor M14 form a second NAND gate, thereby forming an SR latch structure. Regarding the latch unit 141, in the first half of the oscillation cycle, the first trigger signal is high and the second trigger signal is low, then: the first clock signal is high and the second clock signal is low; in the second half of the oscillation cycle, the first trigger signal is low and the second trigger signal is high, then: the first clock signal is low and the second clock signal is high. It should be noted that the latch unit 141 of this example can start oscillation by various starting methods such as initializing the input, and there are no excessive restrictions on this.

[0106] In another example, Figure 3 As shown, the latch module 140 includes a latch unit 141 and a start-up unit 142; wherein, the latch unit 141 is the same as the previous example, and the relevant content can be found in the above, and will not be repeated here; the start-up unit 142 controls the latch unit 141 to start oscillation based on the start signal, which helps to shorten the start-up time of the latch unit 141 and achieve fast startup. In a specific embodiment, the start-up unit 142 includes a first inverter INV1, a second inverter INV2, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, and an eighteenth MOS transistor M18. Among them:

[0107] The input end of the first inverter INV1 receives the start signal OSC_EN and is connected to the gate of the fifteenth MOS transistor M15 and the gate of the sixteenth MOS transistor M16. The output end of the first inverter INV2 is connected to the input end of the second inverter INV2. The output end of the second inverter INV2 is connected to the gate of the seventeenth MOS transistor M17 and the gate of the eighteenth MOS transistor M18. The fifteenth MOS transistor M15 is connected in parallel between the source and drain of the eighth MOS transistor M8 (that is, the source of the fifteenth MOS transistor M15 is connected to the source of the eighth MOS transistor M8, and the drain of the fifteenth MOS transistor M15 is connected to the drain of the eighth MOS transistor M8). The sixteenth MOS transistor M16 is connected in series between the source of the ninth MOS transistor M9 and the drain of the tenth MOS transistor M10 ( That is, the drain of the sixteenth MOS transistor M16 is connected to the source of the ninth MOS transistor M9, and the source of the sixteenth MOS transistor M16 is connected to the drain of the tenth MOS transistor M10), the seventeenth MOS transistor M17 is connected in parallel between the source and drain of the twelfth MOS transistor M12 (that is, the source of the seventeenth MOS transistor M17 is connected to the source of the twelfth MOS transistor M12, and the drain of the seventeenth MOS transistor M17 is connected to the drain of the twelfth MOS transistor M12), and the eighteenth MOS transistor M18 is connected in series between the source of the thirteenth MOS transistor M13 and the drain of the fourteenth MOS transistor M14 (that is, the drain of the eighteenth MOS transistor M18 is connected to the source of the thirteenth MOS transistor M13, and the source of the eighteenth MOS transistor M18 is connected to the drain of the fourteenth MOS transistor M14).

[0108] In this embodiment, the fifteenth MOS transistor M15 and the seventeenth MOS transistor M17 are of the same device type, namely, PMOS transistors. The sixteenth MOS transistor M16 and the eighteenth MOS transistor M18 are of the same device type, namely, NMOS transistors. The first inverter INV1 and the second inverter INV2 form a startup chain, using a downward pulse as a startup signal to control the latch unit 141 to start oscillation. In practical applications, the two inverters are implemented using MOS transistors. Specifically, the first inverter INV1 includes a first PMOS transistor P1 and a first NMOS transistor N1, and the second inverter INV2 includes a second PMOS transistor P2 and a second NMOS transistor N2. The gate of the corresponding PMOS transistor and the gate of the corresponding NMOS transistor are connected to each other as the input of the corresponding inverter, the source of the corresponding PMOS transistor is connected to the power supply voltage, the drain of the corresponding PMOS transistor and the drain of the corresponding NMOS transistor are connected to each other as the output of the corresponding inverter, and the source of the corresponding NMOS transistor is connected to the reference ground.

[0109] In another example, Figure 4 As shown, the latch module 140 includes a latch unit 141 and a feed unit 143. The latch unit 141 is the same as in the first example, and the relevant details can be found above and will not be repeated here. The feed unit 143 includes a first feed section 143a and a second feed section 143b. Pre-charging is controlled by two control signals (i.e., a first control signal F1 and a second control signal F2) to reduce signal transmission delay. In one specific embodiment, the first feed section 143a includes a nineteenth MOS transistor M19, and the second feed section 143b includes a twentieth MOS transistor M20. Wherein: the gate of the nineteenth MOS transistor M19 receives the second control signal F2, the source of the nineteenth MOS transistor M19 is connected to the reference ground, and the drain of the nineteenth MOS transistor M19 is connected to the source of the ninth MOS transistor M9, that is, connected to the node J1; the gate of the twentieth MOS transistor M20 receives the first control signal F1, the source of the twentieth MOS transistor M20 is connected to the reference ground, and the drain of the twentieth MOS transistor M20 is connected to the source of the thirteenth MOS transistor M13, that is, connected to the node J2.

[0110] In this embodiment, the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 are of the same device type, namely, NMOS transistors. The design of the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 introduces two additional precharge current paths into the latch unit 141. Precharging causes the voltages of nodes J1 and J2 to rise in advance, thereby reducing signal transmission delay in the latch unit 141. It should be noted that the latch unit 141 of this example can initiate oscillation through various startup methods, such as initializing the input, and no further restrictions are imposed on this aspect.

[0111] In another example, Figure 5As shown, the latch module 140 includes a latch unit 141, a start unit 142 and a feed unit 143; wherein, the latch unit 141 is the same as the first example, and the relevant content can be found above in detail, which will not be repeated here; the start unit 142 is the same as the second example, and the relevant content can be found above in detail, which will not be repeated here; the feed unit 143 is the same as the third example, and the relevant content can be found above in detail, which will not be repeated here.

[0112] The control module 150 receives the first clock signal and the second clock signal, and generates two sets of control signals based on the first clock signal and the second clock signal, namely, the first control signal and its inverted signal, and the second control signal and its inverted signal.

[0113] In one example, Figure 1 As shown, the control module 150 includes a third inverter INV3 and a fourth inverter INV4, wherein: the input end of the third inverter INV3 receives the first clock signal and outputs the first control signal F1, the output end of the third inverter INV3 outputs the inverted signal F1N of the first control signal, the input end of the fourth inverter INV4 receives the second clock signal and outputs the second control signal F2, and the output end of the fourth inverter INV4 outputs the inverted signal F2N of the second control signal.

[0114] Next, the technical effect of the relaxation oscillator 100 of this embodiment is demonstrated by combining theoretical analysis and simulation results.

[0115] First, the feasibility of eliminating the influence of comparison misalignment on the oscillation frequency is verified by using the comparison module 130 with the input switch switching function.

[0116] Theoretically, by periodically switching the inputs to adjust the signals connected to the comparator's two inputs, the effects of the offset voltage are averaged rather than being applied to a single half-cycle. Furthermore, the offset voltage has opposite effects on the charge and discharge thresholds in adjacent cycles. Assume that the charge and discharge time of the capacitor from VTL to VTH is affected by the offset and satisfies the following formula.

[0117] Forward trigger time: Reverse trigger time: Where T1 is the forward trigger time, T2 is the reverse trigger time, VTH is the highest capacitor voltage, VTL is the lowest capacitor voltage, and VOS is the offset voltage.

[0118] If the offset voltage VOS is small, the Taylor expansion approximation yields T1 ≈ Tideal + ΔT and T2 ≈ Tideal - ΔT, where ΔT ∝ VOS and Tideal represents the forward and reverse trigger times without the offset. Therefore, the total oscillation period, T = T1 + T2 ≈ 2Tideal, indicating that the offset effect is canceled out to a first-order approximation. Furthermore, simulations using EDA tools revealed that the oscillation period of the comparison module 130 with input switch switching was shortened by 11 ns compared to a comparison module without the input switch switching function, demonstrating its feasibility.

[0119] Secondly, the latch module 140 having the feeding unit 143 is used to verify whether the latch module 140 can effectively reduce the signal transmission delay.

[0120] The design of feed unit 143 introduces two independent pre-charge current paths into latch unit 141, allowing key nodes J1 and J2 to enter a high-level pre-set phase before switching states, effectively shortening the flipping time of the logic gates within the latch unit. Simulations have shown that the average signal transmission delay of a conventional latch module without a feed unit is 7ns. However, the latch module 140 of this embodiment, equipped with a feed unit, reduces this delay to 3ns, a 57.1% reduction. This data demonstrates that the pre-charge mechanism, by optimizing the node voltage buildup process, increases the latch module's response speed by 2.3 times its original performance, significantly enhancing the relaxation oscillator's timing control accuracy and high-frequency operation capability.

[0121] Finally, the overall architecture of the relaxation oscillator 100 is simulated and verified. The simulation results show that it has strong robustness (the charging and discharging module 110, the comparison module 130, the latch module 140 and the control module 150 are all designed symmetrically, which is conducive to enhancing the robustness of the relaxation oscillator 100); oscillation can be achieved under the conditions of -40℃ to 150℃ and the corresponding clock signal waveform can be obtained, as shown in the figure. Figure 6 As shown in FIG, at a nominal temperature of 25°C, the center frequency is 5.8330 MHz and the duty cycle is 49.97%. In addition, at a temperature of -30°C to 120°C, the frequency deviation of the relaxation oscillator is controlled within the range of 0.006%. Figure 7 As shown, the expected effect can be achieved.

[0122] like Figure 8 As shown, this embodiment further provides a clock circuit 10, including a relaxation oscillator 100 for generating a clock signal. Of course, the clock circuit 10 may also include other device structures, such as a frequency divider, and there are no further limitations on this. In practical applications, the clock circuit 10 is typically an anti-interference digital clock circuit.

[0123] like Figure 9 As shown, this embodiment also provides an electronic system 1, including a clock circuit 10. Of course, it can also include other circuit structures, such as specific functional circuits, etc., and there are no further restrictions on this. In practical applications, the electronic system can be a low-power system-on-chip or an Internet of Things system.

[0124] In summary, a relaxation oscillator, clock circuit and electronic system of the present invention, through the design of a charge and discharge module, a voltage average feedback module, a comparison module, a latch module and a control module, proposes a symmetrical oscillator architecture that can autonomously generate a clock signal, with high temperature stability and strong robustness; through the design of a comparison module with an input switch switching function, dynamic offset elimination can be achieved without external clock intervention, without the need for complex timing control, which is conducive to shortening the startup time, and will not introduce additional noise; through the design of a latch module with a feed function, the signal transmission delay of the latch module can be effectively reduced, and startup reliability is improved. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0125] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A relaxation oscillator, characterized in that: The relaxation oscillator comprises: The charging and discharging module includes a first charging and discharging unit and a second charging and discharging unit, which are controlled by two sets of control signals and generate a first ramp signal and a second ramp signal respectively by periodically charging and discharging the capacitor and output them alternately as oscillation signals; a voltage average feedback module, receiving an oscillation signal, and generating a feedback signal by sampling the oscillation signal and comparing the sample with a reference signal; a comparison module, receiving an oscillation signal, a feedback signal, and a reference ground signal, performing periodic input switching on the received signals through two sets of control signals, and generating a first trigger signal and a second trigger signal by comparing the input signals; a latch module, receiving a first trigger signal and a second trigger signal, and generating a first clock signal and a second clock signal based on the first trigger signal and the second trigger signal; The control module receives a first clock signal and a second clock signal, and generates two groups of control signals based on the first clock signal and the second clock signal.

2. The relaxation oscillator according to claim 1, wherein The first charge and discharge unit includes a first current source, a first capacitor, a first MOS transistor, a second MOS transistor, and a third MOS transistor, wherein: an output end of the first current source is connected to the source of the first MOS transistor, a gate of the first MOS transistor receives a first control signal, a drain of the first MOS transistor is connected to the upper plate of the first capacitor, the drain of the second MOS transistor, and the drain of the third MOS transistor, a lower plate of the first capacitor is connected to a reference ground, a gate of the second MOS transistor receives an inverted signal of the second control signal, a source of the second MOS transistor is connected to the reference ground, a gate of the third MOS transistor receives an inverted signal of the first control signal, and a source of the third MOS transistor outputs the first ramp signal as the oscillation signal; The second charge and discharge unit includes a second current source, a second capacitor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, wherein: the output end of the second current source is connected to the source of the fourth MOS transistor, the gate of the fourth MOS transistor receives the second control signal, the drain of the fourth MOS transistor is connected to the upper plate of the second capacitor, the drain of the fifth MOS transistor, and the drain of the sixth MOS transistor, the lower plate of the second capacitor is connected to the reference ground, the gate of the fifth MOS transistor receives the inverted signal of the first control signal, the source of the fifth MOS transistor is connected to the reference ground, the gate of the sixth MOS transistor receives the inverted signal of the second control signal, and the source of the sixth MOS transistor outputs the second ramp signal as the oscillation signal.

3. The relaxation oscillator according to claim 2, characterized in that The current values ​​of the first current source and the second current source are equal, and the capacitance values ​​of the first capacitor and the second capacitor are equal, wherein the first current source and the second current source are implemented by a current mirror.

4. The relaxation oscillator according to claim 1, wherein: The voltage average feedback module includes an integrating amplifier, a resistor and a third capacitor, wherein: the first end of the resistor receives the oscillation signal, the second end of the resistor is connected to the first input end of the integrating amplifier and the upper plate of the third capacitor, the second input end of the integrating amplifier receives the reference signal, and the output end of the integrating amplifier is connected to the lower plate of the third capacitor and outputs the feedback signal.

5. The relaxation oscillator according to claim 1, wherein: The comparison module includes: A switch unit receives an oscillation signal, a feedback signal, and a reference ground signal, performs periodic input switching on the received signals through two sets of control signals, and generates two sets of input signals in each input switching; a first comparing unit, receiving a first group of input signals, and generating the first trigger signal by comparing two input signals in the first group of input signals; The second comparison unit receives a second group of input signals and generates the second trigger signal by comparing two input signals in the second group of input signals.

6. The relaxation oscillator according to claim 1, wherein: The latch module includes: a latch unit, receiving a first trigger signal and a second trigger signal, and generating the first clock signal and the second clock signal based on the first trigger signal and the second trigger signal; Alternatively, the latch module further comprises: a starting unit and / or a feeding unit; The starting unit controls the latch unit to start oscillation based on the starting signal; The feed unit includes a first feed part and a second feed part, and performs pre-charging control through two control signals to reduce signal transmission delay.

7. The relaxation oscillator according to claim 6, characterized in that The latch unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor, wherein: the source of the seventh MOS transistor and the source of the eighth MOS transistor are connected to the power supply voltage, the gate of the seventh MOS transistor and the gate of the ninth MOS transistor receive the first trigger signal, the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the drain of the ninth MOS transistor and outputs the first clock signal, the gate of the eighth MOS transistor is connected to the gate of the tenth MOS transistor, the source of the ninth MOS transistor is connected to the drain of the tenth MOS transistor, and the source of the tenth MOS transistor is connected to the reference ground The source of the eleventh MOS transistor and the source of the twelfth MOS transistor are connected to the power supply voltage, the gate of the eleventh MOS transistor and the gate of the thirteenth MOS transistor receive the second trigger signal, the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor and the drain of the thirteenth MOS transistor and outputs the second clock signal, the gate of the twelfth MOS transistor is connected to the gate of the fourteenth MOS transistor, the source of the thirteenth MOS transistor is connected to the drain of the fourteenth MOS transistor, and the source of the fourteenth MOS transistor is connected to the reference ground, wherein the gate of the tenth MOS transistor is also connected to the drain of the twelfth MOS transistor, and the gate of the fourteenth MOS transistor is also connected to the drain of the eighth MOS transistor.

8. The relaxation oscillator according to claim 7, characterized in that When the latch module includes a startup unit, the startup unit includes a first inverter, a second inverter, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and an eighteenth MOS transistor, wherein: an input end of the first inverter receives a startup signal and is connected to the gate of the fifteenth MOS transistor and the gate of the sixteenth MOS transistor, an output end of the first inverter is connected to the input end of the second inverter, an output end of the second inverter is connected to the gate of the seventeenth MOS transistor and the gate of the eighteenth MOS transistor, the fifteenth MOS transistor is connected in parallel between the source and drain of the eighth MOS transistor, the sixteenth MOS transistor is connected in series between the source of the ninth MOS transistor and the drain of the tenth MOS transistor, the seventeenth MOS transistor is connected in parallel between the source and drain of the twelfth MOS transistor, and the eighteenth MOS transistor is connected in series between the source of the thirteenth MOS transistor and the drain of the fourteenth MOS transistor.

9. The relaxation oscillator according to claim 7 or 8, characterized in that: When the latch module includes a feed unit, the first feed portion includes a nineteenth MOS transistor, wherein: a gate of the nineteenth MOS transistor receives a second control signal, a source of the nineteenth MOS transistor is connected to a reference ground, and a drain of the nineteenth MOS transistor is connected to a source of the ninth MOS transistor; The second feed portion includes a twentieth MOS transistor, wherein: a gate of the twentieth MOS transistor receives a first control signal, a source of the twentieth MOS transistor is connected to a reference ground, and a drain of the twentieth MOS transistor is connected to the source of the thirteenth MOS transistor.

10. The relaxation oscillator according to claim 1, wherein: The control module includes a third inverter and a fourth inverter, wherein: the input end of the third inverter receives the first clock signal and outputs a first control signal, the output end of the third inverter outputs an inverted signal of the first control signal, the input end of the fourth inverter receives the second clock signal and outputs a second control signal, and the output end of the fourth inverter outputs an inverted signal of the second control signal.

11. A clock circuit, characterized in that: The clock circuit comprises: the relaxation oscillator according to any one of claims 1 to 10.

12. An electronic system, characterized in that: The electronic system comprises: the clock circuit according to claim 11.

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