Bridging and weight capacitor mismatch calibration method for successive approximation analog-to-digital converter

Abstract

A bridging and weight capacitor mismatch calibration method of a successive approximation analog-to-digital converter relates to the technical field of integrated circuits, and adopts an iteration method to firstly calibrate a bridging capacitor to obtain a bridging compensation value, then calibrate a weight capacitor to obtain a weight compensation value, and combine to obtain a compensation parameter matrix Pt after tth compensation correction, converting the Pt into a configuration parameter, writing the configuration parameter into the ADC, and performing actual measurement to obtain an actual measurement performance parameter SNDRt after the tth compensation correction of the ADC; and iterating the steps until the difference value between the SNDRt and the SNDRt-1 is smaller than a preset threshold value, or when the compensation correction frequency t reaches a preset upper limit, finishing ADC trimming. The dynamic stepping function and the calculation model innovatively provided by the invention can quickly and accurately calculate the actual bridging and weight capacitance value after the ADC doping process error, and the multi-iteration process can calculate the capacitance value deviation value of the trimming capacitor to the compensation value, so that the actual performance of the ADC after trimming can approach the theoretical limit. The method can be compatible with SAR ADCs of digital domain and analog domain trimming design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bridge connection and weight capacitor mismatch calibration method for a successive approximation analog-to-digital converter. Background Art

[0002] Analog-to-digital converters (ADCs), bridging the physical and digital worlds, have important applications in communications, energy, healthcare, instrumentation, and AI. Successive approximation register (SAR) ADCs are widely used due to their balanced combination of conversion accuracy, speed, power consumption, and cost. The core of a SAR ADC consists of a digital-to-analog converter (DAC), a comparator, a sample-and-hold switch, and digital logic circuits. The mainstream charge redistribution SAR ADC utilizes a binary-weighted capacitor array as the DAC, whose accuracy directly determines the overall SAR ADC conversion accuracy.

[0003] Comparator offset in SAR ADCs can be largely eliminated through input or output offset storage technologies. Capacitor array errors primarily include errors in weight capacitor matching due to process errors and parasitic effects, as well as errors in bridge capacitor accuracy. Under existing manufacturing processes, the capacitor array in a SAR ADC occupies a large area, and its minimum mismatch rate is approximately 0.1%. Reducing capacitor size further amplifies the capacitance error ratio, making the doubling relationship between adjacent weight capacitors in the DAC and the accuracy of the bridge capacitor capacitance the primary factors limiting the ADC's dynamic and static performance. To improve ADC accuracy, capacitor array errors must be calibrated. Summary of the Invention

[0004] Based on the above problems, the purpose of the present invention is to propose a successive approximation register (SAR) ADC capacitor mismatch calibration method based on dynamic stepping and dual-iteration process, which is compatible with SAR ADCs designed for both digital and analog domain trimming, and realizes the numerical calculation and compensation of ADC bridge capacitance and weight capacitance errors.

[0005] The technical solution adopted by the present invention to achieve its invention object is a method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter, comprising the following steps:

[0006] S1, obtain the configuration information of the capacitor array used by the DAC module of the N-bit analog-to-digital converter ADC, the capacitor array includes M-bit bridge capacitors and M+1 segment weight capacitors, and SUM The bit weight capacitor is divided into N-bit equivalent quantized weight capacitors (C1, C2...C N ) and n-bit equivalent redundant weight capacitors (C R1 、C R1...C Rn ), according to the comparator comparison sequence combination (C1 C2 ... C R1 … C Rn … C N ), generating 1×Q SUM The equivalent ideal weight matrix of dimension:

[0007]

[0008] S2. Input the periodic signal required for ADC dynamic testing and collect data samples of length L required for ADC to calculate dynamic indicators;

[0009] S3, convert the data samples output by ADC into length and width [L:Q SUM ] matrix, and the transposed weight matrix W0 T Multiply them to get a decimal data set, perform FFT transformation and calculate the signal-to-noise-and-distortion ratio SNDR0 before adjustment;

[0010] S4. Use the iterative method to calibrate the M-bit bridge capacitor to obtain the bridge compensation scaling ratio [Ratio1 Ratio2… Ratio M ];

[0011] S5, using the iterative method to calibrate the weight capacitor to obtain the weight compensation value [Comp 1W Comp 2W …Comp LpW ], where Lp is the number of columns with the lowest adjustable bit in the weight matrix W;

[0012] S6: The bridge compensation scaling ratio [Ratio1 Ratio2 ... Ratio M ] multiplied by the designed capacitance of the bridge capacitor [C C1 C C2 … C CM ] T Get the bridge compensation value [Comp 1B Comp 2B … Comp MB ], and then the bridge compensation value [Comp 1B Comp 2B … Comp MB ] and the weight compensation value [Comp 1W Comp 2W … Comp LpW ], and the compensation parameter matrix P after the tth compensation correction ADC is obtained t ,

[0013] P t=[Comp 1B Comp 2B … Comp MB Comp 1W Comp 2W … Comp LpW ]

[0014] t is the number of compensation corrections, the first time is 1;

[0015] S7, the compensation parameters obtained by mixing all previous compensation corrections are set as the compensation parameter matrix P t =P t +P t-1 , P0=0;

[0016] S8, according to the ADC preset rule, the compensation parameter matrix P t Convert the ADC configuration parameters into ADC and follow the method of step S2 and step S3 to obtain the measured performance parameter SNDR of ADC after the tth compensation correction. t ;

[0017] S9, if SNDR t With SNDR t-1 The difference between the two values ​​is greater than the preset threshold value ΔdBFs, and t=t+1, and then repeat steps S4 to S8 in sequence until SNDR t With SNDR t-1 When the difference is less than the preset threshold value ΔdBFs, or when the compensation correction times t reaches the preset upper limit of the compensation correction times, the ADC trimming is completed.

[0018] Furthermore, in step S2, for an N-bit ADC without redundant bits, the binary code word Dout[N-1:0]=XX0111XXXXXX... is directly output. For an N-bit ADC with redundant bits, the register is configured to output the original code value Dout[Q_SUM-1:0]=XX0111XXXXXX... of the actual comparison sequence of the comparator.

[0019] Further, step S4 is specifically as follows:

[0020] S41, setting the initial bridge capacitance adjustment position x=1, the number of iterations i=1, and the equivalent weight matrix W=W0;

[0021] S42. Generate coefficient R according to the number of iterations i, R = Ratio = 1 + step0 × e λ(1-i) , where λ is the preset decay rate and step0 is the preset initial adjustment step;

[0022] Then, the coefficient R is used to scale the low-segment weights after the bridge capacitor position x in the equivalent weight matrix W to generate the adjusted equivalent weight matrix W.p :

[0023] W p =W,W p (1, Q x +1:Q SUM )=W(1,Q x +1:Q SUM )*R;

[0024] where Q x is the number of weighted capacitors separated after the bridge capacitor position x;

[0025] S43, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3;

[0026] S44. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p =W, otherwise the coefficient R is updated to 1 / Ratio, and the adjusted equivalent weight matrix W is regenerated according to the method in step S42 p , and store it as W;

[0027] S45, compare the number of iterations i and the preset upper limit of the number of iterations i max , if i max , let i=i+1 and go to step S42, if i=i max , then the compensation calculation of the current x-th bridge capacitor is completed, and the final W and i are recorded. max The accumulation of the iteration coefficient R, the i max The cumulative reciprocal of the iteration coefficient R is the compensation scaling ratio of the x-th bridge capacitor. x , and go to step S46;

[0028] S46, determine whether the current bridge capacitance bit x is the lowest bit M, if not, reset the number of iterations i to 1, set the bridge capacitance bit x = x + 1 and go to step S42, if yes, complete the compensation calculation of all bridge capacitances, and temporarily store the final weight matrix W as W B , save the bridge compensation scaling ratio [Ratio1 Ratio2 … Ratio M ].

[0029] Further, step S5 is specifically as follows:

[0030] S51, set the initial adjustment weight capacitance k = Lp, Lp is the column number of the lowest adjustable position in the weight matrix W, set the number of iterations j = 1, and the equivalent weight matrix W = W B ; ​

[0031] S52, generate step S according to the number of iterations j, S = Step k =step0×e λ(1-j) , where λ is the preset decay rate and step0 is the preset initial adjustment step;

[0032] Then the equivalent weight C of the current k-th weight capacitor in the equivalent weight matrix W is KW Increase the step S to generate the adjusted equivalent weight matrix W p :

[0033] W p =W,W p (k) = W(k) + S;

[0034] S53, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3;

[0035] S54. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p is W, otherwise the step S is updated to -Step k , and regenerate the adjusted equivalent weight matrix W according to the method in step S52 p , and store it as W;

[0036] S55, determine whether the current weight capacitor bit k is the highest bit 1, if not, set the weight capacitor bit k = k-1, and go to step S52, the number of iterations j remains unchanged, if yes, go to step S56;

[0037] S56. Compare the number of iterations j with the preset upper limit of the number of iterations j max , if j <j max , then the weight capacitor bit k is reset to Lp, the number of iterations j=j+1 and go to step S52, if j=j max , then the compensation calculation of all weighted capacitors is completed;

[0038] S57, calculate the j of each weight capacitor max The accumulation of iterative steps S, the j max The accumulated negative number of the iterative step S is the compensation value Comp of the k-th weight capacitor kW , temporarily store the final W as the actual simulation weight W cal , temporarily store the final SNDR2 as the optimal SNDR for simulation cal , save the weight compensation value [Comp 1W Comp 2W … Comp LpW ].

[0039] Furthermore, the preset threshold ΔdBFs=0.1dBFs.

[0040] The beneficial effects of the present invention are:

[0041] The present invention is based on the foreground calibration of the capacitor mismatch value calculated by periodic signal sampling. Its self-learning characteristics can overcome the precision error of the trimming capacitor to achieve accurate compensation for the matching error of the quantized weight capacitor and the redundant weight capacitor and the precision error of the bridging capacitor.

[0042] The innovative dynamic step function and calculation model proposed in this invention can quickly and accurately calculate the actual bridge and weight capacitance values ​​after the ADC doping process error, and the dual-iteration process can calculate the capacitance deviation of the trimmed capacitor into the compensation value, so that the actual performance of the ADC after trimming can approach the theoretical limit.

[0043] The present invention utilizes a single ADC dynamic test data set, aims to improve the signal-to-noise and distortion ratio (SNDR), gradually adjusts multiple bridging and weighting parameters based on dynamic attenuation steps, and iteratively calculates the theoretical optimal dynamic performance of the current ADC and the mismatch compensation value of each group of capacitors, and writes them into the ADC.

[0044] The present invention re-collects a dynamic test data set for the compensated ADC and iteratively calculates a second set of capacitance mismatch values. The new results mainly indicate the capacitance deviation of the trimmed capacitor, which is then matrix-accumulated with the first set of compensation values ​​and written to the ADC. This sampling-correction compensation value process can be iterated multiple times to further optimize ADC performance.

[0045] The dynamic step bridge and weighted capacitor value calculation model proposed in this invention, as well as the dual-iteration calibration method combining model calculation iteration with ADC compensation value correction iteration, have been effectively verified through actual measurements on 16-bit and 18-bit SAR ADCs.

[0046] The present invention has high calibration accuracy, and the compensation value correction design can overcome the mismatch of the capacitor array including the trimming capacitor. It is suitable for high-precision SAR ADC, and both dynamic and static indicators after trimming are excellent.

[0047] The present invention can be widely used in capacitor array SAR ADCs, and is compatible with analog domain and digital domain trimming and design of SAR ADCs without increasing the complexity of the ADC design and manufacturing process.

[0048] The present invention has simple requirements for reference signals, and only needs to input a periodic signal for dynamic testing, and has low requirements for external equipment and supporting platforms.

[0049] The present invention has a fast adjustment speed and only requires one set of periodic signal sampling to calculate and generate all adjustment position configuration parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is an overall flow chart of an embodiment of the present invention;

[0051] Figure 2 This is a flow chart of bridge capacitance calibration according to an embodiment of the present invention;

[0052] Figure 3 This is a flow chart of weighted capacitor calibration according to an embodiment of the present invention;

[0053] Figure 4 This is a structural diagram of a single-ended charge redistribution 16-bit high-precision SAR ADC according to an embodiment of the present invention;

[0054] Figure 5 The figure shows a comparison of the dynamic and static performance of a 16-bit high-precision ADC before and after calibration according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] The present invention is applicable to single-ended / dual-ended charge redistribution SAR ADCs trimmed in the analog domain and the digital domain. The following takes the analog domain trimmed single-ended charge redistribution SAR ADC as an example. Figure 4 This is a structural diagram of a single-ended charge redistribution type 16-bit high-precision SAR ADC provided in this embodiment, wherein the DAC capacitor array includes two-stage bridge capacitors, three sub-capacitor arrays, and no redundant weight capacitors. The bridge capacitor segmentation technology reduces the number of capacitors and divides the capacitor array into a "7+4+5" segmented structure including a high-segment MSB capacitor array and a low-segment LSB capacitor array. The highest segment capacitor array is 7 bits, the second highest segment capacitor array is 4 bits, and the lowest segment capacitor array is 5 bits. By adjusting C C1 and C C2 The size of can make the bridge capacitor array weight satisfy the binary relationship.

[0057] The analog trimming module of the 2-stage bridge capacitor is controlled by the logic control module to calibrate the bridge capacitor of the DAC. The quantization accuracy of the trimming module is 1 / 64LSB.

[0058] The high 7-bit quantized weight capacitor of the 16-bit weight capacitor is equipped with an analog trimming module, which is controlled by the logic control module to perform capacitance mismatch calibration on the DAC. The quantization accuracy of the trimming module is 1 / 128LSB.

[0059] For the above SAR ADC, Figures 1 to 3 A specific implementation method of the bridge connection and weight capacitor mismatch calibration method of the successive approximation analog-to-digital converter of the present invention is shown, including the following steps:

[0060] S1. Obtain configuration information of the capacitor array used by the DAC module of the 16-bit analog-to-digital converter ADC. The capacitor array includes 2-bit bridge capacitors and 3-segment weight capacitors. The number of weight capacitors contained in each weight capacitor segment from the high segment to the low segment is 7, 4, and 5, with a total of 16 weight capacitors. There are only quantized weight capacitors, and generate a 1×16-dimensional equivalent ideal weight matrix:

[0061] W0=[32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1];

[0062] The order of the elements in matrix W0 matches the comparison order of the comparator, where the last C 16W That is, the lowest bit quantization weight capacitor C N , its value is recorded as 1C, and so on C 1W The value is 32768C;

[0063] S2. Obtain an output data set of the analog-to-digital converter ADC to be calibrated according to a predetermined rule.

[0064] Input the periodic signal required for ADC dynamic test and collect the length 2 required for ADC to calculate dynamic indicators 16 The ADC directly outputs the binary code word Dout[15:0]=XX0111XXXXXX...

[0065] S3, obtain the dynamic performance of the analog-to-digital converter ADC to be calibrated:

[0066] Convert the data samples output by ADC into length and width[2 16 :16], and the transposed weight matrix W0 T Multiply them to get a decimal data set, perform FFT and then calculate the dynamic index before adjustment, namely the signal-to-noise-distortion ratio SNDR0;

[0067] S4. Using an iterative method, calibrate the 2-bit bridge capacitance to obtain the bridge compensation scaling ratio [Ratio1 Ratio2];

[0068] S5, using the iterative method to calibrate the weight capacitor to obtain the weight compensation value [Comp 1W Comp 2W …Comp 7W ], where Lp is the number of columns with the lowest adjustable bit in the weight matrix W;

[0069] S6, multiply the bridge compensation scaling ratio [Ratio1 Ratio2] obtained in step S4 by the bridge capacitor design capacitance [C C1 CC2 ] T Get the bridge compensation value [Comp 1B Comp 2B ], and then the bridge compensation value [Comp 1B Comp 2B ] and the weight compensation value [Comp 1W Comp 2W … Comp 7W ], and the compensation parameter matrix P after the tth compensation correction ADC is obtained t ,

[0070] P t =[Comp 1B Comp 2B Comp 1W Comp 2W … Comp 7W ]

[0071] t is the number of compensation corrections, the first time is 1;

[0072] S7, the compensation parameters obtained by mixing all previous compensation corrections are set as the compensation parameter matrix P t =P t +P t-1 , P0=0;

[0073] S8, according to the ADC preset rule, the compensation parameter matrix P t Convert the ADC configuration parameters into ADC and follow the method of step S2 and step S3 to obtain the measured performance parameter SNDR of ADC after the tth compensation correction. t Taking the first adjustment as an example, SNDR1 is usually higher than SNDR0 but lower than the optimal SNDR in simulation. cal ;

[0074] S9, if SNDR t With SNDR t-1 The difference between the two values ​​is greater than the preset threshold value ΔdBFs, and t=t+1, and then repeat steps S4 to S8 in sequence until SNDR t With SNDR t-1 When the difference is less than the preset threshold value ΔdBFs, or the compensation correction times t reaches the preset upper limit of compensation correction times, the ADC adjustment is completed;

[0075] The preset threshold in this embodiment is 0.1 dBFs. Usually, after three cycles, the difference between the two is less than 0.1 dBFs, and the ADC adjustment is completed.

[0076] In this embodiment, step S4 is specifically as follows:

[0077] S41, setting the initial bridge capacitance adjustment position x=1, the number of iterations i=1, and the equivalent weight matrix W=W0;

[0078] S42, the iterative step of the bridge capacitance is defined as an exponential decay function with the Euler number as the base, denoted as Ratio;

[0079] Generate coefficient R according to the number of iterations i, R = Ratio = 1 + step0 × e λ(1-i) , where λ is the preset decay rate and step0 is the preset initial adjustment step;

[0080] Then, the coefficient R is used to scale the low-segment weights after the bridge capacitor position x in the equivalent weight matrix W to generate the adjusted equivalent weight matrix W. p :

[0081] W p =W,W p (1, Q x +1:Q SUM )=W(1,Q x +1:Q SUM )*R;

[0082] where Q x is the number of weighted capacitors separated after the bridge capacitor position x;

[0083] First adjust the highest bridge capacitor to adjust the highest bridge capacitor C C1 For example, when the bridge capacitor position x=1, the high-segment weight capacitors divided out are Q1=7. The coefficient R is used to scale the low-segment weights after the bridge capacitor position 1 in the equivalent weight matrix W to generate the adjusted equivalent weight matrix W. p , the specific expression is:

[0084] W p =W, that is, first assign W completely to Wp to save the unadjusted part;

[0085] W p (1, 8:16) = W(1, 8:16) * R, that is, the 8 to 16 bits after the bridge capacitor bit 1 in W are partially adjusted (multiplied by R) and assigned to the 8 to 16 bits of Wp;

[0086] S43, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3;

[0087] S44. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p=W, otherwise the coefficient R is updated to 1 / Ratio, and the adjusted equivalent weight matrix W is regenerated according to the method in step S42 p , and store it as W;

[0088] S45, upper limit of iteration number i max Set it to 20 times, compare the number of iterations i with the preset upper limit of the number of iterations 20, if i<20, set i=i+1 and go to step S42, repeat steps S42 to S44 in sequence until the set upper limit of the number of iterations i=20 is reached, then complete the compensation calculation of the current x-th bridge capacitor, record the final W and the accumulation of the 20 iteration coefficients R, the reciprocal of the accumulation of the 20 iteration coefficients R is the compensation scaling ratio Ratio of the x-th bridge capacitor x , and go to step S46;

[0089] S46, determine whether the current bridge capacitance bit x is the lowest bit 2, if not, reset the number of iterations i to 1, set the bridge capacitance bit x = x + 1 and go to step S42, repeat steps S42 to S45 in sequence, if yes, complete the compensation calculation of all bridge capacitances, and temporarily store the final weight matrix W as W B , save the bridge compensation scaling ratio [Ratio1 Ratio2].

[0090] In this embodiment, step S5 is specifically as follows:

[0091] S51, set the initial adjustment weight capacitance k = Lp, Lp is the column number of the lowest adjustable position in the weight matrix W, set the number of iterations j = 1, and the equivalent weight matrix W = W B ;

[0092] S52, define the attenuation function for adjusting the weight capacitor step. The iterative step of the k-th weight capacitor is defined as an exponential attenuation function with the Euler number as the base, denoted as Step k :

[0093] Generate step S according to the number of iterations j, S = Step k =step0×e λ(1-j) , where λ is the preset decay rate and step0 is the preset initial adjustment step;

[0094] Then adjust the equivalent weight matrix W according to the predetermined rules, and adjust the equivalent weight C of the current k-th weight capacitor in the equivalent weight matrix W. KW Increase the step S to generate the adjusted equivalent weight matrix W p :

[0095] W p =W,W p (k) = W(k) + S;

[0096] Prioritize adjusting the lowest weight capacitor. Taking the adjustment of the lowest weight capacitor as an example, the number of columns of the lowest adjustable position in the equivalent weight matrix W is 7, k=7, and the lowest equivalent weight C in the weight matrix W is 7W Add step Step7 to generate the adjusted equivalent weight matrix W p , the specific expression is:

[0097] W p =W, that is, first assign W completely to Wp (to save the unadjusted part);

[0098] W p (7)=W(7)+Step7, that is, the C of the 7th position in W is 7W After local adjustment (add Step 7), assign it to the 7th bit of Wp;

[0099] S53, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3;

[0100] S54. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p is W, otherwise the step S is updated to -Step k , and regenerate the adjusted equivalent weight matrix W according to the method in step S52 p , and store it as W;

[0101] S55, determine whether the current weight capacitor bit k is the highest bit 1, if not, set the weight capacitor bit k = k-1, and go to step S52, repeat steps S52 to S54 in sequence, and the number of iterations j remains unchanged. If yes, go to step S56;

[0102] S56, upper limit of iteration number j max Set it to 50 times, compare the number of iterations j with the preset upper limit of 50, if j<50, then reset the weight capacitor bit k to 7, set the number of iterations j=j+1 and go to step S52, repeat steps S52 to S55 in sequence until the number of iterations j reaches the set upper limit of the number of iterations, that is, j=50, and the compensation calculation of all weight capacitors is completed;

[0103] S57, calculate the cumulative value of 50 iteration steps S for each weight capacitor, and the negative number of the cumulative value of 50 iteration steps S is the compensation value Comp of the k-th weight capacitor kW , temporarily store the final W as the actual simulation weight W cal , temporarily store the final SNDR2 as the optimal SNDR for simulation cal , save the weight compensation value [Comp1W Comp 2W … Comp LpW ].

[0104] In this embodiment, a bridge and weight capacitor mismatch calibration method for a successive approximation analog-to-digital converter is first performed to calibrate the bridge capacitor, then to calibrate the capacitor mismatch, and then to enter the iterative process of compensation value correction. In this embodiment, the performance comparison of the 16-bit high-precision ADC before and after calibration is shown in FIG. Figure 5 As shown in the figure, the dynamic effective bit ENOB is improved by 1.3 bits, the static DNL maximum value is improved from -0.6~1.8LSB to ±0.5LSB, and the INL maximum value is improved from ±5LSB to ±0.5LSB.

[0105] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0106] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0107] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0108] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0109] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other manner. Any person skilled in the art may utilize the above-disclosed technical content to modify or modify the present invention into equivalent embodiments. However, any simple modifications, equivalent variations, and modifications to the above embodiments that do not depart from the technical content of the present invention and are based on the technical essence of the present invention remain within the scope of protection of the present invention.

Claims

1. A method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter, characterized in that: The steps include: S1, obtain the configuration information of the capacitor array used by the DAC module of the N-bit analog-to-digital converter ADC, the capacitor array includes M-bit bridge capacitors and M+1 segment weight capacitors, and SUM The bit weight capacitor is divided into N-bit equivalent quantized weight capacitors (C1, C2...C N ) and n-bit equivalent redundant weight capacitors (C R1 、C R1 ...C Rn ), according to the comparator comparison sequence combination (C1C2…C R1 …C Rn …C N ), generating 1×Q SUM The equivalent ideal weight matrix of dimension: S2. Input the periodic signal required for ADC dynamic testing and collect data samples of length L required for ADC to calculate dynamic indicators; S3, convert the data samples output by ADC into length and width [L:Q SUM ] matrix, and the transposed weight matrix W0 T Multiply them to get a decimal data set, perform FFT transformation and calculate the signal-to-noise-and-distortion ratio SNDR0 before adjustment; S4. Use the iterative method to calibrate the M-bit bridge capacitor to obtain the bridge compensation scaling ratio [Ratio1 Ratio2 …Ratio M ]; S5, using the iterative method to calibrate the weight capacitor to obtain the weight compensation value [Comp 1W Comp 2W … Comp LpW ], where Lp is the number of columns with the lowest adjustable bit in the weight matrix W; S6, the bridge compensation scaling ratio [Ratio1Ratio2…Ratio M ] multiplied by the designed capacitance of the bridge capacitor [C C1 C C2 … C CM ] T Get the bridge compensation value [Comp 1B Comp 2B … Comp MB ], and then the bridge compensation value [Comp 1B Comp 2B … Comp MB ] and the weight compensation value [Comp 1W Comp 2W … Comp LpW ], and the compensation parameter matrix P after the tth compensation correction ADC is obtained t , P t =[Comp 1B Comp 2B … Comp MB Comp 1W Comp 2W … Comp LpW ] t is the number of compensation corrections, the first time is 1; S7, the compensation parameters obtained by mixing all previous compensation corrections are set as the compensation parameter matrix P t =P t +P t-1 , P0=0; S8, according to the ADC preset rule, the compensation parameter matrix P t Convert the ADC configuration parameters into ADC and follow the method of step S2 and step S3 to obtain the measured performance parameter SNDR of ADC after the tth compensation correction. t ; S9, if SNDR t With SNDR t-1 The difference between the two values ​​is greater than the preset threshold value ΔdBFs, and t=t+1, and then repeat steps S4 to S8 in sequence until SNDR t With SNDR t-1 When the difference is less than the preset threshold value ΔdBFs, or when the compensation correction times t reaches the preset upper limit of the compensation correction times, the ADC trimming is completed.

2. The method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter according to claim 1, wherein: In step S2, for an N-bit ADC without redundant bits, the binary code word Dout[N-1:0]=XX0111XXXXXX... is directly output. For an N-bit ADC with redundant bits, the register is configured to output the original code value Dout[Q_SUM-1:0]=XX0111XXXXXX... of the actual comparison sequence of the comparator.

3. The method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter according to claim 1, wherein: Step S4 is specifically as follows: S41, setting the initial bridge capacitance adjustment position x=1, the number of iterations i=1, and the equivalent weight matrix W=W0; S42. Generate coefficient R according to the number of iterations i, R = Ratio = 1 + step0 × e λ(1-i) , where λ is the preset decay rate and step0 is the preset initial adjustment step; Then, the coefficient R is used to scale the low-segment weights after the bridge capacitor position x in the equivalent weight matrix W to generate the adjusted equivalent weight matrix W. p : W p =W,W p (1,Q x +1:Q SUM )=W(1,Q x +1:Q SUM )*R; where Q x is the number of weighted capacitors separated after the bridge capacitor position x; S43, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3; S44. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p =W, otherwise the coefficient R is updated to 1 / Ratio, and the adjusted equivalent weight matrix W is regenerated according to the method in step S42 p , and store it as W; S45, compare the number of iterations i and the preset upper limit of the number of iterations i max , if i max , let i=i+1 and go to step S42, if i=i max , then the compensation calculation of the current x-th bridge capacitor is completed, and the final W and i are recorded. max The accumulation of the iteration coefficient R, the i max The cumulative reciprocal of the iteration coefficient R is the compensation scaling ratio of the x-th bridge capacitor. x , and go to step S46;​ S46, determine whether the current bridge capacitance bit x is the lowest bit M, if not, reset the number of iterations i to 1, set the bridge capacitance bit x = x + 1 and go to step S42, if yes, complete the compensation calculation of all bridge capacitances, and temporarily store the final weight matrix W as W B , save the bridge compensation scaling ratio [Ratio1 Ratio2 … Ratio M ].

4. The method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter according to claim 1, wherein: Step S5 is specifically as follows: S51, set the initial adjustment weight capacitance k = Lp, Lp is the column number of the lowest adjustable position in the weight matrix W, set the number of iterations j = 1, and the equivalent weight matrix W = W B ; S52, generate step S according to the number of iterations j, S = Step k =step0×e λ(1-j) , where λ is the preset decay rate and step0 is the preset initial adjustment step; Then the equivalent weight C of the current k-th weight capacitor in the equivalent weight matrix W is KW Increase the step S to generate the adjusted equivalent weight matrix W p : W p =W,W p (k)=W(k)+S; S53, the equivalent weight matrix W before adjustment and the equivalent weight matrix W after adjustment P Calculate the signal-to-noise-distortion ratios SNDR1 and SNDR2 respectively according to the method in step S3; S54. Compare SNDR1 and SNDR2. If SNDR2 is higher, store W. p is W, otherwise the step S is updated to -Step k , and regenerate the adjusted equivalent weight matrix W according to the method in step S52 p , and store it as W; S55, determine whether the current weight capacitor bit k is the highest bit 1, if not, set the weight capacitor bit k = k-1, and go to step S52, the number of iterations j remains unchanged, if yes, go to step S56; S56. Compare the number of iterations j with the preset upper limit of the number of iterations j max , if j <j max , then the weight capacitor bit k is reset to Lp, the number of iterations j=j+1 and go to step S52, if j=j max , then the compensation calculation of all weighted capacitors is completed; S57, calculate the j of each weight capacitor max The accumulation of iterative steps S, the j max The accumulated negative number of the iterative step S is the compensation value Comp of the k-th weight capacitor kW , temporarily store the final W as the actual simulation weight W cal , temporarily store the final SNDR2 as the optimal SNDR for simulation cal , save the weight compensation value [Comp 1W Comp 2W …Comp LpW ].

5. The method for calibrating bridge and weight capacitor mismatch of a successive approximation analog-to-digital converter according to claim 1, wherein: The preset threshold ΔdBFs=0.1dBFs.

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