Coding method and device

Abstract

A coding method and device can be applied to the technical field of communication. The encoding device obtains a sequence to be encoded (namely a first bit sequence), then encodes the first bit sequence based on a basis matrix and an expansion factor to obtain a second bit sequence, and outputs the second bit sequence. The second bit sequence may be transmitted over a channel after other processing. After receiving a signal transmitted through a channel, the decoding device processes the signal to obtain a to-be-decoded sequence, and then decodes the to-be-decoded sequence in combination with a basis matrix and an expansion factor to obtain a first bit sequence. The basis matrix can comprise a first sub-matrix, and the first sub-matrix can be an orthogonal matrix composed of n2 elements. The basis matrix with the structure can improve the degree of parallelism of coding and decoding, is compatible with equipment with low degree of parallelism, and is better in compatibility.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a coding method and device. Background Art

[0002] Channel coding is one of the most core technologies in wireless communications. The complete channel coding process includes, but is not limited to, adding cyclic redundancy check (CRC) codes, block segmentation, error correction coding, rate adaptation, block concatenation, data interleaving, and data scrambling. Error correction coding is the most critical component. Its purpose is to ensure that errors occurring during data transmission can be automatically corrected by the receiver using minimal redundancy. For a given bit error rate, the lower the redundancy required, the higher the coding efficiency.

[0003] The fifth generation (5 th -generation (5G) communications have seen more abundant business application scenarios and new requirements for channel coding. For example, the massive machine type of communication (mMTC) scenario requires smaller file packets to be transmitted, while the ultra-reliable low-latency communications (URLLC) scenario has very high requirements for encoding and decoding delay and low bit error. Therefore, based on the key requirements of the three major 5G application scenarios for channel coding, the 5G standard finally adopted low-density parity check code (LDPC) code and polar code. Compared with traditional linear block codes and convolutional codes, the performance of these two codes is better and can be very close to the limit of Shannon's theory. At the same time, they have their own different characteristics in applicable scenarios and the complexity of codecs. With the sixth generation (6 th With the advent of 6G (6th generation) communications, real-time, high-data-rate applications such as extended reality (XR) and immersive services are emerging commercially. These emerging services place higher demands on peak throughput and area efficiency for codecs. Peak rates are expected to reach terabits per second (Tbps), while decoder power consumption must be further reduced. 5G's LDPC and polar codes may not be able to fully meet these stringent requirements.

[0004] Therefore, how to perform encoding in the next generation communication system is a problem that those skilled in the art are currently studying. Summary of the Invention

[0005] The embodiments of the present application provide a coding method and device that can not only be applied to longer code lengths, but also improve the parallelism of encoding and decoding, while also being effectively compatible with coding devices with low parallelism, thus having better compatibility.

[0006] In a first aspect, an embodiment of the present application provides an encoding method, which is applied to an encoding device. The encoding device can be applied to a terminal side, such as a terminal or an encoding module in a terminal, or a circuit or chip in the terminal responsible for the encoding function (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system-in-package (SIP) chip containing a modem core, etc.); or, the encoding device can be applied to a network side, such as a network device or an encoding module in a network device, or a circuit or chip in the network device responsible for the encoding function (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.). The method includes:

[0007] Obtain a first bit sequence; encode the first bit sequence based on a base matrix and an expansion factor to obtain a second bit sequence, wherein the base matrix includes at least one first sub-matrix, and the first sub-matrix is ​​composed of n 2 elements, where n is an integer greater than or equal to 2; and outputting the second bit sequence.

[0008] In the embodiment of the present application, the first sub-matrix may correspond to a Z*Z sub-block after the base matrix is ​​expanded, where Z is the expansion factor of the base matrix. 2 An orthogonal matrix composed of elements (i.e., the first submatrix), or a Z*Z sub-block after the base matrix is ​​expanded can be split into n 2 Since the orthogonal matrices are independent of each other, the parallelism of encoding and decoding can be effectively improved. At the same time, it is also compatible with hardware with low parallelism (for example, the parallelism can be reduced from Z to a), and the compatibility is better.

[0009] Assuming that at least two of the n elements (non-1 elements) in the first submatrix are in the same row or column, this will cause an address conflict when the encoding device or decoding device reads the bits to be encoded or writes back the encoded bits, requiring additional waiting delay, resulting in a low degree of parallelism in encoding and decoding. However, in the embodiment of the present application, the first submatrix is ​​an orthogonal matrix, and the rows and columns of the n elements (non-1 elements) in the first submatrix are different from each other, thereby avoiding the problem of address conflicts and improving the efficiency of encoding and decoding.

[0010] In a second aspect, an embodiment of the present application provides an encoding method, which is applied to an encoding device, and the encoding device is applied to a terminal side, such as a terminal or an encoding module in a terminal, or a circuit or chip responsible for the encoding function in the terminal (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system-level package (SIP) chip containing a modem core, etc.); Alternatively, the encoding device can be applied to a network side, such as a network device or an encoding module in a network device, or a circuit or chip responsible for the encoding function in a network device (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.), the method comprising:

[0011] Obtain a first bit sequence; encode the first bit sequence based on an offset value matrix and an expansion factor to obtain a second bit sequence, wherein the offset value matrix includes a first element, the first element corresponds to a first submatrix, and the first submatrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2; and outputting the second bit sequence.

[0012] In an embodiment of the present application, the first element in the offset value matrix may correspond to a first submatrix, that is, the first element may correspond to a Z*Z sub-block after the base matrix is ​​expanded, where Z is the expansion factor of the base matrix. Since the orthogonal matrices are independent of each other, the parallelism of the encoding and decoding can be effectively improved, and the encoding device or decoding device with low parallelism can be compatible, with better compatibility. At the same time, since the first submatrix is ​​an orthogonal matrix, the rows and columns of the n elements (non-1 elements) in the first submatrix are different from each other, so the problem of address conflict can be effectively avoided during the encoding and decoding process, the waiting delay when reading bits is reduced, and the coding efficiency is improved.

[0013] With reference to the second aspect, in a possible implementation, encoding the first bit sequence based on the offset value matrix and the expansion factor includes:

[0014] A base matrix is ​​determined based on a first submatrix corresponding to the first element in the offset value matrix; and the first bit sequence is encoded based on the base matrix and the expansion factor.

[0015] In a specific implementation, the encoding device may utilize the relationship between the first element and the first submatrix, combined with the offset value matrix and the expansion factor, to directly encode the first bit sequence. Alternatively, the encoding device may utilize the relationship between the first element and the first submatrix to determine a base matrix, and utilize the base matrix and the expansion factor to encode the first bit sequence. This application does not limit the specific implementation of the encoding.

[0016] With reference to the second aspect, in a possible implementation manner, encoding the first bit sequence based on the offset value matrix and the expansion factor includes:

[0017] The first bit sequence is encoded based on the offset value matrix, the identification matrix and the expansion factor, the dimension of the identification matrix is ​​the same as the dimension of the offset value matrix, the identification matrix includes a second element, the position of the second element in the identification matrix is ​​the same as the position of the first element in the offset value matrix, and the second element is used to indicate the style of the first sub-matrix.

[0018] The style of the above-mentioned first submatrix can represent the rows and columns where the n elements (non-1 elements) in the first submatrix are located. The dimension can represent the size of the matrix, or the number of rows and columns of the matrix. In an embodiment of the present application, the elements in the identification matrix can be used to indicate the style of the first submatrix, or the elements in the identification matrix can be used to indicate the style of the first submatrix determined based on the elements in the offset value matrix. Coding can be effectively implemented by the identification matrix and the offset value matrix, and storage space can be effectively saved relative to the storage base matrix by storing the identification matrix and the offset value matrix.

[0019] In combination with the first aspect or the second aspect, in a possible implementation manner, the method further includes: determining the expansion factor, where the value of the expansion factor is greater than a threshold.

[0020] As an example, the expansion factor can be the expansion factor of the base matrix, which can be represented by Z. The threshold can be equal to or greater than 384. This expands the value of Z, not only making it applicable to larger code lengths, but also improving decoding parallelism and encoding throughput. Furthermore, since the embodiments of the present application can split a Z*Z sub-block in the base matrix into n a×a orthogonal matrices, it is also compatible with devices with low parallelism and is compatible with existing parallelism, thus achieving better compatibility.

[0021] As another example, the expansion factor may be the expansion factor of the first submatrix, which may be represented by a. The threshold may be equal to or greater than 384 / n. When 384 / n is not an integer, the threshold may be determined by rounding, such as by rounding up or rounding down.

[0022] In this application, "a" and "a" have the same meaning and can be replaced with each other.

[0023] In a third aspect, an embodiment of the present application provides a decoding method, which is applied to a decoding device. The decoding device can be applied to a terminal side, such as a terminal or a decoding module in a terminal, or a circuit or chip in the terminal responsible for the decoding function (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system-in-package (SIP) chip containing a modem core, etc.); or, the decoding device can be applied to a network side, such as a network device or a decoding module in a network device, or a circuit or chip in the network device responsible for the decoding function (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.). The method includes:

[0024] Obtain a sequence to be decoded; decode the sequence to be decoded based on a base matrix and an expansion factor to obtain a first bit sequence, wherein the base matrix includes at least one first sub-matrix, and the first sub-matrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2.

[0025] In a fourth aspect, an embodiment of the present application provides a decoding method, which is applied to a decoding device. The decoding device can be applied to the terminal side, such as a terminal or a decoding module in the terminal, or a circuit or chip in the terminal responsible for the decoding function (such as a modem chip, also known as a baseband chip, or a system on chip (SoC) chip or system-level package (SIP) chip containing a modem core, etc.); Alternatively, the decoding device can be applied to the network side, such as a network device or a decoding module in a network device, or a circuit or chip in the network device responsible for the decoding function (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.). The method includes:

[0026] Obtain a sequence to be decoded; decode the sequence to be decoded based on an offset value matrix and an expansion factor to obtain a first bit sequence, wherein the offset value matrix includes a first element, the first element corresponds to a first sub-matrix, and the first sub-matrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2.

[0027] With reference to the second aspect, in a possible implementation, decoding the to-be-decoded sequence based on the offset value matrix and the extension factor includes:

[0028] A base matrix is ​​determined based on a first submatrix corresponding to the first element in the offset value matrix; and the sequence to be decoded is decoded based on the base matrix and the extension factor.

[0029] With reference to the fourth aspect, in a possible implementation manner, decoding the to-be-decoded sequence based on the offset value matrix and the extension factor includes:

[0030] The sequence to be decoded is decoded based on the offset value matrix, the identification matrix, and the expansion factor, where the dimension of the identification matrix is ​​the same as the dimension of the offset value matrix, the identification matrix includes a second element, the position of the second element in the identification matrix is ​​the same as the position of the first element in the offset value matrix, and the second element is used to indicate the style of the first submatrix.

[0031] The pattern of the first submatrix may indicate the rows or columns in which the n elements (non-1 elements) in the first submatrix are located. The dimension may indicate the size of the matrix, or the number of rows and columns in the matrix.

[0032] In combination with the third aspect or the fourth aspect, in a possible implementation manner, the method further includes: determining the expansion factor, where the value of the expansion factor is greater than a threshold.

[0033] In combination with the first to fourth aspects, in a possible implementation, Z=n*a.

[0034] In combination with the first to fourth aspects, in a possible implementation manner, different first sub-matrices have the same pattern; or, there are at least two first sub-matrices with different patterns.

[0035] In combination with the first to fourth aspects, in a possible implementation, when n=2, the first submatrix P satisfies the following relationship:

[0036]

[0037] or,

[0038]

[0039] Among them, element -1 represents an all-zero matrix of a×a, element P1 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P1 times, and element P2 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P2 times.

[0040] In the embodiment of the present application, a cyclic shift of the a×a unit matrix P1 times may indicate that each element in the a×a unit matrix is ​​cyclically shifted P1 times (or P1 bits). Similarly, a cyclic shift of the a×a unit matrix P2 times may indicate that each element in the a×a unit matrix is ​​cyclically shifted P2 times (or P2 bits).

[0041] In combination with the first to fourth aspects, in a possible implementation, P1=P2.

[0042] In the embodiment of the present application, when P1=P2, the storage capacity of the base matrix or the storage capacity of the offset value matrix stored in the encoding device or the decoding device can be reduced, saving storage space.

[0043] In combination with the first to fourth aspects, in a possible implementation, when n=3, the first submatrix P satisfies the following relationship:

[0044]

[0045] or,

[0046]

[0047] or,

[0048]

[0049] or,

[0050]

[0051] or,

[0052]

[0053] or,

[0054]

[0055] Among them, element -1 represents an all-zero matrix of a×a, element P1 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P1 times, element P2 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P2 times, and element P3 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P3 times.

[0056] In combination with the first to fourth aspects, in a possible implementation, P1=P2=P3.

[0057] In combination with the first to fourth aspects, in a possible implementation manner, the first submatrix is ​​included in a matrix corresponding to information bits in a core matrix of a base matrix, or is included in a matrix corresponding to check bits in a core matrix of a base matrix.

[0058] In combination with the first to fourth aspects, in a possible implementation manner, the first element is included in a matrix corresponding to information bits in the core matrix, or is included in a matrix corresponding to check bits in the core matrix.

[0059] In combination with the first to fourth aspects, in a possible implementation manner, the first submatrix is ​​included in an extended matrix; or the first element is included in an extended matrix.

[0060] In an embodiment of the present application, by adopting the form of the first sub-matrix shown above, a larger expansion factor Z can be supported, such as Z can be greater than 384, thereby effectively improving the parallelism of encoding and decoding, while also being compatible with encoding devices or decoding devices with low parallelism, and having better compatibility.

[0061] In a fifth aspect, an embodiment of the present application provides an encoding device for executing the method in any one of the first and second aspects or any possible implementation. The encoding device includes a module having the function of executing the method in any one of the first and second aspects or any possible implementation.

[0062] In a sixth aspect, embodiments of the present application provide a decoding device for executing the method of any one of the third to fourth aspects or any possible implementation thereof. The decoding device includes a module for executing the method of any one of the third to fourth aspects or any possible implementation thereof.

[0063] The modules in the fifth aspect or the sixth aspect may also be replaced by units or means, etc. The aforementioned modules may be implemented by software, or by hardware, or by a combination of software and hardware.

[0064] In a seventh aspect, embodiments of the present application provide an encoding device, comprising a processing circuit configured to execute the method described in any one of the first and second aspects, or any possible implementation thereof. The processing circuit is configured to execute a program stored in a memory, and when the program is executed, the method described in any one of the first and second aspects, or any possible implementation thereof, is executed.

[0065] In a possible implementation, the memory is located outside the encoding device.

[0066] In a possible implementation, the memory is located within the encoding device.

[0067] In the embodiment of the present application, the processing circuit and the memory may also be integrated into one device, that is, the processing circuit and the memory may also be integrated together. For example, the encoding device may be a chip responsible for encoding functions, such as a baseband chip or a SoC chip or SIP chip including a modem module.

[0068] In a possible implementation, the encoding device further includes a transceiver circuit, which is used to receive information (or input information) or send information (or output information). Exemplarily, the encoding device can be a terminal device or a network device.

[0069] In an eighth aspect, embodiments of the present application provide a decoding device, comprising a processing circuit configured to execute the method described in any one of the third to fourth aspects or any possible implementation thereof. The processing circuit is configured to execute a program stored in a memory. When the program is executed, the method described in any one of the third to fourth aspects or any possible implementation thereof is executed.

[0070] In a possible implementation, the memory is located outside the decoding device.

[0071] In a possible implementation, the memory is located within the decoding device.

[0072] In the embodiment of the present application, the processing circuit and the memory may also be integrated into one device, that is, the processing circuit and the memory may also be integrated together. For example, the decoding device may be a chip responsible for decoding functions, such as a baseband chip or a SoC chip or SIP chip including a modem module.

[0073] In a possible implementation, the decoding device further includes a transceiver circuit, which is used to receive information (or input information) or send information (or output information). Exemplarily, the decoding device can be a terminal device or a network device.

[0074] In the ninth aspect, an embodiment of the present application provides an encoding device, which includes a processing circuit and a transceiver circuit. The processing circuit can be a logic circuit, and the transceiver circuit can be an interface circuit, and the logic circuit is coupled to the interface; the interface circuit is used to input and / or output information, and the logic circuit is used to execute the method in any aspect of the first aspect to the second aspect or any possible implementation of any aspect of the first aspect to the second aspect.

[0075] In a tenth aspect, an embodiment of the present application provides a decoding device, which includes a processing circuit and a transceiver circuit. The processing circuit may be a logic circuit, and the transceiver circuit may be an interface circuit, and the logic circuit is coupled to the interface; the interface circuit is used to input and / or output information, and the logic circuit is used to execute the method in any aspect of the third to fourth aspects or any possible implementation of any aspect of the third to fourth aspects.

[0076] In the eleventh aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When the computer-readable storage medium is run on a computer, the method shown in any one of the above-mentioned first to fourth aspects or any possible implementation method is executed.

[0077] In a twelfth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer, enables the method shown in any one of the above-mentioned first to fourth aspects or any possible implementation to be executed.

[0078] The computer shown in the eleventh aspect or the twelfth aspect may include but is not limited to a terminal device or a network device, etc.

[0079] In a thirteenth aspect, an embodiment of the present application provides a communication system, comprising an encoding device and a decoding device, wherein the encoding device may be the device provided in the fifth, seventh, and ninth aspects, and the decoding device may be the device provided in the sixth, eighth, and tenth aspects. The encoding device may be used to execute the method described in the first aspect or any possible implementation of the first aspect, and the decoding device may be used to execute the method described in the third aspect or any possible implementation of the third aspect; or, the encoding device may be used to execute the method described in the second aspect or any possible implementation of the second aspect, and the decoding device may be used to execute the method described in the fourth aspect or any possible implementation of the fourth aspect.

[0080] In a fourteenth aspect, an embodiment of the present application provides a base matrix for coding, wherein the base matrix includes at least one first sub-matrix, and the first sub-matrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2.

[0081] The check matrix obtained by expanding the above-mentioned base matrix also falls within the protection scope of this application.

[0082] In a fifteenth aspect, an embodiment of the present application provides an offset value matrix for encoding and decoding, wherein the offset value matrix includes a first element, the first element corresponds to a first sub-matrix, and the first sub-matrix is ​​composed of n 2An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2.

[0083] In a possible implementation, the first element is used to determine a first sub-matrix, where the first sub-matrix is ​​a matrix in a base matrix.

[0084] Other implementation methods or beneficial effects of the above-mentioned fourteenth or fifteenth aspect can be referred to the first to fourth aspects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 is a schematic diagram of a basegraph (BG) provided in an embodiment of the present application;

[0086] Figure 2 This is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application;

[0087] Figure 3 This is a schematic diagram of the architecture of the communication system provided in an embodiment of the present application;

[0088] Figure 4a is a schematic diagram of a Tanner diagram provided in an embodiment of the present application;

[0089] Figure 4b This is a schematic diagram of a unilateral structure provided in an embodiment of the present application;

[0090] Figure 4c This is a schematic diagram of a bilateral structure provided by an embodiment of the present application;

[0091] Figure 5 This is a flow chart of a communication method provided in an embodiment of the present application;

[0092] Figure 6 is a schematic diagram of a cyclic shift matrix provided in an embodiment of the present application;

[0093] Figure 7a This is a schematic diagram of an orthogonal sub-block provided in an embodiment of the present application;

[0094] Figure 7b This is a schematic diagram of an orthogonal sub-block provided in an embodiment of the present application;

[0095] Figure 8 Schematic diagram of the structure of a base matrix of an LDPC code provided in an embodiment of the present application;

[0096] Figure 9a and Figure 9b Schematic diagram of the structure of a matrix A in a core matrix provided in an embodiment of the present application;

[0097] Figure 10Schematic diagram of the structure of a matrix B in a core matrix provided in an embodiment of the present application;

[0098] Figure 11a (1) and Figure 11b (1) is a schematic structural diagram of a core array provided in an embodiment of the present application;

[0099] Figure 11a (2) and Figure 11b (2) is a schematic structural diagram of another core array provided in an embodiment of the present application;

[0100] Figure 12a This is a schematic diagram of the structure of a base matrix provided in an embodiment of the present application;

[0101] Figure 12b is a schematic structural diagram of another basis matrix provided in an embodiment of the present application;

[0102] Figure 13 This is a schematic diagram of an LDPC code encoding process provided in an embodiment of the present application;

[0103] Figure 14 (2) is a schematic diagram of an offset value matrix provided in an embodiment of the present application;

[0104] Figure 14 (1) and Figure 15 is a schematic diagram of an identification matrix provided in an embodiment of the present application;

[0105] Figure 16 This is a schematic structural diagram of a device provided in an embodiment of the present application;

[0106] Figure 17 This is a schematic structural diagram of a device provided in an embodiment of the present application;

[0107] Figure 18 It is a structural diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0108] To facilitate understanding of the technical solution of the present application, the present application will be further described below with reference to the accompanying drawings.

[0109] The terms "first" and "second" in the specification, claims, and drawings of this application are used only to distinguish different objects and are not used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device.

[0110] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It will be understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0111] In this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three and more than three, and "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. "Or" means that two relationships can exist, such as only A exists, only B exists; when A and B are not mutually exclusive, it can also mean that three relationships exist, such as only A exists, only B exists, and A and B exist at the same time. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0112] In this application, "sending" and "receiving" indicate the direction of signal transmission. For example, "sending information to XX" can be understood as the destination of the information is XX, which can include direct sending through the air interface, and also include indirect sending through the air interface by other units or modules. "Receiving information from YY" can be understood as the source of the information is YY, which can include direct receiving from YY through the air interface, and also include indirect receiving from YY through the air interface from other units or modules. "Sending" can also be understood as the "output" of the chip interface, and "receiving" can also be understood as the "input" of the chip interface. In other words, sending and receiving can be carried out between devices, for example, between network devices and terminal devices, or can be carried out within a device, for example, sending or receiving between components, modules, chips, software modules or hardware modules within the device through a bus, trace or interface.

[0113] The fifth generation (5 th -generation, 5G) uses quasi cyclic (QC) low density parity check (QC-LDPC) code. Figure 1 It is a schematic diagram of a basic sample graph (basegraph, BG) provided in an embodiment of the present application. BG is the core of the entire LDPC code design. BG is the prerequisite for the design of the LDPC code parity-check matrix (PCM) or base matrix (or called the basic matrix), and also determines the macro characteristics and overall performance of the LDPC code. In 5G, in order to adapt to the needs of different communication scenarios, LDPC codes can flexibly support different code lengths and code rates. At the same time, in order to improve communication reliability, LDPC codes can also support the characteristics of incremental redundancy (IR) hybrid automatic repeat request (IR hybrid automatic repeat request, IR-HARQ). Figure 1 H in core H represents the core matrix, or core matrix. The core matrix may include information bits or systematic bits (systematic bits), and check bits or parity bits (parity bits). rex Represents the extended matrix, or the extended matrix. The number of columns of the extended matrix is ​​the same as the number of columns of the core matrix. zero represents an all-zero matrix, H diag Represents the unit matrix. Figure 1 The matrix shown can also be called a raptor-like LDPC code. core Perform the lower right diagonal H diagThe matrix codeword is expanded to flexibly support IR-HARQ and rate matching. For the description of Lapter-like, please refer to the introduction of term 2 below, which will not be described in detail here.

[0114] The design of the LDPC base matrix needs to consider decoding performance and throughput. Generally speaking, for the same code length, a base matrix with a smaller dimension can support greater decoding parallelism (i.e., a larger value of the expansion factor Z) than a base matrix with a larger dimension, thereby improving the throughput of the decoding device and meeting the peak rate requirements. However, compared to a base matrix with a larger dimension, a base matrix with a smaller dimension has a limited number of elements, which limits the design freedom and makes performance improvement and optimization more difficult. Conversely, a base matrix with a larger dimension has more elements, greater design freedom, and greater potential for performance optimization, but reduces decoding parallelism. Under certain hardware complexity conditions, the throughput of a base matrix with a larger dimension is not as good as that of a base matrix with a smaller dimension, making it more challenging to meet the peak rate requirements. The above-mentioned base matrix dimensionality is relative, and this application does not limit the specific dimensions of the base matrix with a smaller dimension or the specific dimensions of the base matrix with a larger dimension. In this application, dimension can refer to the size of the matrix, or the number of rows and columns of the matrix.

[0115] Although the 5G LDPC matrix has achieved several times the decoding throughput improvement compared to third- or fourth-generation concatenated codes (such as turbo convolutional coding), how to make the LDPC matrix have higher peak throughput and support higher throughput and parallelism for the next generation (such as 6G) remains an urgent issue.

[0116] In view of this, the present application provides a coding method and apparatus, and provides a low-density parity check (LDPC) code structure. The LDPC code structure can support highly parallel and high-throughput encoding and decoding, while being compatible with hardware with low parallelism and various hardware, with better compatibility. The LDPC code can support a larger expansion factor and a longer code length. Furthermore, the LDPC code has a Laputa-like structure, simple encoding, and more flexible code length and code rate support.

[0117] The LDPC codes, LDPC encoding, and other LDPC-related names shown in this application are examples only. Other names may be adopted as standards evolve, and this application does not limit them. Any code structure that satisfies the structure of the base matrix, offset matrix, or identity matrix shown below falls within the scope of protection of this application.

[0118] The following introduces the communication system involved in the embodiments of the present application.

[0119] The method provided in the embodiment of the present application can be applied to various communication systems, for example, it can be an Internet of Things (IoT) system, a narrowband internet of things (NB-IoT) system, a long term evolution (LTE) system, or a fifth-generation (5G) communication system, a new radio (NR) system, and new communication systems that will emerge in the future development of communications. Among them, the IoT network can include, for example, but is not limited to the Internet of Vehicles. The communication methods in the Internet of Vehicles system can be collectively referred to as vehicle-to-everything (V2X, X can represent anything). For example, V2X may include: vehicle-to-vehicle (V2V) communication, vehicle-to-infrastructure (V2I) communication, vehicle-to-pedestrian (V2P) communication or vehicle-to-network (V2N) communication, etc. The following Figure 2 In the embodiment, the terminal device (such as terminal device 3) and the terminal device (such as terminal device 4) can communicate via device-to-device (D2D) technology, machine-to-machine (M2M) technology, or V2X technology. The method provided in the embodiment of the present application can also be applied to non-terrestrial network (NTN) communication (also referred to as non-terrestrial network communication).

[0120] The method provided in the embodiments of the present application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi, etc. The method provided in the embodiments of the present application can be applied to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series protocols, such as 802.11be protocol, 802.11bn protocol, or the next generation protocol of 802.11bn protocol, etc., which are not listed one by one.

[0121] The method provided in the embodiment of the present application can be applied between two entities in a communication system, such as one of the two entities can send information to the other entity, or receive information sent by the other entity. In a wireless communication system, including communication devices, wireless communication can be carried out using air interface resources between communication devices. Air interface resources may include at least one of time domain resources, frequency domain resources, code resources and space resources, which is not limited in this application. For example, the aforementioned two entities may include a network device and a terminal device, or may include a chip that can be placed in a network device, and a chip that can be placed in a terminal device, etc. Of course, as the standard progresses, other types of entities may appear in the future, which is not limited in this embodiment of the present application.

[0122] Figure 2 This is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application. Figure 2 As shown, the communication system may include at least one network device and at least one terminal device, such as Figure 2 The terminal devices 1 to 4 in the figure can communicate with the network device via an air interface Uu link or an NTN link. For example, the terminal device 3 and the terminal device 4 can communicate via a sidelink such as D2D. Figure 2 The form of the terminal device shown is only an example. In a specific implementation, the terminal device may also include an on-board device or an on-board terminal in the Internet of Vehicles. The embodiments of the present application do not limit the specific form of the terminal device when applied to the Internet of Vehicles or the Internet.

[0123] Figure 3 This is a schematic diagram of the architecture of the communication system provided in the embodiment of the present application. Figure 3 As shown, the scenarios of the communication system may include at least one of the following: a point-to-point single connection between a network device and a terminal device, a point-to-point dual connectivity (DC) between a network device and a terminal device, a multi-hop single connection between a network device and a terminal device, or a multi-hop dual connection between a network device and a terminal device.

[0124] Figure 2 A network device and multiple terminal devices are shown as an example. Figure 3 In a specific implementation, the communication system may further include a greater number of network devices, and each network device may include a greater or lesser number of terminal devices within its coverage area, which is not limited in this embodiment of the present application. Figure 2 and Figure 3The architecture shown is only an example and does not limit the network architecture applicable to this application. As long as any network-side device in the cellular network communicates or perceives other devices, it is a network architecture that can be used in this application.

[0125] The following is a detailed description of terminal devices and network devices.

[0126] A terminal device is a device with wireless transceiver functions. The terminal device can communicate with an access network device (or may also be referred to as an access device or a network device shown below) in a radio access network (RAN). The terminal device may also be referred to as user equipment (UE), access terminal, terminal, subscriber unit, user station, mobile station, remote station, remote terminal, mobile device, user terminal, user agent or user device, etc. In one possible implementation, the terminal device may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; or it may be deployed on the water, including a ship; or it may be deployed in the air, such as on an airplane, a balloon or a satellite, etc. In another possible implementation, the terminal device may be a handheld device with wireless communication functions, a vehicle-mounted device, a wearable device, a sensor, a terminal in the Internet of Things, a terminal in the Internet of Vehicles, a drone, a 5G network or any form of terminal device in a future network, etc., and the embodiments of the present application are not limited to this. In another possible implementation, the terminal device may also be a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in unmanned driving, a wireless terminal in telemedicine, a wireless terminal in a smart grid, a wireless terminal in a smart city, or a wireless terminal in a smart home, etc.

[0127] In the embodiments of the present application, the device for realizing the function of the terminal device may be a terminal device; or it may be a device capable of supporting the terminal device to realize the function, such as a chip system. The device may be installed in the terminal device or used in combination with the terminal device. In the embodiments of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices. For ease of description, when referring to some examples below, the technical solution provided in the embodiments of the present application will be described by taking the device for realizing the function of the terminal device as a UE as an example.

[0128] A network device may be a device deployed in a wireless access network to provide wireless communication services to terminal devices. The network device may also be referred to as an access network device, access device, or RAN device. For example, the network device may be a next-generation node B (gNB), a next-generation evolved node B (ng-eNB), or a network device in 6G communications. The network device may be any device with wireless transceiver capabilities, including but not limited to the base stations shown above (including base stations deployed on satellites). The network device may also be a device with base station functions in 6G. As an example, the network device may be an access node, wireless relay node, or wireless backhaul node in a wireless local area network (Wi-Fi) system. As another example, the network device may be a wireless controller in a cloud radio access network (CRAN) scenario. As yet another example, the network device may be a wearable device or an in-vehicle device capable of providing wireless communication services. As yet another example, the network device may be a small cell, a transmission reception point (TRP) (or also referred to as a transmission point), etc. In systems with different wireless access technologies, the names of devices with network device functions may be different, and the embodiments of the present application will not list them one by one.

[0129] Network devices can be fixed or mobile. For example, a helicopter or drone can be configured to act as a mobile network device, and one or more cells can move based on the location of the mobile network device. In other examples, a helicopter or drone can be configured to act as a device that communicates with another network device.

[0130] In some deployments of network devices, the network device may include a centralized unit (CU) and a distributed unit (DU). For example, some protocol layer functions of the network device are centrally controlled by the CU, while some or all of the remaining protocol layer functions are distributed in the DU, which is centrally controlled by the CU. In other deployments of network devices, the CU may be divided into a CU-control plane (CP) and a CU-user plane (UP). In still other deployments of network devices, the network device may be an open radio access network (ORAN) architecture. When the network device is an ORAN architecture, the network device may be a functional entity or module in the ORAN. For example, the network device may be a combination of one or more of a CU, a DU, or a RU. In an ORAN system, a CU may also be referred to as an open (O)-CU, a DU may also be referred to as an O-DU, a CU-CP may also be referred to as an O-CU-CP, and a CU-UP may also be referred to as an O-CU-UP. The network device deployment methods listed here are only examples. As standard technologies evolve, network devices may have other deployment forms, and the embodiments of the present application are not limited thereto.

[0131] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, and different RAN nodes implement part of the functions of the access network respectively. For example, the RAN node can be a CU, DU, CU-CP, CU-UP, or RU. The CU and DU can be set up separately, or they can be included in the same network element, such as an indoor baseband processing unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0132] The RAN node may support one or more types of fronthaul interfaces, with different fronthaul interfaces corresponding to DUs and RUs with different functions. If the fronthaul interface between the DU and the RU is a common public radio interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and the RU is another type of interface, relative to the CPRI, some of the downlink and / or uplink baseband functions, such as precoding, digital beamforming (BF), or one or more of inverse fast Fourier transform (IFFT) / cyclic prefix (CP) for downlink, are moved from the DU to the RU for implementation; and for uplink, one or more of digital beamforming (BF), or fast Fourier transform (FFT) / cyclic prefix (CP) removal, are moved from the DU to the RU for implementation. In one possible implementation, the interface may be an enhanced common public radio interface (eCPRI). In the eCPRI architecture, the division between the DU and RU is different, corresponding to different types (category, Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, and F.

[0133] Taking eCPRI Cat A as an example, for downlink transmission, based on layer mapping, the DU is configured to implement layer mapping and one or more of the preceding functions (i.e., coding, rate matching, scrambling, modulation, and layer mapping), while other functions after layer mapping (e.g., resource element (RE) mapping, digital beamforming (BF), or one or more of IFFT / CP addition) are moved to the RU for implementation. For uplink transmission, based on RE demapping, the DU is configured to implement demapping and one or more of the preceding functions (i.e., decoding, derate matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and one or more of RE demapping), while other functions after demapping (e.g., one or more of digital BF or FFT / CP removal) are moved to the RU for implementation. It is understood that for a functional description of the DU and RU corresponding to various types of eCPRI, please refer to the eCPRI protocol and will not be detailed here.

[0134] In one possible design, the processing unit for implementing baseband functions in the BBU is called a baseband high layer (BBH) unit, and the processing unit for implementing baseband functions in the RRU / AAU / RRH is called a baseband low layer (BBL) unit.

[0135] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, CU may also be called O-CU (Open CU), DU may also be called O-DU, CU-CP may also be called O-CU-CP, CU-UP may also be called O-CU-UP, and RU may also be called O-RU. Any unit of CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0136] The network device and / or terminal device can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it can also be deployed on the water surface; it can also be deployed on aircraft, balloons and satellites in the air. The embodiments of this application do not limit the scenarios in which the network device and the terminal device are located. In addition, the terminal device and the network device can be hardware devices, or they can be software functions running on dedicated hardware, software functions running on general-purpose hardware, such as virtualization functions instantiated on a platform (e.g., a cloud platform), or entities including dedicated or general-purpose hardware devices and software functions. This application does not limit the specific forms of the terminal device and the network device.

[0137] In the embodiments of the present application, the apparatus for implementing the functions of a network device may be a network device; it may also be a device capable of supporting the network device in implementing the functions, such as a chip system. The apparatus may be installed in the network device or used in conjunction with the network device. For ease of description, when referring to some specific examples below, the technical solutions provided in the embodiments of the present application are described using the example of a base station as the apparatus for implementing the functions of a network device.

[0138] The technical solutions provided in the embodiments of this application can be applied to channel coding / decoding, modulation, and demodulation between communication devices. Channel coding / decoding between communication devices can include: channel coding / decoding between a network device and a terminal device, channel coding / decoding between network devices, or channel coding / decoding between terminal devices.

[0139] The following will describe the method provided by the embodiment of the present application using an encoding device and a decoding device as examples. Alternatively, the encoding device may also be referred to as a transmitter, which may be a device for transmitting a modulated signal, and the decoding device may also be referred to as a receiver, which may be a device for receiving the aforementioned signal. The embodiments of the present application do not limit the specific names of the encoding device and the decoding device. As an example, the encoding device may be a terminal device or a chip or functional module of a terminal device, etc., and the decoding device may be a network device or a chip or functional module of a network device, etc. As another example, the encoding device may be a network device or a chip or functional module of a network device, and the decoding device may be a terminal device or a chip or functional module of a terminal device. As yet another example, the encoding device and the decoding device may be different terminal devices, etc. The specific forms of the encoding device and the decoding device are not listed here.

[0140] The following introduces the terms involved in this application.

[0141] 1. LDPC Code

[0142] LDPC code is a linear block code whose check matrix has a sparse property. The proportion of 1 elements in the check matrix is ​​less than the threshold, so it is also called low-density parity-check code. For an LDPC code with K information bits and code length N, the dimension of its check matrix H is (NK)×N. The corresponding codeword c can be defined by the check matrix H as

[0143] c={c|H·c T =0,c∈{0,1} N}

[0144] Among them, {0,1} N Indicates a sequence of length N, where the element is 0 or 1. T represents the transpose of c, and H represents a matrix with (NK) rows and N columns, whose elements are 0 or 1. The above-mentioned check matrix H can also be understood as a matrix expanded using the expansion factor.

[0145] In the check matrix H, each row corresponds to a check equation of the LDPC code, and the NK check equations correspond to the NK check nodes of the LDPC code. Each column corresponds to a code element of the LDPC code, and the N code elements correspond to the N variable nodes of the LDPC code. The non-zero elements h in the check matrix H are i,j Indicates that the i-th check node is connected to the j-th variable node. The number of non-zero elements in each row of the check matrix is ​​the degree of the check node (or row weight), and the number of non-zero elements in each column is the degree of the variable node (or column weight). If the degrees of all check nodes are equal, the degrees of all variable nodes are also equal, and the LDPC code corresponding to the matrix is ​​a regular code; otherwise, it is an irregular code. A regular LDPC code check matrix H with a code length of 10 and a code rate of 1 / 2 is shown below, where v0, v1, ..., v9 represent variable nodes and c0, c1, ..., c4 represent check nodes:

[0146]

[0147] LDPC codes can be represented by graph models. Commonly used graph models include Tanner graphs, factor graphs, and tree graphs. Among them, Tanner graphs are relatively concise and intuitive. Figure 4a is a schematic diagram of a Tanner graph provided in an embodiment of the present application. The Tanner graph of the above-mentioned check matrix H is represented as follows Figure 4a As shown in , the degree of a node can be defined as the number of edges connected to it.

[0148] For the sake of brevity, this application uses H to represent the check matrix, or uses K to represent the number of information bits before encoding, and uses N to represent the number of bits after encoding (that is, an LDPC code or sequence with a code length of N), etc., but the letter form shown in this application should not be understood as a limitation on the parameters.

[0149] Generally speaking, the check matrix H can also be equivalently represented by another simplified matrix, such as a base matrix. For example, the check matrix H is as follows:

[0150]

[0151] The above check matrix can also be called the check matrix of QC-LDPC. When Z=3, the above check matrix can be simplified to the following basis matrix H base :

[0152]

[0153] Among them, the basis matrix H base Each element in corresponds to a Z×Z square matrix. When the element is -1, it indicates that the corresponding position is a zero matrix. When the value of the element is greater than or equal to 0, it indicates that the corresponding position is a cyclic shift matrix of the unit matrix. If the value of the element is t, and t is greater than or equal to 0, then t indicates the cyclic shift matrix after the unit matrix is ​​cyclically shifted t times. In other words, the element -1 can represent a zero matrix, or can be replaced by a zero matrix, or corresponds to an all-zero matrix. The element 0 can represent a unit matrix, or can be replaced by a unit matrix, or corresponds to a unit matrix. Elements greater than 0 (such as t) can represent a cyclic shift matrix of the unit matrix, or can be replaced by a cyclic shift matrix of the unit matrix, or correspond to a cyclic shift matrix of the unit matrix, or a cyclic shift matrix after the unit matrix is ​​cyclically shifted t times. The description here about the elements in the base matrix and the check matrix after the base matrix is ​​expanded also applies to the following text and will not be repeated below.

[0154] In addition, for convenience, the base graph H can be used bg Denotes the basis matrix H base The connection relationship between the check node and the variable node in the base graph can be 0 or 1, 0 means there is no connection relationship, and 1 means there is a connection relationship. base The corresponding base graph H bg for:

[0155]

[0156] 2. Raptor-like LDPC

[0157] Wireless network channel coding requires flexible code rate to meet the needs of HARQ implementation. Generally speaking, the quasi-Laput QC LDPC can easily support the rate matching of LDPC codes and IR-HARQ. For example, the quasi-Laput QC LDPC code has Figure 1 Features shown: Figure 1 The LDPC parity check matrix consists of two matrices: Part 1 (Part-1) and Part 2 (Part-2). Part 1 is a high-rate LDPC matrix, typically with a dual-diagonal (check bits in the core matrix) or lower triangular structure. Part 1 can independently perform encoding and decoding as a high-rate LDPC code and is also called the core matrix. Part 2 can be divided into two parts: the left matrix has the same number of columns as the core matrix, and the right matrix is ​​a unit matrix with a column weight of 1 (column weight refers to the number of non-zero elements in a column after expansion). Part 2 is also called the expanded matrix. Combining Part 2 and Part 1 forms a complete LDPC code.

[0158] 3. Unilateral structure

[0159] Figure 4b This is a schematic diagram of a unilateral structure provided in the embodiment of the present application. Figure 4b As shown, each element in the matrix has an offset value Q. For example, if Q = -1, it means that the element corresponds to the Z*Z all-zero matrix. For another example, if Q = 0, it means that the element corresponds to the Z*Z identity matrix. For another example, if Q > 0, it means that the element corresponds to the matrix after the Z*Z identity matrix is ​​cyclically shifted Q times, such as the matrix after the Z*Z identity matrix is ​​cyclically shifted Q times to the right.

[0160] 4. Bilateral structure

[0161] Figure 4c This is a schematic diagram of a bilateral structure provided by an embodiment of the present application. Figure 4c As shown, each element in the matrix has two or more offset values, such as Q1 and Q2. For example, this element can represent a matrix in which the unit matrix is ​​cyclically shifted Q1 and Q2 times and then superimposed.

[0162] Although the polygonal structured basis matrix has better decoding performance than the unilateral structured basis matrix, the polygonal structure has larger row and column weights, and therefore has higher encoding and decoding complexity. At the same time, the polygonal structure is also not friendly to the existing encoding and decoding hardware with limited parallelism.

[0163] The following describes the method involved in this application.

[0164] Figure 5This is a flow chart of a communication method provided by an embodiment of the present application. The communication method involves an encoding process and a decoding process. The encoding-related process can also be called an encoding method, and the decoding-related process can be called a decoding method. Figure 5 As shown, the method includes:

[0165] 501. The encoding device obtains a first bit sequence.

[0166] The length of the first bit sequence may be K, that is, the first bit sequence may include K bits, where K is a positive integer.

[0167] As an example, the first bit sequence may include cyclic redundancy check (CRC) bits. For example, the first bit sequence may be obtained after the encoding device performs CRC. As another example, the first bit sequence may not include CRC bits. The embodiments of the present application do not limit whether the first bit sequence includes CRC bits.

[0168] Generally speaking, the encoding device can determine the value of K based on the transmission resource, the modulation order and the coding rate. As a possible implementation, the transmission resource is the number N of available resource elements (REs). RE , the coding rate is R, the modulation order (that is, the number of bits carried by each RE) is Q, then K = N RE *Q*R. As another possible implementation, using multiple-input multiple-output (MIMO) technology, the transmission resources can be the number of REs available in multiple layers, N. RE_MIMO , correspondingly, K = N RE_MIMO *Q*R. Exemplary, N RE_MIMO =V*N RE_1 , V is the number of MIMO layers, N RE_1 The value of K can also be determined in other ways, which is not limited in this embodiment of the present application.

[0169] 502. The encoding device encodes the first bit sequence to obtain a second bit sequence.

[0170] For the specific description of step 502, please refer to implementation methods 1 and 2 below, which will not be described in detail here.

[0171] In one possible implementation, Figure 5 The illustrated method may further include:

[0172] The encoding device determines the expansion factor.

[0173] Generally speaking, the encoding device may determine the spreading factor before encoding the first bit sequence.

[0174] As an example, the expansion factor can be represented by Z, which can represent the expansion factor of the base matrix. As another example, the expansion factor can be represented by a, which can represent the expansion factor of the first submatrix. For a description of the first submatrix, please refer to Implementation 1 below and will not be described in detail here.

[0175] Exemplarily, the expansion factor may be based on the length K of the first bit sequence and the number K of columns of information bits in the base matrix. b Alternatively, the expansion factor may be determined based on the length of the first bit sequence and the number of columns of information bits in the offset value matrix. The number of columns of information bits in the base matrix may be equal to n times the number of columns of information bits in the offset value matrix. For example, the expansion factor Z may satisfy K b ×Z≥K. For example, Z can be the minimum value that satisfies the above relationship. For another example, the expansion factor a can satisfy K b ×a×n≥K. That is, Z=n×a. For the description of n, please refer to the following, such as the description of n in the first sub-matrix in Implementation 1.

[0176] In the embodiment of the present application, the value of the expansion factor Z may be greater than a threshold value. For example, the threshold value may be equal to 384. Alternatively, the threshold value may be greater than 384. The embodiment of the present application does not limit the specific value of the threshold value.

[0177] Given the relationship between Z and a, in the embodiments of this application, the description of Z also applies to a. For example, when the expansion factor is a, the threshold value may be equal to or equal to 384 / n. When 384 / n is not an integer, the threshold value may be determined by rounding, such as by rounding up or rounding down. Similarly, the description of Z below, like the description of Table 1 or Table 2, also applies to a.

[0178] The relationship between n and Z is introduced below.

[0179] As an example, the value of n may be determined by the expansion factor Z, or in other words, the value of n corresponds to the value of Z. For example, when Z>384, n≥2. For another example, when Z is less than or equal to 384, n=1.

[0180] For example, the corresponding relationship between the value of n and the value of Z can be expressed in a table, as shown in Table 1. The relationship shown in Table 1 is only an example and should not be understood as limiting the present application.

[0181] Table 1

[0182]

[0183] For another example, the corresponding relationship between the value of n and the value of Z can be shown in Table 2.

[0184] Table 2

[0185]

[0186] The set indices in Table 2 may correspond to different base matrices. These different base matrices may include base matrices with different dimensions, base matrices with the same dimensions but different offset values ​​at the same position, or base matrices with the same dimensions but different first submatrices at the same position. The specific contents of the base matrices, offset matrices, or identification matrices corresponding to the different set indices are not limited.

[0187] There is a one-to-one correspondence between columns 2 and 3 in Table 2. For example, if the set index is 0, when Z = 2, n = 1; if Z = 256, n = 1; and if Z = 512, n = 2. For another example, if the set index is 6, when Z = 416, n = 2; and if Z = 624, n = 3. This list is not repeated here.

[0188] For Table 1 or Table 2, the encoding device can determine a value of Z from multiple fixed values. For example, the encoding device can determine a value of Z based on Table 1 or Table 2, and K and K b The relationship between determines a value of Z from a plurality of fixed values. Table 1 or Table 2 only exemplarily shows n=2 or n=3. In a specific implementation, n may also be equal to 4 or 5, etc., which will not be listed here.

[0189] In combination with Table 1 or Table 2, when Z is greater than 384, the dimension of the first submatrix in the base matrix can be 2*2 or 3*3, etc. The relationship between Z and a is as follows:

[0190]

[0191] In the embodiment of the present application, when the encoding device uses Table 2 to determine the expansion factor, it is not only compatible with the 5G standard, but also adds support for larger Z values. For example, the value of Z is increased from 384 supported by 5G to 1152, so that a longer code length can be applied. It can also be compatible with existing encoding and decoding hardware, reducing implementation complexity.

[0192] For another example, the value of n can vary depending on the range of the value of Z. For example, when the value of Z is in the first range, n = 2; when the value of Z is in the second range, n = 3; and when the value of Z is in the third range, n = 4. For another example, when the value of Z is in range #1, n = 1. The embodiments of this application do not limit the specific values ​​of each range.

[0193] In a specific implementation, the value of the expansion factor Z determined by the coding device in some implementations may be greater than 384, and the value of the expansion factor Z determined in other implementations may be less than or equal to 384. The embodiment of the present application is illustrated by taking Z greater than 384 as an example, that is, when Z is greater than 384, a Z*Z sub-block in the base matrix can be split into n a×a orthogonal matrices. This is compatible with the 5G standard. However, in a specific implementation, when Z is less than 384, the structure of the LDPC code shown in the embodiment of the present application may be adopted, such as splitting a Z*Z sub-block in the base matrix into n a×a orthogonal matrices. Alternatively, when Z is less than 384, the coding method in new radio (NR) may also be adopted. For the coding method adopted in NR, reference may be made to the relevant standards or protocols, which will not be described in detail here.

[0194] For another example, the correspondence between the value of n and the value of Z can be expressed by a function or a set, etc., which will not be listed here.

[0195] As another example, the value of n may be predefined by the protocol or determined by the encoding device, such as n=1, 2, 3, 4, etc.

[0196] As another example, the value of n may be determined by the network device, such as n=1, 2, 3, 4, etc.

[0197] The relationship between n and Z is described in detail here. For other explanations about Z, n, or a, please refer to the following.

[0198] In one possible implementation, Figure 5 The illustrated method may further include:

[0199] As an example, the encoding apparatus includes a network device, and the decoding apparatus includes a terminal device. The encoding apparatus may transmit modulation and coding scheme (MCS) information, and the decoding apparatus may receive the MCS information. As another example, the encoding apparatus includes a terminal device, and the decoding apparatus includes a network device. The decoding apparatus may transmit MCS information, and the encoding apparatus may receive the MCS information. As yet another example, the encoding apparatus may transmit MCS information to the decoding apparatus, and the decoding apparatus may receive the MCS information.

[0200] The above-mentioned MCS information can be used to indicate the coding rate and / or modulation order. Generally speaking, the coding rate can be used to determine the ratio of the number of information bits before encoding to the number of bits after encoding. If the coding rate is represented by R, then R=K / N. The modulation order can be used to determine the number of bits corresponding to a constellation point in the constellation diagram, or the number of bits corresponding to a modulation symbol after modulation. For example, the coding device can determine the coding rate and modulation order by obtaining the MCS information, and determine the value of K in combination with the transmission resources. Furthermore, the coding device can also determine the value of Z (or the value of a), etc. Then, encoding is performed based on the value of Z. For the specific methods of encoding or decoding, please refer to Implementation Methods 1 to 2 below, which will not be described in detail here.

[0201] 503. The encoding device outputs a second bit sequence.

[0202] The length of the second bit sequence may be N, that is, the second bit sequence may include N bits, where N is a positive integer.

[0203] 504. The encoding device sends a signal obtained by processing the second bit sequence.

[0204] Correspondingly, the decoding device receives the signal.

[0205] After the encoding device outputs the second bit sequence, the encoding device may further process the second bit sequence. The processing may include, but is not limited to, rate matching, modulation, multiple-input multiple-output (MIMO) coding (MIMO precoding), subcarrier mapping, or inverse fast Fourier transform (IFFT). The encoding device may then transmit the signal obtained by processing the second bit sequence through a channel. The decoding device receives the signal transmitted through the channel and processes the aforementioned signal (e.g., performs inverse processing corresponding to the aforementioned processing) to obtain a sequence to be decoded.

[0206] 505. The decoding device obtains a sequence to be decoded.

[0207] Exemplarily, the decoding device can obtain the sequence to be decoded through demodulation. Demodulation is the inverse process of modulation, that is, the process of restoring the received signal into a bit sequence. Exemplarily, demodulation methods can include hard decision and soft decision. The output of hard decision demodulation is 0 or 1, and the output of soft decision demodulation is a log-likelihood ratio (LLR). The description of how the decoding device obtains the sequence to be decoded can also be found in step 504 and so on, and will not be described in detail here.

[0208] 506. The decoding device decodes the sequence to be decoded to obtain a first bit sequence.

[0209] Decoding is the inverse process of encoding. Exemplarily, the decoding methods that can be adopted by the decoding device include but are not limited to hard decision decoding methods, soft decision decoding methods or hybrid decoding methods. For example, the decoding methods include minimum sum (MS) decoding, belief propagation decoding, etc. For example, the decoding device can initialize the input sequence to be decoded and perform iterative processing. After the iteration, hard decision detection is performed and the hard decision result is verified. If the decoding result meets the verification equation, the decoding is successful, the iteration is terminated, and the judgment result is output. If the decoding result does not meet the verification equation, the iterative processing is performed again within the maximum number of iterations. If the maximum number of iterations is reached and the verification still fails, the decoding fails. The decoding method shown here is only an example, and the embodiments of the present application do not limit other decoding processes. The description of the base matrix or offset value matrix used by the decoding device during decoding can be found below.

[0210] In the embodiment of the present application, the above steps 501 to 503 can be implemented by an encoding device, such as a chip, a functional module, or a device. For example, the sending step in the above step 504 can be implemented by an encoding device. The above steps 505 and 506 can be implemented by a decoding device, such as a chip, a functional module, or a device. For example, the receiving step in the above step 504 can be implemented by a decoding device. In a specific implementation, Figure 5 The method shown can be divided into an encoding method and a decoding method. Optionally, the encoding method and the decoding method can also be referred to as a communication method.

[0211] In the embodiment of the present application, the basis matrix includes n 2 An orthogonal matrix (ie, the first submatrix) composed of n elements, or the elements in the offset matrix are corresponding to n 2 An orthogonal matrix composed of elements can make a Z*Z sub-block after the base matrix is ​​expanded into n 2 a×a orthogonal matrices. Since the orthogonal matrices are independent of each other, the parallelism of encoding and decoding can be effectively improved, and the encoding device or decoding device with low parallelism is compatible with better compatibility. At the same time, since the first sub-matrix is ​​an orthogonal matrix, the rows and columns of the n elements in the first sub-matrix are different from each other, so the problem of address conflict can be effectively avoided during the encoding process, the waiting delay when reading bits is reduced, and the coding efficiency is improved. Furthermore, Z in the embodiment of the present application can be greater than the threshold (such as 374), which expands the value of Z relative to the 5G standard, thereby improving the parallelism of encoding and decoding and improving the throughput of encoding and decoding.

[0212] The following describes in detail the encoding method provided in the embodiments of the present application.

[0213] In the embodiment of the present application, a specific implementation manner in which the encoding device encodes the first bit sequence may include:

[0214] As a possible implementation manner 1, the encoding device may encode the first bit sequence based on the base matrix and the expansion factor.

[0215] The above expansion factor may be a as shown in the embodiment of the present application, or may be Z as shown in the embodiment of the present application, where Z=n×a.

[0216] In the embodiment of the present application, the base matrix may include a first sub-matrix, which is composed of n 2 The first submatrix is ​​an orthogonal matrix consisting of n elements, where n is an integer greater than or equal to 2. The first submatrix can satisfy at least one of the following: the first submatrix is ​​an n*n square matrix; n elements in the first submatrix can be greater than or equal to 0, and the rows and columns of these n elements are different; the first submatrix has n 2 -n elements are replaced by -1. For example, -1 can also be replaced by "-" or null.

[0217] For the first submatrix, element -1 can represent an all-zero matrix of a×a, element 0 can represent an a×a unit matrix, and elements greater than 0 can represent a cyclic shift matrix of the a×a unit matrix. That is, the first submatrix can be expanded from an n*n square matrix to a (n*a)*(n*a) square matrix. Wherein, a is a positive integer, and a can be called the lifting factor (lifting factor), lifting size (lifting size) or expansion factor of the first submatrix. The above-mentioned cyclic shift matrix can also be called a circulant permutation matrix (CPM), etc. For ease of description, this application takes the expansion factor as an example for explanation.

[0218] Figure 6 This is a schematic diagram of a cyclic shift matrix provided in an embodiment of the present application. Figure 6 As shown, taking a=4 as an example, the element -1 in the first submatrix can be expressed as a 4*4 all-zero matrix (or replaced by a 4*4 all-zero matrix), the element 0 represents a 4*4 unit matrix (or replaced by a 4*4 unit matrix), and the element 1 represents a cyclic shift matrix after the 4*4 unit matrix is ​​cyclically shifted to the right by 1 bit (or 1 time) (or replaced by a cyclic shift matrix of the 4*4 unit matrix), and so on, which will not be repeated here. Figure 6 The cyclic shift matrix shown is only an example. The cyclic shift matrices of other unit matrices in this application can refer to Figure 6The embodiment of the present application is illustrated by taking right cyclic shift as an example, and as the standard progresses, left cyclic shift may also be adopted in the future, and the embodiment of the present application does not limit this.

[0219] In the embodiment of the present application, whether it is the first sub-matrix or the base matrix, the element -1 represents (or is replaced by) an all-zero matrix, the element 0 represents (or is replaced by) a unit matrix, and the element greater than 0 represents (or is replaced by) a cyclic shift matrix of the unit matrix. As the standard progresses, other values ​​(such as X, Y, etc.) may be used to replace "-1", 0, etc. For example, X may be used to replace "-1", that is, X and "-1" have the same meaning, and Y may be used to replace 0, that is, Y and 0 have the same meaning, etc., which are not listed one by one here.

[0220] The following introduces the pattern of the first sub-matrix involved in this application.

[0221] In the present application, the pattern of the first submatrix can represent the rows and columns where the n non-1 elements in the first submatrix are located. In other words, the pattern of the first submatrix can be used to indicate the positions of the n non-1 elements in the first submatrix. In other words, the pattern of the first submatrix can be used to indicate the positions of the n non-1 elements in the first submatrix. For example, the pattern of the first submatrix can be (1) or (2) below, or any one of (3) to (8) below, or any one of (9) to (13) below.

[0222] As an example, n=2, that is, the dimension of the first sub-matrix is ​​2*2. The first sub-matrix P can satisfy the following relationship:

[0223]

[0224] or,

[0225]

[0226] Element -1 represents an a×a all-zero matrix, meaning that element -1 becomes an a×a all-zero matrix after being expanded by expansion factor a. When P1 = 0 or P2 = 0, it represents the a×a identity matrix, meaning that element 0 becomes an a×a identity matrix after being expanded by expansion factor a. When P1 > 0, it represents the cyclic shift matrix of the a×a identity matrix after being cyclically shifted right by P1. When P2 > 0, it represents the cyclic shift matrix of the a×a identity matrix after being cyclically shifted right by P2. In other words, elements greater than 0 become the cyclic shift matrix of the a×a identity matrix after being expanded by expansion factor a.

[0227] Based on the above relationship (1) or relationship (2), it can be known that the matrix dimension of the first submatrix after expansion is (2a)*(2a), that is, the dimension of P is (2a)*(2a). Since n=2, Z=2a, that is, a Z*Z subblock of the base matrix after expansion by the expansion factor Z can correspond to the above P, or a Z*Z subblock after the base matrix is ​​expanded is the same as the matrix of the above first submatrix P after expansion by the expansion factor a. A Z*Z subblock of the above base matrix after expansion by the expansion factor Z can also be called a Z*Z subblock corresponding to the base matrix or a Z*Z subblock in the base matrix or a subblock in the base matrix, etc. The specific description method is not limited in the embodiments of the present application.

[0228] As an example, the dimension of a sub-block in this application may be Z*Z. For example, a sub-block may represent a Z*Z identity matrix, a cyclic shift matrix of a Z*Z identity matrix, or a Z*Z all-zero matrix, where Z represents the expansion factor of the base matrix.

[0229] As another example, a sub-block in the present application may also represent a Z*Z all-zero matrix or a Z*Z unit matrix or a cyclic shift matrix of a Z*Z unit matrix, the corresponding dimension in the base matrix or the corresponding size in the base matrix, or the corresponding element in the base matrix. Figure 4b For the unilateral structure shown in FIG, an element of the base matrix can represent a Z*Z sub-block. However, in this application, a first sub-matrix (i.e., n 2 An orthogonal matrix of elements can represent a Z*Z sub-block.

[0230] Figure 7a This is a schematic diagram of an orthogonal sub-block provided in an embodiment of the present application. A sub-block has a dimension of Z*Z, and the sub-block can be evenly split (e.g., Z=2a) into four a×a matrices. In other words, a sub-block can correspond to a first sub-matrix, and the first sub-matrix can satisfy the above-mentioned relationship (1) or relationship (2). In other words, a sub-block can include a first sub-matrix, or a sub-block can be composed of a first sub-matrix. Figure 7a (1) in can correspond to the style of the above relationship (1), Figure 7a (2) in the above relation can correspond to the style of (2).

[0231] By satisfying the above relationship (1) or relationship (2), the orthogonality between matrices within the sub-block can be effectively guaranteed, making the hardware implementation of the encoding and decoding simple, and also avoiding address conflicts when reading data from the storage. As an example, P1≠P2 can improve the decoding performance. As another example, P1=P2 can reduce the storage capacity of the base matrix stored in the encoding device or the decoding device or the storage capacity of the offset value matrix stored, saving storage space. When P1=P2, the description can also refer to the description of the identification matrix shown below.

[0232] As another example, n=3, that is, the dimension of the first sub-matrix is ​​3*3. The first sub-matrix P can satisfy the following relationship:

[0233]

[0234]

[0235]

[0236]

[0237]

[0238]

[0239] The descriptions of relations (3) to (8) can refer to the descriptions of relations (1) and (2) above, and will not be repeated here.

[0240] When n=3, a Z*Z sub-block corresponding to the base matrix can be evenly split into 9 a×a matrices. In other words, the Z*Z sub-block can correspond to a first sub-matrix, and the first sub-matrix can be one of the above relations (3) to (8). In other words, a Z*Z sub-block can include a first sub-matrix, or the sub-block is composed of the first sub-matrix.

[0241] In order to ensure the orthogonality between matrices within a sub-block, the embodiment of the present application provides the above six (ie, 3*2*1=6) patterns. Figure 7b This is a schematic diagram of an orthogonal sub-block provided in an embodiment of the present application. Figure 7b The first graph in the first row of corresponds to the style of the above relationship (3), the second graph in the first row corresponds to the style of the above relationship (4), and so on.

[0242] In an embodiment of the present application, each first submatrix in the base matrix may correspond to one of the six styles mentioned above. As an example, each first submatrix in the base matrix may adopt the same style, thereby reducing the encoding and decoding complexity, further reducing the storage capacity of the encoding device or the decoding device for storing the base matrix or the storage capacity of the offset value matrix, and saving storage space. As another example, there may be at least two first submatrices with different styles in the base matrix. Compared with the first submatrix with n=2, when n=3, there may be at least two first submatrices with different styles in the base matrix, that is, the styles of the orthogonal matrices (that is, the first submatrices) in at least two sub-blocks corresponding to the base matrix are different, thereby having greater flexibility, so that the base matrix can have a larger design space, so that the designed base matrix can improve decoding performance.

[0243] As an example, at least two of P1, P2, and P3 can be different. As another example, P1 = P2 = P3, which can reduce the amount of storage required by the encoding device or decoding device to store the base matrix or the offset value matrix, saving storage space. For the description of P1 = P2 = P3, please refer to the description of the identification matrix shown below.

[0244] As another example, n=4, that is, the dimension of the first submatrix can be 4*4. A Z*Z sub-block corresponding to the base matrix can be evenly split into 16 a×a sub-matrices. In order to ensure the orthogonality between matrices within the sub-block, the embodiment of the present application provides 24 (i.e., 4*3*2*1) styles. These 24 styles all meet the characteristics met by the first submatrix shown above, and will not be repeated here. Due to limited space, 5 styles are given as examples below. For example, P1=P2=P3=P4. For the description of the values ​​of each element, please refer to the above and will not be described in detail here. When P1=P2=P3=P4, the description can also refer to the description of the identification matrix shown below.

[0245]

[0246]

[0247]

[0248]

[0249]

[0250] The above is illustrated by taking n=2, n=3, and n=4 as examples. In specific implementations, n may also take larger values, which are not listed here one by one.

[0251] The following introduces the basis matrix involved in this application.

[0252] The base matrix shown in the embodiment of the present application can be applied to LDPC codes, polar codes, or other types of codes that will appear later. The base matrix provided in the embodiment of the present application will be described below using LDPC codes as an example.

[0253] Generally speaking, the basis matrix H of LDPC code base It can be as follows:

[0254]

[0255] Where [AB] is the core matrix, and [D1 D2 E] is the extended matrix. Matrix A represents the information bits (or systematic bits) in the core matrix, and matrix B represents the check bits in the core matrix.

[0256] Figure 8 This is a schematic diagram of the structure of an LDPC code base matrix provided in an embodiment of the present application. Figure 8 As shown, the dimension of matrix A can be m a ×n A , that is, the matrix A can include m A ×n A sub-blocks. The dimension of matrix B is m A ×m A , that is, the matrix B can include m A ×m A sub-blocks. The dimension of matrix D is m D ×(n A +m A ), that is, the matrix D can include m D ×(n A +m A ) sub-blocks. The dimension of matrix E is m D ×m D , that is, the matrix E can include m D ×m D Sub-blocks.

[0257] Among them, the length of the information bit K = n A ×Z, the length of the check digit is m A ×Z. The matrix B can be divided into two parts B = [B1 B2], the dimension of matrix B1 is m A ×1, the matrix B1 can have T non-zero matrix sub-blocks, T is an odd number less than or equal to the number of rows of the base matrix. For example, among the T non-zero matrix sub-blocks, T-1 elements can have the same offset value. For example, if the matrix B1 can have 3 non-zero matrix sub-blocks, they can be located in the 0th row, the mth row, and the mth row. A -1 row and xth row (1≤x≤m A-2), whose shift factors are a, b, and a, or a, b, and b, respectively, where a ≥ 0 and b ≥ 0. Matrix B2 is a dual diagonal structure, where the elements in row i and column j are all 0 when i = j and i = j + 1, and -1 in all other positions. Matrix B can be expressed as:

[0258]

[0259] In the matrix B shown in (15), the ellipsis at the diagonal positions is 0, and the ellipsis at the first column is -1. Except for the diagonal positions and the first column, the elements of the other rows or columns not shown are all -1.

[0260] The following describes each matrix in detail.

[0261] As a possible implementation a, each sub-block in at least one sub-block in the matrix A may correspond to a first sub-matrix, or each of the aforementioned sub-blocks may include a first sub-matrix, such as each sub-block in the matrix A except for the sub-block represented by the element -1 may correspond to a first sub-matrix. For example, the m in the matrix A A ×n A Each sub-block in at least one of the sub-blocks includes a first sub-matrix. The style of each first sub-matrix in the matrix A can be the same, or there are at least two first sub-matrices with different styles. The embodiment of the present application does not limit the style of each first sub-matrix in the matrix A. From the perspective of the sub-block, the matrix A can include m A ×n A sub-blocks, or the matrix A can include m A ×n A There are Z*Z sub-blocks. Since each sub-block can correspond to n 2 elements, so when each sub-block in the matrix A corresponds to a first sub-matrix, from the perspective of elements, the matrix A can include m A ×n A ×n 2 elements.

[0262] Figure 9a and Figure 9b This is a schematic diagram of the structure of a matrix A in a core matrix provided in an embodiment of the present application. Figure 9a As shown, each sub-block in the matrix A except the sub-block represented by element -1 may include a 2*2 first sub-matrix. Figure 9b As shown, each sub-block in the matrix A except the sub-block represented by the element -1 may include a 3*3 first sub-matrix. Figure 9a and Figure 9b All are in m A =4,nA =10 is used as an example, but in a specific implementation, the dimension of the matrix A can be larger or smaller, and this embodiment of the present application does not limit this.

[0263] For example, Figure 9a The first sub-matrix corresponding to the first sub-block in the first row of the matrix A is Figure 9a Element -1 is not shown in the first sub-matrix (ie, the white portion omitted is element -1), but this should not be understood as a limitation to the embodiments of the present application. Figure 9a The values ​​of the various elements shown in are merely examples and should not be construed as limiting the embodiments of the present application.

[0264] Figure 9a The gray content inside the box represents the Z*Z all-zero matrix, or it can mean that the elements in the box are -1, or the matrix corresponding to the sub-block is For example, Figure 9a The fifth sub-block in the first row of the matrix A in can correspond to an all-zero matrix of Z*Z, that is, the elements in the fifth sub-block can be -1. Similarly, the sixth sub-block in the first row, the eighth sub-block in the first row, the ninth sub-block in the first row, the second sub-block in the second row, the third sub-block in the second row, the third sub-block in the third row, the sixth sub-block to the eighth sub-block in the third row, the tenth sub-block in the third row, the first sub-block in the fourth row, and the fourth sub-block in the fourth row can respectively correspond to an all-zero matrix of Z*Z. The elements in each sub-block shown here can respectively be an element -1, or can also be considered as a 2*2 square matrix whose elements are all -1, and the embodiments of the present application are not limited to this.

[0265] Figure 9b The pattern of the first sub-matrix in the sub-block is shown exemplarily, and the elements in the first sub-matrix are not shown in detail. Figure 9b For instructions, please refer to Figure 9a , which will not be described in detail here.

[0266] The sub-blocks in matrix A can support a larger expansion factor Z by adopting the form of the first sub-matrix shown above, such as Z can be greater than 384, which effectively improves the parallelism of encoding and decoding. At the same time, it can also be compatible with encoding devices or decoding devices with low parallelism, and has better compatibility.

[0267] As another possible implementation manner b, the matrix B may adopt a unilateral structure, for example, each sub-block includes one element, or each sub-block may correspond to an offset value, or each sub-block may have an offset value.

[0268] Figure 10Schematic diagram of the structure of a matrix B in a core matrix provided in an embodiment of the present application. Figure 10 It is m A =4 is shown as an example, but in a specific implementation, the dimension of the matrix B can be larger, and this embodiment of the application does not limit this. Figure 10 As shown in (1), each sub-block in the matrix B can include one element. Figure 10 The elements not shown in (1) are -1.

[0269] As another possible implementation manner c, each sub-block in at least one sub-block in the matrix B may correspond to a first sub-matrix, or in other words, each sub-block in the at least one sub-block may include a first sub-matrix, such as each sub-block in the matrix B except for the sub-block represented by element -1 may correspond to a first sub-matrix. Figure 10 As shown in (2), each sub-block in the matrix B except the sub-block corresponding to the element -1 may include a first sub-matrix. Figure 10 In (2), the matrix B includes 16 sub-blocks, and the sub-blocks whose specific elements are not shown correspond to the Z*Z all-zero matrix, that is, the third sub-block in the first row, the fourth sub-block in the first row, the first sub-block in the second row, the fourth sub-block in the second row, the second sub-block in the third row, and the third sub-blocks to the fourth sub-blocks in the fourth row correspond to the Z*Z all-zero matrix, or respectively include the element -1.

[0270] Combined with the representation of (15) above, when the matrix B adopts the design of the orthogonal matrix shown above, the matrix B can be expressed as:

[0271]

[0272] Among them, P′ a and P′ b The dimension of P′ is a×a. a It is based on P a Determined, such as P′ a Can be equal to P a . P′ b It is based on P b Determined, such as P′ b Can be equal to P b The above-mentioned matrix B is represented by taking n=2 as an example, and the relationship (2) shown above is used as an example, but it should not be understood as limiting the embodiments of the present application. For other explanations in (16), please refer to (15) and will not be described in detail here.

[0273] For the shape When the offset value of P1 is 0, the above Figure 10The matrices constructed by the construction methods (1) and (2) are equivalent.

[0274] Figure 10 Matrix B in [1] uses a dual-diagonal structure, meaning that the sub-blocks corresponding to the dual-diagonal positions of matrix B are non-zero matrices, and all positions except the sub-block corresponding to the first column are zero matrices. This allows the encoding device to perform simple row-column operations to complete the encoding, avoiding complex encoding methods such as lower-upper (LU) decomposition, effectively reducing the complexity of the codec.

[0275] Figure 11a (1) and Figure 11b (1) is a schematic diagram of the structure of a core matrix provided in an embodiment of the present application. In combination with the above-mentioned implementation method a and implementation method b, each sub-block in the matrix A in the core matrix, except for the sub-block represented by element -1, can correspond to a first sub-matrix, and the matrix B in the core matrix can adopt a unilateral structure. This supports a larger expansion factor Z, such as Z can be greater than 384, which can improve the parallelism of encoding and decoding.

[0276] Figure 11a (2) and Figure 11b (2) is a structural diagram of another core matrix provided in an embodiment of the present application. In combination with the above-mentioned implementation method a and implementation method c, each sub-block in the matrix A in the core matrix except the sub-block represented by element -1 can correspond to a first sub-matrix, and each sub-block in the matrix B except the sub-block represented by element -1 can also correspond to a first sub-matrix. Therefore, the sub-blocks in the core matrix all adopt sub-matrices with orthogonal structures, which can reduce the parallelism of encoding and decoding to a, facilitating the reuse of encoding and decoding hardware.

[0277] Figure 11a The example shown is based on n=2. Figure 11b The example shown is based on n=3. Figure 11a or Figure 11b For other instructions, please refer to Figure 9a or Figure 9b or Figure 10 , which will not be described in detail here.

[0278] As another possible implementation manner d, each sub-block in at least one sub-block in the extended matrix may correspond to a first sub-matrix, or in other words, each sub-block may include a first sub-matrix. For example, each sub-block in the extended matrix, except for the sub-block represented by element -1, may correspond to a first sub-matrix. That is, the sub-blocks in the extended matrix may also be in the form of orthogonal matrices. Figure 12a This is a schematic diagram of the structure of a base matrix provided in an embodiment of the present application. Figure 12aAs shown, each sub-block in at least one sub-block in the extended matrix of the base matrix may also correspond to a first sub-matrix. In other words, a sub-block in the extended matrix may also be split into 4 a×a first sub-matrices. Figure 12a In the figure, n=2 is used as an example, but it should not be understood as a limitation to the embodiments of the present application. Figure 12a In the middle is m A =4,n A =10,m D =5 is shown as an example, but it should not be understood as a limitation to the embodiments of the present application.

[0279] Matrix E in the base matrix is ​​the identity matrix. Therefore, regardless of whether the unit matrix is ​​an orthogonal matrix or a unilateral structure, matrix E remains the identity matrix. For matrix E, every two Z×Z subblocks in the LDPC code matrix are orthogonal, and can be viewed as a special unilateral QC-LDPC code structure with a block length of a.

[0280] As another possible implementation manner e, at least one sub-block in the extended matrix may adopt a unilateral structure, that is, each Z×Z sub-block corresponding to the extended matrix may not be further split. Figure 12b This is a schematic diagram of another basic matrix structure provided by the embodiment of the present application. Figure 12b As shown, the extended array is a unilateral structure. Figure 12b For other instructions, please refer to Figure 12a or Figure 11a or Figure 11b etc., which will not be elaborated here.

[0281] The base matrix shown in the embodiments of the present application may satisfy the above-mentioned implementation mode a, implementation mode c, or implementation mode d. Alternatively, the above-mentioned implementation modes a to e may be combined with each other, such as the core matrix in the base matrix may satisfy the above-mentioned implementation mode a and implementation mode b, or implementation mode a and implementation mode c. Alternatively, the base matrix may satisfy implementation mode a, implementation mode b, and implementation mode d, or implementation mode a, implementation mode b, and implementation mode e, or implementation mode a, implementation mode c, and implementation mode d, or implementation mode a, implementation mode c, and implementation mode e, etc., which will not be described in detail here.

[0282] Through the base matrix shown in the embodiment of the present application, not only can flexible code length and code rate be supported, but also the orthogonal matrix structure can support greater encoding and decoding parallelism, improve throughput encoding and decoding, and at the same time be compatible with hardware with low parallelism, can support various hardware, and have better compatibility.

[0283] When different parts of the base matrix are in the form of orthogonal matrices, that is, when at least one sub-block in the core matrix and the extended matrix of the base matrix corresponds to the first sub-matrix, the values ​​of the elements can be different when the first sub-matrix is ​​located at different positions. For example, Figure 12a or Figure 12b As shown, the elements in the first submatrix of the information bits of the core matrix can be different from the elements in the first submatrix of the check bits of the core matrix. The embodiment of the present application does not limit the pattern or specific values ​​of each first submatrix in the base matrix.

[0284] As an example, the encoding device and the decoding device can store a base matrix. The form of the stored base matrix includes but is not limited to a matrix, a table, etc., and the specific form of storage is not limited in the embodiment of the present application. As another example, the encoding device and the decoding device can store an offset value matrix and an identification matrix, and the offset value matrix and the identification matrix can be used to determine the base matrix. The form of the stored offset value matrix can include but is not limited to a matrix, a table, etc., and the form of the stored identification matrix can include but is not limited to a matrix, a table, etc. For an explanation of the offset value matrix and the identification matrix, please refer to Implementation 2 below, which will not be described in detail here.

[0285] In a specific implementation, the encoding device may encode the first bit sequence based on the base matrix and the expansion factor Z (or expansion factor a). Alternatively, the encoding device may expand the base matrix based on the expansion factor Z (or expansion factor a), and then use the expanded base matrix to encode the first bit sequence. The embodiment of the present application does not limit the encoding process of the first bit sequence by the encoding device in combination with the base matrix and the expansion factor. Correspondingly, the decoding device may decode the sequence to be decoded based on the base matrix and the expansion factor Z (or expansion factor a). Alternatively, the decoding device may expand the base matrix based on the expansion factor Z (or expansion factor a), and then use the expanded base matrix to decode the sequence to be decoded. The embodiment of the present application does not limit the decoding process of the sequence to be decoded by the decoding device in combination with the base matrix and the expansion factor.

[0286] In the implementation method 1 shown above, the encoding device can perform encoding in conjunction with the base matrix. The following example illustrates the encoding process in conjunction with the base matrix:

[0287] As an example, the encoding process could be as follows:

[0288] (1) Add all the rows in the equation system [AB]·[s e1]=0 and eliminate the duplicate terms to obtain e1(0).

[0289] (2) According to the value of e1(0), recursively calculate e1(1) to e1(m A -1);

[0290] (3) Combine the information bit s and the check bit e1 to obtain the codeword c1 = [s e1] after core matrix encoding.

[0291] In the above example, A represents the matrix A shown above, which is also the core matrix in the basis matrix. B represents the matrix B shown above, which is also the core matrix in the basis matrix. s represents the information bit, and e1 represents the check bit. e1(0) represents the first element of the check bit in the core matrix, e1(1) represents the second element of the check bit in the core matrix, and e1(m A -1) indicates the mth check bit in the core array A elements.

[0292] The above encoding process exemplarily illustrates the encoding method of the core matrix in the basis matrix.

[0293] As another example, the encoding process could look like this:

[0294] Figure 13 This is a schematic diagram of the encoding process of an LDPC code provided in an embodiment of the present application. Assume that the input information bit sequence of the encoding device is s, the length is K, and the output encoding codeword sequence is d, the length is N, where N = [K / R]. R represents the encoding rate. According to Figure 8 The basic matrix of the LDPC code shown in Figure 1 is used. The specific encoding process is as follows:

[0295] (1) Encode according to the core matrix [AB] to obtain c1 = [s e1], where the length of e1 is m A ×Z.

[0296] For the description of step (1), please refer to the above encoding process and will not be described in detail here.

[0297] (2) Encode the extended matrix [DE] with c1 as the new information bit sequence, and get c = [c1 e2], where the length of e2 is m D ×Z, the final check digit is recorded as e=[e1 e2], then K=n A Z, the codeword length after extended matrix coding is K+(m A +m D )Z.

[0298] Where D represents the matrix D shown above, i.e., the extended matrix in the base matrix. E represents the matrix E shown above, i.e., the extended frame in the base matrix. The encoding device can encode the information bit sequence by combining the matrix A, matrix B, matrix D, and matrix E in the base matrix.

[0299] (3) Adaptively adjust the code length and code rate according to the system requirements, perform puncturing on the check bits, and discard the last K+(m A +mD )Z-[K / R]bit, and obtain the encoding result of the LDPC code.

[0300] In the embodiment of the present application, for the extended matrix coding, since the parity check matrix E on the right side of the extended matrix is ​​a unit matrix, there is no need to use recursive calculation, and all parity bits can be calculated in parallel. Among them D i,j is a Z×Z matrix. Depending on whether the extended matrix adopts orthogonal code design, D i,j The form of the matrix is ​​different. If the extended matrix adopts orthogonal code design, D i,j is a zero matrix or a matrix composed of orthogonal sub-blocks. If the extended matrix adopts a unilateral design, D i,j is a zero matrix or a cyclic shift matrix of the identity matrix.

[0301] For implementation method 2 shown below, when the encoding device determines the base matrix based on the first submatrix corresponding to the first element in the offset value matrix, the encoding device can also perform encoding according to the above example. The encoding process shown above is only an example, and the embodiments of the present application do not limit the specific encoding process or the specific steps of encoding. However, any use of the structure of the base matrix shown above, or the structure of the offset value matrix and the identification matrix shown below in the encoding process, falls within the scope of protection of this application.

[0302] In the embodiment of the present application, elements greater than or equal to 0 in the base matrix may correspond to offset values, CPM coefficients, cyclic shift values, etc. For example, elements greater than or equal to 0 in the base matrix may be equal to the offset value (or CPM coefficient). In another example, elements greater than or equal to 0 in the base matrix may satisfy a modulo operation relationship with the offset value and the expansion factor Z. For ease of description, the following description uses the offset value as an example.

[0303] As another possible implementation manner 2, the encoding device may encode the first bit sequence based on the offset value matrix and the expansion factor.

[0304] The offset value matrix may include a first element, which may correspond to a first sub-matrix, which may be composed of n 2An orthogonal matrix composed of elements, where n is an integer greater than or equal to 2. For the description of the first sub-matrix, please refer to the above implementation method 1 and will not be elaborated here. Generally speaking, the offset value matrix can be used to determine the base matrix. When the first element in the offset value matrix is ​​greater than or equal to 0, the corresponding position in the base matrix can include a first sub-matrix, and the elements in the first sub-matrix can be determined based on the first element, and the element -1 in the offset value matrix can indicate that the corresponding position in the base matrix is ​​a Z*Z all-zero matrix. For the relationship between the base matrix and the offset value matrix, please refer to the following, which will not be described in detail here. The offset value matrix shown in the embodiment of the present application can also be called a shift value matrix, etc. The specific name of the matrix is ​​not limited in the embodiment of the present application.

[0305] The following example describes the offset matrix:

[0306] As an example 1, n=2, P1=P2, the first element can be equal to P1 or P2. Or, n=3, P1=P2=P3, the first element can be equal to P1 or P2 or P3. Or, n=4, P1=P2=P3=P4, the first element can be equal to P1 or P2 or P3 or P4. The values ​​of n are not listed here one by one. That is, the elements in the first submatrix except -1 are the same, and the first element can be equal to the elements except -1. For example, Figure 9a For example, the dimension of the offset value matrix can be 4*10. Figure 14 (2) is a schematic diagram of an offset value matrix provided in an embodiment of the present application. Figure 14 As shown in (2), the first row and first column element 9 in the offset value matrix can correspond to Figure 9a in The first row and second column element 117 in the offset value matrix may correspond to Figure 9a in I will not list them all here.

[0307] For example 1, when the elements in the first sub-matrix other than -1 are equal, the encoding device or the decoding device can complete encoding and decoding by storing one offset value matrix, thereby effectively saving storage resources.

[0308] As another example 2, the first element may be equal to an element other than -1 in the first submatrix. The other elements in the first submatrix may be determined based on the first element. For example, when n=2, the first element may be equal to P1, and the value of P2 may be determined based on the value of P1, such as P2=P1+x. If the value of x may be defined by a protocol, or broadcast by a network device to each terminal device, the embodiment of the present application does not limit the specific value of x or the method of obtaining it. For another example, when n=3, the first element may be equal to P1, and the value of P2 or P3 may be determined based on the value of P1, such as P2=P1+x1, P3=P1+x2. Similarly, the values ​​of x1 and x2 may be defined by a protocol, or broadcast by a network device to each terminal device, and the embodiment of the present application does not limit the specific value of x1 and x2 or the method of obtaining it.

[0309] With respect to the above-mentioned Example 1 or Example 2, the encoding device or the decoding device may store an offset value matrix.

[0310] As another example 3, the encoding device or decoding device may store n offset value matrices, that is, the number of the offset value matrices is the same as the value of n. The dimensions of these n offset value matrices are the same, and the elements at the same position in the offset value matrix may correspond to different elements of the same first sub-matrix. For example, if n=2, the encoding device or decoding device may store two offset value matrices, such as offset value matrix #1 and offset value matrix #2. For example, the first row and first column element in offset value matrix #1 may be the first element #1, and the first row and first column element in offset value matrix #2 may be the first element #2. The first element #1 may be equal to P1, and the first element #2 may be equal to P2. The first element #1 and the first element #2 may be two elements in the first sub-matrix corresponding to the same Z*Z sub-block. For another example, if n=3, the encoding device or decoding device may store three offset value matrices, such as offset value matrix #1, offset value matrix #2, and offset value matrix #3. The elements at the same position in the three offset value matrices may be respectively equal to P1, P2, and P3 in the first sub-matrix corresponding to the same Z*Z sub-block.

[0311] For Example 3, when the elements in the first submatrix other than -1 are not equal, the encoding device or decoding device saves existing resources by storing n offset value matrices compared to storing one base matrix, and the element values ​​can be more flexible.

[0312] In the embodiment of the present application, each of the multiple first elements in the offset value matrix may correspond to a first sub-matrix, that is, the multiple first elements may correspond to multiple first sub-matrices.

[0313] As a possible implementation method f, the styles of the above-mentioned multiple first sub-matrices can all be the same. For example, when n=2, the styles of the multiple first sub-matrices can all satisfy any one of the above-mentioned relationships (1) or (2). For another example, when n=3, the styles of the multiple first sub-matrices can all satisfy any one of the above-mentioned relationships (3) to (8). Exemplarily, the style of the first sub-matrix can be predefined by a protocol, or determined by a network device, or determined by an encoding device, and this embodiment of the present application does not limit this.

[0314] In a specific implementation, the encoding device may determine a base matrix based on the offset value matrix, and then encode the first bit sequence based on the base matrix and the expansion factor; alternatively, the encoding device may directly encode the first bit sequence based on the offset value matrix and the expansion factor. Correspondingly, the decoding device may determine a base matrix based on the offset value matrix, and then decode the sequence to be decoded based on the base matrix and the expansion factor; alternatively, the decoding device may directly decode the sequence to be decoded based on the offset value matrix and the expansion factor.

[0315] As another possible implementation g, among the multiple first sub-matrices, there may be at least two first sub-matrices whose styles are different. For example, when n=2, among the multiple first sub-matrices, there may be a first sub-matrix #1 whose style satisfies the above relationship (1), and there may be a first sub-matrix #2 whose style satisfies the above relationship (2). For another example, when n=3, among the multiple first sub-matrices, there may be at least two of the following: there is a first sub-matrix #1 whose style satisfies the above relationship (3), there is a first sub-matrix #2 whose style satisfies the above relationship (4), there is a first sub-matrix #3 whose style satisfies the above relationship (5), there is a first sub-matrix #4 whose style satisfies the above relationship (6), there is a first sub-matrix #5 whose style satisfies the above relationship (7), and there is a first sub-matrix #6 whose style satisfies the above relationship (8).

[0316] In a specific implementation, the encoding device may determine a base matrix based on the offset value matrix and the identification matrix, and then encode the first bit sequence based on the base matrix and the expansion factor; alternatively, the encoding device may directly encode the first bit sequence based on the offset value matrix, the identification matrix, and the expansion factor. Correspondingly, the decoding device may determine a base matrix based on the offset value matrix and the identification matrix, and then decode the sequence to be decoded based on the base matrix and the expansion factor; alternatively, the decoding device may directly decode the sequence to be decoded based on the offset value matrix, the identification matrix, and the expansion factor.

[0317] In an embodiment of the present application, the dimensions of the identification matrix are the same as the dimensions of the offset value matrix. If the identification matrix includes a second element, the position of the second element in the identification matrix is ​​the same as the position of the first element in the offset value matrix, and the second element is used to indicate the style of the first submatrix. In other words, the second element can be used to indicate the style of the first submatrix determined based on the first element, or in other words, the second element can be used to indicate the style of the first submatrix corresponding to the first element.

[0318] Figure 14 (1) and Figure 15 This is a schematic diagram of an identification matrix provided in an embodiment of the present application. Figure 14 (1) in FIG. 1 is an identification matrix shown with n=2 as an example. Figure 15 The identification matrix is ​​shown using n=3 as an example. As n increases, the values ​​of the elements in the identification matrix can be updated accordingly. For example, when n=4, since the first submatrix may have 24 patterns, the values ​​of the elements in the identification matrix can be greater than or equal to 0 and less than or equal to 23. The values ​​of the elements in the identification matrix are merely examples; in specific implementations, other methods can also be used to identify different patterns. Figure 14 (1) and Figure 15 Only one offset value matrix is ​​shown as an example. For the description of Example 3 above, please refer to Figure 14 or Figure 15 Description.

[0319] like Figure 14 As shown in (1), when n=2, when the encoding device or decoding device stores a Z*Z sub-block, it can use a 1-bit identifier and The offset value of bits (i.e., the element in the offset value matrix). For example, when the flag is 0, it can indicate that the style of the first sub-matrix corresponding to the flag can satisfy the above relationship (2), and when the flag is 1, it can indicate that the style of the first sub-matrix corresponding to the flag can satisfy the above relationship (1). Taking the above example 1 and Figure 9a For example, Figure 14 As shown in , if the first row and first column of the offset value matrix is ​​9 and the first row and first column of the identification matrix is ​​0, then the first submatrix at the corresponding position in the base matrix is That is, the first sub-block in the basis matrix corresponds to For example, the first row and second column of the offset value matrix is ​​117, which means the first row and second column of the matrix is ​​1. Then the first submatrix at the corresponding position in the base matrix is That is, the second sub-block in the basis matrix corresponds to I will not list them all here.

[0320] like Figure 15As shown, when n=3, when there is a Z*Z sub-block in the encoding device or decoding device, a 3-bit identifier and The offset value of bits. For example, when the identifier is 0, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (3); when the identifier is 1, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (4); when the identifier is 2, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (5); when the identifier is 3, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (6); when the identifier is 4, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (7); when the identifier is 5, it can indicate that the style of the first submatrix corresponding to the identifier can satisfy the above relationship (8). Taking the above example 1 and Figure 9b For example, Figure 15 As shown, the first row and first column in the identification matrix is ​​0, which means that the style of the first submatrix at the corresponding position in the basis matrix satisfies the relationship (3), that is, Figure 9b The style of the first sub-matrix corresponding to the first sub-block in the first row of . For example, if the first row and second column in the identification matrix is ​​1, it means that the style of the first sub-matrix at the corresponding position of the basis matrix satisfies the relationship (4), that is, Figure 9b The style of the first sub-matrix corresponding to the second sub-block in the first row of . We will not list them one by one here.

[0321] The relationship between the value of the identifier shown above and the style of the first submatrix is ​​only an example. For example, when n=2, the identifier is 0, which indicates that the style of the first submatrix satisfies the above relationship (1). When the identifier is 1, it indicates that the style of the first submatrix satisfies the above relationship (2). These are not listed here one by one.

[0322] At least one of the above implementations a, c or d can be combined with implementation f or g. Similarly, at least one of the above implementations a, c or d can be combined with any one of Examples 1 to 3. Furthermore, at least one of the above Examples 1 to 3 can be combined with implementation f or g. For example, each sub-block in at least one sub-block in the core matrix of the base matrix can correspond to a first sub-matrix, and the encoding device or decoding device can store the core matrix of the base matrix in the form of an offset value matrix and an identification matrix. If the offset value matrix satisfies Example 1 above, the encoding device or decoding device can store an offset value matrix and an identification matrix. The specific description of the combination will not be described in detail here.

[0323] The above is illustrated using an offset value matrix or an identification matrix as an example. In a specific implementation, the encoding device may also use other forms to store offset values ​​or identifications, or use other forms of offset values ​​to encode the first bit sequence. The specific form of the offset value or the specific form of the identification is not limited in this embodiment of the present application.

[0324] Although the 5G LDPC matrix has several times the decoding throughput improvement compared to the 3G / 4G Turbo convolutional coding, in order to better support high throughput and high parallelism in response to the higher peak throughput requirements of 6G, the most direct and effective method is to increase the expansion factor Z in the LDPC matrix. The embodiments of the present application can not only ensure the LDPC code error rate performance (i.e., decoding performance) after the Z value is expanded, but also support high-parallelism and high-throughput encoding and decoding while being compatible with hardware with low parallelism, making it more friendly to existing hardware.

[0325] Compared with LDPC codes using a bilateral structure, this can effectively save storage resources and is more hardware memory friendly. At the same time, the encoding and decoding complexity of LDPC codes using a bilateral structure is high. However, the encoding and decoding complexity can be reduced by using the embodiments of the present application.

[0326] Compared to LDPC codes with a unilateral structure, when a larger expansion factor Z is used, the existing offset value needs to be redesigned, thereby increasing the design complexity. However, the embodiments of the present application can effectively be compatible with existing LDPC codes and hardware with low parallelism, and are more friendly to existing encoding and decoding hardware with limited parallelism.

[0327] The following describes the device provided in the embodiments of the present application.

[0328] The present application divides the functional modules of the device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in this application is schematic and is only a logical function division. There may be other division methods in actual implementation. The following will be combined with Figures 16 to 18 The device of the embodiment of the present application is described in detail.

[0329] Figure 16 This is a schematic diagram of the structure of a device provided in an embodiment of the present application. Figure 16As shown, the device includes a processing module 1601 and a transceiver module 1602. The transceiver module 1602 can implement corresponding communication functions, and the processing module 1601 is used to implement corresponding processing functions. For example, the transceiver module 1602 can also be called an interface, a communication interface, a communication module, or an input / output interface.

[0330] In some embodiments of the present application, the device can be used to perform the actions performed by the encoding device in the above method embodiments. In this case, the encoding device can be the network device itself or a chip or functional module that can be configured in the network device, or the encoding device can be the terminal device itself or a chip or functional module that can be configured in the terminal device. The transceiver module 1602 is used to perform the transceiver-related operations or input / output-related operations of the encoding device in the above method embodiments, and the processing module 1601 is used to perform the processing-related operations of the encoding device in the above method embodiments.

[0331] Exemplarily, the processing module 1601 can be used to obtain a first bit sequence, and encode the first bit sequence based on a base matrix and an expansion factor, or encode the first bit sequence based on an offset value matrix and an expansion factor to obtain a second bit sequence; the transceiver module 1602 can be used to output the second bit sequence.

[0332] The processing module 1601 may also be used to determine an expansion factor.

[0333] For example, the processing module 1601 may include an acquisition module, an encoding module, etc. Exemplarily, the processing module 1601 may also include a modulation module, etc.

[0334] As an example, the transceiver module 1602 may be configured to transmit a signal obtained after processing the second bit sequence. For example, the transceiver module 1602 may include a radio frequency module, an antenna module, and the like.

[0335] As another example, the transceiver module 1602 can be configured to output a second bit sequence. After outputting the second bit sequence, the second bit sequence can also undergo other processing, such as rate matching, modulation, MIMO encoding, subcarrier mapping, or IFFT. For example, the transceiver module 1602 can include input and output modules.

[0336] Reuse Figure 16In other embodiments of the present application, the device can be used to perform the actions performed by the decoding device in the above method embodiments. In this case, the device can be the terminal device itself, or a chip or functional module that can be configured in the terminal device, or the decoding device can be the network device itself, or a chip or functional module that can be configured in the network device. The transceiver module 1602 is used to perform the transceiver-related operations of the decoding device in the above method embodiments, and the processing module 1601 is used to perform the processing-related operations of the decoding device in the above method embodiments.

[0337] Exemplarily, the transceiver module 1602 may be configured to receive or input a signal transmitted through a channel; the processing module 1601 may be configured to process the signal to obtain a sequence to be decoded.

[0338] Exemplarily, the processing module 1601 may further decode the sequence to be decoded based on the base matrix and the extension factor, or decode the sequence to be decoded based on the offset value matrix and the extension factor to obtain the first bit sequence.

[0339] The processing module 1601 may also be used to determine an expansion factor.

[0340] The processing module 1601 may further include an acquisition module, a decoding module, etc. Exemplarily, the processing module 1601 may further include a demodulation module, etc.

[0341] As an example, the transceiver module 1602 may receive a signal transmitted through a channel, such as a radio frequency module, an antenna module, and the like.

[0342] As another example, the transceiver module 1602 may receive a sequence to be decoded from other modules, such as inputting the sequence to be decoded, so that the processing module decodes the sequence to be decoded. For example, the transceiver module 1602 may include an input and output module.

[0343] Optionally, in each of the above embodiments, the apparatus may further include a storage module, which may be used to store instructions and / or data. The processing unit 1601 may read the instructions and / or data in the storage module to enable the apparatus to implement the above method embodiments. Exemplarily, the storage module may also store the base matrix, offset matrix, or identification matrix described above.

[0344] In the above embodiments, the specific descriptions of terms or steps can be referred to the introduction in the above method embodiments, and will not be described in detail here.

[0345] The specific descriptions of the transceiver module and the processing module shown in the above embodiments are only examples. For the specific functions or execution steps of the transceiver module and the processing module, please refer to the above method embodiments and will not be described in detail here.

[0346] It is understood that the module division in the above-mentioned device is merely a division of logical functions. Each function may correspond to a functional module, or two or more functions may be integrated into a single functional module. In actual implementation, all or some modules may be integrated into a single physical entity, or distributed across different physical entities. Furthermore, the above-mentioned functional modules may be implemented in hardware, software, or a combination of hardware and software.

[0347] In one example, the functional unit in any of the above devices can be one or more integrated circuits configured to implement the above method, such as: one or more application specific integrated circuits (ASICs), or, one or more central processing units (CPUs), one or more microprocessors (MCUs), one or more digital signal processors (DSPs), or, one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0348] The above describes the device of the embodiment of the present application, and the following describes the possible product forms of the device. Figure 16 Any form of product that has the functions of the device described above falls within the scope of protection of the embodiments of the present application. The following description is for illustrative purposes only and does not limit the product form of the device of the embodiments of the present application to this.

[0349] In one possible implementation, Figure 16In the device shown, the processing module 1601 can be one or more processing circuits, the transceiver module 1602 can be a transceiver circuit, or the transceiver module 1602 can also be a sending module and a receiving module, the sending module can be a sending circuit, and the receiving module can be a receiving circuit, and the sending module and the receiving module are integrated into one device, such as a transceiver circuit. In the embodiment of the present application, the processing circuit and the transceiver circuit can be coupled, etc., and the embodiment of the present application does not limit the connection method of the processing circuit and the transceiver circuit. In the process of executing the above method, the process of sending information in the above method can be the process of the processing circuit outputting the above information. When outputting the above information, the processing circuit outputs the above information to the transceiver circuit so that the transceiver circuit transmits (or outputs). After the processing circuit outputs the above information, it may also need to undergo other processing before reaching the transceiver circuit. Similarly, the process of receiving information in the above method can be the process of the processing circuit receiving the input information. When the processing circuit receives the input information, the transceiver circuit receives the above information and inputs it into the processing circuit. Furthermore, after the transceiver circuit receives the above information, the above information may need to be processed further before being input into the processing circuit.

[0350] Figure 17 This is a schematic diagram of the structure of a device provided in an embodiment of the present application. Figure 17 As shown, the device 170 includes one or more processing circuits 1720 and a transceiver circuit 1710 .

[0351] In some embodiments of the present application, the device may be used to execute the steps, methods, or functions performed by the above-mentioned encoding device, such as the processing circuit 1720 may be used to execute the following steps: Figure 16 The functions or steps implemented by the processing module 1601 shown in FIG. 1 , the transceiver circuit 1710 can be used to perform the following steps: Figure 16 The functions or steps implemented by the transceiver module 1602 are shown in FIG. Figure 16 Or the method embodiments shown above will not be described in detail here.

[0352] In other embodiments of the present application, the device is used to execute the steps, methods or functions executed by the above-mentioned decoding device, such as the processing circuit 1720 can be used to execute the following steps: Figure 16 The functions or steps implemented by the processing module 1601 shown in FIG. 1 , the transceiver circuit 1710 can be used to perform the following steps: Figure 16 The functions or steps implemented by the transceiver module 1602 are shown in FIG. Figure 16 Or the method embodiments shown above will not be described in detail here.

[0353] Exemplarily, the processing circuit may be one or more processors, or all or part of the circuits in one or more processors. The transceiver circuit may be a transceiver, or an input / output circuit, or an interface circuit, etc.

[0354] For example, in Figure 17 In various implementations of the apparatus shown, the transceiver circuitry may include a receiver and a transmitter, wherein the receiver is configured to perform a receiving function (or operation) and the transmitter is configured to perform a transmitting function (or operation). The transceiver circuitry is configured to communicate with other devices / apparatuses via a transmission medium.

[0355] Optionally, the device 170 may further include one or more memories 1730 for storing program instructions and / or data. The memory 1730 is coupled to the processing circuit 1720. The coupling in the embodiment of the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, and is used for information exchange between devices, units or modules. The processing circuit 1720 may operate in conjunction with the memory 1730. The processing circuit 1720 may execute program instructions stored in the memory 1730. Optionally, at least one of the above-mentioned one or more memories may be included in the processing circuit.

[0356] The specific connection medium between the transceiver circuit 1710, the processing circuit 1720 and the memory 1730 is not limited in the embodiment of the present application. Figure 17 The memory 1730, the processing circuit 1720 and the transceiver circuit 1710 are connected via a bus 1740. Figure 17 The connections between the other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 17 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0357] In the embodiments of the present application, the processing circuit can be a general processing circuit, a digital signal processing circuit, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc., which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processing circuit can be a microprocessor circuit or any conventional processing circuit, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processing circuit, or can be executed by a combination of hardware and software modules in the processing circuit, etc.

[0358] In the embodiment of the present application, memory may include but is not limited to non-volatile memories such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM) or portable read-only memory (CD-ROM), etc. Memory is any storage medium that can be used to carry or store program code in the form of instructions or data structures and can be read and / or written by a computer (such as the device shown in the present application), but is not limited to this. The memory in the embodiment of the present application can also be a circuit or other arbitrarily capable of realizing a storage function, for storing program instructions and / or data.

[0359] Exemplarily, processing circuit 1720 is primarily used to process communication protocols and communication data, as well as control the entire device, execute software programs, and process software program data. Memory 1730 is primarily used to store software programs and data. Transceiver circuit 1710 may include a control circuit and an antenna. The control circuit is primarily used to convert baseband signals into radio frequency signals and process radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input / output devices, such as a touch screen, display, and keyboard, are primarily used to receive user input and output data to the user.

[0360] When the device is powered on, processing circuit 1720 reads the software program stored in memory 1730, interprets and executes the software program's instructions, and processes the software program's data. When data needs to be transmitted wirelessly, processing circuit 1720 performs baseband processing on the data to be transmitted and outputs the baseband signal to the RF circuit. The RF circuit then performs RF processing on the baseband signal and transmits it via the antenna as electromagnetic waves. When data is sent to the device, the RF circuit receives the RF signal via the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to processing circuit 1720. Processing circuit 1720 converts the baseband signal into data and processes the data.

[0361] In another implementation, the RF circuit and antenna may be arranged independently of the processing circuit for baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be arranged remotely from the device.

[0362] The device shown in the embodiment of the present application may also have Figure 17The embodiments of the present application do not limit the number of components, etc. The methods executed by the processing circuit and the transceiver circuit shown above are only examples, and the specific steps executed by the processing circuit and the transceiver circuit can refer to the methods described above.

[0363] In another possible implementation, Figure 16 In the illustrated device, the processing module 1601 may be one or more logic circuits, and the transceiver module 1602 may be an input / output interface, also known as a communication interface, an interface circuit, or an interface, etc. Alternatively, the transceiver module 1602 may be a sending module and a receiving module, where the sending module may be an output interface and the receiving module may be an input interface, and the sending module and the receiving module may be integrated into one module, such as an input / output interface.

[0364] Figure 18 This is a schematic diagram of the structure of a device provided in an embodiment of the present application. Figure 18 As shown, Figure 18 The device shown includes a logic circuit 1801 and an interface circuit 1802. That is, the processing module 1601 can be implemented using the logic circuit 1801, and the transceiver module 1602 can be implemented using the interface circuit 1802. The logic circuit 1801 can be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, etc., and the interface circuit 1802 can be a communication interface, an input / output interface, a pin, etc. For example, Figure 18 The above device is shown as an example of a chip, which includes a logic circuit 1801 and an interface circuit 1802 .

[0365] In the embodiment of the present application, the logic circuit and the interface can also be coupled to each other. The embodiment of the present application does not limit the specific connection method of the logic circuit and the interface. For example, the logic circuit 1801 can be used to perform the following Figure 16 The functions or steps implemented by the processing module 1601 shown in FIG. 1 and FIG. 2 can be used to implement the interface circuit 1802. Figure 16 The functions or steps implemented by the transceiver module 1602 are shown in FIG. Figure 16 Or the method embodiments shown above will not be described in detail here.

[0366] The device shown in the embodiment of the present application can implement the method provided in the embodiment of the present application in the form of hardware, or can implement the method provided in the embodiment of the present application in the form of software, etc., and the embodiment of the present application is not limited to this.

[0367] An embodiment of the present application further provides a communication system, which includes an encoding device and a decoding device. The encoding device and the decoding device can be used to execute the method in any of the aforementioned embodiments.

[0368] In addition, the present application also provides a computer program, which is used to implement the operations and / or processing performed by each device in the method provided by the present application.

[0369] The present application also provides a computer-readable storage medium having computer code stored therein. When the computer code is run on a computer, the computer executes the operations and / or processes performed by each device in the method provided by the present application.

[0370] The present application also provides a computer program product, which includes computer code or computer program. When the computer code or computer program is run on a computer, the operations and / or processes performed by the method provided in the present application are executed.

[0371] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0372] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of the present application.

[0373] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0374] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0375] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A coding method, characterized in that: The method comprises: Obtaining a first bit sequence; The first bit sequence is encoded based on a base matrix and an expansion factor to obtain a second bit sequence, wherein the base matrix includes at least one first sub-matrix, and the first sub-matrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2; Output the second bit sequence.

2. A coding method, characterized in that: The method comprises: Obtaining a first bit sequence; The first bit sequence is encoded based on an offset value matrix and an expansion factor to obtain a second bit sequence, wherein the offset value matrix includes a first element, the first element corresponds to a first sub-matrix, and the first sub-matrix is ​​composed of n 2 An orthogonal matrix consisting of elements, where n is an integer greater than or equal to 2; Output the second bit sequence.

3. The method according to claim 2, characterized in that The encoding of the first bit sequence based on the offset value matrix and the expansion factor to obtain a second bit sequence includes: determining a base matrix based on a first submatrix corresponding to the first element in the offset value matrix, where the base matrix includes the first submatrix; The first bit sequence is encoded based on the base matrix and the spreading factor.

4. The method according to claim 2 or 3, characterized in that The encoding of the first bit sequence based on the offset value matrix and the expansion factor includes: The first bit sequence is encoded based on the offset value matrix, the identification matrix and the expansion factor, the dimension of the identification matrix is ​​the same as the dimension of the offset value matrix, the identification matrix includes a second element, the position of the second element in the identification matrix is ​​the same as the position of the first element in the offset value matrix, the second element is used to indicate the style of the first sub-matrix, and the style of the first sub-matrix represents the rows and columns where the elements other than -1 in the first sub-matrix are located.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: The expansion factor is determined, the value of the expansion factor being greater than a threshold.

6. The method according to any one of claims 1 to 5, characterized in that When n=2, the first submatrix P satisfies the following relationship: or, Among them, element -1 represents an all-zero matrix of a×a, element P1 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P1 times, and element P2 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P2 times.

7. The method according to claim 6, characterized in that P1=P2.

8. The method according to any one of claims 1 to 5, characterized in that When n=3, the first submatrix P satisfies the following relationship: or, or, or, or, or, Among them, element -1 represents an all-zero matrix of a×a, element P1 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P1 times, element P2 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P2 times, and element P3 represents a cyclic shift matrix after the unit matrix of a×a is cyclically shifted P3 times.

9. The method according to claim 8, characterized in that P1=P2=P3.

10. The method according to any one of claims 6 to 9, characterized in that: The expansion factor Z is equal to a*n.

11. The method according to any one of claims 1 to 10, characterized in that The first sub-matrix is ​​included in the matrix corresponding to the information bits in the core matrix of the base matrix, or is included in the matrix corresponding to the check bits in the core matrix of the base matrix.

12. A coding device, characterized in that: The method comprises a module for executing the method according to any one of claims 1 to 11.

13. An encoding device, characterized in that: The method comprises a processing circuit and a transceiver circuit, wherein the transceiver circuit is used to input and / or output information, and the processing circuit is used to execute the method according to any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium is used to store a computer program. When the computer program is executed, the method according to any one of claims 1 to 11 is executed.

15. A computer program product, characterized in that When the computer program product is executed, the method according to any one of claims 1 to 11 is performed.

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