EtherCAT master station topology dynamic control system based on FPGA

Abstract

The invention provides an FPGA-based EtherCAT master station topology dynamic control system, and the system comprises an EtherCAT master station which is integrated with an FPGA chip, and is provided with a main network port and a redundant network port; a plurality of EtherCAT slave stations, the EtherCAT slave stations are connected in sequence, and the main network port of the EtherCAT master station is connected to the head end slave stations of the plurality of EtherCAT slave stations; the FPGA chip is used for confirming that a network topology structure formed by the EtherCAT master station and the EtherCAT slave station is in a linear mode or an annular mode according to the connection state of the redundant network port; wherein in the linear mode, the redundant network port is in a forbidden state, and in the annular mode, the redundant network port is connected to a tail end slave station in the plurality of EtherCAT slave stations; and the FPGA chip is also used for controlling the connection state of the redundant network port so as to switch the network topology structure between a linear mode and an annular mode.

Description

Technical Field

[0001] The present application relates to the field of industrial Ethernet field communications, and specifically to an EtherCAT master station topology dynamic control system based on FPGA. Background Art

[0002] Currently, EtherCAT technology, widely used in industrial automation, typically uses a CPU as the core processor to implement its EtherCAT master functionality, with the EtherCAT protocol stack implemented entirely in software. While this software approach offers the advantage of simplified development, it also has limitations. For example, in terms of real-time performance, software execution of protocol stack instructions carries inherent delays and uncertainties. This is especially true when the EtherCAT master performs complex logical operations, requiring CPU intervention. This can easily introduce jitter into the EtherCAT master system and make precise time control difficult. Furthermore, EtherCAT master systems typically pre-set a specific network topology. Changes to the network connection often require hardware reconfiguration or even replacement, resulting in a lack of the ability to dynamically adapt to different network topologies. This reduces the deployment flexibility and reliability of the EtherCAT master system. Summary of the Invention

[0003] In view of this, the present application provides an FPGA-based EtherCAT master station topology dynamic control system, which migrates the parts of the EtherCAT protocol that require high real-time processing to the FPGA for parallel processing, and dynamically identifies and controls the network topology structure according to the connection status of the redundant network ports by the FPGA, thereby solving the problems of insufficient real-time performance and fixed network topology and inability to flexibly adapt caused by software implementation of the EtherCAT master station in the existing technology.

[0004] An embodiment of the present application provides an FPGA-based EtherCAT master station topology dynamic control system, comprising: an EtherCAT master station integrated with an FPGA chip, the EtherCAT master station being configured with a main network port and a redundant network port; a plurality of EtherCAT slave stations, the EtherCAT slave stations being connected in sequence, the main network port of the EtherCAT master station being connected to the head-end slave station of the plurality of EtherCAT slave stations; the FPGA chip being used to confirm, based on the connection status of the redundant network port, whether the network topology structure formed by the EtherCAT master station and the EtherCAT slave stations is a linear mode or a ring mode; wherein, in the linear mode, the redundant network port is in a disabled state, and in the ring mode, the redundant network port is connected to the end slave station among the plurality of EtherCAT slave stations; the FPGA chip is also used to control the connection status of the redundant network port to switch the network topology structure between the linear mode and the ring mode.

[0005] In one possible implementation, when the FPGA chip detects that the redundant network port is in the disabled state, it connects the redundant network port to the terminal slave station to switch the network topology from the linear mode to the ring mode.

[0006] In one possible implementation, when the FPGA chip detects that the redundant network port has not received a response frame returned from the EtherCAT slave station for a preset period of time, the connection between the redundant network port and the terminal slave station is disconnected.

[0007] In one possible implementation, when the network topology is in the ring mode, when the FPGA chip detects that there is at least one breakpoint in the multiple EtherCAT slave stations, it sends a bundle frame through the main network port and the redundant network port respectively, so that the bundle frame reaches all the EtherCAT slave stations.

[0008] In one possible implementation, when the network topology is in linear mode or ring mode, when the FPGA chip detects that the main network port has not received a response frame returned from the EtherCAT slave station for a preset period of time, it sends a cluster frame to the multiple EtherCAT slave stations through the redundant network port and receives response frames returned by the multiple EtherCAT slave stations.

[0009] In a possible implementation, the EtherCAT master station further includes a CPU unit connected to the FPGA chip via a communication interface, and the CPU unit is communicatively connected to at least one EtherCAT slave station via the FPGA chip.

[0010] In a possible implementation, the CPU unit is configured to parse configuration parameters of the EtherCAT slave and generate PDO configuration instructions for periodic process data and / or SDO configuration instructions for aperiodic service data according to the configuration parameters;

[0011] The FPGA chip is used to periodically send PDO bundle frames to corresponding EtherCAT slaves among the multiple EtherCAT slaves according to the PDO configuration instructions; and the FPGA chip is also used to send SDO request frames to corresponding EtherCAT slaves among the multiple EtherCAT slaves within the communication interval between two adjacent PDO bundle frames according to the SDO configuration instructions.

[0012] In one possible implementation, the FPGA chip is also used to stop the currently transmitted SDO request frame at a predetermined periodic sending moment of the PDO bundle frame, and send the PDO bundle frame corresponding to the predetermined periodic sending moment; and temporarily store the SDO request frame that has not been sent in the cache area of ​​the FPGA chip.

[0013] In a possible implementation, the PDO configuration instruction includes a communication cycle, a data mapping relationship, an input data address, and an output data address;

[0014] The FPGA chip is used to read the real-time control data from the output data address at regular intervals according to the communication cycle in the PDO configuration instruction and the data mapping relationship, and encapsulate the real-time control data into the PDO bundle frame;

[0015] The FPGA chip is also used to receive the PDO input bundle frame fed back by the EtherCAT slave station, write the PDO input data indicated by the PDO input bundle frame into the input data address; and send a data update notification to the CPU unit.

[0016] In a possible implementation, the SDO configuration instruction includes an instruction operation type and a data cache address;

[0017] The FPGA chip is used to read the SDO write data from the data cache address and encapsulate it into the SDO request frame when the instruction operation type is a write operation;

[0018] The FPGA chip is also used to parse the received SDO response frame and write it into the data cache address when the instruction operation type is a read operation.

[0019] In this way, the FPGA-based EtherCAT master station topology dynamic control system provided by this application is configured with an EtherCAT master station with an integrated FPGA chip. The EtherCAT master station is provided with a main network port and a redundant network port. The main network port is connected to multiple EtherCAT slaves in series. The access or disabling of the redundant network port enables the network topology to flexibly operate in a ring mode or a linear mode. The FPGA chip can detect the connection status of the redundant network port in real time, and dynamically control the connection status of the redundant network port through the ring network control module according to the reliability requirements of the application scenario, thereby realizing rapid switching between the two network topologies. When the Ethernet network environment is stable and the fault tolerance requirements are not high, the FPGA chip can switch the network topology to a linear mode to simplify the wiring and maintenance complexity. When the Ethernet network environment is risky and high reliability is required, the FPGA chip switches the network topology to a ring mode, using redundant links to improve the fault tolerance of the control system. The FPGA chip's ability to dynamically switch across network topologies, combined with its parallel processing capabilities, enables the control system to efficiently and in real time process EtherCAT protocol tasks, ensuring nanosecond-level high-precision synchronization between EtherCAT slaves and achieving low-latency deterministic control.

[0020] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 The following is a schematic diagram showing the structure of an FPGA-based EtherCAT master station topology dynamic control system according to an embodiment of the present application;

[0023] Figure 2 The linear network topology structure of an EtherCAT master station and multiple EtherCAT slave stations in an FPGA-based EtherCAT master station topology dynamic control system according to an embodiment of the present application is shown;

[0024] Figure 3 The ring mode network topology structure of the EtherCAT master station and multiple EtherCAT slave stations in the FPGA-based EtherCAT master station topology dynamic control system of the embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0026] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0027] like Figure 1 As shown, an embodiment of the present application provides an FPGA-based EtherCAT master station topology dynamic control system (hereinafter referred to as: control system), which includes an EtherCAT master station. The EtherCAT master station is integrated with an FPGA chip. The FPGA chip can be a field programmable gate array (Field-Programmable Gate Array) integrated circuit chip. The FPGA chip can include a distributed clock synchronization unit. The interior of the FPGA chip can include multiple logic processing modules, so the FPGA chip can perform multiple data processing operations simultaneously, which is particularly suitable for implementing parallel processing tasks.

[0028] Integrating an FPGA chip into the EtherCAT master can leverage the FPGA's parallel processing capabilities to handle EtherCAT protocol tasks that, in related technologies, require serial processing by the CPU and require high real-time performance. These tasks include assembling and parsing cluster frames, rapidly transmitting and receiving cluster frames, and real-time monitoring of EtherCAT slave status. Compared to related technologies that implement EtherCAT protocol tasks through software, FPGA chips offer high timeliness in executing these tasks, thus addressing the lack of real-time performance inherent in related technologies that rely on software to process the EtherCAT protocol.

[0029] The EtherCAT master is equipped with two physical network interfaces: a primary network port and a redundant network port. These two network ports can be configured as standard Ethernet interfaces (such as RJ45) and connected to the physical layer chip (PHY), which in turn is connected to the FPGA chip. The primary network port and the redundant network port are the channels for the EtherCAT master to communicate with external EtherCAT slaves. The primary network port is the default communication interface of the EtherCAT master. The redundant network port is the backup interface of the EtherCAT master. Although the redundant network port is physically connected, it may be in a connected state or a disabled state. The disabled state means that the redundant network port is not connected to any EtherCAT slave or is logically closed.

[0030] An EtherCAT master manages multiple EtherCAT slaves. EtherCAT slaves can be connected sequentially using standard Ethernet cables to form a slave chain. "Sequential connection" means the second EtherCAT slave is connected to the OUT port of the first slave, the third EtherCAT slave is connected to the OUT port of the second EtherCAT slave, and so on. The first slave is always connected to the EtherCAT master.

[0031] like Figure 2 As shown in Figure 1, the network topology between an EtherCAT master and multiple EtherCAT slaves can form a linear model. That is, all EtherCAT slaves are connected end to end via Ethernet cables, with the EtherCAT master connected to the head end of the multiple EtherCAT slaves to form a chain-like linear link.

[0032] When an EtherCAT master sends a cluster frame to an EtherCAT slave, the cluster frame originates from the EtherCAT master and passes through each EtherCAT slave in turn. Each EtherCAT slave extracts the input data and inserts the output data in real time before the cluster frame returns to the EtherCAT master. In online mode, cluster frames are sent and received via the master network port.

[0033] like Figure 3 As shown in Figure 1, the network topology between an EtherCAT master and multiple EtherCAT slaves can form a ring network. Unlike a linear network, in a ring network topology, the OUT port of each slave is connected back to the IN port of the redundant network port of the EtherCAT master, forming a closed ring link.

[0034] The ring mode of the network topology allows for the transmission of cluster frames over two data transmission links. When the EtherCAT master sends a cluster frame, it can traverse each EtherCAT slave in sequence along one direction of the ring link (for example, the direction starting from the primary network port). At the same time, the EtherCAT master can also be configured to send the same cluster frame in the opposite direction of the ring link (for example, the direction starting from the redundant network port). In this way, even if an EtherCAT slave or connection point on the ring link fails, causing the slave link to be interrupted, the cluster frame can still be transmitted through the other data transmission link, thereby improving the fault tolerance of the EtherCAT master.

[0035] During the transmission of cluster frames, the FPGA chip can use hardware timers and distributed clocks (DC) to achieve a synchronization deviation between EtherCAT slaves of better than 100ns within a 1ms communication cycle.

[0036] The FPGA chip is configured to continuously monitor the connection status of the redundant network ports. This monitoring can be achieved through the following methods: At the physical layer, the FPGA chip monitors the connection status of the redundant network ports through physical layer signals, such as detecting whether the redundant network ports have normal Ethernet signals. At the protocol layer, the FPGA chip monitors the connection status of the redundant network ports through protocol layer heartbeats or diagnostic messages. For example, an EtherCAT master determines whether a redundant network port is connected to an end slave by sending or receiving specific, non-business-related heartbeat or diagnostic messages.

[0037] Based on the above detection method, the FPGA chip can also further detect the connection status of the main network port to confirm whether the network topology formed between the current EtherCAT master station and multiple EtherCAT slave stations is "linear mode" or "ring mode". For example: If the FPGA chip detects that the main network port has an Ethernet signal, but the redundant network port has no Ethernet signal or is in a disabled state, the network topology is confirmed to be in linear mode. If the FPGA chip detects that the main network port is connected to the first-end slave station, and the redundant network port is also connected to the end slave station, and a ring link is formed in the data transmission (which can be confirmed by the transmission and return of diagnostic messages in the ring link), then the current network topology is confirmed to be in ring mode, which provides a basis for the dynamic control of the subsequent network topology.

[0038] The FPGA chip can dynamically switch the network topology between linear and ring modes by controlling the connection status of redundant network ports. Specifically, the FPGA chip can be configured with a ring network control module to achieve the switching of the network topology and monitor the connection status of the redundant network ports.

[0039] For example, in the case where the Ethernet network environment may be at high risk (for example, the connection cable of the EtherCAT slave may be physically damaged or the electromagnetic interference is strong), the FPGA chip can actively switch the network topology to ring mode. The specific operation is: the FPGA chip controls the activation of the redundant network port and connects the redundant network port to the end slave through a physical connection (such as relay control, network port automatic negotiation, etc.). After the network topology is switched to ring mode, the cluster frame can be transmitted separately through two independent data transmission links. Even if a disconnection occurs somewhere in the middle of the linear link (for example, an EtherCAT slave fails, the connector is loose, or the cable is broken), the cluster frame can still be transmitted through another data transmission link, skipping the protocol stack renegotiation process required by related technologies (such as EtherCAT network topology reconfiguration, EtherCAT slave state machine reset, etc.), thereby ensuring that even in harsh or unreliable industrial environments, EtherCAT protocol tasks can be carried out continuously, stably, and quickly, avoiding the risk of the entire control system being paralyzed due to a single point failure of the EtherCAT slave, and improving the continuity and security of the control system.

[0040] In a relatively stable Ethernet network environment with less demanding fault tolerance, the FPGA chip can switch the network topology to linear mode. The ring network control module within the FPGA chip can use control logic to disable or float redundant network ports, resulting in a network topology with simpler wiring, lower maintenance complexity, and fewer potential points of failure.

[0041] In this way, the FPGA-based EtherCAT master station topology dynamic control system provided by this application is configured with an EtherCAT master station with an integrated FPGA chip. The EtherCAT master station is provided with a main network port and a redundant network port. The main network port is connected to multiple EtherCAT slaves in series. The access or disabling of the redundant network port enables the network topology to flexibly operate in ring mode or linear mode. The FPGA chip can detect the connection status of the redundant network port in real time. It can not only identify whether the current network is in "linear mode" or "ring mode", but also dynamically control the connection status of the redundant network port through the ring network control module according to the reliability requirements of the application scenario, thereby realizing rapid switching between the two network topologies. When the Ethernet network environment is stable and the fault tolerance requirements are not high, the FPGA chip can switch the network topology to linear mode to simplify the wiring and maintenance complexity. When the Ethernet network environment is risky and high reliability is required, the FPGA chip switches the network topology to ring mode, using redundant links to improve the fault tolerance of the control system. The FPGA chip's ability to dynamically switch across network topologies, combined with its parallel processing capabilities, enables the control system to efficiently and in real time process EtherCAT protocol tasks, ensuring nanosecond-level high-precision synchronization between EtherCAT slaves and achieving low-latency deterministic control.

[0042] In some embodiments, when the FPGA chip detects that the redundant network port is in a disabled state, it connects the redundant network port to the end slave station to switch the network topology from a linear mode to a ring mode.

[0043] Specifically, the ring network control module within the FPGA chip can have preconfigured logic for detecting the network topology and the connection status of redundant network ports. During control system initialization or operation, if the FPGA chip detects that the redundant network port is currently disabled (for example, when initially configured in linear mode, the redundant network port may be physically floating or logically disabled), and the control system needs to switch the network topology to ring mode to improve redundancy based on application requirements or fault recovery strategies, the FPGA chip initiates the switching process.

[0044] Specifically, in the switching process, the FPGA chip sends control instructions to the relevant hardware interface, physically or logically enables the redundant network port, and connects it to the OUT interface of the end slave in the current slave link. After the connection is completed, the FPGA chip verifies the correct establishment of the ring link by sending a specific diagnostic message (for example, a cluster frame with a specific tag). The diagnostic message is sent from the main network port and should be received by the redundant network port after passing through all EtherCAT slaves. If it is received successfully, it confirms that the network topology has been switched to ring mode; if it is not received, it may indicate that the connection failed. The FPGA chip can retry or maintain the current state and report an error.

[0045] In some embodiments, when the FPGA chip detects that the redundant network port has not received a response frame returned by the EtherCAT slave for a preset period of time, the connection between the redundant network port and the end slave is disconnected.

[0046] Specifically, when the ring network control module within the FPGA chip detects that the redundant network port has not received the expected response frame within a preset time (for example, 100ms), the FPGA chip determines that there may be a fault in the current ring topology, such as a link interruption between the redundant network port and the end slave station, or a fault in the end slave station itself. To prevent erroneous data from circulating on the damaged link and affecting normal communication on the primary network port, the FPGA chip's control logic performs a disconnect operation.

[0047] The disconnection operation is specifically manifested as the FPGA chip sending a control command to the relevant hardware interface, placing the redundant network port in a disabled or floating state, thereby disconnecting it from the OUT interface of the terminal slave station. In this way, the network topology degenerates from a ring mode to a linear mode, that is, the primary network port is connected to the head-end slave station, and the redundant network port no longer participates in communication. The clustered frames will be sent and received through the primary network port. At the same time, the FPGA chip will continuously monitor the status of the primary network port and decide, based on a preset strategy, whether to attempt to switch the network topology back to a ring mode or maintain the current linear mode. The FPGA chip's automatic fault isolation and topology recovery capabilities further enhance the robustness and reliability of the control system.

[0048] In some embodiments, when the network topology is in ring mode, when the FPGA chip detects that the connection between two EtherCAT slaves is disconnected, it sends a cluster frame through the main network port and redundant network port of the EtherCAT master station respectively, so that the cluster frame reaches all EtherCAT slaves.

[0049] like Figure 1Specifically, a slave status monitoring module can be configured within the FPGA chip. This module continuously monitors the status of EtherCAT slaves and the connectivity of the network topology during operation in a ring-shaped network topology. When the slave status monitoring module detects a disconnection in the data transmission link between two adjacent EtherCAT slaves in the network topology, resulting in the ring link being split into two independent data transmission sub-chains, the FPGA chip sends a clustered frame simultaneously or sequentially from the primary and redundant network ports.

[0050] The clustered frames sent by the primary network port will traverse all EtherCAT slaves connected to the primary network port until a breakpoint is encountered. Similarly, the clustered frames sent by the redundant network port will traverse all EtherCAT slaves connected to the redundant network port until a breakpoint is encountered. In this way, even if the ring link is broken, the FPGA chip can still ensure that the clustered frames sent by the EtherCAT master can reach every EtherCAT slave in the network topology, thereby maintaining monitoring and control of all EtherCAT slaves and maximizing visibility and control capabilities over all EtherCAT slaves.

[0051] In some embodiments, when the network topology is in linear mode or ring mode, when the FPGA chip detects that the main network port has not received a response frame returned from the EtherCAT slave station for a preset period of time, it sends a cluster frame to multiple EtherCAT slave stations through the redundant network port and receives response frames returned by multiple EtherCAT slave stations.

[0052] Specifically, the ring network control module within the FPGA chip continuously monitors the communication status of the main network port. Regardless of whether the current network topology is linear or ring, if the ring network control module detects that the main network port has not received a valid response frame from the EtherCAT slave within a preset time, it determines that the main network port may be faulty.

[0053] To maintain control system operation, the FPGA chip initiates redundancy switching and reconfigures the redundant network port, currently in standby mode, switching its functionality from redundant or suspended to communicating with the end slave. For example, the FPGA chip updates the registers or state machine used to handle EtherCAT communication logic so that subsequent cluster frame transmission and reception operations are performed through the redundant network port, bypassing the faulty primary network port.

[0054] After configuring the redundant network port, the FPGA chip reestablishes connections to all EtherCAT slaves through the redundant network port. This is achieved through initialization or resynchronization. The FPGA chip continues to send messages and listen for responses until it confirms that all EtherCAT slaves have reconnected and are correctly identified, completing the redundancy switchover and reestablishing connections. The FPGA chip's redundant switching of the primary network port improves the control system's availability and fault tolerance in the event of a primary network port failure.

[0055] In some embodiments, the EtherCAT master station further includes a CPU unit connected to the FPGA chip via a communication interface, and the CPU unit is communicatively connected to at least one EtherCAT slave station via the FPGA chip.

[0056] Specifically, the CPU unit can be connected to the FPGA chip through the QSPI and FSMC bus interfaces, and the CPU is communicatively connected to at least one EtherCAT slave station through the link layer module integrated in the FPGA chip.

[0057] The CPU (Central Processing Unit) is the core control component of the EtherCAT master station, responsible for processing the application layer functions of the EtherCAT protocol, such as EtherCAT slave station configuration, data logic processing, slave station control, etc.

[0058] The CPU unit communicates with EtherCAT slaves via the link layer module integrated within the FPGA chip. This module handles the link layer functions of the EtherCAT protocol, such as packet encapsulation and decapsulation, and error detection and correction. This allows the CPU unit to focus on application layer processing while offloading underlying network communication tasks to the FPGA chip, reducing control system communication jitter and improving real-time performance.

[0059] For example, when the CPU needs to send an SDO configuration instruction to an EtherCAT slave, it can write the relevant data to the data cache address configured in the FPGA chip and send the control instruction to the FPGA chip via the FSMC bus interface. After receiving the instruction, the FPGA chip reads the data from the data cache address, encapsulates it into a bundled frame in the EtherCAT protocol format, and then sends it to the EtherCAT slave through the primary network port or redundant network port.

[0060] Similarly, when an EtherCAT slave sends an SDO request frame, the FPGA passes it to the CPU via the FSMCF bus interface. After processing the SDO request frame, the CPU writes the result to the designated data cache address and notifies the FPGA. Following the instructions, the FPGA encapsulates the data in the data cache address into an SDO response frame and sends it to the CPU via the FSMC bus interface. Alternatively, the FPGA directly encapsulates the data into an SDO response frame and sends it to the requesting EtherCAT slave via the primary or redundant network port.

[0061] In this way, through the collaborative work of the CPU unit and FPGA chip, the EtherCAT master station can achieve efficient and reliable data communication to meet the needs of various complex application scenarios.

[0062] In some embodiments, the CPU unit is configured to parse configuration parameters of the EtherCAT slave and generate PDO configuration instructions for periodic process data and / or SDO configuration instructions for aperiodic service data according to the configuration parameters.

[0063] The FPGA chip is used to periodically send PDO bundle frames to corresponding EtherCAT slaves among multiple EtherCAT slaves according to PDO configuration instructions; and the FPGA chip is also used to send SDO request frames to corresponding EtherCAT slaves among multiple EtherCAT slaves within the communication interval between two adjacent PDO bundle frames according to SDO configuration instructions.

[0064] Specifically, after parsing the EtherCAT slave's XML configuration file, the CPU extracts configuration parameters related to periodic process data (PDOs) and aperiodic service data (SDOs). Based on these configuration parameters, the CPU generates specific PDO and SDO configuration instructions. These instructions contain information such as the communication cycle, data mapping relationships, input / output data addresses, and SDO operation type (read / write), object dictionary index, and data cache address required for the FPGA chip to perform the corresponding communication operation.

[0065] like Figure 1 As shown, the FPGA chip can be configured with a PDO state management module and an SDO state management module. After the FPGA chip receives the PDO configuration instruction and the SDO configuration instruction, it will be stored in the PDO state management module and the SDO state management module respectively.

[0066] For PDO communication, the FPGA chip periodically reads real-time control data from the output data address specified by the PDO configuration instructions stored in the PDO state management module, based on the communication cycle defined by the PDO configuration instructions. Based on the data mapping relationship defined in the PDO configuration instructions, the FPGA chip encapsulates the read real-time control data into PDO cluster frames that comply with the EtherCAT protocol specification and sends them to the target EtherCAT slave through the primary or redundant network port.

[0067] For SDO communication, the FPGA chip sends SDO request frames to corresponding EtherCAT slaves within the periodic communication interval between two PDO bundle frames, based on the operation type specified in the SDO configuration instructions. This ensures that SDO communication does not interfere with the periodic transmission of PDOs. The FPGA chip flexibly handles aperiodic service requests while ensuring efficient exchange of real-time control data.

[0068] Thus, the control device provided by the embodiments of the present application achieves a clear division of labor and coordination between the application-layer configuration and underlying network communication of the EtherCAT master station by having the CPU unit generate PDO configuration instructions and / or SDO configuration instructions, and the FPGA chip executes specific communications based on the PDO configuration instructions and / or SDO configuration instructions. The CPU unit focuses on logic and configuration, while the FPGA chip focuses on real-time communication execution, thus ensuring the efficient and reliable operation of the EtherCAT master station.

[0069] In some embodiments, the FPGA chip is further configured to stop the currently transmitted SDO request frame (if it is being transmitted) at a predetermined periodic sending moment of the PDO bundle frame, and to send the PDO bundle frame corresponding to the predetermined periodic sending moment. Figure 1 As shown in FIG, for an SDO request frame that is not sent completely due to an interruption, the FPGA chip will temporarily store it in its internal interaction buffer module.

[0070] After the PDO bundle frame is sent, the FPGA chip checks its interaction buffer module to see if there is an SDO request frame waiting to be sent. If so, the FPGA chip retrieves the SDO request frame from the interaction buffer module and continues to send the SDO request frame in the next available communication interval until the SDO request frame is sent.

[0071] This allows the FPGA chip to execute the periodic transmission of SDO request frames according to the SDO configuration instructions within the PDO communication interval, even if they are required to be sent within the PDO communication interval. This ensures that the periodic transmission of PDO bundle frames is not delayed. Furthermore, by temporarily storing unfinished SDO request frames in a buffer and continuing to send them within the next PDO communication interval, communication initiated according to the SDO configuration instructions is ultimately completed. This ensures the real-time nature of periodic process data communication, enabling coordinated processing of communications executed according to PDO and SDO configuration instructions.

[0072] In some embodiments, the CPU unit generates a PDO configuration instruction including a communication cycle, a data mapping relationship, an input data address, and an output data address according to the configuration parameters of the EtherCAT slave station, and the PDO configuration instruction is transmitted to the FPGA chip.

[0073] After the FPGA chip receives the PDO configuration instruction, the PDO status management module performs timing operations based on the communication cycle and data mapping relationship defined in the PDO configuration instruction. At the arrival of each communication cycle, the FPGA chip reads the corresponding real-time control data from the output data address specified by the PDO configuration instruction. Based on the EtherCAT protocol stack, the FPGA chip encapsulates the read real-time control data, combines it with the data mapping relationship, and encapsulates it into a PDO cluster frame. This frame is then sent to the corresponding EtherCAT slave station through the primary or redundant network port of the EtherCAT master station (depending on the current network topology).

[0074] At the same time, the FPGA chip is also responsible for processing feedback from the EtherCAT slave. When the FPGA chip receives a PDO bundle frame from the EtherCAT slave, the PDO state management module in the FPGA chip parses the bundle frame and, based on the data mapping relationship, writes the PDO input data contained therein to the input data address specified in the PDO configuration instruction.

[0075] After completing the data writing, the FPGA chip performs a notification operation, that is, sends a data update notification to the CPU unit, so that the CPU unit knows the update of the data in the input data address, so that it can read and utilize the real-time status or feedback information from the EtherCAT slave station in time for further application layer processing or logical judgment.

[0076] In some embodiments, the CPU unit generates an SDO configuration instruction including an instruction operation type and a data cache address according to configuration parameters of the EtherCAT slave station, and the CPU unit transmits the SDO configuration instruction to the FPGA chip.

[0077] After the FPGA chip receives an SDO configuration instruction, the SDO status management module checks the instruction operation type defined in the instruction. If the instruction operation type is configured as a write operation, the FPGA chip performs the following operations: The FPGA chip reads the corresponding SDO write data from the data cache address specified in the SDO configuration instruction. Based on the instruction operation type (write operation) and the data read from the data cache address, the FPGA chip encapsulates the write data into an SDO request frame according to the EtherCAT protocol stack. The SDO request frame is then sent to the corresponding EtherCAT slave in the multiple EtherCAT slaves within the communication interval between two adjacent PDO bundle frames.

[0078] When the instruction operation type is a read operation, the FPGA chip performs a different operation flow. Based on the instruction operation type (read operation) and possible object dictionary index information (defined in the SDO configuration instruction), the FPGA chip sends the corresponding SDO request frame to the corresponding EtherCAT slave in the multiple EtherCAT slaves, requesting to read data from the specific object dictionary.

[0079] After receiving and processing the corresponding SDO request frame, the EtherCAT slave returns an SDO response frame to the EtherCAT master. The SDO response frame is the EtherCAT slave's response to the SDO request frame and contains the requested data or operation results. After receiving the SDO response frame, the FPGA chip parses it. Once parsed, the FPGA writes the valid data contained in the SDO response frame to the data buffer address specified in the SDO configuration directive. Through this process, the FPGA chip accurately executes the reading and writing of the aperiodic service data defined by the SDO configuration directive.

[0080] In this way, by implementing the SDO communication process through the FPGA chip, the SDO communication operations (such as data reading and writing) are transferred from the CPU unit to the FPGA chip for execution, utilizing the parallel processing capability and real-time advantages of the FPGA chip, reducing the burden on the CPU unit and allowing the CPU unit to focus on application layer logic processing, thereby achieving efficient and reliable management of EtherCAT slave station configuration parameters and service requests, and improving the overall performance and response speed of the entire EtherCAT master station system.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An EtherCAT master station topology dynamic control system based on FPGA, characterized in that: An EtherCAT master station is integrated with an FPGA chip, and the EtherCAT master station is configured with a primary network port and a redundant network port; A plurality of EtherCAT slave stations, the EtherCAT slave stations are connected in sequence, and the main network port of the EtherCAT master station is connected to the head end slave station of the plurality of EtherCAT slave stations; The FPGA chip is used to confirm whether the network topology formed by the EtherCAT master station and the EtherCAT slave station is a linear mode or a ring mode according to the connection status of the redundant network port; wherein, in the linear mode, the redundant network port is in a disabled state, and in the ring mode, the redundant network port is connected to the end slave station among the multiple EtherCAT slave stations; The FPGA chip is also used to control the connection status of the redundant network port to switch the network topology between the linear mode and the ring mode.

2. The FPGA-based EtherCAT master station topology dynamic control system according to claim 1, characterized in that: When the FPGA chip detects that the redundant network port is in the disabled state, it connects the redundant network port to the terminal slave station to switch the network topology from the linear mode to the ring mode.

3. The FPGA-based EtherCAT master station topology dynamic control system according to claim 1, characterized in that: When the FPGA chip detects that the redundant network port has not received a response frame returned from the EtherCAT slave station for a preset period of time, the connection between the redundant network port and the terminal slave station is disconnected.

4. The FPGA-based EtherCAT master station topology dynamic control system according to claim 1, characterized in that: When the network topology is in the ring mode, when the FPGA chip detects that there is at least one breakpoint in the multiple EtherCAT slave stations, it sends a cluster frame through the main network port and the redundant network port respectively, so that the cluster frame reaches all the EtherCAT slave stations.

5. The FPGA-based EtherCAT master station topology dynamic control system according to claim 1, characterized in that: When the network topology is in linear mode or ring mode, when the FPGA chip detects that the main network port has not received a response frame returned from the EtherCAT slave station for a preset period of time, it sends a cluster frame to the multiple EtherCAT slave stations through the redundant network port and receives response frames returned by the multiple EtherCAT slave stations.

6. The FPGA-based EtherCAT master station topology dynamic control system according to any one of claims 1 to 5, characterized in that: The EtherCAT master station further includes a CPU unit connected to the FPGA chip via a communication interface, and the CPU unit is communicatively connected to at least one EtherCAT slave station via the FPGA chip.

7. The FPGA-based EtherCAT master station topology dynamic control system according to claim 6, characterized in that: The CPU unit is used to parse the configuration parameters of the EtherCAT slave station and generate PDO configuration instructions for periodic process data and / or SDO configuration instructions for aperiodic service data according to the configuration parameters; The FPGA chip is used to periodically send PDO bundle frames to corresponding EtherCAT slaves among the multiple EtherCAT slaves according to the PDO configuration instructions; and the FPGA chip is also used to send SDO request frames to corresponding EtherCAT slaves among the multiple EtherCAT slaves within the communication interval between two adjacent PDO bundle frames according to the SDO configuration instructions.

8. The FPGA-based EtherCAT master station topology dynamic control system according to claim 7, characterized in that: The FPGA chip is also used to stop the currently transmitted SDO request frame at a predetermined periodic sending moment of the PDO bundle frame, and send the PDO bundle frame corresponding to the predetermined periodic sending moment; and temporarily store the SDO request frame that has not been sent in the cache area of ​​the FPGA chip.

9. The FPGA-based EtherCAT master station topology dynamic control system according to claim 7, characterized in that: The PDO configuration instruction includes a communication cycle, a data mapping relationship, an input data address, and an output data address; The FPGA chip is used to read the real-time control data from the output data address at regular intervals according to the communication cycle in the PDO configuration instruction and the data mapping relationship, and encapsulate the real-time control data into the PDO bundle frame; The FPGA chip is also used to receive the PDO input bundle frame fed back by the EtherCAT slave station, write the PDO input data indicated by the PDO input bundle frame into the input data address; and send a data update notification to the CPU unit.

10. The FPGA-based EtherCAT master station topology dynamic control system according to claim 7, characterized in that: The SDO configuration instruction includes an instruction operation type and a data cache address; The FPGA chip is used to read the SDO write data from the data cache address and encapsulate it into the SDO request frame when the instruction operation type is a write operation; The FPGA chip is also used to parse the received SDO response frame and write it into the data cache address when the instruction operation type is a read operation.

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