A data packet sending method, a data processing unit, a host and a network card
By acquiring and parsing the cache descriptor on the host side, reading and sending aggregated data packets, the problem of low PCIe bandwidth utilization in the Virtio virtualization protocol is solved, achieving more efficient data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING JAGUAR MICROSYSTEMS CO LTD
- Filing Date
- 2025-06-05
- Publication Date
- 2026-05-22
Smart Images
Figure CN120658696B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of network data transmission technology, specifically to a data packet sending method, a data processing unit, a host, a network interface card (NIC), and a computer program product. Background Technology
[0002] Network packets are small data packets in network transmission. When receiving network packets based on the traditional Virtio virtualization protocol, each time a Virtio network device sends a network packet, it needs to read a cached descriptor from the host-side descriptor table via PCIe (Peripheral Component Interconnect Express). Based on the read cached descriptor, it reads a network packet from the host-side descriptor table buffer and notifies the host software. However, because the data volume of network packets is small, only a small amount of data is read each time, resulting in very low bandwidth utilization of PCIe. Summary of the Invention
[0003] The purpose of this application is to provide a data packet sending method, a data processing unit, a host, a network card, and a computer program product to improve the bandwidth utilization of PCIe for sending network small packets based on the Virtio virtualization protocol.
[0004] To achieve the above objectives, according to a first aspect of this application, a data packet sending method is provided, the method comprising:
[0005] Receive a packet sending notification from the host, and obtain a first cache descriptor and a second cache descriptor; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet;
[0006] The aggregated data packet is read from the cache unit on the host side according to the address of the cache unit;
[0007] Extract the individual data packets from the aggregated data packet according to the length of each individual data packet;
[0008] The extracted data packets are sent to the peer device.
[0009] Optionally, obtaining the first cache descriptor and the second cache descriptor includes:
[0010] The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.
[0011] Optionally, extracting the individual data packets from the aggregated data packet based on their lengths includes:
[0012] Based on the cache line alignment principle, each data packet is extracted from the aggregated data packet according to the length of each data packet.
[0013] Optionally, the second cache descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each network packet, and the multiple length fields with the same bit width are used to describe the actual length of each data packet.
[0014] In the above method, when network packets need to be sent, the data processing unit receives a packet sending notification from the host, obtains a first cache descriptor and a second cache descriptor, reads the aggregated data packet according to the first cache descriptor, and parses the aggregated data packet according to the second cache descriptor to obtain each original network packet. While maintaining compatibility with the existing Virtio protocol, this method increases the amount of network packet data that the data processing unit can read each time, reduces the number of times descriptors and data packets are read, and enables the PCIe bus to transmit data more efficiently, thereby improving PCIe bandwidth utilization. The data processing unit does not need to frequently read cache descriptors from the host-side descriptor table through PCIe, thus reducing the PCIe access frequency and overhead. The aggregated data packet transmission method reduces data transmission fragmentation, enabling the data processing unit to process and send data packets more efficiently, improving overall data transmission efficiency.
[0015] According to a second aspect of this application, a data packet sending method is provided, the method comprising:
[0016] Each data packet to be sent is written sequentially into the host-side buffer unit according to the principle of buffer line alignment to form an aggregated data packet;
[0017] A first cache descriptor and a second cache descriptor are generated, and the first cache descriptor and the second cache descriptor are written into the descriptor table on the host side; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet;
[0018] A packet sending notification is sent to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
[0019] Optionally, the first cache descriptor further includes a next cache descriptor index; the next cache descriptor index is the storage location of the second cache descriptor in the descriptor table on the host side.
[0020] Optionally, the second cache descriptor includes a mode field and multiple length fields with the same bit width. The mode field is used to describe the bit width corresponding to the actual length of each network packet in the current mode, and the multiple length fields with the same bit width are used to describe the actual length of each data packet.
[0021] In the above method, the host aggregates multiple network packets into a single aggregated data packet and stores it in a host-side cache unit. The length of each network packet is stored in a second cache descriptor. This allows the data processing unit to read the aggregated data packet based on the first cache descriptor and parse it using the second cache descriptor to obtain the individual original network packets. While maintaining compatibility with the existing Virtio protocol, this method increases the number of descriptors and network packet data that the data processing unit can read at once, reducing the number of descriptor and data packet reads. This allows for more efficient data transmission on the PCIe bus, improving PCIe bandwidth utilization. The data processing unit does not need to frequently read cached descriptors from the host-side descriptor table via PCIe, thus reducing PCIe access frequency and overhead. Furthermore, the aggregated data packet transmission method reduces data transmission fragmentation, enabling the data processing unit to process and send data packets more efficiently, improving overall data transmission efficiency.
[0022] According to a third aspect of this application, a data processing unit is provided, comprising:
[0023] The descriptor acquisition module is used to receive a packet sending notification sent by the host and acquire a first cache descriptor and a second cache descriptor; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet;
[0024] The data read module is used to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;
[0025] The data packet parsing module is used to extract the individual data packets from the aggregated data packet according to the length of each individual data packet;
[0026] The data packet sending module is used to send the extracted data packets to the peer device.
[0027] Optionally, the descriptor acquisition module is specifically used for:
[0028] The first cache descriptor and the second cache descriptor are read from the host side using a single PCIe read operation.
[0029] Optionally, the data packet parsing module is specifically used for:
[0030] Based on the cache line alignment principle, each data packet is extracted from the aggregated data packet according to the length of each data packet.
[0031] According to a fourth aspect of this application, a host is provided, comprising:
[0032] The write data module is used to write the individual data packets to be sent into the cache unit on the host side in order according to the principle of cache line alignment to form an aggregated data packet;
[0033] The write descriptor module is used to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into the descriptor table on the host side; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet contained in the aggregate data packet;
[0034] The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
[0035] According to a fifth aspect of this application, a network interface card (NIC) is provided, including the data processing unit as described above and / or the host as described above.
[0036] According to a sixth aspect of this application, a computer program product is provided, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in the first or second aspect. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a flowchart of a data packet sending method according to Embodiment 1 of this application.
[0039] Figure 2This is a schematic diagram of a Virtio system framework in an embodiment of this application.
[0040] Figure 3 This is a flowchart illustrating the network data transmission between the DPU and the host in the Virtio 1.0 protocol Split mode as described in this application embodiment.
[0041] Figure 4 This is a flowchart illustrating the network data transmission between the DPU and the host in the Packed mode of the Virtio 1.0 protocol in this embodiment of the application.
[0042] Figure 5 This is a simplified schematic diagram of the Virtio system in the embodiments of this application.
[0043] Figure 6 This is a schematic diagram of the data packet transmission direction delay model in an embodiment of this application.
[0044] Figure 7 This is a schematic diagram illustrating the data packet transmission principle using Split mode as an example in this application embodiment.
[0045] Figure 8 This is a schematic diagram of the field structure of the second cache descriptor in Embodiment 1 of this application.
[0046] Figure 9 This is a flowchart of a data packet sending method according to Embodiment 2 of this application. Detailed Implementation
[0047] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.
[0048] See Figure 1 Embodiment 1 of this application provides a data packet sending method applied in a data processing unit (DPU), wherein the data processing unit (DPU) transmits data with a host. The method includes:
[0049] Step S11: Receive a packet sending notification sent by the host, and obtain a first cache descriptor and a second cache descriptor; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet.
[0050] Specifically, for example, such as Figure 2The diagram illustrates a system for implementing a Virtio backend device based on a DPU (Data Processing Unit). A single DPU chip can support multiple virtual machines (VMs), each VM can run multiple Guest OSs, and the Virtio frontend driver runs within the Guest OS. Simultaneously, a single VM can load multiple Virtio frontend drivers. Virtio uses Virt-queues to implement its I / O mechanism; each Virt-queue is a queue that carries a large amount of data. virtio-net is typically used in pairs, with one queue for sending and one for receiving. The host in step S11 refers to a virtual machine (VM), which can also be understood as... Figure 2 Guest OS 0~n; backend devices refer to Figure 2 The components include Virtio-net, Virtio-crypto, and Virtio-blk. Specifically, assuming the host wants to send network data to the DPU, firstly, the host can add the buffer containing the data to the Virt-queue using the function `Virt-queue_add_buf`, then call the `Virt-queue_kick` function. `Virt-queue_kick` calls the `Virt-queue_notify` function, notifying the DPU by writing data to a register. The DPU then calls `Virt-queue_get_buf` to retrieve the received data from the Virt-queue.
[0051] The following describes the network data transmission process between the hardware DPU and the host in the traditional packed and split modes using the Virtio protocol.
[0052] In Split mode, the host and DPU communicate via a Virt-queue to send network data, as follows: Figure 3 As shown, the specific steps are as follows:
[0053] Step 1: The host-side driver writes the data packet into the host-side buffer, assembles the buffer's base address, length, and other information into a buffer descriptor entry, fills it into the descriptor table, fills the header descriptor id into the entry of the available ring (avring), and updates the available ring index.
[0054] Step 2: The host sends a send notification to the DPU;
[0055] Step 3: The DPU parses the send notification, looks up the queue-related configuration information stored locally, obtains the address of each ring, and then initiates a request to read the avring index and avring entry.
[0056] Step 4: The DPU parses the relevant information of the descriptor table entry based on the read-back entering entry, and initiates a request for the Descriptor Table (reading the cache descriptor) based on this information;
[0057] Step 5: The DPU parses the entire buffer data information based on the entry information of the Descriptor Table read back, initiates a read buffer request, processes the read data, and sends it to the destination port;
[0058] Step 6: The DPU updates the entries for the used ring on the host side, including the buffer ID and buffer length;
[0059] Step 7: DPU updates the host-side used ring index;
[0060] Step 8: The DPU sends an MSI-X interrupt to the host to inform the host that the data transmission is complete.
[0061] In Packed mode, the host and DPU communicate via a Virt-queue to transmit network data, as follows: Figure 4 As shown, the specific steps are as follows:
[0062] Step 1: The host-side driver writes data to the host-side buffer, assembles the buffer information into an entry, and then fills it into the entry in the descriptor table, updating the local available ring wrap cnt.
[0063] Step 2: The host sends a send notification to the DPU;
[0064] Step 3: The DPU parses the send notification, looks up the configuration information related to the queue stored locally, obtains the ring base address, and then initiates a request to read the Descriptor Table entry;
[0065] Step 4: The DPU parses the address, length and other information of the buffer based on the read Descriptor Table entry, initiates a request to read the buffer data, and sends the read data to the destination port;
[0066] Step 5: The DPU updates the host-side Descriptor Table, including the buffer ID and wrap cnt;
[0067] Step 6: The DPU sends an MSI-X interrupt to the host to inform the host that the data transmission is complete.
[0068] Based on the above process analysis, it can be seen that the packed mode simplifies the ring structure compared to the split mode. It reduces the original three rings (avring, descriptor table, and usedring) to a single descriptor table. The avring wrap_cnt replaces the function of the avring indicating the producer index, and the ushering wrap_cnt replaces the function of the usedring indicating the consumer index. The packed mode operates on two fewer rings than the split mode, effectively reducing the number of PCIe operations per I / O. Since the physical bandwidth of PCIe is generally a decisive factor affecting performance, the packed mode offers significantly higher packet transmission performance than the split mode.
[0069] exist Figure 2 In the system, the performance of small packets in the sending direction is an important indicator of DPU capability. Due to the limitations of the Virtio virtualization protocol, the performance of small packets in the sending direction in packed mode can only reach a maximum of 250Mpps, and split is even lower, reaching less than 200Mpps. Moreover, when the software processes I / O, it needs to handle complex protocol processes for both large and small packets, so the efficiency of small packet processing is very low. In view of this, the method in this embodiment is used to improve the processing efficiency of network small packets.
[0070] The method in this embodiment is applicable to Split mode and Packed mode. When the data processing unit receives a packet sending notification from the host (informing that there is a new data packet to be sent), it obtains the first cache descriptor and the second cache descriptor from the host side. The first cache descriptor and the second cache descriptor are written into the descriptor table by the host.
[0071] The address of the cache unit on the host side points to the cache unit in the host memory used to store aggregated data packets, and the data processing unit reads the aggregated data packets from the cache unit at this address.
[0072] The aggregation identifier indicates that the cache unit stores aggregated data packets, which are data packets composed of multiple small packets. The data processing unit needs to extract each network small packet from the aggregated data packet after reading it.
[0073] Step S12: Read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;
[0074] Specifically, when the host prepares data, it writes multiple small network packets into the cache unit in order according to the cache line alignment principle to form an aggregated data packet. When the data processing unit reads the data packet, it reads the aggregated data packet from the cache unit through a single PCIe read operation, thereby realizing the reading of multiple small packet data through a single PCIe operation.
[0075] Step S13: Extract each data packet from the aggregated data packet according to the length of each data packet.
[0076] Specifically, when the host writes each data packet into the cache unit, it writes each data packet into the cache unit in sequence according to the cache line alignment principle. Therefore, after the data processing unit knows the length of each data packet, it can extract each data packet from the aggregated data packet in sequence.
[0077] Step S14: Send the extracted data packet to the peer device.
[0078] This embodiment considers the Virtio-net hardware offload scenario, where Virtio-net sends network data, simplifying the model as follows: Figure 5 As shown, the host is responsible for preparing data packets and filling in each ring of data. The data is forwarded via the DPU and sent out through Ethernet. The following section explains in detail how the method in this embodiment analyzes the latency of each major module in the path, identifies areas for improvement, and thus enhances performance.
[0079] TX direction delay model as follows Figure 6 As shown:
[0080] T1: The latency for the host to send a notification, which is the latency of one PCIe write, typically 1000ns;
[0081] T2: DPU reads available ring index latency per operation. Assuming a symmetric PCIe link latency model, the latency from request initiation to response reception is 2000ns (unique to Split mode).
[0082] T3: DPU reads available ring entry latency per cycle, with a latency value of 1000ns; (unique to split mode)
[0083] T4: DPU single read buffer descriptor latency, latency value is 1000ns;
[0084] T5: Delay of DPU reading TX packet (data packet in the sending direction) in a single operation, with a delay value of 1000ns;
[0085] T6: The delay when the DPE processes TX data and sends it to the MAC port. The delay value is the internal delay of the DPU.
[0086] t0: Internal queue scheduling latency of DPE, which is an indeterminate latency;
[0087] t1: The uncertain latency between T4 and T5. Different buffer descriptor structures correspond to different latency values. This latency is introduced by the fact that data from different queues on the same port cannot be interleaved within the DPU. For example, in a chained buffer descriptor structure, the DPU needs to cache all buffer descriptors before initiating a read data request.
[0088] The above analysis shows that the total processing time for one I / O data (i.e., one data packet) is:
[0089] The concept behind the method in this embodiment, T1+T2+T3+T4+T5+T6+t0+t1, is to reduce the total data processing time, thereby improving data transmission performance.
[0090] in:
[0091] The reduction in T1 time can be achieved by aggregating the number of notify calls on the host.
[0092] T2 has the same time as T1, and latency is reduced by aggregating the host index.
[0093] The reduction in T3 time allows for reading more entries in a single PCIe read operation, thereby improving PCIe read bandwidth utilization.
[0094] T4 is the latency for reading the host's descriptor entry. A single entry is 16 bytes, but the maximum number of bytes a PCIe word can carry is 1024 bytes. If a PCIe operation reads only one entry, the bandwidth utilization of 1.5% (16 ÷ 1024) is very low. This latency can be reduced by aggregating entries and reducing the number of PCIe reads.
[0095] T5 represents the latency for reading buffered data from the host, and it accounts for a very large proportion of the overall data flow. When processing large packets, the PCIe read bandwidth is already saturated and cannot be improved, resulting in the highest performance. However, when processing small packets, the effective bytes per PCIe read are relatively low, and the PCIe bandwidth is also relatively low.
[0096] T6, t0, and t1 are the processing latency within the DPU. High-performance DPUs can already achieve very low latency, so improvements are limited.
[0097] It should be noted that T4 and T5 are the times for reading entry and buffer data, which account for a large proportion of the I / O processing time. Especially when processing I / O data of chained descriptors, the benefits of effectively reducing the time of T4 and T5 are enormous.
[0098] Therefore, the method in this embodiment aims to reduce T4 and T5 latency. Reducing T4 latency mainly involves reducing the number of entries read by the DPU. That is, when the driver software prepares a single entry, it needs to carry information about multiple small packet I / O operations. When the DPU reads such an entry, it reads many small packet data into the DPU through a single PCIe read operation, increasing the effective data returned by each read request. This significantly reduces the number of PCIe reads, thereby reducing T5 latency. Based on the above idea, for the processing of network small packets, this embodiment reduces the number of PCIe reads by the DPU by increasing the amount of corresponding data packet information carried in a single entry, thus reducing I / O processing latency and improving performance.
[0099] In this embodiment, when network packets need to be sent, the data processing unit receives a packet sending notification from the host, obtains a first cache descriptor and a second cache descriptor, and parses the aggregated data packet according to the first and second cache descriptors to obtain each original network packet. This method, while maintaining compatibility with the existing Virtio protocol, increases the number of descriptors and network packet data that the data processing unit can read each time, while reducing the number of times descriptors and data packets are read, thereby improving PCIe bandwidth utilization. Furthermore, the aggregated data packet transmission method reduces data transmission fragmentation, enabling the data processing unit to process and send data packets more efficiently, thus improving overall data transmission efficiency.
[0100] In some embodiments, obtaining the first cache descriptor and the second cache descriptor in step S10 includes: reading the first cache descriptor and the second cache descriptor from the host side through a single PCIe read.
[0101] Specifically, the first cache descriptor includes:
[0102] Buffer Address: Points to the starting location of the actual data (aggregated data packet) in the host memory;
[0103] Buffer Length: This indicates the length of the buffer unit pointed to by the descriptor. This length can be the effective data length of the entire aggregated data packet or the maximum data length of the buffer unit, depending on the design requirements of the descriptor.
[0104] Aggregation Flag: Contains a flag indicating whether the packet pointed to by the descriptor is an aggregate packet;
[0105] Next Buffer Descriptor Index: This stores the index of the next descriptor in the descriptor chain. If the value of the next buffer descriptor index is 0, it indicates that this is the last descriptor in the chain. In this embodiment, the next buffer descriptor index of the first buffer descriptor is the same as the index of the second buffer descriptor. In specific implementations, the addresses of the first and second buffer descriptors are contiguous, thus multiple buffer descriptors, including the first and second buffer descriptors, can be read in a single PCIe read operation.
[0106] It should be noted that the first cache descriptor in this embodiment contains fields such as cache unit address, cache unit length, flag, and next cache descriptor index, which are the same as the field structure of the cache descriptor in the existing Virtio protocol, and therefore can be compatible with the existing Virtio protocol.
[0107] In some embodiments, the second cache descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each network packet in the pattern, and the multiple length fields with the same bit width are used to describe the actual length of each data packet.
[0108] Specifically, the host side needs to ensure that the actual length of each data packet filled into the second buffer descriptor under the same mode must correspond to the same bit width. Only in this way can the data processing unit identify where the next network packet length (Packet_len) is. In order to improve the utilization of the 16-byte (128-bit) length entry, bits [1:0] are used to represent the maximum value of a single Packet_len, that is, the bit width occupied, and it is named the mode field (mode), as shown in the following example:
[0109] mode=0: This means that a Packet_len is a maximum of 64 bytes, occupying 6 bits. lnn=0 means 1 byte, lnn=1 means 2 bytes, and so on, with lnn=63 meaning 64 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can transmit a maximum of 21 (126 ÷ 6) small packets of data smaller than 64 bytes.
[0110] mode=1: This means that a Packet_len is at most 128 bytes, occupying 7 bits. lnn=0 represents a length of 1 byte, lnn=1 represents a length of 2 bytes, and so on, with lnn=127 representing a length of 128 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of at most 18 (126 ÷ 7) small packets of data smaller than 128 bytes.
[0111] mode=2: This means that a Packet_len is at most 256 bytes, occupying 8 bits. lnn=0 represents a length of 1 byte, lnn=1 represents a length of 2 bytes, and so on, with lnn=255 representing a length of 256 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of at most 15 (126 ÷ 8) small packets of data smaller than 256 bytes.
[0112] mode=3: This means that a Packet_len is at most 512 bytes, occupying 9 bits. lnn=0 represents a length of 1 byte, lnn=1 represents a length of 2 bytes, and so on, with lnn=511 representing a length of 512 bytes. Therefore, the remaining 126 bits (128 bits - 2 bits) can complete the transmission of at most 14 (126 ÷ 9) small packets of data smaller than 512 bytes.
[0113] Using mode=0 as an example, the field layout is shown as follows: Figure 8 The meanings of each field are explained in the table below:
[0114]
[0115]
[0116] Other modes are similar to mode=0, and will not be shown here.
[0117] The data processing unit checks the aggregation identifier in the first cache descriptor. If the aggregation identifier is set to 1 (meaning it is an aggregated data packet), the data processing unit obtains the length of each network packet of the aggregated data packet according to the second cache descriptor.
[0118] The first cache descriptor in this embodiment is compatible with the existing Virtio protocol. Furthermore, by reading multiple cache descriptors in a single PCIe read operation, compared to the traditional method of performing a PCIe descriptor read operation for each small packet, the overhead of PCIe descriptor reading is significantly reduced. This is especially true when multiple network packets are aggregated, where this embodiment offers a significant performance advantage. The method in this application, while maintaining compatibility with the existing Virtio protocol, reduces PCIe overhead and improves system performance.
[0119] In some embodiments, each data packet included in the aggregated data packet is written to the cache unit on the host side according to the cache line alignment principle, and each data packet occupies an integer number of cache lines;
[0120] Specifically, cache line alignment refers to storing data on specific boundaries (usually multiples of the cache line size) to optimize data access efficiency. For example, if the host-side allocated free buffer is 4KB, and the network packets being sent are small, such as... Figure 2As shown, the host sequentially writes network packets from the target queue, such as Tx_small_packet_0, Tx_small_packet_1, Tx_small_packet_2, ..., Tx_small_packet_n-1, into the host-side buffer according to the cache line alignment principle. Taking a cache line of 64 bytes as an example, since the length of a network packet is not an integer multiple of 64 bytes, any portion of the packet shorter than 64 bytes will be padded with 0s to make it an integer multiple of 64 bytes. Therefore, each network packet occupies an integer multiple of a cache line, and each buffer contains storage space for multiple cache lines.
[0121] The step of extracting the individual data packets from the aggregated data packet based on the length of each individual data packet includes:
[0122] Based on the cache line alignment principle, each data packet is extracted from the aggregated data packet according to the length of each data packet.
[0123] Specifically, since the host writes each data packet to the cache unit according to the cache line alignment principle, the data processing unit, after reading the aggregated data packet, can also extract the individual data packets from the aggregated data packet according to the cache line alignment principle and the length of each individual data packet; for example... Figure 7 As shown, Descriptor Entry0 is the storage location of the first buffer descriptor, and Descriptor Entry1 is the storage location of the second buffer descriptor. The data processing unit assembles the data of length pkt_len0 taken from buffer0 into tx_small_packet0 according to pkt_len0 and sends it out. Then, according to the cache_line alignment principle, the corresponding length is filtered out. Similarly, the tx_small_packet1 message is parsed according to pkt_len1 and then sent out via Ethernet. All n small packets are parsed out in sequence and sent out via Ethernet.
[0124] In this embodiment, when network packets need to be sent, the data processing unit receives a packet sending notification from the host, obtains a first cache descriptor and a second cache descriptor, reads the aggregated data packet according to the first cache descriptor, and parses the aggregated data packet according to the second cache descriptor to obtain the individual original network packets. While maintaining compatibility with the existing Virtio protocol, this method reduces the number of times the data processing unit reads descriptors and data packets through PCIe, reducing PCIe access overhead and thus improving PCIe bandwidth utilization. Furthermore, the aggregated data packet transmission method reduces data transmission fragmentation, enabling the data processing unit to process and send data packets more efficiently, thereby improving overall data transmission efficiency.
[0125] Corresponding to the method in Embodiment 1, Embodiment 2 of this application provides a data packet sending method applied to the host side, see below. Figure 9 The method in Example 2 includes:
[0126] Step S21: Write the data packets to be sent into the cache unit on the host side in order according to the principle of cache line alignment to form an aggregated data packet;
[0127] Step S22: Generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into the descriptor table on the host side; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet contained in the aggregate data packet;
[0128] Step S23: Send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
[0129] In some embodiments, the first cache descriptor further includes a next cache descriptor index; the next cache descriptor index is the storage location of the second cache descriptor in the descriptor table on the host side.
[0130] In some embodiments, the second cache descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each network packet, and the multiple length fields with the same bit width are used to describe the length of each data packet.
[0131] It should be noted that the method in Embodiment 2 corresponds to the method in Embodiment 1. Any content not detailed in Embodiment 2 can be obtained by referring to the content of Embodiment 1. Therefore, no further details will be provided in Embodiment 2.
[0132] Embodiment 3 of this application provides a data processing unit, including:
[0133] The descriptor acquisition module is used to receive a packet sending notification sent by the host and acquire a first cache descriptor and a second cache descriptor; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet;
[0134] The data read module is used to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit;
[0135] The data packet parsing module is used to extract the individual data packets from the aggregated data packet according to the length of each individual data packet;
[0136] The data packet sending module is used to send the extracted data packets to the peer device.
[0137] It should be noted that the data processing unit in this embodiment corresponds to the method described in Embodiment 1. The contents of the data processing unit in this embodiment that are not described in detail can be obtained by referring to the contents of the method described in Embodiment 1, and will not be repeated in this embodiment.
[0138] Embodiment 4 of this application provides a host, including:
[0139] The write data module is used to write the individual data packets to be sent into the cache unit on the host side in order according to the principle of cache line alignment to form an aggregated data packet;
[0140] The write descriptor module is used to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into the descriptor table on the host side; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet contained in the aggregate data packet;
[0141] The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
[0142] It should be noted that the host in this embodiment corresponds to the method described in Embodiment 2. The contents of the host in this embodiment that are not described in detail can be obtained by referring to the contents of the method described in Embodiment 2, and will not be repeated in this embodiment.
[0143] Embodiment 5 of this application provides a network interface card (NIC) including the data processing unit described in Embodiment 3 and / or the host described in Embodiment 4.
[0144] Embodiment Six of this application provides a computer program product, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in Embodiment One.
[0145] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the method described in Embodiment 1 above. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the method of Embodiment 1 above.
[0146] Embodiment 7 of this application provides a computer program product, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in Embodiment 2.
[0147] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the method described in Embodiment 2 above. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the method of Embodiment 2 above.
[0148] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A data packet sending method, characterized in that, The method includes: The system receives a packet notification from the host and uses a single PCIe read operation to read the first cache descriptor and the second cache descriptor from the host side. The first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier. The aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet. The second cache descriptor includes the length of each data packet in the aggregate data packet. The aggregated data packet is read from the cache unit on the host side according to the address of the cache unit; Extract the individual data packets from the aggregated data packet according to the length of each individual data packet; The extracted data packets are sent to the peer device.
2. The method according to claim 1, characterized in that, The step of extracting the individual data packets from the aggregated data packet based on the length of each individual data packet includes: Based on the cache line alignment principle, each data packet is extracted from the aggregated data packet according to the length of each data packet.
3. The method according to any one of claims 1 to 2, characterized in that, The second cache descriptor includes a pattern field and multiple length fields with the same bit width. The pattern field is used to describe the bit width corresponding to the actual length of each network packet under the pattern, and the multiple length fields with the same bit width are used to describe the actual length of each data packet.
4. A data packet sending method, characterized in that, The method includes: Each data packet to be sent is written sequentially into the host-side buffer unit according to the principle of buffer line alignment to form an aggregated data packet; A first cache descriptor and a second cache descriptor are generated, and the first cache descriptor and the second cache descriptor are written into the descriptor table on the host side; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier; the aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet; A packet sending notification is sent to the data processing unit to drive the data processing unit to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
5. The method according to claim 4, characterized in that, The first cache descriptor also includes a next cache descriptor index; the next cache descriptor index is the storage location of the second cache descriptor in the descriptor table on the host side.
6. The method according to claim 4 or 5, characterized in that, The second cache descriptor includes a mode field and multiple length fields with the same bit width. The mode field is used to describe the bit width corresponding to the actual length of each network packet in the current mode, and the multiple length fields with the same bit width are used to describe the actual length of each data packet.
7. A data processing unit, characterized in that, include: The descriptor acquisition module is used to receive packet notifications sent by the host and read the first cache descriptor and the second cache descriptor from the host side using a single PCIe read operation; the first cache descriptor includes the address of the cache unit on the host side and an aggregation identifier, the aggregation identifier indicating that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet in the aggregate data packet; The data read module is used to read the aggregated data packet from the corresponding cache unit on the host side according to the address of the cache unit; The data packet parsing module is used to extract the individual data packets from the aggregated data packet according to the length of each individual data packet; The data packet sending module is used to send the extracted data packets to the peer device.
8. The data processing unit according to claim 7, characterized in that, The data packet parsing module is specifically used for: Based on the cache line alignment principle, each data packet is extracted from the aggregated data packet according to the length of each data packet.
9. A host computer, characterized in that, include: The write data module is used to write the individual data packets to be sent into the cache unit on the host side in order according to the principle of cache line alignment to form an aggregated data packet; The write descriptor module is used to generate a first cache descriptor and a second cache descriptor, and write the first cache descriptor and the second cache descriptor into the descriptor table on the host side; The first cache descriptor includes the address of the cache unit on the host side and the aggregation identifier; The aggregation identifier indicates that the data packet stored in the cache unit is an aggregate data packet, and the second cache descriptor includes the length of each data packet contained in the aggregate data packet; The notification module is used to send a packet sending notification to the data processing unit to drive the data processing unit to read the first cache descriptor and the second cache descriptor from the host side using a single PCIe read operation, and to read the aggregated data packet from the cache unit and process it according to the first cache descriptor and the second cache descriptor.
10. A network interface card (NIC), characterized in that, Includes the data processing unit as described in any one of claims 7 to 8.
11. A computer program product, characterized in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method described in any one of claims 1 to 6.