Semiconductor device and semiconductor memory device

Abstract

The embodiment of the invention relates to a semiconductor device and a semiconductor memory device. The semiconductor device includes: a first substrate having a first region, a second region, and a third region adjacent to the first region and the second region between the first region and the second region; a first transistor provided in the first region; a second transistor provided in the second region; a first trench provided in the first substrate in the third region; a first conductive layer provided above the first transistor, above the second transistor, and above the first trench, the first conductive layer continuing from the first region to the second region; and a first impurity region containing carbon, the first impurity region being provided at a position adjacent to the first trench in the first substrate.

Description

[0001] This application claims the benefit of priority based on Japanese Patent Application No. 2024-041746 (filing date: March 15, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a semiconductor device and a semiconductor memory device. Background Art

[0003] Semiconductor devices are known that have multiple transistors disposed on a semiconductor substrate. For example, in memory systems, as devices become increasingly miniaturized, there is a demand for smaller and denser configuration areas for semiconductor devices used in memory systems. However, due to limitations in the manufacturing process of semiconductor devices, there are limits to this miniaturization and densification. In particular, when the spacing between adjacent transistors decreases, leakage current between transistors sometimes increases. As a countermeasure to this leakage current, a technique is used to introduce impurities into the semiconductor substrate between transistors that shift the threshold of the transistors (U.S. Patent Application Publication No. 2003 / 0129802). Summary of the Invention

[0004] A semiconductor device according to one embodiment comprises: a first substrate having a first region, a second region, and a third region between the first region and the second region and adjacent to the first region and the second region; a first transistor arranged in the first region; a second transistor arranged in the second region; a first trench arranged in the first substrate in the third region; a first conductive layer arranged above the first transistor, above the second transistor, and above the first trench, and continuous from the first region to the second region; and a first impurity region arranged at a position of the first substrate adjacent to the first trench, and containing carbon.

[0005] According to this embodiment, a semiconductor device can be provided that suppresses leakage current between adjacent transistors and has a good junction breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram for explaining the configuration of a semiconductor device according to one embodiment.

[0007] Figure 2 This is a diagram for explaining an equivalent circuit showing the configuration of a memory cell array of a semiconductor device according to one embodiment.

[0008] Figure 3 This is a diagram for explaining the circuit configuration of a sense amplifier module of a semiconductor device according to one embodiment.

[0009] Figure 4 This is a diagram for explaining the circuit configuration of a row decoder of a semiconductor device according to one embodiment.

[0010] Figure 5 This is a cross-sectional view schematically illustrating a semiconductor device according to one embodiment.

[0011] Figure 6 The diagrams are a plan view and a cross-sectional view of a semiconductor device according to one embodiment.

[0012] Figure 7 1 is a cross-sectional view showing a PN junction region of a semiconductor device according to one embodiment.

[0013] Figure 8 This is a cross-sectional view of a semiconductor device according to one embodiment.

[0014] Figure 9 It is a concentration profile of an impurity implanted into an impurity region of a semiconductor device according to one embodiment.

[0015] Figure 10 This is the concentration distribution of impurities implanted into an impurity region of a semiconductor device according to one embodiment.

[0016] Figure 11 This is a cross-sectional view of a semiconductor device according to a modified example of one embodiment.

[0017] Figure 12 This is a cross-sectional view of a semiconductor device according to a modified example of one embodiment.

[0018] Figure 13 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0019] Figure 14 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0020] Figure 15 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0021] Figure 16 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0022] Figure 17 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0023] Figure 18 sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment and its modified example.

[0024] Figure 19 This is a cross-sectional view of a semiconductor device according to one embodiment.

[0025] Figure 20 This is a cross-sectional view of a semiconductor device according to one embodiment.

[0026] Description of labels

[0027] 10: Semiconductor device, 21: Address decoder, 22: Block selection circuit, 23: Voltage selection circuit, 100, 105, 120, 125: Gate insulating layer, 110, 115, 130, 135: Gate electrode, 140, 145: Gate wiring, 150, 155: Trench, 151, 152: Insulating layer, 160, 165, 170: Impurity region, 190: Through electrode, 195: Via, 220: Block selection unit, 230: Voltage selection unit, 310 : Input and output circuit, 320: Logic control circuit, 330: Status register, 340: Address register, 350: Instruction register, 360: Sequencer, 370: Ready / busy circuit, 380: Voltage generation circuit, 510: Memory cell array, 511, 513, 515, 518, 595: Insulation layer, 512, 516, 593: Via hole, 514, 519, 594: Wiring, 517: Conductive layer, 520: Row decoder, 530: Sense amplifier module, 540 : Data register, 550: Column decoder, 590: Peripheral circuit, 591, 599: Substrate, 592: Processing circuit, 596: Contact, B: Bonding surface, BL: Bit line, C0, C2, C3: Via, C1: Contact, CA: Column address, CAP: Capacitor, DF: Diffusion region, DL, XDL: Latch circuit, INV: Node, IVa, IVb: Converter, LAT: Node, LBUS: Bus, MC: Memory cell, MS: Storage String, NW: N-well, P1~P4: bonding electrode, PL: pillar, PW: P-well, R1~R6: region, S1: 1st surface, S2: 2nd surface, SA: sense amplifier circuit, SEN: node, SGD: select gate line, SGS: select gate line, SL: source line, SLL: source layer, SRC: node, ST: gap, STD: drain select transistor, STP: step portion, STS: source select transistor, SU: string unit, TR: transistor, WL: word line, WR: wiring. DETAILED DESCRIPTION

[0028] Hereinafter, the semiconductor device involved in this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements with substantially the same function and structure are marked with the same reference numerals, and the description is repeated only when necessary. Each embodiment shown below illustrates an apparatus and method for concretizing the technical idea of ​​the embodiment. The technical idea of ​​the embodiment does not limit the material, shape, structure, configuration, etc. of the constituent components to the following. The technical idea of ​​the embodiment may also be a technical idea obtained by applying various changes to the claims.

[0029] [First embodiment]

[0030] use Figures 1 to 10 , a semiconductor device according to the first embodiment is described.

[0031] [1-1. Overall Structure of Semiconductor Device]

[0032] Figure 1 FIG. 1 is a block diagram of a semiconductor device 10 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, an instruction register 350, a sequencer 360, a ready / busy circuit 370, a voltage generating circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0033] I / O circuit 310 controls input and output of signal DQ to an external device (not shown) such as a memory controller that controls semiconductor device 10. Signal DQ is, for example, an 8-bit signal DQ0 to DQ7. I / O circuit 310 includes an input circuit and an output circuit (not shown).

[0034] The input circuit transmits data DAT such as write data WDT received from an external device to the data register 540 , transmits an address ADD to the address register 340 , and transmits a command CMD to the command register 350 .

[0035] The output circuit transmits the status information STT received from the status register 330 , the data DAT such as the read data RDT received from the data register 540 , and the address ADD received from the address register 340 to an external device.

[0036] The logic control circuit 320 receives signals such as a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from external devices and controls the I / O circuit 310 and the sequencer 360 according to the received signals.

[0037] The status register 330 temporarily holds status information STT during, for example, data writing, reading, and erasing operations, and notifies an external device via the input / output circuit 310 whether the operations have been completed normally.

[0038] The address register 340 temporarily holds the address ADD received from the external device via the input / output circuit 310 . The address register 340 transmits the row address RA to the row decoder 520 and transmits the column address CA to the column decoder 550 .

[0039] The command register 350 temporarily stores the command CMD received from the external device via the input / output circuit 310 , and transmits the command CMD to the sequencer 360 .

[0040] The sequencer 360 controls the overall operation of the semiconductor device 10. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generating circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 according to the command CMD stored in the command register 350, thereby executing write operations, read operations, and erase operations.

[0041] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device according to the operation status of the sequencer 360 .

[0042] The voltage generating circuit 380 generates voltages required for write, read, and erase operations under the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generating circuit 380 to the memory cells in the memory cell array 510.

[0043] Memory cell array 510 includes multiple blocks BLK (BLK0-BLKn). n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines. For example, a block BLK is a unit of data erasure. The memory cells are, for example, charge retention transistors, and they store data nonvolatilely using the retained charge. By including such memory cells, semiconductor device 10 functions as, for example, a NAND-type nonvolatile memory.

[0044] The row decoder 520 decodes the row address RA. Based on the result of the decoding, the row decoder 520 selects any one of the plurality of blocks BLK. The row decoder 520 applies voltages required for write, read, and erase operations to the block BLK.

[0045] In a read operation, the sense amplifier module 530 senses (detects) data read from the memory cell array 510. In a read operation, the sense amplifier module 530 sends read data RDT to the data register 540. In a write operation, the sense amplifier module 530 sends write data WDT to the memory cell array 510.

[0046] As described in detail later, the data register 540 includes multiple latch circuits. The latch circuits hold write data WDT and read data RDT. For example, during a write operation, the data register 540 temporarily holds write data WDT received from the input / output circuit 310 and transmits it to the sense amplifier module 530. During a read operation, the data register 540 temporarily holds read data RDT received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0047] The column decoder 550 decodes the column address CA, for example, during a write operation, a read operation, and an erase operation, and selects a latch circuit in the data register 540 based on the result of the decoding.

[0048] In addition, the circuit group arranged outside the memory cell array 510 is sometimes referred to as a peripheral circuit 590 (see Figure 5 The peripheral circuit 590 includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The status register 330, the address register 340, the instruction register 350, and the sequencer 360 may also be included in the peripheral circuit 590. Furthermore, the input / output circuit 310, the logic control circuit 320, the ready / busy circuit 370, and the voltage generation circuit 380 may also be included in the peripheral circuit 590.

[0049] As described above, the semiconductor device 10 includes the memory cell array 510 including a plurality of memory cells and the peripheral circuit 590 for driving the plurality of memory cells.

[0050] [1-2. Configuration of Memory Cell Array]

[0051] use Figure 2 , the circuit structure of the memory cell array 510 is described. Figure 2 This is a diagram for explaining an equivalent circuit showing the configuration of a memory cell array of a semiconductor device according to one embodiment.

[0052] As described above, the memory cell array 510 includes multiple blocks BLK. Each of the multiple blocks BLK includes multiple string units SU. Each of the multiple string units SU includes multiple memory strings MS. One end of each of the multiple memory strings MS is connected to a peripheral circuit 590 such as a sense amplifier module 530 via a bit line BL. The other end of each of the multiple memory strings MS is connected to the peripheral circuit 590 via a common source line SL.

[0053] A memory string MS is provided between a bit line BL and a source line SL. The memory string MS includes a drain select transistor STD, a plurality of memory cells MC, and a source select transistor STS connected in series between the bit line BL and the source line SL. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

[0054] A memory cell MC is, for example, a field effect transistor (FET) that includes a charge storage layer in its gate insulating layer. The threshold voltage of a memory cell MC varies depending on the amount of charge held in the charge storage layer. By setting one or more threshold voltages, a memory cell MC can store one or more bits of data. Word lines WL are connected to the gate terminals of the multiple memory cells MC corresponding to a memory string MS. These word lines WL are commonly connected to multiple (or all) memory strings MS in a block BLK.

[0055] The selection transistors (STD, STS) are, for example, field-effect transistors. The gate terminals of the selection transistors (STD, STS) are connected to selection gate lines (SGD, SGS), respectively. The selection gate line SGD connected to the drain selection transistor STD is provided corresponding to the string unit SU and is commonly connected to multiple (or all) memory strings MS in one string unit SU. The selection gate line SGS connected to the source selection transistor STS is commonly connected to multiple (or all) memory strings MS in one block BLK.

[0056] One end of the word line WL and the select gate line (SGD, SGS) is connected to a peripheral circuit 590 such as the row decoder 520 .

[0057] [1-3. Configuration of the Sense Amplifier Module]

[0058] use Figure 3 , the circuit structure of the sense amplifier module 530 is described. Figure 3 FIG. 1 is a diagram for explaining a circuit configuration of a sense amplifier module of a semiconductor device according to an embodiment. Figure 3 As shown, the sense amplifier module 530 includes a sense amplifier circuit SA, a plurality of latch circuits DL, and a latch circuit XDL.

[0059] The sense amplifier circuit SA is provided for one or more bit lines BL. For example, during a read operation, the sense amplifier circuit SA senses data read from the corresponding bit line BL and determines whether the read data is "0" or "1."

[0060] Multiple latch circuits DL and latch circuits XDL are provided corresponding to the multiple sense amplifier circuits SA. Specifically, multiple latch circuits DL and latch circuits XDL are provided for each bit line BL, with multiple latch circuits DL provided for one sense amplifier circuit SA. The number of latch circuits DL is designed based on, for example, the number of bit lines BL that can hold data in one memory cell MC. The multiple latch circuits DL and latch circuits XDL temporarily hold data associated with the corresponding bit lines BL.

[0061] exist Figure 3 1 shows one sense amplifier circuit SA and a plurality of latch circuits DL and latch circuits XDL provided corresponding to the sense amplifier circuit SA in the sense amplifier module 530. A plurality of control signals supplied to the sense amplifier circuit SA and the like are controlled by the sequencer 360.

[0062] like Figure 3 As shown, the sense amplifier circuit SA includes transistors TR31 to TR38 and a capacitor CAP. Transistor TR31 is a low-voltage P-channel MOS (Metal Oxide Semiconductor) transistor. Transistors TR32 to TR38 are low-voltage N-channel MOS transistors.

[0063] Low-voltage CMOS transistors, which include low-voltage P-channel MOS transistors and low-voltage N-channel MOS transistors, are transistors to which a relatively low voltage is applied and are also called low-voltage (LV, VLV) MOS transistors. On the other hand, high-voltage CMOS transistors, which include high-voltage P-channel MOS transistors and high-voltage N-channel MOS transistors described later, are transistors to which a relatively high voltage is applied and are also called high-voltage (HV) MOS transistors. Here, a relatively high voltage is, for example, a voltage higher than that of the low-voltage CMOS transistor.

[0064] The first terminal of transistor TR31 is connected to a power supply line that supplies power supply voltage Vdd, and the gate terminal of transistor TR31 is connected to node INV. The first terminal of transistor TR32 is connected to the second terminal of transistor TR31, and the second terminal of transistor TR32 is connected to node COM. A control signal BLX is input to the gate terminal of transistor TR32. The first terminal of transistor TR33 is connected to node COM, and the second terminal of transistor TR33 is connected to the corresponding bit line BL via a high-voltage N-channel MOS transistor (not shown). The control signal BLC is input to the gate terminal of transistor TR33.

[0065] A first terminal of the transistor TR34 is connected to the node COM, a second terminal of the transistor TR34 is connected to the node SRC, and a gate terminal of the transistor TR34 is connected to the node INV.

[0066] A first terminal of transistor TR35 is connected to a second terminal of transistor TR31, a second terminal of transistor TR35 is connected to a node SEN, and a control signal HLL is input to a gate terminal of transistor TR35. A first terminal of transistor TR36 is connected to a node SEN, a second terminal of transistor TR36 is connected to a node COM, and a control signal XXL is input to a gate terminal of transistor TR36.

[0067] A ground voltage VSS is input to a first terminal of transistor TR37, and a gate terminal of transistor TR37 is connected to a node SEN. A first terminal of transistor TR38 is connected to a second terminal of transistor TR37, and a second terminal of transistor TR38 is connected to a bus line LBUS. A control signal STB is input to a gate terminal of transistor TR38. A first terminal of capacitor CAP is connected to the node SEN, and a clock signal CLK is input to a second terminal of capacitor CAP.

[0068] The latch circuit DL includes inverters IVa and IVb and transistors TR41 and TR42. As described above, the latch circuit DL is provided in the data register 540. Transistors TR41 and TR42 are low-voltage N-channel MOS transistors. Hereinafter, the transistors TR41 and TR42 included in the latch circuit DL may be simply referred to as transistors TR.

[0069] Inverter IVa has an input terminal connected to node LAT and an output terminal connected to node INV. Inverter IVb has an input terminal connected to node INV and an output terminal connected to node LAT.

[0070] Transistor TR41 has a first terminal connected to node INV, a second terminal connected to bus line LBUS, and a gate terminal to which control signal STI is input. Transistor TR42 has a first terminal connected to node LAT, a second terminal connected to bus line LBUS, and a gate terminal to which control signal STL is input.

[0071] Latch circuit XDL, for example, has a configuration substantially similar to latch circuit DL and is connected to bus LBUS to enable data transmission and reception between sense amplifier circuit SA and latch circuit DL. Latch circuit XDL is connected to input / output circuit 310 and is used to input and output data between sense amplifier circuit SA and input / output circuit 310.

[0072] The latch circuit XDL is also used for cache operation of the semiconductor device 10. That is, even if all the latch circuits DL corresponding to the sense amplifier circuits SA are in use, the semiconductor device 10 can receive data from the outside as long as there is a latch circuit XDL that can be used.

[0073] Next, the operation of the sense amplifier circuit SA configured as described above will be briefly described. When data is written to the memory cell MC, charge is injected into the memory cell MC to raise the threshold. In this case, the node INV of the latch circuit DL is controlled to an "H" level (e.g., storing "1" data). Consequently, the transistor TR34, whose gate terminal is connected to the node INV, is turned on, supplying the voltage supplied to the node SRC (e.g., 0V) to the bit line BL. On the other hand, when charge is not injected into the memory cell MC and the threshold is not changed, the node INV of the latch circuit DL is controlled to an "L" level (e.g., storing "0" data). Consequently, the transistor TR31, whose gate terminal is connected to the node INV, is turned on, supplying a predetermined positive voltage (the voltage supplied to the power supply voltage Vdd) to the bit line BL.

[0074] When performing a read operation, node INV is controlled to "L" level, and transistor TR31 is turned on. Furthermore, bit line BL is precharged by transistor TR31 via transistors TR41 and TR42. Transistor TR35 is also turned on, and node SEN is charged to a predetermined potential.

[0075] Then, with transistor TR35 turned off and control signal XXL controlled to "H" level, transistor TR36 turns on. Consequently, if the corresponding memory cell MC is in the on state, the potential of node SEN decreases, and transistor TR37 turns off. On the other hand, if the corresponding memory cell MC is in the off state, the potential of node SEN remains at "H" level, and transistor TR37 turns on.

[0076] Next, the transistor TR38 is turned on by the control signal STB, and the potential corresponding to the on / off state of the transistor TR37 is read to the bus line LBUS and held in the latch circuit DL.

[0077] Figure 3 The circuit configuration of the sense amplifier circuit SA, multiple latch circuits DL, and latch circuit XDL shown is merely an example; configurations other than those described above are also possible. Specifically, the number and type of transistors TR included in each of the sense amplifier circuit SA and latch circuits DL and XDL may differ from the configuration described above. For example, the sense amplifier circuit SA and latch circuits DL and XDL may include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors.

[0078] [1-4. Row Decoder Circuit Configuration]

[0079] use Figure 4 , the circuit structure of the row decoder 520 is described. Figure 4 FIG. 1 is a diagram for explaining a circuit configuration of a row decoder of a semiconductor device according to one embodiment. Figure 4 As shown, the row decoder 520 includes an address decoder 21 , a block selection circuit 22 , and a voltage selection circuit 23 .

[0080] The address decoder 21 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines VOLSEL. The address decoder 21 refers to address data of the address register 340 included in the peripheral circuit 590 based on a control signal from the sequencer 360, for example.

[0081] The address decoder 21 decodes the referenced address data and controls the transistors TR22 and TR23 corresponding to the address data to be turned on, and controls the other transistors TR22 and TR23 to be turned off. The transistors TR22 and TR23 are transistors included in the block selection circuit 22 and the voltage selection circuit 23, respectively, which will be described later.

[0082] For example, the address decoder 21 controls the block select line BLKSEL and the voltage select line VOLSEL corresponding to the address data to the "H" level, and controls the other block select lines BLKSEL and the voltage select line VOLSEL to the "L" level. The above example is an example of a case where N-type transistors are used in the block select circuit 22 and the voltage select circuit 23. If P-type transistors are used in the block select circuit 22 and the voltage select circuit 23, the voltages applied to the respective wirings are reversed.

[0083] exist Figure 4 In the example shown in FIG. 5 , one block selection line BLKSEL is provided in the address decoder 21 for one block BLK included in the memory cell array 510. However, this configuration can be modified as appropriate. For example, one block selection line BLKSEL may be provided for two or more blocks BLK.

[0084] The block selection circuit 22 includes a plurality of block selection units 220. Each of the plurality of block selection units 220 corresponds to a block BLK of the memory cell array 510. Each of these plurality of block selection units 220 includes a plurality of transistors TR22 corresponding to a word line WL and a select gate line (SGD, SGS). Transistor TR22 selects the word line WL corresponding to the target memory cell MC and is sometimes referred to as a "word line selection transistor."

[0085] Transistor TR22 is a high-voltage N-channel MOS transistor that functions as a block driver transistor. The drain terminals of transistor TR22 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS). The source terminals of transistor TR22 are electrically connected to the voltage output terminal OTM via wiring WR and the voltage selection circuit 23. The voltage output terminal OTM is electrically connected to the voltage generation circuit 380. The gate terminals of transistors TR22 are commonly connected to the corresponding block select line BLKSEL.

[0086] Although not shown, the block select circuit 22 includes a plurality of transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors are high-voltage CMOS transistors. These transistors electrically connect the select gate lines (SGD, SGS) included in the unselected blocks BLK within the memory cell array 510 to the ground voltage supply terminal. Furthermore, the word lines WL included in the unselected blocks BLK are in a floating state.

[0087] The voltage selection circuit 23 includes a plurality of voltage selection units 230 corresponding to the word lines WL and the selection gate lines (SGD, SGS). Each of the plurality of voltage selection units 230 includes a plurality of transistors TR23.

[0088] Transistor TR23 is a high-voltage N-channel MOS transistor that functions as a voltage selection transistor. The drain terminal of transistor TR23 is electrically connected to the corresponding word line WL or select gate line (SGD, SGS) via wiring WR and block selection circuit 22. The source terminal of transistor TR23 is electrically connected to the corresponding voltage output terminal OTM. The gate terminal of transistor TR23 is connected to the corresponding voltage selection line VOLSEL.

[0089] Thus, the row decoder 520 belonging to the peripheral circuit 590 includes a plurality of transistors TR22, TR23, etc. However, Figure 4 The circuit configuration of the row decoder 520 shown is an example, and the number and types of transistors TR22, TR23, etc. included in the row decoder 520 are not limited to the above example.

[0090] [1-5. Cross-sectional Structure of Semiconductor Device 10]

[0091] use Figure 5 , a cross-sectional structure of the semiconductor device 10 is described. Figure 5 1 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment. Figure 5 As shown, the main surface of the substrate 591 of the peripheral circuit 590 extends in the X direction and the Y direction. The direction perpendicular to the X direction and the Y direction is the Z direction. In the following description, the Z direction may be referred to as "up" or "above", and the opposite direction may be referred to as "down" or "below".

[0092] like Figure 5 As shown, the memory cell array 510 and the peripheral circuit 590 are bonded to each other at the bonding surface B. Bonding electrodes P1 are provided on the bonding surface B side of the memory cell array 510. Bonding electrodes P2 are provided on the bonding surface B side of the peripheral circuit 590. The circuits provided in the memory cell array 510 are electrically connected to the circuits provided in the peripheral circuit 590 via bonding electrodes P1 and P2.

[0093] The peripheral circuit 590 includes a substrate 591 , a processing circuit 592 , vias 593 , wirings 594 , an insulating layer 595 , and a bonding electrode P2 .

[0094] The substrate 591 is a semiconductor substrate. A silicon substrate is used as the semiconductor substrate. However, an SOI (Silicon On Insulator) substrate or a compound semiconductor substrate may also be used as the semiconductor substrate.

[0095] The processing circuit 592 includes transistors provided on the substrate 591. For example, the processing circuit 592 includes a row decoder 520 and a sense amplifier module 530. The processing circuit 592 also includes a capacitor and a resistor in addition to the transistors.

[0096] The via 593 is a wiring extending in the Z direction and provided in an opening of the insulating layer 595. The via 593 electrically connects the processing circuit 592 and the wiring 594. Figure 5 , only one layer of wiring 594 is shown, but wiring 594 is provided in multiple layers in the Z direction via insulating layers 595, and adjacent wirings 594 in the Z direction are connected by vias 593. Similarly, adjacent wirings 594 and bonding electrodes P2 in the Z direction are also connected by vias 593.

[0097] At the end of the peripheral circuit 590, an N-type transistor is provided, which is sandwiched between the P-type well PW. + Diffusion region DF. The N + The diffusion region DF is connected to the bonding electrode P1 of the memory cell array 510 through the via 593 provided in the processing circuit 592 , the wiring 594 , the contact portion 596 , and the bonding electrode P2 .

[0098] The memory cell array 510 includes memory strings MS, slits ST, a source layer SLL, insulating layers 511 , 513 , 515 , and 518 , contacts C1 , vias C2 and C3 , wirings 514 and 519 , vias 512 and 516 , and a conductive layer 517 .

[0099] The memory string MS includes a pillar PL, a plurality of conductive layers 517, and a plurality of insulating layers 518. The pillar PL extends in the Z direction. A plurality of pillars PL are provided in the Z direction. Figure 5 In the example of , two pillars PL are stacked in the Z direction. A structure including the stacked pillars PL and a plurality of memory strings MS is referred to as a string unit SU.

[0100] The pillar PL includes a core layer, a semiconductor layer, an insulating layer, and a charge storage layer. The core layer is the core of the pillar PL and is an insulator. A semiconductor layer is provided around the core layer, an insulating layer is provided around the semiconductor layer, a charge storage layer is provided around the insulating layer, and an insulating layer is provided around the charge storage layer. A plurality of conductive layers 517 and a plurality of insulating layers 518 are alternately stacked along the Z direction. The plurality of conductive layers 517 are provided in a manner that surrounds the insulating layer on the outside of the pillar PL. The portion of one of the plurality of conductive layers 517 that faces the pillar PL is the memory cell MC. In other words, the conductive layer 517 functions as the gate electrode of the memory cell MC.

[0101] The plurality of conductive layers 517 extend in the Y direction. The plurality of conductive layers 517 function as word lines WL and select gate lines (SGD, SGS). Step portions STP are provided at the ends of the plurality of conductive layers 517. The stepped shape of the step portions STP allows each of the plurality of conductive layers 517 to be sequentially exposed from the underlying conductive layer 517 and connected to wiring 519 via vias C0.

[0102] The semiconductor layer of the pillar PL is connected to the via 516 and the source layer SLL. The via 516 is connected to the wiring 519 functioning as the bit line BL. The bit line BL extends in the X direction. The bit line BL is connected to the bonding electrode P1 through the via 516.

[0103] A via 512, an insulating layer 513, a wiring 514, and an insulating layer 515 are provided above the source layer SLL. + The wiring 514 at the position corresponding to the diffusion region DF is connected to the bonding electrode P2 of the peripheral circuit 590 through the via C3, wiring 519, via 516, and bonding electrode P1. The substrate 591 is electrically connected to the source layer SLL through the via C1, wiring 519, via 516, and bonding electrode P1.

[0104] [1-6. Overview of Word Line Select Transistor (TR22)]

[0105] First, use Figure 6 and Figure 7 , the detailed structure of the word line selection transistor is described. Figure 6 As described above, the word line selection transistor corresponds to a plan view and a cross-sectional view of a semiconductor device according to an embodiment. Figure 4 of transistor TR22. Figure 6 The transistor TR22 shown is the transistor TR22 included in the block selection unit 220 which is a part of the peripheral circuit 590 .

[0106] like Figure 6As shown, transistors TR22 are arranged adjacent to each other in the D1 direction. When distinguishing between the two transistors TR22, they are referred to as transistors TR22-1 and TR22-2, respectively. Otherwise, these transistors are simply referred to as transistor TR22. Transistor TR22 is a transistor whose channel is a portion of a semiconductor substrate 591. Transistor TR22-1 includes a gate insulating layer 100 and a gate electrode 110. Transistor TR22-2 includes a gate insulating layer 120 and a gate electrode 130. Gate wiring 140 is provided over gate electrodes 110 and 130. Gate wiring 140 extends in the D1 direction, crossing over gate electrodes 110 and 130. With this configuration, a common voltage is applied to the gate electrodes of the multiple transistors TR22 arranged in the D1 direction.

[0107] A trench (trench 150) is provided in substrate 591 between transistors TR22-1 and TR22-2. Trench 150 includes a recessed portion formed in the upper portion of substrate 591 and an insulator disposed within the recessed portion. An impurity region 160 is provided adjacent to trench 150 in substrate 591. Impurity region 160 includes a first impurity that changes the threshold value of transistor TR22. When substrate 591 is an N-type semiconductor, the first impurity is, for example, boron. When substrate 591 is a P-type semiconductor, the first impurity is, for example, phosphorus or arsenic. In this embodiment, the case where substrate 591 is an N-type semiconductor and the first impurity is boron is described.

[0108] The transistors TR22 are arranged in correspondence with the word lines WL provided in the string units SU. Therefore, as the memory cell array 510 becomes smaller and the capacity increases, the distance between adjacent transistors TR22 becomes shorter. As a result, the leakage current between adjacent transistors TR22 may increase.

[0109] Trench 150 and impurity region 160 are provided to suppress leakage current between transistors TR22-1 and TR22-2. Specifically, trench 150 is provided to extend the effective distance between transistors TR22-1 and TR22-2. Impurity region 160 is provided to suppress the formation of an inversion layer in substrate 591 and the generation of carriers when a voltage is applied to gate wiring 140.

[0110] For example, when substrate 591 is an N-type semiconductor, increasing the amount of boron in impurity region 160 shifts the threshold of the semiconductor in impurity region 160 toward the positive direction. Consequently, compared to a case where impurity region 160 is absent, carriers generated by the voltage supplied to gate wiring 140 are less likely to be generated in the semiconductor in impurity region 160. As described above, the provision of trench 150 and impurity region 160 can suppress leakage current between transistors TR22-1 and TR22-2.

[0111] Even with the above configuration, when the distance between adjacent transistors TR22-1 and TR22-2 becomes closer (for example, when the distance becomes less than 500 nm), leakage current between transistors TR22-1 and TR22-2 may increase. This leakage current can be suppressed by increasing the amount of boron implanted into impurity region 160.

[0112] When a voltage is applied to gate wiring 140, carriers generated by the electric field are primarily generated in the surface layer of the semiconductor (in this embodiment, the surface layer of substrate 591 that is in contact with the sidewalls and bottom of trench 150). Specifically, to suppress leakage current between transistors TR22-1 and TR22-2, it is necessary to increase the boron concentration in the surface layer of substrate 591 that is in contact with the sidewalls and bottom of trench 150. However, since boron readily diffuses during heat treatment, the total amount of boron implanted into impurity region 160 must be increased to maintain the boron concentration in the surface layer of substrate 591 at a predetermined level.

[0113] As described above, in order to suppress leakage current between transistors TR22-1 and TR22-2, it is necessary to increase the total amount of boron implanted into impurity region 160. However, when the total amount of boron in impurity region 160 is increased, the following phenomenon may occur.

[0114] like Figure 5 As shown, a portion of the peripheral circuit 590 is provided with an N-type transistor sandwiched between two P-type wells PW. + Diffusion region DF: In other words, a PN junction region formed by the junction of a P-well and an N-well exists in the substrate 591 . Figure 7 FIG. 1 is a cross-sectional view showing a PN junction region of a semiconductor device according to one embodiment. Figure 7 As shown, a P well PW and an N well NW are formed on the substrate 591. A P well PW is provided on the upper portion of the P well PW. + N well NW is provided on the upper part of the N well + Area. P + The N region is a region containing impurities at a higher concentration than that of the P-well PW. + The region is a region containing impurities at a higher concentration than the N well NW. A trench 150 is provided near the boundary between the P well PW and the N well NW. Figure 6 Likewise, an impurity region 160 is provided.

[0115] As described above, when the substrate 591 is an N-type semiconductor, since boron is implanted into the impurity region 160, the substrate 591 in the impurity region 160 becomes a P-type semiconductor. Figure 7In the configuration of , PN junctions are formed between the P-well PW and the N-well NW, and between the impurity region 160 and the N-well NW.

[0116] When in order to suppress Figure 6 When the leakage current generated between the transistors TR22-1 and TR22-2 increases the total amount of boron contained in the impurity region 160, Figure 7 The junction breakdown voltage of the PN junction between the impurity region 160 and the N well NW is degraded. As a result, especially in the case of P + Region and N + In regions where a high voltage is applied between regions, leakage current may increase due to the aforementioned degradation of the PN junction withstand voltage. Therefore, there is an upper limit to the total amount of boron implanted into impurity region 160 to suppress leakage current generated between transistors TR22-1 and TR22-2.

[0117] [1-7. Configuration of Word Line Select Transistor (TR22) According to This Embodiment]

[0118] use Figures 8 to 10 , the structure of the transistor TR22 involved in this embodiment is described. Figure 8 This is a cross-sectional view of a semiconductor device according to one embodiment. Figure 9 and Figure 10 This is the concentration distribution of impurities implanted into an impurity region of a semiconductor device according to one embodiment. Figure 8 The cross-sectional view shown is Figure 6 In the following description, the cross-sectional view shown is similar to that shown in FIG. Figure 6 The configurations shown are the same as those shown, and description thereof may be omitted. Figure 8 The transistor TR22 shown is the transistor TR22 included in the block selection unit 220 which is a part of the peripheral circuit 590 .

[0119] like Figure 8 As shown, the semiconductor device 10 includes a substrate 591, a transistor TR22-1, and a transistor TR22-2. A trench 150 is provided between the transistor TR22-1 and the transistor TR22-2. The trench 150 is a groove (or recess) provided in the substrate 591. An insulating layer ( Figure 16 Insulating layers 151 and 152 are shown. Transistor TR22-1 is provided in region R1. Transistor TR22-2 is provided in region R2. Trench 150 is provided in region R3. Region R3 is located between regions R1 and R2 and is adjacent to both regions R1 and R2. Gate wiring 140 is provided above transistor TR22-1, above transistor TR22-2, and above trench 150, extending continuously from region R1 to region R2.

[0120] As described above, since the transistors TR22-1 and TR22-2 are adjacent to each other via the trench 150, the word line WL connected to the transistor TR22-1 and the word line WL connected to the transistor TR22-2 of the word lines WL provided in the memory cell array 510 are adjacent to each other.

[0121] On the other hand, Figure 6 In contrast, in a position adjacent to trench 150 in substrate 591, impurity region 170 is provided in addition to impurity region 160. Impurity region 160 contains a first impurity that changes the threshold value of transistor TR22. Impurity region 170 contains a second impurity that suppresses diffusion of the first impurity during heat treatment, etc. When the first impurity is boron, carbon, for example, can be used as the second impurity.

[0122] The substrate 591 is sometimes referred to as the "first substrate". The transistor TR22-1 is sometimes referred to as the "first transistor". The transistor TR22-2 is sometimes referred to as the "second transistor". The region R1 is sometimes referred to as the "first region". The region R2 is sometimes referred to as the "second region". The region R3 is sometimes referred to as the "third region". The trench 150 is sometimes referred to as the "first trench". The gate wiring 140 is sometimes referred to as the "first conductive layer". The impurity region 160 and the impurity region 170 are sometimes collectively referred to as the "first impurity region". The substrate 591 has a first surface S1 and a second surface S2. The second surface S2 is the surface opposite to the first surface S1. The transistor TR22 is provided on the first surface S1.

[0123] exist Figure 8 In FIG, for convenience of explanation, the impurity region 160 containing the first impurity and the impurity region 170 containing the second impurity are shown as being provided in different regions. However, the impurity region 160 and the impurity region 170 may partially overlap or completely overlap. Figure 8 In FIG. 1 , impurity region 170 is disposed outside impurity region 160 relative to trench 150. This means that, in the impurity concentration distribution, the peak of the second impurity is located outside the peak of the first impurity. Alternatively, the peak of the first impurity may be located outside the peak of the second impurity, or the positions of the two peaks may coincide.

[0124] Figure 9 The concentration distribution shown is the distribution of impurities in the direction from the bottom of the trench 150 toward the second surface S2 of the substrate 591 . Figure 9 The boron concentration distributions shown are all after the impurity ions are implanted and a thermal history equivalent to that in the manufacturing process of the semiconductor device 10 is given. Figure 9In FIG. 5 , the vertical axis (Dose Concentration) represents the concentration of the implanted impurities, and the horizontal axis (Depth) represents the depth of the implanted impurities. Figure 9 The lower concentration distribution (Without Carbon) is the concentration distribution when only boron ions are implanted into the substrate 591 . Figure 9 The concentration distribution above (With Carbon) is the concentration distribution when carbon and boron are ion-implanted into the substrate 591. Figure 9 As shown, by ion-implanting carbon together with boron into the substrate 591 , it is possible to suppress the diffusion of boron in the substrate 591 even after the heat treatment.

[0125] As described above, although boron easily diffuses into substrate 591 due to heat treatment, etc., carbon has the function of suppressing boron diffusion. Therefore, by providing impurity region 160 containing boron and impurity region 170 containing carbon adjacent to trench 150, it is possible to suppress the diffusion of boron into substrate 591 due to subsequent heat treatment, etc., after boron has been implanted into substrate 591 by ion implantation. Therefore, when boron is implanted into substrate 591 by ion implantation or other means, the total amount of implanted boron can be reduced by implanting boron under low acceleration conditions so that the boron concentration profile has a peak near the surface of substrate 591, adjacent to the sidewalls and bottom of trench 150.

[0126] Figure 10 The concentration distribution shown is the distribution of impurities in the direction from the bottom of the trench 150 toward the second surface S2 of the substrate 591. Figure 10 , the boron concentration distribution and the carbon concentration distribution are shown together. The peak of the carbon concentration distribution exists at a position deeper than the peak of the boron concentration distribution (closer to the second surface S2). Moreover, the height of the peak of the carbon concentration distribution is higher than the height of the peak of the boron concentration distribution. Specifically, the difference in the height of the two peaks is more than one order of magnitude.

[0127] In this embodiment, the boron and carbon contained in the impurity regions 160 and 170 are not impurities uniformly present in the substrate 591. Since the impurities in this embodiment are implanted into the substrate 591 by, for example, ion implantation, Figure 10 In the concentration distribution shown, there is a portion where the concentrations of carbon and boron gradually decrease from the bottom of the trench 150 toward the second surface S2.

[0128] exist Figure 10, the carbon concentration distribution peak is shown as being located deeper than the boron concentration distribution peak. However, the present invention is not limited to this example. For example, the carbon concentration distribution peak may be located shallower than the boron concentration distribution peak, or both peaks may be located at the same position. Similarly, the carbon concentration distribution peak may be lower in height than the boron concentration distribution peak, or both peaks may be the same height.

[0129] As described above, according to the semiconductor device 10 of this embodiment, by including the first impurity (boron) that changes the threshold value of the transistor TR22 and the second impurity (carbon) that suppresses diffusion of the first impurity during heat treatment, etc. in the impurity region 160 between the trench 150 and the substrate 591, the total amount of the first impurity implanted into the impurity region 160 can be reduced, and the first impurity can be concentrated near the surface layer of the substrate 591 adjacent to the sidewalls and bottom of the trench 150. As a result, it is possible to achieve both reduction in leakage current between adjacent transistors TR22 and suppression of breakdown voltage degradation of the PN junction.

[0130] [1-8. Modifications]

[0131] use Figures 11 and 12 , a modification example of the first embodiment is described.

[0132] Figure 11 and Figure 12 This is a cross-sectional view of a semiconductor device 10 according to a modified example of one embodiment. Figure 11 and Figure 12 The composition shown is Figure 8 The structure shown is similar, but the position of the carbon-containing impurity region 170 is different from Figure 8 The composition shown is different.

[0133] Specifically, in Figure 11 In the structure shown, the impurity region 170 is provided at a position corresponding to the sidewall portion of the trench 150, but the impurity region 170 is not provided at a position corresponding to the bottom of the trench 150. Figure 11 In the illustrated configuration, since the impurity region 170 is not provided at the position corresponding to the bottom of the trench 150, the diffusion of boron is not suppressed at the bottom side of the trench 150. As a result, the width of the impurity region 160 at the bottom of the trench 150 is larger than the width of the impurity region 160 at the sidewall portion of the trench 150. The width of the impurity region 160 indicates the region where boron exists. More specifically, it indicates that there is a concentration distribution of 1E13 / cm 3 However, the width of the impurity region 160 may be such that there is 1E14 / cm in the concentration distribution. 3 Above or 1E15 / cm 3above the width of the boron region.

[0134] On the other hand, Figure 12 In the structure shown, the impurity region 170 is provided at a position corresponding to the bottom of the trench 150, but the impurity region 170 is not provided at a position corresponding to the sidewall portion of the trench 150. Figure 12 In the illustrated configuration, since impurity regions 170 are not provided at positions corresponding to the sidewalls of trench 150, boron diffusion is not suppressed on the sidewalls of trench 150. As a result, the width of impurity regions 160 at the sidewalls of trench 150 is larger than the width of impurity regions 160 at the bottom of trench 150.

[0135] As shown in the above-described modification, the impurity region 170 does not need to be provided on the entire sidewall portion and the bottom portion of the trench 150 , and only needs to be provided to cut off the leakage current path between the transistors TR22 - 1 and TR22 - 2 .

[0136] [1-9. Manufacturing method]

[0137] use Figures 13 to 18 , a manufacturing method of the structure involved in the first embodiment and its modified examples is described. Figures 13 to 18 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment and a modified example thereof. Figures 13 to 16 , the method of forming the trench 150 and the impurity region 160 will be described. Then, the timing of forming the impurity region 170 in the first embodiment will be described. Figures 17 and 18 , the timing for forming the impurity region 170 in each of the modified examples will be described.

[0138] like Figure 13 As shown, after gate insulating layers 100 and 120 and gate electrodes 110 and 130 are formed on substrate 591, trench 150 is formed by etching the upper portion of substrate 591 in the region exposed from gate electrodes 110 and 130. Trench 150 can be formed using gate electrodes 110 and 130 as a mask or using a separately formed resist as a mask. With the sidewalls and bottom of trench 150 exposed, boron is implanted to form impurity region 160.

[0139] Then, if Figure 14 As shown, an insulating layer 151 is formed on gate electrodes 110 and 130 and within trench 150. Insulating layer 151 is formed using an isotropic film deposition method. For example, insulating layer 151 is formed by chemical vapor deposition (CVD). For example, a silicon oxide layer is formed as insulating layer 151. Alternatively, other insulating layers may be formed as insulating layer 151.

[0140] Then, if Figure 15 As shown, anisotropic etching is performed on the insulating layer 151. Since the insulating layer 151 is etched mainly from above by this etching, when viewed from above, a portion of the insulating layer 151 formed on the sidewalls of the gate electrodes 110 and 130 and the sidewalls of the trench 150, where the insulating layer 151 is formed thick, remains, while the insulating layer 151 formed on the upper surfaces of the gate electrodes 110 and 130 and the bottom of the trench 150 is removed.

[0141] Then, if Figure 16 As shown, an insulating layer 152 is formed on the gate electrodes 110 and 130 and inside the trench 150. The insulating layer 152 is formed by an isotropic film forming method. For example, the insulating layer 152 is formed by a CVD method similar to the insulating layer 151. Then, the insulating layer 152 is etched to expose the gate electrodes 110 and 130, and then the gate wiring 140 is formed, thereby forming Figure 8 、 Figure 11 as well as Figure 12 The trench 150 and the impurity region 160 are formed. In the above-described manufacturing method, the position where the impurity region 170 is formed can be adjusted by the timing of carbon implantation.

[0142] For the sake of Figure 8 As shown, the impurity region 170 is formed in the region corresponding to the sidewall portion and the bottom portion of the trench 150. Figure 13 As shown, after forming the trench 150 in the substrate 591 and before forming the insulating layer 151, carbon is implanted while exposing the sidewalls and bottom of the trench 150. Alternatively, carbon may be implanted after boron implantation or after carbon implantation.

[0143] For the sake of Figure 11 As shown, the impurity region 170 is not formed at the bottom of the trench 150, but the impurity region 170 is formed on the sidewall portion of the trench 150. Figure 17 As shown, after forming the trench 150 in the substrate 591 and before forming the insulating layer 151, carbon is implanted into the substrate 591 from an oblique direction while the sidewalls and bottom of the trench 150 are exposed. The oblique direction means an inclination relative to the normal to the main surface of the substrate 591. Similarly to the above, carbon can be implanted after boron implantation, or boron can be implanted after carbon implantation.

[0144] For the sake of Figure 12 As shown, the impurity region 170 is not formed on the sidewall portion of the trench 150, but the impurity region 170 is formed at the bottom of the trench 150. Figure 18As shown, carbon is implanted while insulating layer 151 formed on the sidewalls of gate electrodes 110 and 130 and the sidewalls of trench 150 remains and substrate 591 is exposed at the bottom of trench 150. In this case, since impurity region 160 has already been formed, carbon is implanted after boron implantation.

[0145] The same effects as those of the first embodiment can be obtained in the modified example of this embodiment as well.

[0146] [2. Second embodiment]

[0147] use Figure 19 A semiconductor device 10A according to a second embodiment will now be described. The semiconductor device 10A according to the second embodiment is similar to the semiconductor device 10 according to the first embodiment, but differs from the semiconductor device 10 according to the first embodiment in that a region having impurity regions 160 and 170 formed adjacent to the trench 150 and a region having only the impurity region 165 formed adjacent to the trench 155 without the impurity region 170 are provided on the same substrate 591.

[0148] like Figure 19 As shown in FIG. 5 , a transistor TR22 and a transistor TR10 (TR10-1, TR10-2) are provided on a substrate 591. The transistor TR22 and the transistor TR10 (TR10-1, TR10-2) are provided on a substrate 591. Figure 8 The transistors TR22 shown are identical, so their description is omitted. Transistors TR10-1 and TR10-2 are adjacent in the D1 direction across trench 155. When the two transistors TR10 are distinguished, they are referred to as transistors TR10-1 and TR10-2, respectively. When these transistors do not need to be distinguished, they are referred to as transistor TR10.

[0149] Transistor TR10 is a transistor having a portion of semiconductor substrate 591 as a channel. Transistor TR10-1 includes a gate insulating layer 105 and a gate electrode 115. Transistor TR10-2 includes a gate insulating layer 125 and a gate electrode 135. Gate wiring 145 is provided on gate electrodes 115 and 135. Gate wiring 145 extends in the direction D1, crossing gate electrodes 115 and 135. With this configuration, a common voltage is applied to the gate electrodes of the plurality of transistors TR10 arranged in a row.

[0150] A trench (trench 155) is provided in substrate 591 between transistors TR10-1 and TR10-2. Trench 155 comprises a recessed portion formed in the upper portion of substrate 591 and an insulator disposed within the recessed portion. Impurity region 165 is provided in substrate 591 adjacent to trench 155. Impurity region 165 includes a first impurity that changes the threshold value of transistor TR10. When substrate 591 is an N-type semiconductor, the first impurity is, for example, boron. When substrate 591 is a P-type semiconductor, the first impurity is, for example, phosphorus or arsenic.

[0151] Unlike transistor TR22, transistor TR10 has impurity region 165 formed in trench 155, but no impurity region 170. That is, no second impurity (e.g., carbon) is intentionally implanted into impurity region 165. Therefore, the concentration of the second impurity in impurity region 165 is 1E13 / cm 3 However, the concentration of the second impurity contained in the impurity region 165 may be 1E14 / cm 3 Below or 1E15 / cm 3 Since transistors TR22 and TR10 are formed in the same substrate 591, trenches 150 and 155 are subjected to the same heat treatment. Therefore, impurity regions 165 adjacent to trench 155 are more susceptible to thermal diffusion than impurity regions 160 adjacent to trench 150. Consequently, the width of impurity regions 165 is greater than that of impurity regions 160.

[0152] The above configuration can be formed by covering trench 155 adjacent to transistor TR10 with a mask when carbon is implanted to form impurity region 170. For example, the above configuration can be formed by implanting carbon using a mask with an opening in a region where diffusion of impurity region 160 (boron diffusion) is to be suppressed.

[0153] Transistor TR10-1 is sometimes referred to as the "third transistor." Transistor TR10-2 is sometimes referred to as the "fourth transistor." Region R4 is sometimes referred to as the "fourth region." Region R5 is sometimes referred to as the "fifth region." Region R6 is sometimes referred to as the "sixth region." Trench 155 is sometimes referred to as the "second trench." Gate wiring 145 is sometimes referred to as the "second conductive layer." Impurity region 165 is sometimes referred to as the "second impurity region."

[0154] As described above, according to the semiconductor device 10A according to the present embodiment, the same configuration as that of the first embodiment can be applied only to necessary regions.

[0155] [3. Third embodiment]

[0156] use Figure 20A semiconductor device 10B according to the third embodiment will now be described. The semiconductor device 10B according to the third embodiment is similar to the semiconductor device 10A according to the second embodiment, but differs from the semiconductor device 10A according to the second embodiment in that a substrate 591 having impurity regions 160 and 170 formed in the trench 150 and a substrate 599 having impurity region 165 formed in the trench 155 are stacked. Figure 20 The transistor TR22 shown is a transistor TR22 included in the block selection unit 220 as a part of the peripheral circuit. The transistor TR10 is a transistor included in a circuit as another part of the peripheral circuit.

[0157] like Figure 20 As shown, the semiconductor device 10B according to this embodiment has a structure in which substrates 591 and 599 and a memory cell array 510 are stacked. The relationship between the substrate 591 and the memory cell array 510 is similar to Figure 5 The relationship shown is the same. That is, gate wiring 140 provided on substrate 591 is connected to bonding electrode P2 via via 593, and bonding electrode P2 is connected to bonding electrode P1 provided on memory cell array 510. Bonding electrode P3 is provided on the lower surface of substrate 591, and gate wiring 140 and bonding electrode P3 are connected via through electrode 190 that penetrates substrate 591.

[0158] Transistor TR22 and Figure 8 The transistor TR22 shown is the same as that shown in FIG. 1 , and therefore its description is omitted. Figure 19 The transistor TR10 shown is the same as that shown in FIG. 1 , so the description thereof is omitted. Figure 8 Similarly, impurity regions 160 and 170 are formed in the trench 150 between the adjacent transistors TR22. On the other hand, in the substrate 599, the impurity region 165 is formed in the trench 155 between the adjacent transistors TR10, but the impurity region 170 is not formed.

[0159] A via 195 is provided in the gate wiring 145 near an end portion of the substrate 599. The via 195 is connected to the bonding electrode P4, and the bonding electrode P4 is connected to the bonding electrode P3.

[0160] As described above, the above-mentioned structure can be formed by forming a transistor for suppressing diffusion of the impurity region 160 (diffusion of boron) on the substrate 591, forming other transistors on the substrate 599, and connecting the substrate 591 and the substrate 599 by bonding electrodes P3 and P4.

[0161] The substrate 599 is sometimes referred to as the "second substrate." The circuit in which the transistor TR10 is provided is sometimes referred to as the "second peripheral circuit." Specifically, the second peripheral circuit includes: a transistor TR10-1 (third transistor) provided in region R4 (fourth region); a transistor TR10-2 (fourth transistor) provided in region R5 (fifth region); a trench 155 (second trench) provided in the substrate 599 (second substrate) in region R6 (sixth region); a gate wiring 145 (second conductive layer) provided above the transistor TR10-1 (third transistor), above the transistor TR10-2 (fourth transistor), and above the trench 155 (second trench) and extending from region R4 (fourth region) to region R5 (fifth region); and an impurity region 165 (second impurity region) provided in the substrate 599 (second substrate) adjacent to the trench 155 (second trench).

[0162] As described above, according to the semiconductor device 10B according to the present embodiment, the same configuration as that of the first embodiment can be applied only to necessary transistors.

[0163] The present invention has been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments and can be appropriately modified without departing from the scope of the present invention. For example, as long as the main purpose of the present invention is maintained, technical solutions obtained by those skilled in the art by appropriately adding, deleting, or modifying the design of components based on the semiconductor device of this embodiment are also included in the scope of the present invention. Furthermore, as long as there is no contradiction between them, the above-described embodiments can be appropriately combined, and technical matters common to each embodiment are included in each embodiment even if not explicitly described.

[0164] Even if there are other effects different from the effects brought about by the technical solutions of the above-mentioned embodiments, effects that are obvious from the description of this specification or can be easily predicted by those skilled in the art are naturally considered to be brought about by the present invention.

Claims

1. A semiconductor device comprising: A first substrate having a first region, a second region, and a third region between the first region and the second region and adjacent to the first region and the second region; a first transistor disposed in the first region; a second transistor disposed in the second region; a first groove provided in the first substrate in the third region; a first conductive layer provided above the first transistor, above the second transistor, and above the first trench, and continuous from the first region to the second region; as well as The first impurity region is provided at a position of the first substrate adjacent to the first trench and contains carbon.

2. The semiconductor device according to claim 1, The first impurity region contains boron.

3. The semiconductor device according to claim 2, The first substrate includes a first surface on which the first transistor and the second transistor are provided, and a second surface opposite to the first surface. In the concentration distribution of carbon and boron in the direction from the first trench toward the second surface, there is a portion where the concentrations of carbon and boron gradually decrease.

4. The semiconductor device according to claim 2, The first groove includes a sidewall portion and a bottom portion, Carbon is present along the sidewall portion, The thickness of the region where boron exists in the bottom portion is greater than the thickness of the region where boron exists in the sidewall portion.

5. The semiconductor device according to claim 2, The first groove includes a sidewall portion and a bottom portion, Carbon is present along the bottom, The thickness of the region where boron exists in the sidewall portion is greater than the thickness of the region where boron exists in the bottom portion.

6. The semiconductor device according to claim 1, The semiconductor device further comprises: a third transistor disposed in the fourth region; a fourth transistor disposed in the fifth region; a second groove provided in the first substrate in the sixth region; a second conductive layer provided above the third transistor, above the fourth transistor, and above the second trench, and extending continuously from the fourth region to the fifth region; as well as a second impurity region provided at a position adjacent to the second trench of the first substrate; The first substrate includes the fourth region, the fifth region, and the sixth region between the fourth region and the fifth region and adjacent to the fourth region and the fifth region. The concentration of carbon contained in the second impurity region is 1E13 / cm 3 the following.

7. A semiconductor memory device comprising: A first substrate having a first region, a second region, and a third region between the first region and the second region and adjacent to the first region and the second region; a first transistor disposed in the first region; a second transistor disposed in the second region; a first groove provided in the first substrate in the third region; a first conductive layer provided above the first transistor, above the second transistor, and above the first trench, and continuous from the first region to the second region; a first impurity region provided at a position of the first substrate adjacent to the first trench and containing carbon; memory cell array; as well as The first peripheral circuit is provided on the first substrate and drives the memory cell array. The first transistor and the second transistor are included in the first peripheral circuit. The first transistor is connected to a first word line provided in the memory cell array. The second transistor is provided in the memory cell array and connected to a second word line adjacent to the first word line.

8. The semiconductor memory device according to claim 7, The semiconductor memory device further includes a second substrate provided with a second peripheral circuit connected to the memory cell array. The second substrate includes a fourth region, a fifth region, and a sixth region between the fourth region and the fifth region and adjacent to the fourth region and the fifth region. The second peripheral circuit includes: a third transistor disposed in the fourth region; a fourth transistor disposed in the fifth region; a second groove provided in the second substrate in the sixth region; a second conductive layer provided above the third transistor, above the fourth transistor, and above the second trench, and extending continuously from the fourth region to the fifth region; and A second impurity region is provided in a position of the second substrate adjacent to the second trench.

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