Method of manufacturing semiconductor device and fan-out panel level package

Abstract

A method of manufacturing a semiconductor device and a fan-out panel level package are provided. A method of manufacturing a semiconductor device may include forming a semiconductor sub-package by performing a fan-out wafer level package process; singulating the semiconductor sub-package from the at least one wafer; and reconstructing the semiconductor sub-package into a fan-out panel level package (FOPLP).

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 564,830, filed on March 13, 2024, and U.S. Non-Provisional Application No. 18 / 752,237, filed on June 24, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure relate to a semiconductor package and a method of manufacturing the same, and more particularly, to a hybrid reconstructed panel-level package and a method of manufacturing the same. Background Art

[0003] To meet the growing demand for high-performance computing and artificial intelligence (AI), the core counts of modern processing units (PUs) (such as central processing units (CPUs), graphics processing units (GPUs), accelerated processing units (APUs), etc.) have been increasing to cope with the slowdown caused by the end of Moore's Law. This has led to chip sizes that are increasingly difficult to arrange for efficient production on current wafer sizes.

[0004] The information disclosed in this background technology section has been known or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired during the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0005] However, the comparative example suffers from a "memory wall" problem due to the increased core count.

[0006] Additionally, there is a need to develop larger form factor package / chip architectures that enable integration of logic and memory dies.

[0007] A solution is also needed to address the increasing challenge of package warpage for large form factor packages.

[0008] Embodiments of the present disclosure may address the above-mentioned problems and / or other problems.

[0009] According to some example embodiments of the present disclosure, a hybrid reconstructed panel-level package and a method of manufacturing the same may be provided.

[0010] According to some example embodiments of the present disclosure, a hybrid reconstructed panel-level package may have a hybrid packaging architecture and may be a large form factor package (e.g., a panel size greater than 80 mm by 80 mm (such as, a panel size of 200 mm by 200 mm or even 600 mm by 600 mm)), may have fine redistribution layer (RDL) line width / space (L / S), and / or may have a high RDL layer count.

[0011] According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor device may be provided, and the method includes: forming a semiconductor sub-package by performing a fan-out wafer-level packaging process; singulating (or dicing) the semiconductor sub-package from at least one wafer; and reconstructing the semiconductor sub-package into a fan-out panel-level package (FOPLP).

[0012] According to some example embodiments of the present disclosure, a FOPLP may be provided, and the FOPLP includes a semiconductor sub-package, the semiconductor sub-package being a fan-out wafer-level package (FOWLP). The semiconductor sub-package may include a first sub-package, the first sub-package including: a redistribution layer; a first bridge on the redistribution layer of the first sub-package; and a semiconductor chip above the first bridge of the first sub-package, the semiconductor chip of the first sub-package being electrically connected to the first bridge of the first sub-package. The semiconductor sub-package may further include a second sub-package, the second sub-package including: a redistribution layer; a first bridge on the redistribution layer of the second sub-package; and a semiconductor chip above the first bridge of the second sub-package, the semiconductor chip of the second sub-package being electrically connected to the first bridge of the second sub-package, wherein, in the FOPLP, the semiconductor sub-packages are arranged adjacent to each other in at least one horizontal direction of the FOPLP.

[0013] According to some example embodiments of the present disclosure, a front-mounted package (FOPLP) may be provided, and the FOPLP includes a semiconductor sub-package, the semiconductor sub-package including a first sub-package, the first sub-package including: a redistribution layer; a first mold layer on the redistribution layer; a first semiconductor chip on the first mold layer; and a second semiconductor chip, different from the first semiconductor chip, on the first mold layer. The semiconductor sub-package may also include a second sub-package. The first mold layer may include: a first bridge electrically connecting one of the first semiconductor chips to a semiconductor chip of the second sub-package, wherein, in the FOPLP, the semiconductor sub-packages are arranged adjacent to each other in at least one horizontal direction of the FOPLP. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0015] Figure 1A A schematic diagram illustrating the predicted yield of semiconductor chips in a fan-out wafer-level packaging process is shown.

[0016] Figure 1B A schematic diagram illustrating the predicted yield of semiconductor chips in a fan-out wafer-level packaging process is shown.

[0017] Figure 1CA schematic diagram illustrating the predicted yield of semiconductor chips in a fan-out wafer-level packaging process is shown.

[0018] Figure 1D A schematic diagram illustrating the predicted yield of semiconductor chips in a fan-out wafer-level packaging process is shown.

[0019] Figure 2 Schematic diagrams illustrating semiconductor packages according to some example embodiments of the present disclosure.

[0020] Figure 3 Schematic diagrams illustrating semiconductor packages according to some example embodiments of the present disclosure.

[0021] Figure 4 Schematic diagrams illustrating sub-packages of a semiconductor package according to some example embodiments of the present disclosure.

[0022] Figure 5 Schematic diagrams illustrating sub-packages of a semiconductor package according to some example embodiments of the present disclosure.

[0023] Figure 6 Schematic cross-sectional views illustrating semiconductor packages according to some example embodiments of the present disclosure.

[0024] Figure 7 Show Figure 6 Schematic cross-sectional view of a portion of a semiconductor package shown in .

[0025] Figure 8A A flowchart illustrating a method of manufacturing a semiconductor package according to some example embodiments of the present disclosure is shown.

[0026] Figure 8B A flowchart illustrating a method of manufacturing a semiconductor package according to some example embodiments of the present disclosure is shown.

[0027] Figure 9 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0028] Figure 10 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0029] Figure 11 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0030] Figure 12 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0031] Figure 13 Shown in Figures 8A to 8BThe method of operations forms a sub-package.

[0032] Figure 14 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0033] Figure 15 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0034] Figure 16 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0035] Figure 17 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0036] Figure 18 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0037] Figure 19 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0038] Figure 20 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0039] Figure 21 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0040] Figure 22 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0041] Figure 23 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0042] Figure 24 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0043] Figure 25 Shown in Figures 8A to 8B The method of operations forms a sub-package.

[0044] Figure 26 Shown in Figures 8A to 8B The method of operations forms a sub-package. DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each of the embodiments provided in the following description does not exclude association with one or more features of another embodiment that is also provided herein or not provided herein but is consistent with the present disclosure. For example, even if a matter described in a particular example embodiment is not described in a different example embodiment, unless otherwise mentioned in its description, the matter may be understood to be associated with or combined with different example embodiments. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future (i.e., all devices that perform the same function regardless of their structure).

[0046] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device (or semiconductor package) is referred to as being "on," "connected to," or "bonded to" another element of the semiconductor device, the element may be directly on, directly connected to, or directly bonded to the other element, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly on," "directly connected to," or "directly bonded to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, like reference numerals refer to like elements.

[0047] For ease of description, spatially relative terms such as "above," "over," "on," "up," "below," "below," "lower," "left," "right," "lower left," "lower right," "upper left," "upper right," "center," and "middle" may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figures. For example, if the semiconductor device in the figures is flipped, an element described as "below" or "beneath" another element would be oriented "above" the other element. Thus, the term "below" can encompass both above and below orientations. The semiconductor device can be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As another example, when elements referred to as "left" and "right" elements are oriented differently in the device or structure that includes these elements, the "left" and "right" elements can be "right" and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, to distinguish the two elements.

[0048] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below could be named the second element without departing from the scope of this disclosure.

[0049] As used herein, a term such as " The expression “at least one of”, when preceding a list of elements, modifies the entire list and does not modify the individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the terms “same” or “equal” are used to compare the sizes of two or more elements, the terms may cover sizes that are “substantially the same” or “substantially equal.”

[0050] It will be understood that when a method of manufacturing a device or structure is described as including multiple steps or operations, a step or operation described as being performed later than another step or operation may be performed before or simultaneously with the other step or operation, unless the other step or operation is described as being required to be performed before the other step or operation. In addition, the method may include additional steps or operations not mentioned in the description.

[0051] Many example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of the embodiments (and intermediate structures). As such, variations from the shapes of the illustrations due, for example, to manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments should not be construed as limited to the specific shapes of the regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The various regions illustrated in the figures are schematic in nature, and the shapes of these regions may not be intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure. Furthermore, in the figures, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0052] For the sake of brevity, conventional elements, structures or layers included in semiconductor packages, including connection pads, adhesive layers, isolation layers, barrier metal patterns, seed layers, etc., may or may not be described in detail herein. For example, when these structural elements are not relevant to certain features of the embodiment, the description of certain connection pads of the semiconductor chip connected to the solder balls or bumps in the semiconductor package may be omitted herein. In addition, when the materials forming known structural elements are not relevant to certain features of the embodiment, the description of those materials may be omitted herein. In this article, the term "connection" between two structures or elements may represent the electrical connection between the two structures or elements. For example, the connection between a semiconductor chip, a semiconductor package and / or a semiconductor device may represent the electrical connection between the corresponding two or more elements. The terms "combination" and "connection" may have the same meaning and may be used interchangeably herein. In addition, the term "isolation" between two structures or elements relates to the electrical insulation or electrical separation between the two structures or elements. For example, the isolation of wiring patterns from each other may mean that the wiring patterns are not electrically connected to each other.

[0053] In the following, reference is made to Figures 1A to 26 Various example embodiments of the present disclosure are described.

[0054] To meet the growing demand for high-performance computing and AI, the core counts of modern processors (CPUs, GPUs, APUs, etc.) have been increasing, countering the slowdown brought on by the end of Moore's Law. For example, the core counts of modern CPUs have recently surpassed 64 cores (66 cores in print). To further meet the needs of modern AI and gaming, current GPU chips feature over a thousand GPU cores. However, as CPU / GPU core counts increase, a new bottleneck has emerged: the "memory wall." The memory wall describes the processor / memory performance gap, which has steadily grown over the past few decades. If memory latency and bandwidth become insufficient to provide the processor with sufficient instructions and data to continue computing, the processor will increasingly stall waiting for memory. The trend of placing more and more cores on a chip exacerbates this situation, as each core has relatively narrow access to shared memory resources. In today's computing architectures, processors extract data from a memory hierarchy, from the fast but low-capacity L1 cache to the L2 cache, to the L3 cache, and then to the relatively slow but high-capacity dynamic random access memory ("DRAM"). To bridge this gap, high-bandwidth memory (HBM) has been introduced and integrated directly with the compute engine using advanced packaging, including 2.5D and 3D integrated circuit (IC) packages. Placing HBM closer to the processor core helps reduce latency while increasing storage capacity. However, latency still exists when transferring large amounts of data between the processor core and HBM via a silicon interposer or active silicon. At the same time, standard HBM that adheres to JEDEC standards has increasingly high power requirements. For example, for a 12H 24GB HBM3, HBM3 power consumption approaches 30W at 6.4Gbps.

[0055] Silicon interposer-based 2.5D packages can be used in large form factor (FF) GPUs, AI, and networking chips. However, silicon interposer-based 2.5D packages are expected to reach their limits, constrained by manufacturing efficiency and technical challenges, including increased warpage and mechanical integrity. Fan-out interposers (at the fan-out or panel level) based on embedded silicon bridges have also been proposed to surpass these limits.

[0056] As package form factors increase, the risk of package warpage increases. Therefore, a solution is needed to address the increasing challenge of package warpage for large form factor packages.

[0057] Furthermore, the AI ​​revolution is driving the need to develop larger form factor (FF) packages / chip architectures that integrate logic dies and memory dies (e.g., DRAM), with more memory placed as close as possible to the logic die to increase memory bandwidth and capacity. This demand is particularly relevant for high-performance computing (HPC) and data centers.

[0058] HBM can be integrated with logic chips into a single package to provide the desired memory bandwidth and capacity to address the memory wall challenge. This type of integration can be achieved using a silicon interposer via a 2.5D IC package. For example, the package can include one channel of HBM chips (e.g., HBM2, HBM3, HBM4) on each side of a logic chip (e.g., a GPU or other application-specific integrated circuit (ASIC)). For example, the package can include six HBM3 chips on a chip, with three HBM3 chips on each side of a central GPU. This chip can be implemented using a 2.5D package with a silicon interposer.

[0059] The silicon bridge can be embedded in fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) that uses overmolding to build a panel-level interposer. The embedded silicon bridge can be used to provide fine electrical routing between system-on-chip (SoC), HBM, and other ASICs because this type of embedded silicon bridge can be manufactured using back-end-of-line (BEOL) manufacturing processes.

[0060] Fan-out packages with fine line width / spacing are typically manufactured via fan-out wafer-level packaging using a fine feature stepper with a limited lithography window size (e.g., 2x the mask size). Fan-out wafer-level packaging can include finer feature sizes (such as finer RDL line width / spacing (L / S)) and higher RDL layer counts. L / S can refer to the width and pitch of the metal traces. However, the fan-out wafer-level packaging of the comparative embodiment may have issues including being limited to a small form factor of a 12-inch wafer size (300 mm diameter).

[0061] For example, in the fan-out wafer level packaging process, refer to Figure 1A Referring to FIG. D , the maximum size of semiconductor chips 910 (also referred to as semiconductor chip dies, silicon chips, or molded chips) that can be economically manufactured from wafer 920 is very limited. Figure 1A 1 to 2 are schematic diagrams for explaining the predicted yield of semiconductor chips in a fan-out wafer-level packaging process.

[0062] Reference Figure 1A, where the semiconductor chip 910 is 80 mm (width) by 80 mm (height), four semiconductor chips 910 can be economically manufactured (ie, with minimal process defects) from the wafer 920 when the wafer 920 has a diameter of 300 mm. Figure 1B , in the case where the semiconductor chip 910 is 100 mm (width) by 100 mm (height), and in the case where the wafer 920 has a diameter of 300 mm, one semiconductor chip 910 can be economically manufactured from the wafer 920. Figure 1C , in the case where the semiconductor chip 910 is 120 mm (width) by 120 mm (height), and in the case where the wafer 920 has a diameter of 300 mm, one semiconductor chip 910 can be economically manufactured from the wafer 920. Figure 1D , in the case where semiconductor chip 910 is 150 mm (width) by 150 mm (height), no semiconductor chip 910 can be economically manufactured from wafer 920 when wafer 920 has a diameter of 300 mm. Therefore, in the fan-out wafer-level packaging process, the maximum size of semiconductor chip 910 that can be economically manufactured from wafer 920 (in the case where wafer 920 has a diameter of 300 mm) may be 120 mm (width) by 120 mm (height). In addition, given this manufacturing constraint, it may not be possible to directly manufacture semiconductor chip 910 (or molded package) having a size of 150 mm (width) by 150 mm (height) using the fan-out wafer-level packaging process.

[0063] While it may be technically possible to manufacture more than four semiconductor chips 910 from a wafer 920 if the wafer 920 has a diameter of 300 mm, at least some of the semiconductor chips 910 in such an arrangement would be too close to the edge of the wafer 920, which could result in at least some of the semiconductor chips 910 being defective. That is, at the edge of a wafer (e.g., wafer 920), process errors are very high, potentially leading to defects in the semiconductor chips 910 placed at the edge of the wafer. Therefore, it is generally uneconomical to manufacture more than four semiconductor chips 910 each having a size of 80 mm (width) by 80 mm (height), or more than one semiconductor chip 910 each having a size of 100 mm (width) by 100 mm (height), or 120 mm (width) by 120 mm (height), from a single wafer 920 having a diameter of 300 mm.

[0064] Another type of fan-out packaging is fan-out panel-level packaging. Compared to fan-out wafer-level packaging, fan-out panel-level packaging may have advantages including a larger package form factor and disadvantages including a larger RDL L / S and a lower RDL layer count.

[0065] Because the panel-level packaging in the comparative embodiment includes coarse wiring L / S and a low RDL count (e.g., 1 RDL layer), a large form factor package with fine features and a large number of RDL layers in the comparative embodiment may not be achievable by fan-out panel-level packaging alone. For example, when forming the large form factor package of the comparative embodiment, it may be difficult to control manufacturing tolerances due to the larger size.

[0066] According to some example embodiments of the present disclosure, a large form factor panel-level package (e.g., a fan-out panel-level package (FOPLP)) having a hybrid packaging architecture may be provided. For example, a large form factor panel-level package may be formed by reconstructing and integrating a plurality of singulated fan-out packages (also referred to as sub-packages, interposer blocks, or sub-interposers). For example, a sub-package to be reconstructed into a large form factor panel-level package (or FOPLP) may have fine features including, but not limited to, fine line / space (L / S) and multiple redistribution (RDL) layers. For example, a sub-package may have a line width (or L / S) of 1 μm to 2 μm and may include 6 RDL layers. For example, the sub-packages may each be a fan-out wafer-level package (FOWLP) manufactured in a fan-out wafer-level packaging process, or may each be a FOPLP manufactured in a fan-out panel-level packaging process.

[0067] According to some example embodiments of the present disclosure, an expanded form factor can be achieved by integrating multiple fan-out packages as sub-packages (or interposer blocks or sub-interposers) into one panel-level package (e.g., FOPLP) through reconstruction. For example, the one panel-level package (e.g., FOPLP) can be a large form factor package with fine features and a large number of RDL layers for routing through the structure and / or meeting signal integrity / power integrity (SI / PI) requirements.

[0068] According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor package having a hybrid package architecture may be provided.

[0069] According to some example embodiments of the present disclosure, a semiconductor package (e.g., FOPLP) having a hybrid packaging architecture may be provided that integrates the advantages of fan-out wafer-level packaging and fan-out panel-level packaging while also avoiding the disadvantages of fan-out wafer-level packaging and fan-out panel-level packaging. Such advantages of fan-out wafer-level packaging may include finer feature sizes (such as finer RDL L / S) and higher RDL layer counts, and such disadvantages that may be avoided of fan-out wafer-level packaging may include a smaller form factor (compared to fan-out panel-level packaging). Such advantages of fan-out panel-level packaging may include a larger package form factor, and such disadvantages that may be avoided of fan-out panel-level packaging may include a coarse RDL L / S and lower RDL layer count (compared to fan-out wafer-level packaging).

[0070] According to some example embodiments of the present disclosure, a semiconductor package (e.g., FOPLP) having a hybrid packaging architecture that can be manufactured by the method can be a large form factor package (e.g., greater than 80 mm by 80 mm (such as a full panel size of 150 mm by 150 mm, 200 mm by 200 mm, 300 mm by 300 mm, or even 600 mm by 600 mm)) and can have fine RDL L / S and a high RDL layer count. For example, the semiconductor package can be a large form factor package that enables an increased amount of ASICs and memories to be integrated into a single package with fine features and a large number of RDL layers for routing and / or meeting signal SI / PI requirements.

[0071] Reference Figures 2 to 8B , a semiconductor package 1 according to some example embodiments of the present disclosure is described below. The semiconductor package 1 is an example of a semiconductor package (e.g., FOPLP) having a hybrid package architecture, and the semiconductor package may be a large form factor package, have a fine RDL L / S, and have a high RDL layer count.

[0072] Figure 2 A schematic diagram illustrating a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figure 2 A schematic diagram illustrating a semiconductor package 1 having a first configuration according to some example embodiments of the present disclosure is shown. Figure 3 A schematic diagram illustrating a semiconductor package 1 having a second configuration according to some example embodiments of the present disclosure is shown. Figure 4 A schematic diagram illustrating a sub-package 2 of a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figure 5 A schematic diagram illustrating a sub-package 2 of a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figure 6A schematic cross-sectional view illustrating a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figure 7 Show Figure 6 Schematic cross-sectional view of a portion of a semiconductor package 1 shown in FIG.

[0073] According to some example embodiments of the present disclosure, the semiconductor package 1 may be a hybrid reconstructed panel-level package manufactured using a hybrid reconstructed panel-level packaging process. For example, the semiconductor package 1 may be a FOPLP including a sub-package 2. As further described herein, the sub-package 2 may be singulated from a package (e.g., a FOWLP or a FOPLP) and reconstructed into the semiconductor package 1 using a fan-out panel-level packaging process of the hybrid reconstructed panel-level packaging process. In the case where the sub-package 2 is singulated from the FOWLP, such a FOWLP (and the sub-package 2 of the FOWLP) may be manufactured using a fan-out wafer-level packaging process of the hybrid reconstructed panel-level packaging process. In the case where the sub-package 2 is singulated from the FOPLP, such a FOPLP (and the sub-package 2 of the FOPLP) may be manufactured using an additional fan-out panel-level packaging process of the hybrid reconstructed panel-level packaging process. According to some example embodiments, the additional fan-out panel-level packaging process for manufacturing the sub-package 2 may be the same as or substantially similar to the fan-out panel-level packaging process for reconstructing the sub-package 2 into the semiconductor package 1, such that the fan-out panel-level packaging process is iteratively performed to form the sub-package 2 and then to form the semiconductor package 1. According to some example embodiments, the additional fan-out panel-level packaging process for manufacturing the sub-package 2 may be different from the fan-out panel-level packaging process for reconstructing the sub-package 2 into the semiconductor package 1.

[0074] like Figure 2As shown in , semiconductor package 1 may include any number (N) of sub-packages 2 greater than 1. In the illustrated example, six sub-packages 2 (N=6) are shown. For example, semiconductor package 1 may include sub-package 2A, sub-package 2B, sub-package 2C, sub-package 2D, sub-package 2E, and sub-package 2F, wherein sub-package 2A, sub-package 2C, sub-package 2D, and sub-package 2F may be corner sub-packages that may define respective corners of semiconductor package 1 and have a first shape, while sub-package 2B and sub-package 2E may be inner sub-packages that further define portions between the corners of semiconductor package 1 and have a second shape that may be different from the first shape. For example, in a plan view, sub-package 2A may be the upper left corner of semiconductor package 1, sub-package 2B may be adjacent to the right side of sub-package 2A, sub-package 2C may be adjacent to the right side of sub-package 2B and may define the upper right corner of semiconductor package 1, sub-package 2D may be adjacent to the lower side of sub-package 2A and define the lower left corner of semiconductor package 1, sub-package 2E may be adjacent to the right side of sub-package 2D, and sub-package 2F may be adjacent to the right side of sub-package 2E and may define the lower right corner of semiconductor package 1. However, the embodiments of the present disclosure are not limited thereto. For example, the arrangement and number of sub-packages 2 in semiconductor package 1 may be changed. For example, as Figure 3 As shown in , the semiconductor package 1 may include sub-package 2A, sub-package 2C, sub-package 2D, and sub-package 2F while omitting sub-package 2B and sub-package 2E and only including four sub-packages 2 as corner sub-packages. In other example embodiments of the present disclosure, the semiconductor package 1 may have sub-packages 2 that do not include the edges of the semiconductor package 1 (such as, for example, a semiconductor package 1 having nine sub-packages 2 may have four corner sub-packages 2, four edge sub-packages 2, and a center sub-package 2). According to some example embodiments, the semiconductor package 1, the sub-packages 2, and the arrangement of the sub-packages 2 within the semiconductor package 1 may each have a rectangular shape. In other possible embodiments, the sub-packages 2 may have other shapes (such as triangles, hexagons, irregular shapes, etc.) depending on the desired final shape of the semiconductor package 1.

[0075] Reference Figures 2 to 7 , each of the sub-packages 2 may include a first semiconductor chip 10 , a second semiconductor chip 12 , and a first bridge 30 .

[0076] The first semiconductor chip 10 may be, for example, a SoC or an ASIC. According to some example embodiments, the first semiconductor chips 10 may be arranged in an array pattern. For example, the array pattern may be a five (row) by five (column) array pattern, but the embodiments of the present disclosure are not limited thereto. For example, the first semiconductor chips 10 may be arranged in any configuration. According to some example embodiments, the first semiconductor chips 10 may be chips of the same or different types (including but not limited to SoCs, ASICs, fabric chips, input / output (I / O) chips, HBMs, SerDe chips, etc.), and the chips may have the same or different sizes.

[0077] The second semiconductor chip 12 may be, for example, a memory device (e.g., HBM). According to some example embodiments, the second semiconductor chip 12 may be arranged at and along at least one side of each of the sub-packages 2 that defines an outer side of the semiconductor package 1. For example, each of the corner sub-packages (e.g., sub-package 2A, sub-package 2C, sub-package 2D, and sub-package 2F) may include at least one row (or at least one column) of second semiconductor chips 12 at and along a first side of the corner sub-package that defines a first outer side of the semiconductor package 1, and at least one column (or at least one row) of second semiconductor chips 12 at and along a second side of the corner sub-package that defines a second outer side of the semiconductor package 1. Furthermore, the inner sub-packages (e.g., sub-package 2B and sub-package 2E) may include at least one row (or at least one column) of second semiconductor chips 12 at and along one side of the inner sub-package that defines the outer side of semiconductor package 1. However, the arrangement of the second semiconductor chips 12 according to example embodiments of the present disclosure is not limited. For example, the second semiconductor chips 12 may be arranged in any configuration. According to some example embodiments, the second semiconductor chips 12 may be chips of the same or different types (including but not limited to SOCs, ASICs, fabric chips, I / O chips, HBMs, SerDe chips, etc.), and the chips may have the same or different sizes.

[0078] Furthermore, the arrangement of the first and second semiconductor chips 10 and 12 relative to each other is not limited. For example, one or more of the first semiconductor chips 10 (or second semiconductor chips 12 ) may be stacked on one or more of the second semiconductor chips 12 (or first semiconductor chips 10 ).

[0079] The first bridge (first bridge chip) 30 may be, for example, an embedded bridge and may include silicon (Si). According to some example embodiments, a plurality of first bridges 30 may electrically connect the first semiconductor chip 10 to respective adjacent components (such as, for example, an adjacent one of the first semiconductor chips 10 , an adjacent one of the second semiconductor chips 12 , and an adjacent one of the second bridges 20 (described below)). For example, in a plan view, four first bridges 30 may be provided at respective sides (e.g., the left side, top side, right side, and bottom side in the plan view) of each of the first semiconductor chips 10 to electrically connect the first semiconductor chip 10 to the components adjacent to the first semiconductor chip 10 on the respective sides (e.g., an adjacent one of the first semiconductor chips 10 , an adjacent one of the second semiconductor chips 12 , or an adjacent one of the second bridges 20 ).

[0080] The semiconductor package 1 may further include a second bridge 20. The second bridge 20 may be referred to as a top connection bridge and may include, for example, silicon. The second bridge 20 may be connected to the sub-package 2 by the gap G (eg, see Figure 3 and Figure 6 ) are stacked so that the adjacent sub-packages 2 in the sub-packages 2 are electrically connected. The gap G may be in a first horizontal direction (eg, direction X; for example, see Figure 3 and Figures 6 and 7 ) and a second horizontal direction (e.g., direction Y; see, for example, Figure 3 and Figures 6 and 7 ) extends between pairs of adjacent sub-packages 2 in the sub-packages 2. According to some example embodiments, the second bridge 20 may overlap the gap G. According to some example embodiments, the first horizontal direction and the second horizontal direction may be non-parallel and non-perpendicular to each other, or may be perpendicular to each other.

[0081] In some embodiments, the second bridge 20 can overlap with pairs of adjacent sub-packages 2 in the sub-package 2 separated by a gap G, and can each electrically connect together the pairs of first bridges 30 of the pairs of adjacent sub-packages 2 closest to the gap G, thereby electrically connecting the adjacent sub-packages 2.

[0082] Therefore, since the second bridge 20 is electrically connected to the pair of first bridges 30 , a pair of first semiconductor chips 10 respectively belonging to a pair of sub-packages 2 adjacent to each other (excluding the first bridge chip 30 ) can be electrically connected together through the second bridge 20 overlapping the pair of sub-packages 2 .

[0083] The semiconductor package 1 may further include a molding material 90 that surrounds each of the sub-packages 2 and forms outer edges (e.g., the left edge, top edge, right edge, and bottom edge in plan view) of the semiconductor package 1. For example, portions of the molding material 90 may be between and in contact with each pair of adjacent sub-packages 2.

[0084] Reference Figures 6 and 7 , the following describes the configuration of a pair of sub-packages 2 adjacent to each other. As an example, Figures 6 and 7 Schematic cross-sectional views of sub-package 2D and sub-package 2A are shown, and the following description may refer to sub-package 2D and sub-package 2A. However, one of ordinary skill in the art will understand that the following description may apply to each pair of sub-packages 2 adjacent to each other. In addition, for clarity, Figures 6 and 7 Illustration of some components (eg, some first semiconductor chips 10 ) may be omitted.

[0085] Reference Figures 6 and 7 , each of the sub-packages 2 may include at least one lower RDL layer 40 , a first mold layer 50 , at least one upper RDL layer 60 , a second mold layer 70 , a first semiconductor chip 10 , a second semiconductor chip 12 , and a first bridge 30 .

[0086] According to example embodiments, the at least one lower RDL layer 40 may include four RDL layers. For example, the lower RDL layer 40 may include a plurality of RDL layers in a vertical direction (eg, direction Z; for example, see Figure 3 and Figures 6 and 7 ) in the order shown. However, embodiments of the present disclosure are not limited thereto, and more or less than four RDL layers may be included in at least one lower RDL layer 40. For example, the number of lower RDL layers 40 may be six or more (e.g., seven or more). According to some example embodiments, the line width (or L / S) of the RDL layer 40 may be 1 μm to 2 μm.

[0087] According to some example embodiments, each of the lower RDL layers 40 may include a dielectric layer including interconnect structures for electrical connection between components. The interconnect structures may include, for example, interconnect patterns 46 and interconnect vias 47. The interconnect patterns 46 may extend horizontally in one or more layers of the lower RDL layers 40, and the interconnect vias 47 may extend vertically (e.g., direction Z) through the dielectric layer of at least one layer of the lower RDL layers 40 to electrically connect at least two of the interconnect patterns 46 and / or at least two semiconductor devices (e.g., the first semiconductor chip 10, the second semiconductor chip 12, and / or another semiconductor chip within or outside the sub-package 2). The interconnect patterns 46 and the interconnect vias 47 may include a material including at least one of the following: copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), and alloys thereof (e.g., TiN, TaN). However, the metal materials are not limited thereto. The dielectric layer may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN).

[0088] According to some example embodiments, the interconnection pattern 46 of the first RDL layer 41 may be exposed from the lower surface of the dielectric layer of the first RDL layer 41 and may be electrically connected to a component outside the sub-package 2. For example, such an interconnection pattern 46 may be a pad for electrical connection. For example, the interconnection pattern 46 may be a land grid array copper pad, and solder bumps may be formed under at least some of the pads. According to some example embodiments, a spring-based electrical connection may provide electrical contact between the interconnection pattern 46 and the exterior of the sub-package 2.

[0089] According to some example embodiments, the exposed lower surface of the interconnection pattern 46 of the first RDL layer 41 and the lower surface of the dielectric layer of the first RDL layer 41 may define a lower surface of the sub-package 2. According to some example embodiments, ball grid array (BGA) balls may be mounted on the lower surface of the sub-package 2 for electrical connection.

[0090] According to some example embodiments, a first mold layer 50 may be formed on the upper surface of at least one lower RDL layer 40. Pillars 48 (e.g., copper pillars) and the first bridge 30 may be provided in the first mold layer 50. For example, the first mold layer 50 may surround and contact the side surfaces of the pillars 48 and the side surfaces of the first bridge 30. The pillars 48 may extend vertically from the interconnection patterns 46 of the RDL layer 40 and may be electrically connected to the interconnection patterns 46 of the RDL layer 40. The pillars 48 may extend through the first mold layer 50 so as to be exposed at the upper surface of the first mold layer 50. The first bridge 30 may be electrically connected to the interconnection patterns 46 of the RDL layer 40.

[0091] According to some example embodiments, the upper RDL layer 60 may be on the upper surface of the first mold layer 50 and at least partially on the upper surface of the first bridge 30 , and may electrically connect components in the first mold layer 50 (e.g., the pillars 48 and / or the first bridge 30 ) to components above the upper RDL layer 60 (e.g., the first semiconductor chip 10 and / or the second semiconductor chip 12 ). For example, the upper RDL layer 60 may include a dielectric layer including an interconnect structure for electrical connection between the components. For example, the interconnect structure may include a first pad 54 (or bump) electrically connecting the pillar 48 to the first semiconductor chip 10 , and may also include a second pad 32 (or bump) electrically connecting the first bridge 30 to one or more of the first semiconductor chip 10 , the second semiconductor chip 12 , and the second bridge 20 . The interconnect structure may also include vias to form electrical connections to the pads (e.g., the first pad 54 and / or the second pad 32 ). According to some example embodiments, the first pad 54 (or bump) and the second pad 32 (or bump) may include a material including at least one of the following materials: copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), and alloys thereof (e.g., TiN, TaN). However, the metal material is not limited thereto. The dielectric layer may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN). According to some example embodiments, the upper RDL layer 60 may be one or more RDL layers.

[0092] According to some example embodiments, a second mold layer 70 may be on an upper surface of the upper RDL layer 60. In the second mold layer 70, the first semiconductor chip 10 and the second semiconductor chip 12 may be disposed. For example, the second mold layer 70 may surround and contact the side surfaces of the first semiconductor chip 10 and the side surfaces of the second semiconductor chip 12. The upper surfaces of the first semiconductor chip 10 and the second semiconductor chip 12 may be exposed from the upper surface of the second mold layer 70, and at least at contact points with the upper RDL layer 60, the lower surfaces of the first semiconductor chip 10 and the second semiconductor chip 12 may be exposed from the lower surface of the second mold layer 70. According to some example embodiments, the upper surface of the first semiconductor chip 10, the upper surface of the second semiconductor chip 12, and the upper surface of the second mold layer 70 may define the upper surface of the sub-package 2.

[0093] As discussed above, the molding material 90 may surround each of the sub-packages 2 and form the outer sides (e.g., the left side, top side, right side, and bottom side in plan view) of the semiconductor package 1. For example, a first portion 92 of the molding material 90 may form the outer sides of the semiconductor package 1. The first portion 92 of the molding material 90 may contact the side surfaces of the lower RDL layer 40 (e.g., the dielectric layer of the lower RDL layer 40), the side surfaces of the first molding layer 50, the side surfaces of the upper RDL layer 60 (e.g., the dielectric layer of the upper RDL layer 60), and the side surfaces of the second molding layer 70. A second portion 94 of the molding material 90 may be formed within the gap G between adjacent pairs of sub-packages 2. For example, the second portion 94 may be between sub-package 2D and sub-package 2A, within gap G, and may contact the side surfaces of the lower RDL layer 40 (e.g., the dielectric layer of the lower RDL layer 40), the side surfaces of the first mold layer 50, and the side surfaces of the upper RDL layer 60 (e.g., the dielectric layer of the upper RDL layer 60) of each of sub-package 2D and sub-package 2A. A third portion 96 of the molding material 90 may extend from the upper end of the second portion 94 of the molding material 90. For example, the third portion 96 of the molding material 90 may extend over the upper surface of the upper RDL layer 60 and the side surfaces of the second mold layer 70 of the adjacent pair of sub-packages 2 (e.g., sub-package 2D and sub-package 2A). The third portion 96 of the molding material 90 may surround (e.g., at least partially surround) and contact the bottom and side surfaces of the second bridge 20. For example, the second bridge 20 may be within the third portion 96 of the molding material 90 , and the upper surface of the second bridge 20 may be exposed from the upper surface of the third portion 96 of the molding material 90 .

[0094] According to some example embodiments, the third pad 22 (or bump) may extend through the third portion 96 of the molding material 90 and may electrically connect at least some of the first bridges 30 (e.g., first bridges 30 below the third portion 96 and / or adjacent to the second portion 94) to the second bridge 20 via the second pad 32 (or bump). According to some example embodiments, the third pad 22 (or bump) may include a material including at least one of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, nickel (Ni), gold (Au), cobalt (Co), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), and alloys thereof (e.g., TiN, TaN), however, the metal material is not limited thereto. The third pad 22 (or bump) may include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon carbonitride (SiCN).

[0095] Refer to Figures 8 to Figure 25 , the manufacturing process of the semiconductor package 1 is described below.

[0096] Figure 8A A flowchart illustrating a method 100 of manufacturing a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figure 8B A flowchart illustrating a method 200 of manufacturing a semiconductor package 1 according to some example embodiments of the present disclosure is shown. Figures 9 to 25 Shown in Figures 8A to 8B The method of operations forms a sub-package. Figure 26 Shown in Figures 8A to 8B The method and operations are performed to form a semiconductor package.

[0097] Reference Figure 8A The method 100 may include forming a plurality of sub-packages 2 (operation 110 ), singulating the sub-packages 2 (operation 120 ), and reconstructing the sub-packages 2 into semiconductor packages 1 (operation 130 ).

[0098] Operation 110 may include manufacturing a FOWLP as the sub-package 2 by performing a fan-out wafer-level packaging process, or manufacturing a FOPLP as the sub-package 2 by performing a fan-out panel-level packaging process. In the case where the sub-package 2 is a FOWLP, the sub-package 2 may have fine RDL features and a large RDL layer count by using a stepper with a small lithography window size in the fan-out wafer-level packaging process. According to some example embodiments, any number of sub-packages 2 that are later reconstructed into the semiconductor package 1 may be manufactured from the same wafer or different wafers. An example of a wafer is Figure 1A To wafer 920 of FIG. D. According to some example embodiments, the wafer may have a circular shape in a plan view. According to some example embodiments, operation 110 may include the following Figure 8B Operations 205 to 245 of method 200 are performed.

[0099] Operation 120 may include singulating the sub-packages 2 from the wafer from which the sub-packages 2 are manufactured. For example, in the case where a plurality of sub-packages 2 are manufactured from the same wafer, the plurality of sub-packages 2 may be separated from each other by performing singulation. Figure 8B The method 200 performs operation 120 at different times. For example, according to an example embodiment, operation 120 may be performed at Figure 8B Operation 120 is performed after operation 245 of method 200 and before operation 250. According to example embodiments, operation 120 may be performed at a different time before operation 245.

[0100] Operation 130 may include reconstructing the sub-package 2 into the semiconductor package 1 after being singulated in operation 120. For example, the semiconductor package may be a FOPLP having a hybrid package architecture, and the semiconductor package may be a large form factor package, have a fine RDL L / S, and have a high RDL layer count. Operation 130 may include the following: Figure 8B According to some example embodiments, operation 130 may refer to performing a fan-out panel level packaging process.

[0101] Reference Figure 8B The method 200 may include forming a lower RDL layer 40 (operation 205), forming pillars 48 (operation 210), providing a first bridge 30 (operation 215), forming a first molding layer 50 (operation 220), forming an upper RDL layer 60 (operation 225), providing semiconductor chips (e.g., a first semiconductor chip 10 and a second semiconductor chip 12) and a sacrificial die 80 (operation 230), forming a second molding layer 70 (operation 235), separating the carrier 300 (operation 240), exposing and removing the sacrificial die 80 (operation 245), connecting the sub-package 2 with the second bridge 20 (operation 250), forming a panel-level molding (e.g., a molding material 90) (operation 255), and exposing the semiconductor chips (e.g., the first semiconductor chip 10 and the second semiconductor chip 12) (operation 260).

[0102] Reference Figure 9 Operation 205 may include forming a lower RDL layer 40 on the upper surface of the carrier 300. For example, the carrier 300 may be a substrate configured to support components thereon during a manufacturing process. The lower RDL layer 40 may include, for example, a first RDL layer 41, a second RDL layer 42, a third RDL layer 43, and a fourth RDL layer 44, but embodiments of the present disclosure are not limited thereto.

[0103] Reference Figure 10 Operation 210 may include forming pillars 48 on the upper surface of the lower RDL layer 40. For example, pillars 48 may be formed on the upper surface of the fourth RDL layer 44. For example, the interconnection patterns 46 (refer to Figure 7 ) is formed on the pillar 48. According to some example embodiments, any number of pillars 48 may be provided.

[0104] Reference Figure 11 , operation 215 may include providing a first bridge 30 on the upper surface of the lower RDL layer 40. For example, the first bridge 30 may be provided on the upper surface of the fourth RDL layer 44. For example, the first bridge 30 may be provided so as to be electrically connected to the interconnection pattern 46 (refer to Figure 7According to some example embodiments, any number of first bridges 30 may be provided.

[0105] Reference Figure 12 Operation 220 may include forming a first mold layer 50 on the upper surface of the lower RDL layer 40. For example, the first mold layer 50 may be formed on the upper surface of the fourth RDL layer 44. For example, the first mold layer 50 may surround and contact the side surfaces of the pillars 48 and the first bridge 30.

[0106] Reference Figure 13 Operation 225 may include forming an upper RDL layer 60 on the upper surface of the first mold layer 50. According to some example embodiments, the upper RDL layer 60 may include any number of RDL layers and may also include any number of first pads 54 (or bumps) and second pads 32 (or bumps).

[0107] Reference Figure 14 Operation 230 may include disposing a first semiconductor chip 10, a second semiconductor chip 12, and a sacrificial die 80 on the upper surface of the upper RDL layer 60. For example, the first semiconductor chip 10 may be disposed so as to be electrically connected to the pillars 48 via the first pads 54 (or bumps), and to at least some of the first bridges 30 via some of the second pads 32 (or bumps). For example, the second semiconductor chip 12 may be disposed so as to be electrically connected to at least some of the first bridges 30 via some of the second pads 32 (or bumps). For example, the sacrificial die 80 may be disposed at a lateral end of the sub-package 2, which may correspond to a side of the sub-package 2 that will be adjacent to another sub-package 2. According to some example embodiments, the thickness of the sacrificial die 80 may be greater than the thickness of each of the first semiconductor chip 10 and the second semiconductor chip 12. For example, the upper surface of the sacrificial die 80 may be at a higher level than the upper surfaces of the first and second semiconductor chips 10 and 12. According to some example embodiments, any number of first and second semiconductor chips 10 and 12 may be disposed.

[0108] Reference Figure 15 Operation 235 may include forming a second mold layer 70 on the upper surface of the upper RDL layer 60. For example, the second mold layer 70 may surround and contact the upper and side surfaces of the first and second semiconductor chips 10 and 12, and may surround and contact the upper and inner side surfaces of the sacrificial die 80.

[0109] Reference Figure 16, operation 240 may include separating the carrier 300 from the lower RDL layer 40. For example, the carrier 300 may be separated from the first RDL layer 41. According to some example embodiments, operation 240 may be performed after operation 235 and before operation 245, but embodiments of the present disclosure are not limited thereto. For example, operation 240 may be performed after one or more of operation 245, operation 250, operation 255, and operation 260.

[0110] Reference Figures 17 and 18 , operation 245 may include exposing and removing the sacrificial die 80. For example, referring to Figure 17 , exposing the sacrificial die 80 may include grinding away the upper surface of the second mold layer 70 so as to expose the upper surface of the sacrificial die 80 from the second mold layer 70. According to some example embodiments, a portion of the sacrificial die 80 may also be ground away during such a process, or the entirety of the sacrificial die 80 may remain after grinding. Figure 18 Removing the sacrificial die 80 may include etching the exposed sacrificial die 80. For example, etching may include wet etching using, for example, potassium hydroxide (KOH).

[0111] According to some embodiments, reference Figure 19 ,exist Figure 14 After operation 230 shown in Figure 15 Prior to operation 235 shown in FIG, a dielectric layer 400 may be provided (e.g., deposited) on the upper surfaces of the first semiconductor chip 10 and the second semiconductor chip 12. The dielectric layer 400 may be configured to protect the first semiconductor chip 10 and the second semiconductor chip 12 during an etching process (e.g., a wet etching process) such as described above with respect to operation 245. For example, Figures 20 to 23 An embodiment including a dielectric layer 400 is shown while undergoing operation 235 , operation 240 , and operation 245 .

[0112] According to some example embodiments, operations 205 to 245 may be performed for any number of intermediate packages 2'. Thus, any number of intermediate packages 2' (intermediate packages 2' may also be referred to as sub-packages 2) that have undergone operations 205 to 245 may then be processed as described above with respect to Figure 8A The semiconductor package 1 is reconstructed as described in operation 130 .

[0113] According to some example embodiments, it is possible to Figure 8BThe intermediate package 2' may be singulated before or after various operations of method 200. For example, the intermediate package 2' may be singulated before any one of operations 210 to 250, and the remaining operations of method 200 may be performed after singulation. In other words, operation 120 of method 100 may be performed before any one or more of operations 210 to 250, and the remaining operations of method 200 may be performed after singulation.

[0114] Reference Figure 24 Operation 250 may include connecting any number of sub-packages 2 by connecting the second bridges 20. For example, the sub-packages 2 may be connected in a panel layout (e.g., referring to FIG. Figures 2 to 3 The sub-packages 2 are arranged according to the exemplary layout of the sub-packages 2 shown in FIG. 1 , and the second bridges 20 may be mounted on the pairs of sub-packages 2 arranged adjacent to each other so that each second bridge 20 overlaps a pair of sub-packages 2. For example, referring to FIG. Figure 7 The second bridges 20 may have second pads 32 (or bumps) on their bottom surfaces, and the bottom surfaces of the second bridges 20 are electrically connected to the corresponding paired first bridges 30 via the second pads 32 (or bumps). For example, the second bridges 20 may be connected to the corresponding paired first bridges 30 via a thermocompression bonding (TCB) process or another mounting process.

[0115] Reference Figure 25 , operation 255 may include forming a molding material 90 which may be referred to as panel level molding. For example, referring to Figure 7 , the molding material 90 may be formed to include a first portion 92 , a second portion 94 , and a third portion 96 .

[0116] Reference Figure 26 Operation 260 may include exposing the first semiconductor chip 10 and the second semiconductor chip 12. For example, the exposing may include grinding away the upper surface of the second mold layer 70 and the upper surface of the molding material 90 (e.g., the upper surface of the first portion 92 and the third portion 96) to expose the upper surfaces of the first semiconductor chip 10 and the second semiconductor chip 12 from the second mold layer 70. By performing the grinding process, the upper surfaces of the second mold layer 70, the molding material 90, the first semiconductor chip 10, and the second semiconductor chip 12 may become coplanar with each other.

[0117] According to the above, the semiconductor package 1 according to some example embodiments of the present disclosure may be manufactured.

[0118] According to some example embodiments, the semiconductor package 1 may be a semiconductor interposer.

[0119] According to some example embodiments, the sub-packages 2 may each be a semiconductor interposer block (also referred to as a “semiconductor sub-interposer”).

[0120] According to some example embodiments, a hybrid reconstructed panel-level package (e.g., semiconductor package 1) may be provided with an additional substrate thereunder, and / or the hybrid reconstructed panel-level package may be configured to be directly integrated with other components (e.g., a printed circuit board (PCB) and / or a power delivery unit).

[0121] According to some example embodiments, the FOPLP (eg, the semiconductor package 1 ) may be provided in a large form factor, such as, for example, a wafer larger than a standard 12-inch wafer (300 mm in diameter).

[0122] Although non-limiting example embodiments have been described above with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a semiconductor sub-package by performing a fan-out wafer-level packaging process; singulating semiconductor subpackages from at least one wafer; as well as Reconstructing semiconductor sub-packages into fan-out panel-level packages.

2. The method according to claim 1, wherein The steps of forming a semiconductor subpackage include: A first sub-package among the semiconductor sub-packages is formed by the following steps: forming a redistribution layer of the first subpackage; providing a first bridge on the redistribution layer of the first subpackage; and disposing a semiconductor chip over the first bridge of the first sub-package, the semiconductor chip of the first sub-package being electrically connected to the first bridge of the first sub-package; and A second sub-package among the semiconductor sub-packages is formed by the following steps: forming a redistribution layer of the second sub-package; providing a first bridge on the redistribution layer of the second sub-package; and A semiconductor chip is disposed over the first bridge of the second sub-package, and the semiconductor chip of the second sub-package is electrically connected to the first bridge of the second sub-package.

3. The method according to claim 1, wherein The steps to reconstruct a semiconductor sub-package into a fan-out panel-level package include: arranging a first sub-package among the semiconductor sub-packages and a second sub-package among the semiconductor sub-packages adjacent to each other; and A second bridge is provided that electrically connects the first bridge of the first sub-package to the first bridge of the second sub-package.

4. The method according to claim 3, wherein: The second bridge is on the first sub-package and the second sub-package.

5. The method according to claim 4, wherein Reconfiguring the semiconductor sub-package into a fan-out panel-level package further includes forming a molding material between the first sub-package and the second sub-package and at least partially surrounding the second bridge.

6. The method according to claim 3, wherein: The number of redistribution layers of at least one of the first sub-package and the second sub-package is four or more.

7. The method according to claim 3, wherein: The number of redistribution layers of each of the first sub-package and the second sub-package is four or more.

8. The method according to claim 3, wherein: The redistribution layer of at least one of the first sub-package and the second sub-package has a line width / space equal to or less than 2 μm.

9. The method according to claim 2, wherein: The steps to reconstruct a semiconductor sub-package into a fan-out panel-level package include: arranging the first sub-package and the second sub-package adjacent to each other; and A second bridge is provided that electrically connects the first bridge of the first sub-package to the first bridge of the second sub-package.

10. The method according to claim 9, wherein: The second bridge is on the first sub-package and the second sub-package.

11. A fan-out panel-level package, comprising: A semiconductor sub-package, wherein the semiconductor sub-package is a fan-out wafer-level package, and the semiconductor sub-package includes a first sub-package and a second sub-package, wherein: The first sub-package includes: a redistribution layer; a first bridge on the redistribution layer of the first sub-package; and a semiconductor chip above the first bridge of the first sub-package, the semiconductor chip of the first sub-package being electrically connected to the first bridge of the first sub-package; and The second sub-package includes: a redistribution layer; a first bridge on the redistribution layer of the second sub-package; and a semiconductor chip above the first bridge of the second sub-package, the semiconductor chip of the second sub-package being electrically connected to the first bridge of the second sub-package, and In the fan-out panel-level package, the semiconductor sub-packages are arranged adjacent to each other in at least one horizontal direction of the fan-out panel-level package.

12. The fan-out panel-level package according to claim 11 , further comprising: The second bridge electrically connects the first bridge of the first sub-package to the first bridge of the second sub-package.

13. The fan-out panel level package according to claim 12, wherein: The second bridge is on the first sub-package and the second sub-package.

14. The fan-out panel-level package according to claim 13 , further comprising: A molding material is between the first sub-package and the second sub-package and at least partially surrounds the second bridge.

15. The fan-out panel level package according to claim 11, wherein: The number of redistribution layers of at least one of the first sub-package and the second sub-package is four or more.

16. The fan-out panel level package according to claim 11, wherein: The number of redistribution layers of each of the first sub-package and the second sub-package is four or more.

17. The fan-out panel level package according to claim 11, wherein: The redistribution layer of at least one of the first sub-package and the second sub-package has a line width / space equal to or less than 2 μm.

18. A fan-out panel-level package, comprising: A semiconductor subpackage includes a first subpackage and a second subpackage, wherein: The first sub-package includes: a redistribution layer; a first molding layer on the redistribution layer; a first semiconductor chip on the first molding layer; and a second semiconductor chip, different from the first semiconductor chip, on the first molding layer. The first mold layer includes: a first bridge electrically connecting one of the first semiconductor chips to the semiconductor chip of the second sub-package, and In the fan-out panel-level package, the semiconductor sub-packages are arranged adjacent to each other in at least one horizontal direction of the fan-out panel-level package.

19. The fan-out panel-level package according to claim 18, further comprising: The second bridge electrically connects the first bridge of the first sub-package to the bridge of the second sub-package, and the bridge of the second sub-package is electrically connected to the semiconductor chip of the second sub-package.

20. The fan-out panel level package according to claim 19, wherein: The second bridge is on the first sub-package and the second sub-package.

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