Semiconductor device

Abstract

The invention provides a semiconductor device capable of improving heat dissipation performance. The semiconductor device includes: a buffer layer containing iron atoms, the upper surface of the buffer layer having nitrogen polarity; the barrier layer is arranged on the buffer layer, and the upper surface of the barrier layer has nitrogen polarity; and a channel layer over the barrier layer, the upper surface of the channel layer having nitrogen polarity.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) using a nitride semiconductor has been proposed.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2017 / 002317

[0006] In recent years, as the operating speed of semiconductor devices increases, the amount of heat generated increases, and there is a growing demand for improved heat dissipation. Summary of the Invention

[0007] An object of the present disclosure is to provide a semiconductor device capable of improving heat dissipation.

[0008] The semiconductor device disclosed herein comprises: a buffer layer containing iron, wherein the upper surface of the buffer layer has nitrogen polarity; a barrier layer on the buffer layer, wherein the upper surface of the barrier layer has nitrogen polarity; and a channel layer on the barrier layer, wherein the upper surface of the channel layer has nitrogen polarity.

[0009] Effects of the Invention

[0010] According to the present disclosure, heat dissipation can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0012] Figure 2 This is a cross-sectional view (Part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 3 This is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to an embodiment.

[0014] Figure 4 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 3).

[0015] Figure 5 This is a cross-sectional view (Part 4) showing a method for manufacturing a semiconductor device according to an embodiment.

[0016] Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 5).

[0017] Figure 7 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (No. 6).

[0018] Figure 8 It is a cross-sectional view showing a semiconductor device according to a modification of the embodiment.

[0019] Figure 9 This is a diagram showing the relationship between the polarity of the upper surface of the nitride semiconductor layer and the distribution of the concentration of Fe atoms.

[0020] Description of Reference Numerals

[0021] 1, 2: semiconductor device; 10: substrate; 20: nitride semiconductor layer; 21: buffer layer; 21A, 22A, 23A, 24A, 27A, 28A: upper surface; 21B, 22B, 23B, 24B, 27B, 28B: lower surface; 22: barrier layer; 23: channel layer; 24: cap layer; 26: channel region; 27: nucleation layer; 28: second buffer layer; 31: dielectric film; 31D, 31S: opening; 40D, 40S: recess; 41D, 41S: regrown layer; 42D: drain electrode; 42S: source electrode; 43: gate electrode; 50: passivation film; 50D, 50G, 50S: opening; 60: SiC substrate; 61, 62: GaN layer; 63: interface; L1: distance. DETAILED DESCRIPTION

[0022] [Description of Embodiments of the Present Disclosure]

[0023] First, embodiments of the present disclosure will be described below.

[0024] [1] A semiconductor device according to one embodiment of the present disclosure comprises: a buffer layer containing iron, wherein the upper surface of the buffer layer has nitrogen (N) polarity; a barrier layer above the buffer layer, wherein the upper surface of the barrier layer has nitrogen polarity; and a channel layer above the barrier layer, wherein the upper surface of the channel layer has nitrogen polarity.

[0025] Since the buffer layer contains iron as a dopant, the buffer layer can be made to have high resistance, making it easy to obtain high output power and high-frequency characteristics. In addition, the inventors of the present application have discovered that when the upper surface of the buffer layer, the upper surface of the barrier layer, and the upper surface of the channel layer have nitrogen polarity, the diffusion of iron atoms doped in the buffer layer from the buffer layer to the channel layer is less likely to occur than when these upper surfaces have gallium (Ga) polarity. The iron atoms in the channel layer degrade the electron mobility of the two-dimensional electron gas (2DEG) in the channel layer. Generally, iron is not doped in the buffer layer. Moreover, in this semiconductor device, since the upper surface of the buffer layer, the upper surface of the barrier layer, and the upper surface of the channel layer have nitrogen polarity, the diffusion of iron atoms from the buffer layer to the channel layer and the decrease in electron mobility caused by the iron atoms diffused into the channel layer are less likely to occur. This semiconductor device generates heat due to the movement of electrons in the channel layer. Therefore, by reducing the distance between the buffer layer and the channel layer, high electron mobility can be obtained, and the heat dissipation (heat conduction) from the channel layer to the substrate can be improved.

[0026] [2] In [1], the barrier layer may have a thickness of 1 nm to 50 nm. A thickness of 1 nm to 50 nm reduces the likelihood of electron mobility decreasing and iron atoms diffusing from the buffer layer to the channel layer, while also improving thermal conductivity.

[0027] [3] In [1], the distance (interval) between the upper surface of the buffer layer and the lower surface of the channel layer may be greater than 1 nm and less than 50 nm. When the distance (interval) between the upper surface of the buffer layer and the lower surface of the channel layer is greater than 1 nm and less than 50 nm, a decrease in electron mobility and diffusion of iron atoms into the channel layer are less likely to occur, and thermal conductivity in the vertical direction described later is easily improved.

[0028] [4] In any one of [1] to [3], the average concentration of iron atoms in the channel layer may be 2×10 16 cm -3 The average concentration of iron atoms in the channel layer is 2×10 16 cm -3 Thereafter, high electron mobility can be easily obtained in the channel region.

[0029] [5] In any one of [1] to [4], the average concentration of iron atoms in the buffer layer may be 5×10 17 cm -3 The average concentration of iron atoms in the buffer layer is 5×10 17 cm -3As described above, the buffer layer can be made to have a high resistance.

[0030] [6] In [1], the barrier layer may have a thickness of 1 nm to 50 nm, and the average concentration of iron atoms in the channel layer may be 2×10 16 cm -3 Hereinafter, the average concentration of iron atoms in the buffer layer is 5×10 17 cm -3 The thickness of the barrier layer is between 1 nm and 50 nm, which makes it difficult for electron mobility to decrease and for iron atoms to diffuse from the buffer layer to the channel layer, and at the same time, it is easy to improve the heat conduction from the channel layer to the substrate. The average concentration of iron atoms in the channel layer is 2×10 16 cm -3 The following makes it easy to obtain high electron mobility in the channel region. The average concentration of iron atoms in the buffer layer is 5×10 17 cm -3 As described above, the buffer layer can be made to have a high resistance.

[0031] [7] In any of [1] to [6], the buffer layer may be a gallium nitride layer, the barrier layer may be an aluminum gallium nitride layer, and the channel layer may be a gallium nitride layer. In this case, the buffer layer, barrier layer, and channel layer can be easily and stably formed.

[0032] [Details of the embodiments of the present disclosure]

[0033] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited thereto. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, duplicate descriptions may sometimes be omitted by marking them with the same reference numerals. In the present disclosure, "looking down" means observing an object from above in a direction perpendicular to the upper surface of the substrate (vertical direction).

[0034] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0035] like Figure 1 As shown, the semiconductor device 1 of the embodiment mainly includes a substrate 10 , a nitride semiconductor layer 20 , a dielectric film 31 , a passivation film 50 , a regrown layer 41S, a regrown layer 41D, a gate electrode 43 , a source electrode 42S, and a drain electrode 42D.

[0036] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is a carbon (C) polar surface. When the upper surface of the substrate 10 is a C polar surface, the nitride semiconductor layer 20 can undergo crystal growth with the nitrogen (N) polar surface as the growth plane.

[0037] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, a channel layer 23, and a cap layer 24. The nitride semiconductor layer 20 may include a nucleation layer between the substrate 10 and the buffer layer 21.

[0038] The buffer layer 21 is located on the substrate 10. The buffer layer 21 contains iron (Fe) atoms. Iron is doped into the buffer layer 21 as an impurity (dopant). The buffer layer 21 is, for example, a gallium nitride (GaN) layer containing iron (Fe). In other words, the buffer layer 21 is an iron-doped GaN layer. The thickness of the buffer layer 21 is, for example, greater than 10 nm and less than 1000 nm. For example, the buffer layer 21 has a resistivity of greater than 1 MΩ·m.

[0039] The barrier layer 22 is located on the buffer layer 21. The barrier layer 22 is, for example, an aluminum gallium nitride (AlGaN) layer. The band gap of the barrier layer 22 is larger than the band gap of the channel layer 23. The thickness of the barrier layer 22 is, for example, not less than 1 nm and not more than 50 nm. The composition of the barrier layer 22 is, for example, Al Y Ga 1－Y N (0.15≤Y≤0.55). The conductivity type of the barrier layer 22 is, for example, n-type or non-doped (i-type). Even if iron is not doped in the barrier layer 22, the barrier layer 22 may contain Fe atoms diffused from the buffer layer 21 doped with iron. A scandium aluminum nitride (ScAlN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer. Y Ga 1－Y In the case of N, the ratio of Al in the group III element in the barrier layer 22 is Y×100%.

[0040] The channel layer 23 is located on the barrier layer 22. The channel layer 23 is, for example, a GaN layer. The band gap of the channel layer 23 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 23 is, for example, greater than 1 nm and less than 50 nm. Between the channel layer 23 and the barrier layer 22, strain is generated due to the difference in their lattice constants, and the strain induces piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (2DEG) is generated near the surface of the channel layer 23 opposite to the barrier layer 22, forming a channel region 26. The conductivity type of the channel layer 23 is, for example, n-type or non-doped (i-type). Generally, iron is not doped in the channel layer 23. Even in this case, the channel layer 23 may contain iron atoms diffused from the buffer layer 21 through the barrier layer 22. At this time, the average concentration of Fe atoms in the channel layer 23 is lower than the average concentration of Fe atoms in the barrier layer 22 , and the average concentration of Fe atoms in the barrier layer 22 is lower than the average concentration of Fe atoms in the buffer layer 21 .

[0041] The cap layer 24 is located on the channel layer 23. The cap layer 24 is, for example, an AlGaN layer and has a thickness of, for example, 0.2 nm to 10 nm.

[0042] On the C-polarity surface of the SiC substrate, the buffer layer 21, barrier layer 22, channel layer 23, and cap layer 24 undergo crystal growth with the N-polarity surface as the growth plane. Therefore, the upper surfaces 21A, 22A, 23A, and 24A of the buffer layer 21, barrier layer 22, channel layer 23, and cap layer 24, respectively, have N-polarity. Furthermore, the lower surfaces 21B, 22B, 23B, and 24B of the buffer layer 21, barrier layer 22, channel layer 23, and cap layer 24, respectively, have gallium (Ga) polarity or aluminum (Al) polarity.

[0043] A source recess 40S and a drain recess 40D are formed in the nitride semiconductor layer 20. The bottoms of the recesses 40S and 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 23A of the channel layer 23. In other words, the recesses 40S and 40D are formed deeper than the upper surface 23A of the channel layer 23. The bottoms of the recesses 40S and 40D may be located in the channel layer 23 or in the barrier layer 22.

[0044] The dielectric film 31 is located on the nitride semiconductor layer 20. The dielectric film 31 is in contact with the upper surface 24A of the cap layer 24. For example, the relative dielectric constant of the dielectric film 31 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric film 31 may also be a high dielectric constant film. The dielectric film 31 is, for example, a silicon nitride (SiN) film. The dielectric film 31 may also be a dielectric oxide film or a dielectric oxynitride film. The dielectric oxide film or the dielectric oxynitride film may also include at least one selected from the group consisting of hafnium (Hf), lanthanum (La) and zirconium (Zr). In addition, the dielectric oxide film or the dielectric oxynitride film may also include at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric film 31 may also be hafnium silicate (HfSiO x ) film, hafnium aluminate (HfAlO x ) film, a hafnium silicon oxynitride (HfSiON) film, or a hafnium aluminum oxynitride (HfAlON) film. The thickness of dielectric film 31 is, for example, not less than 1 nm and not more than 30 nm. Dielectric film 31 has an opening 31S for the source and an opening 31D for the drain. Opening 31S is connected to recess 40S, and opening 31D is connected to recess 40D.

[0045] The regrown layer 41S is located above the channel layer 23 or the barrier layer 22 within the recess 40S. The regrown layer 41D is located above the channel layer 23 or the barrier layer 22 within the recess 40D. The regrown layers 41S and 41D are, for example, n-type GaN layers. The regrown layers 41S and 41D contain germanium (Ge) or Si as n-type impurities. The resistance of the regrown layers 41S and 41D is lower than that of the channel layer 23. For example, the regrown layers 41S and 41D are formed by regrowth of the n-type GaN layer after the recesses 40S and 40D are formed in the nitride semiconductor layer 20.

[0046] The source electrode 42S is located on the regrown layer 41S, and the drain electrode 42D is located on the regrown layer 41D. The source electrode 42S is in contact with the regrown layer 41S, and the drain electrode 42D is in contact with the regrown layer 41D. The source electrode 42S is in ohmic contact with the regrown layer 41S, and the drain electrode 42D is in ohmic contact with the regrown layer 41D.

[0047] The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 is, for example, a SiN film. The thickness of the passivation film 50 is, for example, 5 nm to 50 nm in the uniform thickness portion on the dielectric film 31. The passivation film 50 includes an opening 50S for the source electrode, an opening 50D for the drain electrode, and an opening 50G for the gate electrode. The opening 50S reaches the source electrode 42S, and the opening 50D reaches the drain electrode 42D. When viewed from above, the opening 50G is located between the openings 50S and 50D. The opening 50G reaches the dielectric film 31.

[0048] In a plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is located on the passivation film 50 and the dielectric film 31 and is in contact with the dielectric film 31 through the opening 50G.

[0049] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 7 It is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0050] First, if Figure 2 As shown, a nitride semiconductor layer 20 is formed on a substrate 10 by, for example, metal organic chemical vapor deposition (MOCVD). During the formation of the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a channel layer 23, and a cap layer 24 are sequentially formed. During this formation process, iron is doped into the buffer layer 21, but not into the barrier layer 22 or the channel layer 23.

[0051] When forming the buffer layer 21, the temperature in the chamber is set to 1000° C. to 1100° C., the pressure in the chamber is set to 10 kPa to 15 kPa, and the V / III ratio is set to 1000 to 1100. The V / III ratio is the ratio of the amount (moles) of the group V element supplied per unit time to the amount (moles) of the group III element supplied per unit time.

[0052] Then, if Figure 3 As shown, a dielectric film 31 is formed on the nitride semiconductor layer 20 .

[0053] Then, if Figure 4As shown, an opening 31S for the source and an opening 31D for the drain are formed in the dielectric film 31, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottoms of the recesses 40S and 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 23A of the channel layer 23. In other words, the recesses 40S and 40D may be formed deeper than the upper surface 23A of the channel layer 23. The bottoms of the recesses 40S and 40D may be located in the channel layer 23 or in the barrier layer 22. The opening 31S, the opening 31D, the recess 40S, and the recess 40D can be formed, for example, by reactive ion etching (RIE) using a mask (not shown).

[0054] Then, if Figure 5 As shown, a regrown layer 41S is formed on the channel layer 23 or the barrier layer 22 in the recess 40S, and a regrown layer 41D is formed on the channel layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D can be formed by, for example, physical vapor deposition (PVD) such as evaporation, sputtering, or molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD).

[0055] Then, if Figure 6 As shown, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. To form the source electrode 42S and the drain electrode 42D, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is first formed. When forming the metal layer, for example, film formation is performed using a growth mask (not shown). The growth mask, which has openings in the regions where the metal layer is to be formed, is then removed along with the metal layer (not shown) formed on the growth mask. In other words, lift-off is performed.

[0056] Then, if Figure 7 As shown, a passivation film 50 is formed on the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The passivation film 50 covers the dielectric film 31, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D.

[0057] Next, an opening 50G for a gate is formed in the passivation film 50 (see Figure 1 The opening 50G can be formed by, for example, RIE using a mask (not shown).

[0058] Next, the gate electrode 43 is formed on the passivation film 50 and the dielectric film 31 through the opening 50G (see FIG. Figure 1 When forming gate electrode 43, for example, a metal layer is formed using a growth mask (not shown), and then the growth mask having an opening in the region where gate electrode 43 is to be formed is removed together with the metal layer (not shown) formed on the growth mask. In other words, lift-off is performed.

[0059] Next, an opening 50S for the source and an opening 50D for the drain are formed in the passivation film 50 (see Figure 1 The opening 50S and the opening 50D can be formed by, for example, RIE using a mask (not shown).

[0060] In this manner, the semiconductor device 1 can be manufactured.

[0061] In the semiconductor device 1 of the embodiment, since the buffer layer 21 contains Fe as an impurity (dopant), the buffer layer 21 can be made to have a high resistance, making it easy to obtain high output and high-frequency characteristics. In addition, since the upper surface 21A of the buffer layer 21, the upper surface 22A of the barrier layer 22, and the upper surface 23A of the channel layer 23 have N polarity, compared with the case where these upper surfaces have Ga polarity, it is less likely for Fe atoms to diffuse from the buffer layer 21 to the channel layer 23 and for the electron mobility to decrease due to the Fe atoms diffused into the channel layer 23. Therefore, by reducing the distance L1 between the upper surface 21A of the buffer layer 21 and the lower surface 23B of the channel layer 23, a high electron mobility can be obtained in the channel region 26, and at the same time, the heat dissipation (heat conduction) from the channel layer 23 to the substrate 10 can be improved.

[0062] Furthermore, since upper surface 22A of barrier layer 22 and upper surface 23A of channel layer 23 have N polarity, the distance between channel region 26 and source electrode 42S and drain electrode 42D can be easily shortened, thereby easily achieving low resistance.

[0063] The thickness of the barrier layer 22 is, for example, not less than 1 nm and not more than 50 nm. If the thickness of the barrier layer 22 is less than 1 nm, the density of the 2DEG may be low, thereby reducing the mobility of electrons, or the number of Fe atoms diffusing from the buffer layer 21 to the channel layer 23 may increase. If the thickness of the barrier layer 22 is greater than 50 nm, the heat conduction from the channel layer 23 to the substrate 10 may be reduced. The thickness of the barrier layer 22 may also be not less than 5 nm and not more than 40 nm, or may be not less than 10 nm and not more than 30 nm. In this embodiment, the thickness of the barrier layer 22 is equal to the distance L1.

[0064] The average concentration of Fe atoms in the channel layer 23 is, for example, 2×10 16 cm-3 The average concentration of Fe atoms in the channel layer 23 is 2×10 16 cm -3 Then, high electron mobility is obtained in the channel region 26. The average value of the concentration of Fe atoms in the channel layer 23 may be, for example, 1.5×10 16 cm -3 Below, it can also be 1×10 16 cm -3 The characteristics will not be degraded even if the concentration of Fe atoms in the channel layer 23 is too low.

[0065] The average concentration of Fe atoms in the buffer layer 21 is, for example, 5×10 17 cm -3 The average concentration of Fe atoms in the buffer layer 21 is 5×10 17 cm -3 The above can make the buffer layer 21 have a high resistance. The average value of the concentration of Fe atoms in the buffer layer 21 can also be 7×10 17 cm -3 Above, it can also be 1×10 18 cm -3 The average concentration of Fe atoms in the buffer layer 21 is, for example, 1×10 20 cm -3 When the average concentration of Fe atoms in the buffer layer 21 is greater than 1×10 20 cm -3 If the concentration of Fe atoms is higher than 1×10 20 cm -3 If the buffer layer 21 is thick, Fe may precipitate, causing abnormal growth of the barrier layer 22 and the channel layer 23 on the buffer layer 21. For example, the buffer layer 21 has a resistivity of 1 MΩ·m or more.

[0066] The concentration of Fe atoms in the buffer layer 21 and the concentration of Fe atoms in the channel layer 23 can be measured by secondary ion mass spectrometry (SIMS).

[0067] Furthermore, when the buffer layer 21 is a GaN layer, the barrier layer 22 is an AlGaN layer, and the channel layer 23 is a GaN layer, the buffer layer 21 , the barrier layer 22 , and the channel layer 23 can be easily and stably formed.

[0068] Next, a modification of the embodiment will be described. The modification differs from the first embodiment mainly in the configuration of the nitride semiconductor layer 20 . Figure 8 It is a cross-sectional view showing a semiconductor device according to a modification of the embodiment.

[0069] like Figure 8 As shown, in the semiconductor device 2 according to the modified example of the embodiment, the nitride semiconductor layer 20 includes a nucleation layer 27 and a second buffer layer 28 in addition to the buffer layer 21 , the barrier layer 22 , the channel layer 23 , and the cap layer 24 .

[0070] Nucleation layer 27 is located between substrate 10 and buffer layer 21 . Nucleation layer 27 is, for example, an AlN layer. Upper surface 27A of nucleation layer 27 has N polarity, and lower surface 27B has Al polarity. Nucleation layer 27 functions as a nucleus for the growth of nitride semiconductor layer 20 .

[0071] The second buffer layer 28 is located between the buffer layer 21 and the barrier layer 22. The second buffer layer 28 is, for example, a GaN layer, and the conductivity type of the second buffer layer 28 is non-doped (i-type). The upper surface 28A of the second buffer layer 28 has N polarity, and the lower surface 28B has Ga polarity. The second buffer layer 28 makes it difficult for Fe atoms to diffuse from the buffer layer 21 to the channel layer 23. Therefore, the average value of the concentration of Fe atoms in the channel layer 23 of the modified example is smaller than the average value of the concentration of Fe atoms in the channel layer 23 of the embodiment. In addition, in the modified example, the average value of the concentration of Fe atoms in the channel layer 23 is smaller than the average value of the concentration of Fe atoms in the barrier layer 22, the average value of the concentration of Fe atoms in the barrier layer 22 is smaller than the average value of the concentration of Fe atoms in the second buffer layer 28, and the average value of the concentration of Fe atoms in the second buffer layer 28 is smaller than the average value of the concentration of Fe atoms in the buffer layer 21.

[0072] The other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1. The semiconductor device 2 also provides the same effects as those of the semiconductor device 1.

[0073] It should be noted that the distance L1 is, for example, greater than 1 nm and less than 50 nm. If the distance L1 is less than 1 nm, the barrier layer 22 may become thinner, resulting in a lower 2DEG density, a decrease in electron mobility, or increased diffusion of Fe atoms from the buffer layer 21 to the channel layer 23. If the distance L1 is greater than 50 nm, heat dissipation from the channel layer 23 to the substrate 10 may be reduced. The distance L1 may also be greater than 5 nm and less than 40 nm, or further may be greater than 10 nm and less than 30 nm.

[0074] Here, an experiment conducted by the inventors of this application is described. In this experiment, SiC substrates 60 with a top surface polarity of C polarity or Si polarity were prepared. A GaN layer 61 containing Fe was formed on each SiC substrate 60, and a GaN layer 62 not intentionally doped with Fe atoms was formed on the GaN layer 61. In the formation of the GaN layer 61, the average concentration of Fe atoms was 1×10 18 cm -3 The Fe atoms were doped in a manner such that the thickness of the GaN layer 61 was set to 500 nm. In addition, the thickness of the GaN layer 62 was set to 1200 nm. Then, the concentration of Fe atoms was measured for each sample by SIMS. The results are shown in Figure 9 It should be noted that in sample No. 1 using a SiC substrate 60 having an upper surface polarity of Si polarity, the polarity of each upper surface of the GaN layer 61 and the GaN layer 62 is Ga polarity, and in sample No. 2 using a SiC substrate 60 having an upper surface polarity of C polarity, the polarity of each upper surface of the GaN layer 61 and the GaN layer 62 is N polarity.

[0075] like Figure 9 As shown in FIG. 1 , the concentration of Fe atoms in the GaN layer 62 decreases as the distance from the interface 63 between the GaN layer 61 and the GaN layer 62 increases. However, in sample No. 1, the concentration of Fe atoms in the GaN layer 62 decreases to 1×10 16 cm -3 This means that when the GaN layer 61 is used as a buffer layer and the GaN layer 62 is used as a channel layer with the same polarity as in Sample No. 1, in order to make the concentration of Fe atoms in the channel region 1×10 16 cm -3 The channel region and the buffer layer containing Fe need to be separated by 800 nm or more. On the other hand, in sample No. 2, the concentration of Fe atoms in the GaN layer 62 is reduced to 1×10 16 cm -3 This means that when the GaN layer 61 is used as a buffer layer and the GaN layer 62 is used as a channel layer with the same polarity as in Sample No. 2, if the channel region and the buffer layer containing Fe are separated by about 50 nm, the concentration of Fe atoms in the channel region can be made 1×10 16 cm -3 Therefore, according to Sample No. 2, the distance between the buffer layer containing Fe and the channel region can be significantly shortened compared to Sample No. 1, and the thermal resistance can be significantly reduced.

[0076] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

Claims

1. A semiconductor device comprising: a buffer layer containing iron atoms, wherein an upper surface of the buffer layer has nitrogen polarity; a barrier layer on the buffer layer, wherein an upper surface of the barrier layer has nitrogen polarity; and A channel layer is located above the barrier layer, and an upper surface of the channel layer has nitrogen polarity.

2. The semiconductor device according to claim 1, wherein The barrier layer has a thickness of 1 nm to 50 nm.

3. The semiconductor device according to claim 1, wherein A distance between an upper surface of the buffer layer and a lower surface of the channel layer is greater than or equal to 1 nm and less than or equal to 50 nm.

4. The semiconductor device according to any one of claims 1 to 3, wherein The average concentration of iron atoms in the channel layer is 2×10 16 cm -3 the following.

5. The semiconductor device according to any one of claims 1 to 3, wherein The average concentration of the iron atoms in the buffer layer is 5×10 17 cm -3 above. The semiconductor device according to claim 1 , wherein: The thickness of the barrier layer is greater than or equal to 1 nm and less than or equal to 50 nm. The average concentration of iron atoms in the channel layer is 2×10 16 cm -3 the following, The average concentration of iron atoms in the buffer layer is 5×10 17 cm -3 above.

7. The semiconductor device according to any one of claims 1 to 3 and claim 6, wherein The buffer layer is a gallium nitride layer, The barrier layer is an aluminum gallium nitride layer, The channel layer is a gallium nitride layer.

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