Semiconductor element and manufacturing method thereof

Abstract

A semiconductor device includes an epitaxial layer, a gate structure, a well and a source. The epitaxial layer has a first conductivity type. The gate structure and the well are located in the epitaxial layer. The well has a second conductivity type different from the first conductivity type. The well extends from a sidewall of the gate structure to a bottom surface of the gate structure. The source electrode is arranged above the epitaxial layer and is electrically connected to the well. The breakdown voltage of the semiconductor element is improved, and the on-resistance is reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof. Background Art

[0002] Metal oxide semiconductor field effect transistors (MOSFETs) are widely used in electronic devices due to their advantages such as fast switching speed, good high-frequency characteristics, high input impedance and low driving power.

[0003] Generally speaking, the on-state resistance of a MOSFET in its on-state is a key parameter affecting its power consumption. MOSFETs with a trench gate structure can help reduce on-state resistance, shrink device size, and increase chip density, thereby reducing costs.

[0004] However, the gate structure of the trench gate MOSFET has a large electric field concentration effect, which reduces the breakdown voltage of the device and thus causes reliability issues.

[0005] Therefore, how to propose a semiconductor device and a manufacturing method thereof that can solve the above problems is one of the issues that the industry is eager to invest research and development resources to solve. Summary of the Invention

[0006] In view of this, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.

[0007] To achieve the above objectives, according to some embodiments of the present invention, a semiconductor device includes an epitaxial layer, a gate structure, a well, and a source. The epitaxial layer has a first conductivity type. The gate structure and the well are located in the epitaxial layer. The well has a second conductivity type different from the first conductivity type. The well extends from a sidewall of the gate structure to a bottom surface of the gate structure. The source is located above the epitaxial layer and electrically connected to the well.

[0008] According to other embodiments of the present invention, a method for manufacturing a semiconductor element includes forming an epitaxial layer on a substrate. The epitaxial layer has a first conductivity type. The method also includes performing a first implantation process to form a first portion of a well in the epitaxial layer. The well has a second conductivity type different from the first conductivity type. The method also includes performing a second implantation process to form a second portion of the well having the second conductivity type in the epitaxial layer and adjacent to the first portion. The method also includes performing a third implantation process to form a heavily doped region having the second conductivity type in the epitaxial layer and adjacent to the well. The method also includes removing a portion of the epitaxial layer to form a groove. The groove exposes a top surface of the second portion of the well. The method also includes forming a gate structure in the groove.

[0009] In summary, in the semiconductor device and its manufacturing method of the present invention, by increasing the doping depth of the well so that the well covers the edge of the gate structure, electric field concentration at the edge can be reduced. Furthermore, through two ion implantation processes, a first portion and a second portion of the well are formed, wherein the first portion surrounds the sidewall of the gate structure, and the second portion extends to the bottom surface of the gate structure. The intersection of the gate structure sidewall and bottom surface is covered by the well, thereby improving the breakdown voltage of the semiconductor device and reducing the on-resistance.

[0010] These and other aspects of the invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, but variations and modifications may be made therein without departing from the spirit and scope of the novel concepts of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings illustrate one or more embodiments of the present invention and, together with the written description, serve to explain the principles of the present invention. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein:

[0012] Figure 1 FIG2 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0013] Figures 2 to 5 FIG2 is a partial cross-sectional view illustrating an intermediate stage of a method for forming a semiconductor device according to some embodiments of the present invention.

[0014] Figure 6 and Figure 7 are partial cross-sectional views of semiconductor devices according to other embodiments of the present invention. DETAILED DESCRIPTION

[0015] The following drawings illustrate embodiments of the present invention. For clarity, many practical details are included in the following description. However, it should be understood that these practical details are not intended to limit the present invention. In other words, in some embodiments of the present invention, these practical details are not essential. Furthermore, to simplify the drawings, some conventional structures and components are depicted in simplified schematic form.

[0016] Please refer to Figure 1 , which is a partial cross-sectional view of a semiconductor device 10 according to some embodiments of the present invention. Figure 1 As shown in FIG, the semiconductor device 10 includes a substrate 100, an epitaxial layer 110, a current spreading layer 120, a well 130, a source doped region 140, a heavily doped region 150, a gate structure 160, a source 170, and a drain 180.

[0017] like Figure 1 As shown in FIG, an epitaxial layer 110 is located on a substrate 100. A current diffusion layer 120 is located in the epitaxial layer 110. A well 130 has a first portion 132 and a second portion 134, both located in the epitaxial layer 110 and above the current diffusion layer 120. A source doped region 140 and a heavily doped region 150 are located in the epitaxial layer 110 and above the well 130. A gate structure 160 includes a gate oxide layer 162 and a gate electrode 164, both located in the epitaxial layer 110 and above the well 130. The source doped region 140 is also located between the gate structure 160 and the heavily doped region 150.

[0018] In some embodiments, the source 170 is formed on the top surface 110a of the epitaxial layer 110 and is located above the heavily doped region 150. In other words, the heavily doped region 150 is located between the well 130 and the source 170. The source 170 is electrically connected to the well 130. The drain 180 is formed under the substrate 100. The source 170 and the drain 180 include a conductive metal.

[0019] In some embodiments, the substrate 100, the epitaxial layer 110, the current diffusion layer 120, and the source doping region 140 have a first conductivity type. For example, the substrate 100, the epitaxial layer 110, the current diffusion layer 120, and the source doping region 140 are n-type semiconductor layers. In some embodiments, the doping concentration of the source doping region 140 is greater than the doping concentration of the epitaxial layer 110. For example, the doping concentration of the substrate 100 is 10 14 # / cm 3 with 10 17 # / cm 3The doping concentration of the epitaxial layer 110 is between 10 17 # / cm 3 with 10 20 # / cm 3 The doping concentration of the source doping region 140 is between 10 18 # / cm 3 with 10 21 # / cm 3 The epitaxial layer 110 may be formed as a drift region of the semiconductor device 10 .

[0020] In some embodiments, the well 130 and the heavily doped region 150 have a second conductivity type different from the first conductivity type. For example, the well 130 and the heavily doped region 150 are p-type semiconductor layers. In some embodiments, the doping concentration of the heavily doped region 150 is greater than the doping concentration of the well 130. The well 130 is also called a lightly doped region. For example, the doping concentration of the well 130 is between 10 and 10. 17 # / cm 3 with 10 20 # / cm 3 The doping concentration of the heavily doped region 150 is between 10 18 # / cm 3 with 10 21 # / cm 3 between.

[0021] As previously described, the gate structure 160 includes a gate oxide layer 162 and a gate electrode 164. In some embodiments, the gate oxide layer 162 may include, for example, silicon dioxide, and the gate electrode 164 may include a polysilicon gate or a conductive metal.

[0022] To improve the reliability of semiconductor devices, in some embodiments of the present invention, the doping depth of the well 130 is increased to prevent electric field concentration at the edge of the gate structure 160 , thereby increasing the breakdown voltage and reducing the on-resistance.

[0023] Therefore, if Figure 1 As shown in FIG, the well 130 extends from the sidewall 160b of the gate structure 160 to the bottom surface 160a of the gate structure 160. In other words, in some embodiments, the boundary 160c between the sidewall 160b and the bottom surface 160a of the gate structure 160 is completely covered by the well 130.

[0024] Specifically, if Figure 1As shown in FIG, a first portion 132 of the well 130 surrounds and contacts the sidewall 160 b of the gate structure 160. A second portion 134 is located below the gate structure 160, and a top surface of the second portion 134 contacts the bottom surface 160 a of the gate structure 160. In some embodiments, the doping concentration of the first portion 132 is substantially equal to the doping concentration of the second portion 134.

[0025] In some embodiments, the vertical depth D1 of the bottom surface 134b of the second portion 134 relative to the top surface 110a of the epitaxial layer 110 is greater than 1 micron to ensure that the well 130 completely covers the junction 160c. In addition, in some embodiments, the top surface of the second portion 134 (its position is equivalent to Figure 1 The vertical depth D2 of the bottom surface 160 a of the gate structure 160 in the first portion 132 is greater than the vertical depth D2 of the top surface 132 a of the first portion 132.

[0026] In some embodiments, as Figure 1 As shown in FIG, the second portion 134 has an opening OP. The epitaxial layer 110 may contact the bottom surface 160 a of the gate structure 160 through the opening OP.

[0027] Please refer to Figures 2 to 5 , which is a partial cross-sectional view of an intermediate stage of a manufacturing method for forming a semiconductor device 10 according to some embodiments of the present invention. It is noteworthy that the partial cross-sectional view of the intermediate stage of the manufacturing method depicts a plurality of semiconductor devices 10 that are periodically arranged and connected.

[0028] First, if Figure 2 As shown in FIG, an epitaxial layer 110 is formed on a substrate 100. Next, a first ion implantation process is performed to form a current diffusion layer 120 in the epitaxial layer 110. The current diffusion layer 120 is configured to reduce the on-resistance of the semiconductor device 10. In some embodiments, the substrate 100, the epitaxial layer 110, and the current diffusion layer 120 have a first conductivity type. For example, the substrate 100, the epitaxial layer 110, and the current diffusion layer 120 are n-type semiconductor layers. In some embodiments, the doping concentration of the substrate 100 is between 10 and 10. 14 # / cm 3 with 10 17 # / cm 3 The doping concentration of the epitaxial layer 110 is between 10 17 # / cm 3 with 10 20 # / cm 3 The doping concentration of the current diffusion layer 120 is between 10 16 # / cm 3 with 10 19 # / cm3 between.

[0029] Then, if Figure 2 As shown in FIG, a second ion implantation process is performed using mask 210, mask 212, and mask 214 as ion implantation masks to form a first portion 132 of a well in epitaxial layer 110. The well has a second conductivity type different from the first conductivity type. For example, the well is a p-type semiconductor layer. In some embodiments, mask 210, mask 212, and mask 214 comprise the same material. In other embodiments, mask 210 and mask 214 comprise the same material, such as silicon oxide (SiO2), while mask 212 comprises a different material from mask 210 and mask 214, such as polysilicon.

[0030] Next, please refer to Figure 3 A third ion implantation process is performed through masks 216, 218, and 220 to form a second well portion 134 in the epitaxial layer 110. The second portion 134 is adjacent to the first portion 132. The doping concentration of the first portion 132 is substantially equal to the doping concentration of the second portion 134. The first portion 132 and the second portion 134 are collectively referred to as the well 130. As previously described, in some embodiments, a distance greater than 1 micron is provided between the bottom surface 134b of the second portion 134 and the top surface 110a of the epitaxial layer 110. In other words, a vertical depth D1 of the bottom surface 134b is greater than 1 micron.

[0031] Please refer to Figure 4 .like Figure 4 As shown in , after the third ion implantation process, a fourth ion implantation process is performed to form a source doped region 140 having a first conductivity type, such as an n-type semiconductor layer, in the epitaxial layer 110 and adjacent to the first portion 132 of the well 130. In some embodiments, the source doped region 140 is formed such that the first portion 132 of the well 130 forms a top surface 132a. In some embodiments, a vertical depth D2 of the top surface 132a of the first portion 132 is less than a vertical depth D1 of the bottom surface 134b of the second portion 134.

[0032] Next, a fifth ion implantation process is performed to form a heavily doped region 150 in the epitaxial layer 110 and located on the well 130. The heavily doped region 150 has a second conductivity type, such as a p-type semiconductor layer. In some embodiments, the doping concentration of the heavily doped region 150 is greater than the doping concentration of the well 130. For example, the doping concentration of the well 130 is 10 17 # / cm 3 with 10 20 # / cm 3 The doping concentration of the heavily doped region 150 is between 1018 # / cm 3 with 10 21 # / cm 3 In some embodiments, the bottom depth of the heavily doped region 150 is between the vertical depth D1 and the vertical depth D2.

[0033] Next, a portion of the epitaxial layer 110 is removed to form a plurality of grooves T1 to expose the top surface 134a of the second portion 134 of the well 130. For example, Figure 4 As shown in FIG, a recess T1 is formed by etching through the hard mask 240. In some embodiments, the recess T1 further exposes the sidewall 132b of the first portion 132 of the well 130. In some embodiments, the hard mask 240 includes silicon dioxide.

[0034] Please refer to Figure 5 Next, a gate structure is formed in the recess T1. As previously mentioned, in some embodiments, the gate structure includes a gate oxide layer and a gate electrode. In some embodiments, the gate oxide layer is formed in two stages.

[0035] For example, in some embodiments, the first gate oxide layer 162 - 1 is conformally deposited in the recess T1 and on the top surfaces of the source doped region 140 and the heavily doped region 150 .

[0036] Next, a gate electrode 164 is deposited to further fill the groove T1 and completely cover the first gate oxide layer 162 - 1 .

[0037] Next, the formed gate electrode 164 is planarized, for example, by chemical mechanical polishing / planarization (CMP), to remove the first gate oxide layer 162-1 and the portion of the gate electrode 164 that is higher than the source doped region 140, thereby exposing the top surfaces of the source doped region 140 and the heavily doped region 150, and making the first gate oxide layer 162-1 and the gate electrode 164 flush with the top surface of the source doped region 140.

[0038] Next, a second gate oxide layer 162-2 is deposited to cover the source doped region 140, the heavily doped region 150, the first gate oxide layer 162-1, and the gate electrode 164, such that the gate electrode 164 is encapsulated by the first gate oxide layer 162-1 and the second gate oxide layer 162-2. The first gate oxide layer 162-1 and the second gate oxide layer 162-2 are collectively referred to as the gate oxide layer 162. The gate oxide layer 162 and the gate electrode 164 are collectively referred to as the gate structure 160.

[0039] Since the groove T1 (such as Figure 4As shown in FIG1 , the top surface 134a of the second portion 134 of the well 130 and the sidewall 132b of the first portion 132 are exposed, so that the gate structure 160 formed in the recess T1 contacts the top surface 134a and the sidewall 132b. In other words, the junction 160c between the bottom surface 160a and the sidewall 160b of the gate structure 160 is completely covered by the well 130. In this way, the electric field accumulation near the junction 160c can be prevented, thereby increasing the breakdown voltage of the semiconductor device. In some embodiments, as shown in FIG1 , the top surface 134a of the second portion 134 of the well 130 and the sidewall 132b of the first portion 132 are exposed, so that the gate structure 160 formed in the recess T1 contacts the top surface 134a and the sidewall 132b. In other words, the junction 160c between the bottom surface 160a and the sidewall 160b of the gate structure 160 is completely covered by the well 130. In this way, the electric field accumulation near the junction 160c can be prevented, thereby increasing the breakdown voltage of the semiconductor device. Figure 5 As shown in FIG, the second portion 134 has an opening OP. The epitaxial layer 110 contacts the gate structure 160 through the opening OP.

[0040] Next, portions of the second gate oxide layer 162 - 2 are removed to expose top surfaces of the source doped region 140 and the heavily doped region 150 , and to separate the gate structures 160 from each other.

[0041] Finally, a source electrode 170 is formed on the source doped region 140 and the heavily doped region 150. The source electrode 170 is electrically connected to the well 130. At the same time, a drain electrode 180 is formed under the substrate 100, as shown in FIG. Figure 5 The semiconductor device structure formed is shown in Figure 1 The semiconductor device 10 shown in FIG. 1 is a vertical MOSFET having a trench gate structure.

[0042] Please refer to Figure 6 and Figure 7 , which are partial cross-sectional views of the semiconductor element 20 and the semiconductor element 30 according to other embodiments of the present invention. Figure 6 As shown in FIG, the difference between the semiconductor device 20 and the semiconductor device 10 is that the depth of the bottom surface 134b of the second portion 134 of the semiconductor device 20 is less than the depth of the bottom surface 132c of the first portion 132. Figure 7 As shown in FIG, the difference between the semiconductor device 30 and the semiconductor device 10 is that the depth of the bottom surface 134 b of the second portion 134 of the semiconductor device 30 is greater than the depth of the bottom surface 132 c of the first portion 132 .

[0043] From the above detailed description of the specific embodiments of the present invention, it is apparent that in the semiconductor device and its manufacturing method of the present invention, by increasing the doping depth of the well so that the well covers the edge of the gate structure, electric field concentration at the edge can be reduced. Furthermore, through two ion implantation processes, a first portion and a second portion of the well are formed, wherein the first portion surrounds the sidewall of the gate structure and the second portion extends to the bottom surface of the gate structure. The intersection of the gate structure sidewall and bottom surface is covered by the well, thereby improving the breakdown voltage of the semiconductor device and reducing the on-resistance.

[0044] The foregoing description is intended to illustrate and describe exemplary embodiments of the present invention only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. The above teachings may be modified or varied.

[0045] The embodiments are chosen and described to illustrate the present invention and its practical application, thereby inspiring others skilled in the art to utilize the present invention and its various embodiments and to make various modifications as may be appropriate for the specific use contemplated. Alternative embodiments will be readily apparent to those skilled in the art without departing from the spirit and scope of the present invention. The scope of the present invention is therefore to be determined by the appended claims and not by the foregoing description and the exemplary embodiments described therein.

[0046]

Explanation of symbols

[0047] 10, 20, 30: semiconductor components

[0048] 100:Substrate

[0049] 110: epitaxial layer

[0050] 110a, 132a, 134a: top surface

[0051] 120: Current diffusion layer

[0052] 130: Trap

[0053] 132: First Part

[0054] 132b, 160b: sidewall

[0055] 132c,134b: Bottom surface

[0056] 134: Second part

[0057] 140: Source doping region

[0058] 150:Heavily doped area

[0059] 160: Gate structure

[0060] 160a: bottom

[0061] 160c: Junction

[0062] 162: Gate oxide layer

[0063] 162-1: First gate oxide layer

[0064] 162-2: Second gate oxide layer

[0065] 164: Gate electrode

[0066] 170: Source

[0067] 180: Drain

[0068] 210,212,214,216,218,220: Mask

[0069] 240:Hard Mask

[0070] D1, D2: vertical depth

[0071] OP: Opening

[0072] T1: Groove.

Claims

1. A semiconductor element, characterized in that: Include: an epitaxial layer having a first conductivity type; a gate structure located in the epitaxial layer; a well located in the epitaxial layer, the well having a second conductivity type different from the first conductivity type, wherein the well extends from a sidewall of the gate structure to a bottom surface of the gate structure; as well as The source is located above the epitaxial layer and electrically connected to the well.

2. The semiconductor device according to claim 1, wherein The junction between the sidewall and the bottom surface of the gate structure is completely covered by the well.

3. The semiconductor device according to claim 1, wherein The vertical depth of the bottom surface of the well is greater than 1 micron.

4. The semiconductor device according to claim 1, wherein The well has a first portion and a second portion, wherein the first portion surrounds and contacts the sidewall of the gate structure, and the second portion is located below the gate structure and contacts the bottom surface.

5. The semiconductor device according to claim 4, wherein The second portion has an opening and allows the epitaxial layer to contact the bottom surface of the gate structure through the opening.

6. A method for manufacturing a semiconductor device, characterized in that: Include: forming an epitaxial layer on a substrate, wherein the epitaxial layer has a first conductivity type; performing a first implantation process to form a first portion of a well having a second conductivity type different from the first conductivity type in the epitaxial layer; performing a second implantation process to form a second portion of the well having the second conductivity type in the epitaxial layer and adjacent to the first portion; performing a third implantation process to form a heavily doped region of the second conductivity type in the epitaxial layer and adjacent to the well; removing a portion of the epitaxial layer to form a groove exposing a top surface of the second portion of the well; as well as A gate structure is formed in the groove.

7. The method according to claim 6, wherein The groove further exposes a sidewall of the first portion of the well.

8. The method according to claim 6, wherein A distance between a bottom surface of the second portion and a top surface of the epitaxial layer is greater than 1 micron.

9. The method according to claim 6, wherein The gate structure is formed in the groove so that the gate structure contacts the top surface of the second portion of the well.

10. The method according to claim 6, wherein The gate structure is formed in the groove so that the junction between the sidewall and the bottom surface of the gate structure is completely covered by the well.

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