Laminated packaging structure and packaging method
By using BCB material or dry film as the adhesion layer in FOPOP packaging, combined with the conductive structure and plastic sealing layer, the process complexity and warping problems caused by the bump manufacturing of chips in the existing technology are solved, achieving the effect of simplifying the process and improving packaging reliability.
Patent Information
- Application Number
- CN202510860981.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-25
- Publication Date
- 2025-09-16
AI Technical Summary
In the existing FOPOP packaging technology, the die in the lower package needs to be bumped, which makes the process complicated and may cause chip warping.
BCB material or dry film is used as the adhesive layer, the chip is fixed by flip-chip method, and a conductive structure is formed on the PI layer to connect with the redistribution layer, avoiding the manufacture of bumps. The plastic encapsulation layer is used to protect the chip, reduce impedance and prevent warping.
The packaging process is simplified, the bump manufacturing step is avoided, the process complexity is reduced, and the chip warping is prevented by the use of an adhesion layer, thereby improving the reliability and efficiency of the packaging.
Smart Images
Figure CN120659370A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip packaging, in particular to a stacked packaging structure and a packaging method. Background Art
[0002] In the existing FOPOP packaging technology, the lower package uses a Tall Pillar conductive structure as a through layer, such as Figure 4 As shown, whether it is a Chip First or Chip Last solution, the Die in the lower package needs to be bumped, with only a slight difference in the height of the bump component. Summary of the Invention
[0003] In order to overcome the deficiencies of the prior art, the present invention provides a stacked packaging structure and a packaging method.
[0004] To achieve the above-mentioned purpose, a stacked packaging structure is designed, including a second redistribution layer and a chip. A PI layer is provided on one surface of the second redistribution layer, a chip is provided on one surface of the PI layer, a plurality of opening areas are provided on the surface of the PI layer, the chip I / O port corresponds to some of the opening areas and is electrically connected to the second redistribution layer, a conductive structure is provided in some of the opening areas, a first redistribution layer is provided at the other end of the conductive structure, and a first UBM layer is provided on one surface of the first redistribution layer.
[0005] The other side surface of the second redistribution layer is connected to the solder balls through the second UBM layer.
[0006] A plastic sealing layer is provided between the PI layer and the first redistribution layer, and the plastic sealing layer wraps the conductive structure and the chip.
[0007] The chip is connected to the PI layer via an adhesive layer.
[0008] To achieve the above object, a packaging method of a stacked packaging structure is designed, comprising the following steps: S1, providing a first carrier board, and forming a release layer on one side surface of the first carrier board; S2, forming a PI layer on one surface of the release layer, wherein the PI layer has a plurality of opening areas; S3, forming a conductive structure in a portion of the opening area of the PI layer; S4, providing a chip, attaching an uncured adhesive layer to a surface of the chip where an I / O port is located, and exposing the adhesive layer at the I / O port; S5, flip chip, the chip I / O port is located in the corresponding opening area on the PI layer; S6, plastic seal; S7, thinning until one end surface of the conductive structure is exposed; S8, forming a first redistribution layer on the thinned surface, and forming a first UBM layer on the surface of the first redistribution layer; S9, temporarily bonding a second carrier to the surface of the first UBM layer; S10, removing the first carrier plate and the release layer; S11, forming a second redistribution layer on the exposed surface of one side of the chip, and forming a second UBM layer on the surface of the second redistribution layer; S12, ball planting on the surface of the second UBM layer; S13, removing the second carrier board and scribing.
[0009] The step S4 can be replaced by: attaching an uncured adhesive layer on the surface of the PI layer, and exposing the adhesive layer in the opening area, wherein the position of the adhesive layer matches the position of the chip mounting.
[0010] The thickness of the conductive structure is greater than the chip height by 30 um, preferably greater than 130 um.
[0011] In step S6, the thickness of the plastic package exceeds the thickness of the chip by 100 μm.
[0012] The adhesive layer is made of BCB material or dry film.
[0013] In step S11 , the second redistribution layer is electrically connected to the exposed chip I / O port.
[0014] Compared with the prior art, the present invention utilizes the viscosity of BCB material or dry film to fix the chip in the lower package, and no bump is required for the lower chip in advance, and no filling material is used in the package to prevent chip warping. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is a structural schematic diagram of the present invention.
[0016] Figure 2 This is a schematic diagram of the POP packaging structure formed by the present invention.
[0017] Figure 3 It is a schematic diagram of the process of the present invention.
[0018] Figure 4 This is a schematic diagram of the prior art before the present invention improves it. DETAILED DESCRIPTION
[0019] The present invention will be further described below with reference to the accompanying drawings.
[0020] like Figure 1As shown, a PI layer 3 is provided on one side surface of the second redistribution layer 12, a chip 6 is provided on one side surface of the PI layer 3, a plurality of opening areas 4 are provided on the surface of the PI layer 3, the chip I / O port 8 corresponds to part of the opening area 4, and forms an electrical connection with the second redistribution layer 12, and a conductive structure 5 is provided in part of the opening area 4, a first redistribution layer 9 is provided at the other end of the conductive structure 5, and a first UBM layer 10 is provided on one side surface of the first redistribution layer 9.
[0021] The other side surface of the second redistribution layer 12 is connected to the solder ball 14 through the second UBM layer 13 , and is electrically connected to the outside world through the solder ball 14 .
[0022] A plastic encapsulation layer 15 is provided between the PI layer 3 and the first redistribution layer 9 . The plastic encapsulation layer 15 wraps the conductive structure 5 and the chip 6 to provide protection.
[0023] The chip 6 is connected to the PI layer 3 via an adhesive layer 7. The adhesive layer 7 is made of BCB material or dry film, which utilizes its stickiness when not cured to avoid the use of underfill, thereby preventing the warping problem caused by underfill.
[0024] The packaging method of the above-mentioned stacked packaging structure includes the following steps: S1, providing a first carrier board 1, and forming a release layer 2 on one side surface of the first carrier board 1; the carrier board 1 provides support.
[0025] S2, forming a PI layer 3 on one surface of the release layer 2, with a plurality of opening areas 4 provided on the PI layer 3; the positions of the opening areas 4 respectively match the positions of the tall pillar conductive structure and the chip I / O ports.
[0026] S3. A conductive structure 5 is formed in the partially opened area 4 of the PI layer 3. The conductive structure 5 serves as a through-layer, electrically connecting the first redistribution layer 9 and the second redistribution layer 12. The thickness of the conductive structure 5 is greater than the height of the chip 6 by 30 μm, preferably greater than 130 μm.
[0027] S4, providing a chip 6, attaching an uncured adhesive layer 7 to the surface of the chip where the I / O port 8 is located, and exposing the adhesive layer 7 at the I / O port 8 to prevent the adhesive layer 7 from affecting the electrical connection of the chip I / O port.
[0028] S5 , flip-chip 6 , the chip I / O port 8 is located at the corresponding opening area 4 on the PI layer 3 , so as to facilitate subsequent electrical connection with the second redistribution layer 12 .
[0029] S6, plastic encapsulation, the thickness of the plastic encapsulation exceeds the thickness of chip 6 by 100um.
[0030] S7 , thinning until one end surface of the conductive structure 5 is exposed, so as to facilitate the subsequent production of a redistribution layer and form an electrical connection with the redistribution layer.
[0031] S8 , forming a first redistribution layer 9 on the thinned surface, and forming a first UBM layer 10 on the surface of the first redistribution layer 9 .
[0032] S9 , temporarily bonding a second carrier 11 to the surface of the first UBM layer 10 , wherein the second carrier 11 provides support after the first carrier is removed.
[0033] S10, removing the first carrier board 1 and the release layer 2 to expose the PI layer and the I / O ports of the chip.
[0034] S11 , forming a second redistribution layer 12 on the exposed surface of one side of the chip 6 , and forming a second UBM layer 13 on the surface of the second redistribution layer 12 .
[0035] S12 , planting balls on the surface of the second UBM layer 13 to form solder balls 14 , and establishing electrical connection with the outside world through the solder balls 14 .
[0036] S13, removing the second carrier board 11 and scribing.
[0037] Step S4 can be replaced by: attaching an uncured adhesive layer 7 to the surface of the PI layer 3 and exposing the adhesive layer 7 in the opening area 4. The position of the adhesive layer 7 matches the position of the chip mounting. The adhesive layer 7 can be made of BCB material or dry film.
[0038] In step S11, the second redistribution layer 12 is electrically connected to the exposed chip I / O port 8. 3. The pads on the chip surface are directly led out from the second redistribution layer 12, without the need to pre-fabricate a conductive connection structure on the chip, thereby reducing impedance.
[0039] This invention forms a lower package structure within a Point-of-Preflash (POP) package, including a tall pillar Cu layer with through-holes and flip-chip fan-out I / O. The PI layer, combined with BCB material or dry film, forms an adhesion layer for the chip during FC, eliminating the need for underfill. During use, the first UBM layer electrically connects to other package structures within the POP, forming the final POP package.
Claims
1. A stacked package structure comprising a second redistribution layer and a chip, characterized in that: A PI layer (3) is provided on one side surface of the second redistribution layer (12), a chip (6) is provided on one side surface of the PI layer (3), a plurality of opening areas (4) are provided on the surface of the PI layer (3), the chip I / O port (8) corresponds to a portion of the opening areas (4), and is electrically connected to the second redistribution layer (12), and a conductive structure (5) is provided in the portion of the opening areas (4), the other end of the conductive structure (5) is provided with a first redistribution layer (9), and a first UBM layer (10) is provided on one side surface of the first redistribution layer (9).
2. The stacked package structure according to claim 1, wherein: The other side surface of the second redistribution layer (12) is connected to the solder ball (14) via the second UBM layer (13).
3. The stacked package structure according to claim 1, wherein: A plastic encapsulation layer (15) is provided between the PI layer (3) and the first redistribution layer (9), and the plastic encapsulation layer (15) wraps the conductive structure (5) and the chip (6).
4. The stacked package structure according to claim 1, wherein: The chip (6) is connected to the PI layer (3) via an adhesive layer (7).
5. A packaging method for a stacked package structure, characterized in that: The steps include: S1, providing a first carrier plate (1), and forming a release layer (2) on one side surface of the first carrier plate (1); S2, forming a PI layer (3) on one surface of the release layer (2), wherein a plurality of opening areas (4) are provided on the PI layer (3); S3, forming a conductive structure (5) in a partial opening area (4) of the PI layer (3); S4, providing a chip (6), attaching an uncured adhesive layer (7) to a surface of a side where the chip I / O port (8) is located, and exposing the adhesive layer (7) at the I / O port (8); S5, flip-chip (6), chip I / O port (8) is located at the corresponding opening area (4) on the PI layer (3); S6, plastic seal; S7, thinning until one end surface of the conductive structure (5) is exposed; S8, forming a first redistribution layer (9) on the thinned surface, and forming a first UBM layer (10) on the surface of the first redistribution layer (9); S9, temporarily bonding a second carrier (11) to the surface of the first UBM layer (10); S10, removing the first carrier plate (1) and the release layer (2); S11, forming a second redistribution layer (12) on the surface of one side of the exposed chip (6), and forming a second UBM layer (13) on the surface of the second redistribution layer (12); S12, planting balls on the surface of the second UBM layer (13); S13, removing the second carrier board (11) and dicing.
6. The packaging method of a stacked package structure according to claim 5, wherein: The step S4 can be replaced by: attaching an uncured adhesive layer (7) on the surface of the PI layer (3), and exposing the adhesive layer (7) in the opening area (4), wherein the position of the adhesive layer (7) matches the position of the chip (6) to be mounted.
7. The packaging method of a stacked package structure according to claim 5, wherein: The thickness of the conductive structure (5) is greater than 30 μm of the chip (6), and preferably greater than 130 μm.
8. The packaging method of a stacked package structure according to claim 5, wherein: In the step S6, the thickness of the plastic package exceeds the thickness of the chip (6) by 100 μm.
9. The packaging method of a stacked package structure according to claim 5, wherein: The adhesive layer (7) is made of BCB material or dry film.
10. The packaging method of a stacked package structure according to claim 5, wherein: In step S11, the second redistribution layer (12) is electrically connected to the exposed chip I / O port (8).