Semiconductor element and manufacturing method thereof
By setting a low-reflectivity, high-boiling-point coating on the metal layer or contact structure and using a laser annealing process, the problems of gap and thermal stress management in the silicon carbide wafer metallization process are solved, and the laser energy utilization rate and the flattening effect of the metal layer are improved.
Patent Information
- Application Number
- CN202410296406.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-15
- Publication Date
- 2025-09-16
AI Technical Summary
In the metallization process of silicon carbide wafers, how to achieve conformal deposition, avoid the formation of voids and defects, and manage the thermal stress of the through-hole filling process to improve yield.
A coating with lower reflectivity and higher boiling point is provided on the metal layer or contact structure, and the coating is made to flow and fill the gaps through a laser annealing process, while the coating remains substantially solid to avoid mixing with the metal layer.
The energy utilization rate of the laser annealing process is improved, the mass loss caused by the vaporization of the metal layer is reduced, the metal contact structure is ensured to have the required electrical and physical properties, and the planarization effect of the metal layer is improved.
Smart Images
Figure CN120659375A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] The semiconductor industry is improving the integration density of various electronic components, such as transistors, by continuously reducing the minimum feature size to allow more electronic components to be integrated into a given area while maintaining the required yield.
[0003] In semiconductor manufacturing, metallization is a common technique for forming interconnect structures using various metals and alloys. Metallization can be achieved through methods such as sputtering, chemical vapor deposition (CVD), or electrodeposition. For example, sputtering and CVD can be combined to increase metal coverage on various structural surfaces.
[0004] However, common silicon carbide (SiC) wafers include trench structures with high aspect ratios, for example, trench structures with aspect ratios greater than 5. Therefore, the metallization process for SiC wafers requires achieving conformal deposition, avoiding void and defect formation, while also managing thermal stress during the via filling process to improve yield.
[0005] Therefore, how to propose a semiconductor device and a manufacturing method thereof that can solve the above problems is one of the issues that the industry is eager to invest research and development resources to solve. Summary of the Invention
[0006] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.
[0007] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device, comprising forming a metal layer over a substrate. The metal layer has voids therein. The method further comprises forming a coating layer to completely cover the metal layer. The method further comprises performing a laser annealing process. During the laser annealing process, the metal layer flows and fills the voids. The coating layer remains substantially solid during the laser annealing process.
[0008] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device, including forming a contact structure above a plurality of gate structures. The gate structures are located on a semiconductor substrate and are spaced apart from each other. The contact structure extends between any two adjacent gate structures. The contact structure has a gap. The manufacturing method also includes forming a coating covering the contact structure. The manufacturing method also includes performing a laser annealing process. During the laser annealing process, the contact structure flows and fills the gap. The coating remains substantially solid during the laser annealing process.
[0009] Yet another aspect of the present disclosure relates to a semiconductor device comprising a plurality of gate structures, contact structures, a coating, and a passivation layer. The gate structures are disposed on a semiconductor substrate and spaced apart from one another. The contact structures are disposed on the gate structures and extend between any two adjacent gate structures. The coating covers and contacts the contact structures. The passivation layer is disposed on and contacts the coating.
[0010] In summary, in some embodiments of the semiconductor elements and their manufacturing methods disclosed herein, by providing a coating with a lower reflectivity and a higher boiling point on the metal layer, the absorption rate of the structure to the laser can be improved, thereby improving the energy utilization rate of the laser annealing process and reducing the mass loss caused by the vaporization of the metal layer. Furthermore, the reflectivity of the coating is lower than that of the metal layer, and under the process pressure, the boiling point of the coating is higher than that of the metal layer, so the effect of flattening the metal layer by laser annealing can be improved. In addition, the coating is made of a material with a melting point lower than the melting point of the metal layer under the process pressure, which can avoid the metal layer and the coating from reaching a molten state and mixing during laser heating. Therefore, when forming the metal contact structure of the transistor, the manufacturing method of the embodiment disclosed herein can ensure that the metal contact structure has the required electrical and physical properties. Compared with common semiconductor elements and their manufacturing methods, it can improve the laser energy utilization rate and improve the effect of flattening by laser annealing. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings illustrate one or more embodiments of the present disclosure and, together with the written description, serve to explain the principles of the present disclosure, in which:
[0012] Figures 1 to 3 FIG2 is a partial cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0013] Figures 4 to 6 FIG2 is a partial cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to some other embodiments of the present disclosure.
[0014] Figure 7 Schematic diagram of a partial cross-section of a semiconductor device formed by a manufacturing method according to other embodiments of the present disclosure. DETAILED DESCRIPTION
[0015] The following disclosure is more fully described herein with reference to the accompanying drawings and reference materials, in which exemplary embodiments are illustrated. The present disclosure may be implemented in various forms and is not limited by the following embodiments. However, these embodiments are provided to facilitate a more complete understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0016] Some embodiments of the present disclosure are directed to a method for fabricating a semiconductor device that fills trenches and eliminates voids under a low thermal budget.
[0017] Please refer to Figures 1 to 3 , which are partial cross-sectional schematic diagrams of different intermediate stages of the method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0018] First, please refer to Figure 1 The manufacturing method includes forming a metal layer 104 on the substrate 100. Figure 1 As shown in FIG, the substrate 100 may include a protruding structure 102 thereon. The protruding structure 102 may be a part of the substrate 100 or a component connected to the substrate 100, but the present disclosure is not limited thereto. Figure 1 As shown in FIG, a metal layer 104 is conformally formed on the substrate 100 and the protruding structure 102 by sputtering or chemical vapor deposition. Voids of different sizes may be formed in the metal layer 104 between the protruding structures 102, such as voids V1 and voids V2. Figure 1 As shown in FIG, void V1 is completely enclosed in metal layer 104. Void V2 has openings leading to the sidewalls of protrusion structure 102 and the upper surface of substrate 100, respectively. Furthermore, due to the presence of protrusion structure 102, the conformally formed metal layer 104 has an uneven upper surface. In some embodiments, metal layer 104 comprises aluminum (Al), copper (Cu), or alloys thereof, such as aluminum-silicon (Al-Si) alloy, aluminum-copper (Al-Cu) alloy, or aluminum-silicon-copper (Al-Si-Cu) alloy.
[0019] Next, the manufacturing method includes performing a laser annealing process to heat the metal layer 104 to melt and flow the metal layer 104 and fill the gaps, so that the metal layer 104 contacts and completely covers the outer surface of the protrusion structure 102 .
[0020] However, due to aluminum's high reflectivity (e.g., between 88% and 92% for visible light wavelengths) and thermal conductivity, the efficiency of laser energy utilization in laser annealing is relatively low. Furthermore, aluminum has a relatively low boiling point (2467°C), which can cause vaporization during laser annealing, leading to surface quality loss of the metal layer. Although copper has a slightly lower boiling point (2595°C) than aluminum, its high reflectivity makes it less suitable for laser annealing.
[0021] Therefore, in the manufacturing method of the embodiment of the present disclosure, before performing the laser annealing process, a coating layer (such as Figure 2 The coating 150 in the laser annealing process is used as an anti-reflective coating layer on the metal layer. These coatings have a material different from that of the metal layer and have a lower reflectivity for the laser wavelength used in the laser annealing process, thereby improving the utilization rate of the laser energy. For example, the reflectivity of the coating is at least lower than that of the metal layer. In some embodiments, the material of these coatings also has a higher boiling point, so that during the laser annealing process, the coating covering the metal layer can help reduce the possibility of vaporization of the metal layer and resulting in quality loss. Therefore, in some embodiments, the coating is configured to completely cover the metal layer.
[0022] For details, please refer to Figure 2 After forming the metal layer 104, the manufacturing method includes forming a plating layer 150 covering the metal layer 104. As described above, the plating layer 150 completely covers the metal layer 104. In other words, the plating layer 150 extends through the gaps such as the gap V1 and the gap V2. Figure 2 As mentioned above, the metal layer 104 has an uneven upper surface, so the upper surface of the plating layer 150 covering the metal layer 104 may also fluctuate along with the upper surface of the metal layer 104 and have an uneven feature.
[0023] In some embodiments, the coating layer 150 includes a material having a lower reflectivity and a higher boiling point. For example, the coating layer 150 includes titanium (Ti) or titanium nitride (TiN). In some embodiments, the reflectivity of the coating layer 150 for a laser beam having a specific wavelength is at least lower than the reflectivity of the metal layer 104 for the same wavelength. In some embodiments, the coating layer 150 has a higher boiling point than the metal layer 104, at least under the process pressure of the laser annealing process.
[0024] Next, the manufacturing method includes performing a laser annealing process at a specific process pressure using a laser having a specific wavelength. In some embodiments, the laser frequency used is 1000 Hz. In some embodiments, the pulse bandwidth of the laser is between 80 nanoseconds and 120 nanoseconds. In some embodiments, the energy density of the laser is between 0.5 joules per square centimeter and 3 joules per square centimeter. The laser pulse heating causes the metal layer 104 to melt and flow, thereby filling the gaps. At the same time, the coating 150 remains substantially solid during the laser annealing process to prevent the coating 150 from mixing with the metal layer 104 in a molten state.
[0025] Please refer to Figure 3 , after completing the laser annealing process, Figure 2 The voids V1 and V2 are filled, and the metal layer 104 becomes a structure having a flat surface and substantially completely covering the outer surface of the protruding structure 102 and the upper surface of the substrate 100 .
[0026] It is worth noting that although the coating 150 remains substantially solid during the laser annealing process, its fluidity may still increase slightly due to the heat and deform due to the stress exerted by the underlying metal layer 104 during the flow, forming Figure 3 Furthermore, in some embodiments, the roughness of the coating layer 150 before the laser annealing process may be greater than the roughness of the coating layer 150 ′ after the laser annealing process.
[0027] The manufacturing method of the embodiment disclosed herein can be applied to form a contact structure such as a source contact of a vertical metal oxide semiconductor field effect transistor (MOSFET). For example, please refer to Figures 4 to 6 , which are partial cross-sectional schematic diagrams of different intermediate stages of the method for manufacturing a semiconductor device according to other embodiments of the present disclosure.
[0028] First, please refer to Figure 4 , the manufacturing method is applied to a vertical structured metal oxide semiconductor field effect transistor. Figure 4 In the process stage shown in FIG, the metal oxide semiconductor field effect transistor at the middle stage of the process includes an epitaxial layer 202 disposed on a semiconductor substrate 200 and a plurality of gate structures 210 disposed on the epitaxial layer 202. The epitaxial layer 202 also includes a lightly doped region 204, a heavily doped region 206, and a source doped region 208. Figure 4As shown in FIG, the gate structure 210 includes a gate oxide layer 212, a gate metal layer 214, and an interlayer dielectric layer 216. The gate structures 210 are arranged spaced apart from each other. In some embodiments, the semiconductor substrate 200 is provided with another contact structure 220 on one side opposite to the epitaxial layer 202. Figure 4 In the corresponding embodiment, the contact structure 220 is a drain contact.
[0029] like Figure 4 As shown in , the manufacturing method includes forming a contact structure 218 above the gate structure 210. Figure 4 As shown in FIG, the contact structure 218 extends between two adjacent gate structures 210 and above each doped region. There may be gaps in the contact structure 218. In particular, when the contact structure 218 is conformally formed by sputtering or chemical vapor deposition and reaches a certain thickness, gaps of varying sizes are easily generated in the spacing between the gate structures 210, such as Figure 4 Similarly, the gap V3 is completely enclosed in the contact structure 218. The gap V4 has openings leading to the sidewalls of the gate structure 210 (eg Figure 4 sidewalls of the interlayer dielectric layer 216 shown in FIG) and the upper surface of the epitaxial layer 202 (eg Figure 4 The upper surface of the heavily doped region 206 is shown in FIG. Figure 4 In the corresponding embodiment, the contact structure 218 is a source contact electrically connected to the transistor source doped region 208. Similarly, in some embodiments, the contact structure 218 comprises aluminum, copper, or alloys thereof such as aluminum-silicon alloy, aluminum-copper alloy, or aluminum-silicon-copper alloy.
[0030] Next, please refer to Figure 5 The manufacturing method includes forming a plating layer 150 covering the contact structure 218 as an anti-reflection layer. Figure 5 As shown in FIG, the plating layer 150 extends through voids such as voids V3 and V4 and completely covers the contact structure 218. Similarly, because the contact structure 218 is conformally deposited on the gate structure 210 and has an uneven top surface, the top surface of the plating layer 150 covering the contact structure 218 may also follow the top surface of the contact structure 218 and have uneven features.
[0031] Similarly, the coating 150 is constructed from a different material than the contact structure 218, exhibiting a lower reflectivity and a higher boiling point for the laser wavelength used in the laser annealing process. This improves laser energy utilization and reduces the possibility of vaporization of the contact structure 218 during the laser annealing process, leading to quality loss. Specifically, the reflectivity of the coating 150 is lower than that of the contact structure 218, and under the process pressure, the boiling point of the coating 150 is higher than that of the contact structure 218.
[0032] Furthermore, the material of the coating 150 is selected so that the melting point of the coating 150 is higher than the melting point of the contact structure 218. This not only allows the coating 150 to cover the contact structure 218 in a substantially solid state during the laser annealing process, but also prevents both materials from melting and mixing at high temperatures, thereby ensuring that the source contact of the transistor has the desired electrical and physical properties. For example, the coating 150 may include titanium or titanium nitride.
[0033] Next, the manufacturing method includes performing a laser annealing process using a laser having a specific wavelength to heat the contact structure 218, causing it to melt and flow, thereby filling the gap, so that the contact structure 218 contacts and completely covers the outer surface of the gate structure 210. In some embodiments, the laser frequency used is 1000 Hz. In some embodiments, the laser pulse width is between 80 nanoseconds and 120 nanoseconds. In some embodiments, the laser energy density is between 0.5 joules per square centimeter and 3 joules per square centimeter.
[0034] Please refer to Figure 6 , after completing the laser annealing process, Figure 5 The gaps V3 and V4 in the gate structure 210 are filled, and the contact structure 218 becomes a structure having a flat surface and substantially completely covering and contacting the gate structure 210 and the upper surface of the epitaxial layer 202. Similarly, although the coating layer 150 remains substantially solid, it may still be deformed during the laser annealing process, forming a Figure 6 Furthermore, in some embodiments, the roughness of the coating layer 150 before the laser annealing process may be greater than the roughness of the coating layer 150 ′ after the laser annealing process.
[0035] Please refer to Figure 7 , which is a partial cross-sectional view of a semiconductor device formed according to another embodiment of the present disclosure. Since the coating layer 150' comprises a conductive material such as titanium or titanium nitride, after the laser annealing process is completed, no additional process is required to remove the coating layer 150', and the subsequent metallization process can be directly performed on the coating layer 150'. For example, Figure 7As shown in FIG, a passivation layer 222 is deposited directly on the plating layer 150'. In some embodiments, the passivation layer 222 includes silicon nitride (SiN), silicon oxide (SiO), polyimide (PI), or the like.
[0036] In yet other embodiments of the present disclosure, the metal oxide semiconductor field effect transistor may further include a barrier metal layer. For example, the barrier metal layer may be conformally formed on the gate structure 210 and the epitaxial layer 202 and have a thickness less than that of the contact structure 218. Thus, no significant voids, such as those in the contact structure 218, are formed within the barrier metal layer. Therefore, the manufacturing method includes forming the contact structure 218 above the gate structure 210 and on the barrier metal layer. Voids, similar to voids V3 and V4, may exist within the contact structure 218 or between the contact structure 218 and the barrier metal layer. Next, the manufacturing method includes forming a coating (e.g., similar to coating 150) overlying the contact structure 218 as an anti-reflection layer and performing a laser annealing process. Similarly, the coating extends over the voids and completely covers the contact structure 218. The coating layer is selected from a material having a low reflectivity and a high boiling point for the laser wavelength used in the laser annealing process. During the laser annealing process, the coating remains substantially solid, while the contact structure 218 melts and flows, thereby filling the gaps, so that the contact structure 218 contacts and completely covers the metal barrier layer. The structure after the laser annealing process is similar to Figure 6 , but the difference is that a metal barrier layer is further included between the contact structure 218 and the gate structure 210. In some embodiments, the metal barrier layer is made of titanium or titanium nitride. In other words, in some embodiments, the metal barrier layer and the plating layer 150' are made of the same conductive material.
[0037] The manufacturing method of the embodiment of the present disclosure can also be applied to forming the gate metal of a trench gate metal oxide semiconductor field effect transistor to help the gate metal fill the trench, cover the gate oxide layer, and eliminate gaps in the gate metal without departing from the scope of the present disclosure.
[0038] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in some embodiments of the semiconductor devices and their manufacturing methods of the present disclosure, by providing a coating with a lower reflectivity and a higher boiling point on the metal layer, the structure's absorption rate of laser light can be improved, thereby improving the energy utilization rate of the laser annealing process and reducing the mass loss caused by the vaporization of the metal layer. Furthermore, the reflectivity of the coating is lower than that of the metal layer, and under the process pressure, the boiling point of the coating is higher than that of the metal layer, thereby improving the effect of flattening the metal layer through laser annealing. In addition, the coating is made of a material with a melting point lower than that of the metal layer under the process pressure, which can prevent the metal layer and the coating from reaching a molten state and mixing during laser heating. Therefore, when forming the metal contact structure of the transistor, the manufacturing method of the embodiment of the present disclosure can ensure that the metal contact structure has the required electrical and physical properties. Compared with conventional semiconductor devices and their manufacturing methods, it can improve the laser energy utilization rate and improve the effect of flattening through laser annealing.
[0039] The foregoing description is provided only to illustrate and describe exemplary embodiments of the present disclosure and is not intended to be exhaustive or to limit the invention to the precise form disclosed. The above teachings may be modified or varied.
[0040] The embodiments are chosen and described to illustrate the present disclosure and its practical applications, thereby motivating those skilled in the art to utilize the present disclosure and its various embodiments and to make various modifications as may be appropriate for the particular application contemplated. Alternative embodiments will be readily apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is therefore to be determined by the appended claims and not by the foregoing description and the exemplary embodiments described therein.
[0041]
Explanation of symbols
[0042] 100: base material
[0043] 102: Raised structure
[0044] 104:Metal layer
[0045] 150,150': plating
[0046] 200:Semiconductor substrate
[0047] 202: epitaxial layer
[0048] 204: lightly doped region
[0049] 206:Heavily doped region
[0050] 208: Source doping region
[0051] 210: Gate structure
[0052] 212: Gate oxide layer
[0053] 214: Gate Metal
[0054] 216: interlayer dielectric layer
[0055] 218,220: Contact structure
[0056] 222: passivation layer
[0057] V1, V2, V3, V4: gap.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: Include: forming a metal layer on a substrate, wherein the metal layer has voids; forming a plating layer to completely cover the metal layer; as well as A laser annealing process is performed, wherein the metal layer flows and fills the voids during the laser annealing process, and the plating layer remains substantially solid during the laser annealing process.
2. The manufacturing method according to claim 1, characterized in that The laser annealing process is performed by a laser having a wavelength, and a reflectivity of the plating layer to the wavelength is lower than a reflectivity of the metal layer to the wavelength.
3. The manufacturing method according to claim 1, characterized in that Under the process pressure of the laser annealing process, the boiling point of the coating layer is higher than the boiling point of the metal layer.
4. A method for manufacturing a semiconductor element, characterized in that: Include: forming a contact structure above a plurality of gate structures, wherein the plurality of gate structures are located on a semiconductor substrate and are spaced apart from each other, the contact structure extending between any two adjacent gate structures, and the contact structure having a gap; forming a plating layer to cover the contact structure; as well as A laser annealing process is performed, wherein the contact structure flows and fills the void during the laser annealing process, and the plating layer remains substantially solid during the laser annealing process.
5. The manufacturing method according to claim 4, characterized in that The laser annealing process is performed by a laser having a wavelength, and a reflectivity of the plating layer to the wavelength is lower than a reflectivity of the contact structure to the wavelength.
6. The manufacturing method according to claim 4, characterized in that Also includes: Conformally forming a metal barrier layer to cover the plurality of gate structures and the semiconductor substrate, Forming the contact structure above the plurality of gate structures includes forming the contact structure above the plurality of gate structures and on the metal barrier layer.
7. The manufacturing method according to claim 4, characterized in that Under the process pressure of the laser annealing process, the boiling point of the coating layer is higher than the boiling point of the contact structure.
8. A semiconductor device, characterized in that: Include: A plurality of gate structures are located on the semiconductor substrate and spaced apart from each other; a contact structure located on the plurality of gate structures and extending between any two adjacent ones of the plurality of gate structures; a plating layer covering the contact structure and contacting the contact structure; as well as The passivation layer is located on the plating layer and contacts the plating layer.
9. The semiconductor device according to claim 8, wherein The contact structure and the plating layer include different conductive materials.
10. The semiconductor device according to claim 8, wherein The passivation layer is completely separated from the contact structure via the plating layer.