Semiconductor pattern density optimization structure and optimization method

Abstract

The embodiment of the invention provides a semiconductor pattern density optimization structure and optimization method. The semiconductor pattern density optimization structure comprises a plurality of optimization areas; each optimization area comprises a plurality of test areas, and each test area comprises an optimization sub-area and a filling sub-area; the optimization sub-region comprises a semiconductor device, and the semiconductor device comprises at least one device active layer and at least one device gate layer; the filling sub-region comprises a plurality of filling active layers arranged in an array, a plurality of filling gate layers arranged in an array, and at least one filling gate layer covering each row of filling active layers; the pattern density of the filling active layer and the filling gate layer of each filling sub-region is independently set, and the pattern density ratio of the filling active layer to the filling gate layer is kept unchanged; the pattern densities of the active layers filled in the different filling sub-regions are different, or the pattern densities of the gate layers filled in the different filling sub-regions are different. By adopting the scheme, the pattern density can be optimized, and the characteristic difference between semiconductor devices of an integrated circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor pattern density optimization structure and an optimization method. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the integration density of semiconductor devices has increased accordingly. Through processes such as film formation, photolithography, and chemical mechanical polishing (CMP), multiple integrated circuit semiconductor devices are formed on a substrate. In order to meet the requirements of the chemical mechanical polishing process, it is usually necessary to design fill patterns in the blank areas of the semiconductor layout to form a certain pattern density, referred to as semiconductor pattern density.

[0003] However, due to the existing semiconductor pattern density, there are large differences in characteristics between integrated circuit semiconductor devices. Therefore, how to optimize the pattern density to reduce the differences in characteristics between integrated circuit semiconductor devices has become a technical problem that technicians in this field urgently need to solve. Summary of the Invention

[0004] The technical problem solved by the present invention is to optimize the pattern density and reduce the characteristic differences between integrated circuit semiconductor devices by providing a semiconductor pattern density optimization structure and an optimization method.

[0005] In order to solve the above problems, an embodiment of the present invention provides a semiconductor pattern density optimization structure, comprising: a substrate, comprising: a plurality of optimization areas; each optimization area, comprising a plurality of test areas, each test area comprising an optimization sub-area and a filling sub-area surrounding the optimization sub-area; the optimization sub-area, comprising: a semiconductor device, the semiconductor device comprising: at least one device active layer and at least one device gate layer located on the device active layer; the filling sub-area, comprising: a plurality of filling active layers that are identical to the device active layer and arranged in an array, and a plurality of filling gate layers that are identical to the device gate layer and arranged in an array, and each row of filling active layers is covered with at least one filling gate layer; wherein the pattern density of the filling active layer and the filling gate layer of each filling sub-area are independently set, and the pattern density ratio of the filling active layer to the filling gate layer remains unchanged; the pattern density of the filling active layer in different filling sub-areas is different from each other, or the pattern density of the filling gate layers in different filling sub-areas is different from each other.

[0006] Optionally, the number of the device active layer and the device gate layer includes any one of the following items: when the number of the device active layer and the device gate layer is both 1, the device active layer extends along the first direction, the device gate layer extends along the second direction to cover the device active layer, and the first direction and the second direction are arranged perpendicularly; the number of the device active layers is greater than or equal to 2, each device active layer is correspondingly covered with a device gate layer, the device active layers extend along the first direction and are arranged along the second direction, and each device gate layer extends along the second direction and is arranged along the second direction.

[0007] Optionally, each of the multiple filled active layers arranged in the array extends along the first direction, and the spacing between each filled active layer along the first direction is equal, and the spacing along the second direction is equal to the spacing between adjacent device active layers in the second direction; each of the multiple filled gate layers arranged in the array extends along the second direction, and the spacing between each filled gate layer along the first direction is equal, and the spacing along the second direction is equal to the spacing between adjacent device gate layers in the second direction.

[0008] Optionally, the device active layer has the same shape and size as the filling active layer, and the device gate layer has the same shape and size as the filling gate layer; the area of ​​each optimized region is equal, the area of ​​each test region is equal, the area of ​​each filling sub-region is equal, and the area of ​​each optimized sub-region is equal.

[0009] Optionally, the optimized sub-area further includes: an N-type well layer, a P-type well layer, a NLDD layer, a PLDD layer, an N-type source and drain doped layer, and a P-type source and drain doped layer; the N-type well layer, the P-type well layer, the NLDD layer, the PLDD layer, the N-type source and drain doped layer, and the P-type source and drain doped layer all extend along the first direction; the N-type well layer, the P-type well layer, the NLDD layer, the PLDD layer, the N-type source and drain doped layer, and the P-type source and drain doped layer have the same shape and size, and the spacing between adjacent layers is equal.

[0010] Optionally, the types of the semiconductor devices include: P-type transistors and / or N-type transistors.

[0011] Optionally, surfaces of the NLDD layer, the PLDD layer, the N-type source / drain doped layer, and the P-type source / drain doped layer are all covered with metal silicide.

[0012] Optionally, the active layer at least includes: a channel layer, a source doping layer, a source doping extension region, a drain doping layer and a drain doping extension region; the semiconductor device includes: a source doping layer and a drain doping layer; the semiconductor pattern density optimization structure includes: a gate terminal connected to the device gate layer; a source terminal connected to the source doping layer; a drain terminal connected to the drain doping layer; an N-type well first terminal connected to one end of the N-type well layer, an N-type well second terminal connected to the other end of the N-type well layer; a P-type well first terminal connected to one end of the P-type well layer, and a P-type well first terminal connected to one end of the P-type well layer. The second terminal is connected to the other end of the P-type well layer; the NLDD first terminal is connected to one end of the NLDD layer, and the NLDD second terminal is connected to the other end of the NLDD layer; the PLDD first terminal is connected to one end of the PLDD layer, and the PLDD second terminal is connected to the other end of the PLDD layer; the N-type doped first terminal is connected to one end of the N-type source and drain doped layer, and the N-type doped second terminal is connected to the other end of the N-type source and drain doped layer; the P-type doped first terminal is connected to one end of the P-type source and drain doped layer, and the P-type doped second terminal is connected to the other end of the P-type source and drain doped layer.

[0013] Accordingly, the present application also provides a method for optimizing semiconductor pattern density, which is applied to the semiconductor pattern density optimization structure described in any of the above items, including: calculating the pattern density of each filled sub-area, the pattern density including: the pattern density of the filled active layer and / or the pattern density of the filled gate layer; testing the semiconductor device characteristics of each optimized sub-area, and obtaining the corresponding relationship between the semiconductor device characteristics of each test area and the pattern density, so as to establish a semiconductor device characteristic pattern density query table.

[0014] Optionally, the resistance of the N-type well layer, P-type well layer, NLDD layer, PLDD layer, N-type source and drain doped layer and P-type source and drain doped layer of each optimized sub-area is tested to obtain the relationship between the resistance of each layer in each test area and the pattern density to establish a resistance pattern density query table for each layer.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0016] An embodiment of the present invention provides a semiconductor pattern density optimization structure, comprising: an optimization sub-region and a filling sub-region; the optimization sub-region comprises: a device active layer and a device gate layer; the filling sub-region comprises: a plurality of filling active layers arranged in an array, and a plurality of filling gate layers arranged in an array, and each row of filling active layers is covered with at least one filling gate layer; the pattern density of the filling active layer and the filling gate layer of each filling sub-region is independently set, and the pattern density of the filling active layer of different filling sub-regions is different from each other, or the pattern density of the filling gate layer of different filling sub-regions is different from each other; by designing and independently setting the pattern density of the filling active layer and the filling gate layer between each filling sub-region, the characteristics of the semiconductor device in each optimization sub-region are tested, and the corresponding relationship between the pattern density of the filling active layer and the filling gate layer and the characteristics of the semiconductor device is obtained, so as to reduce the characteristic differences between the semiconductor devices of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] Figures 1 to 8 This is a schematic diagram of a semiconductor pattern density optimization structure according to an embodiment of the present application;

[0019] Figure 9 It is a flow chart of a method for optimizing semiconductor pattern density according to an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] As can be seen from the background technology, the characteristics of integrated circuit semiconductor devices vary greatly. The specific reason is that during layout design, fill graphics are placed irregularly in the blank areas of the layout. In other words, there are currently no design rules regarding the relationship between graphic density and the characteristics of integrated circuit semiconductor devices.

[0022] The unreasonable design of semiconductor pattern density has the following impacts on the semiconductor device manufacturing process:

[0023] First, the density of the semiconductor pattern is too sparse, and there are depressions on the entire substrate, that is, it is uneven, which increases the uneven chemical mechanical polishing rate and causes uneven polishing of the substrate.

[0024] Second, if the semiconductor pattern density is too high, it will absorb a lot of heat and affect the characteristics of the semiconductor device.

[0025] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor pattern density optimization structure, comprising: a substrate, comprising: a plurality of optimization areas; each optimization area, comprising a plurality of test areas, each test area comprising an optimization sub-area and a filling sub-area surrounding the optimization sub-area; the optimization sub-area, comprising: a semiconductor device, the semiconductor device comprising: at least one device active layer and at least one device gate layer located on the device active layer; the filling sub-area, comprising: a plurality of filling active layers that are identical to the device active layer and arranged in an array, and a plurality of filling gate layers that are identical to the device gate layer and arranged in an array, and each row of filling active layers is covered with at least one filling gate layer; wherein the pattern density of the filling active layer and the filling gate layer of each filling sub-area are independently set, and the pattern density ratio of the filling active layer to the filling gate layer remains unchanged; the pattern density of the filling active layer in different filling sub-areas is different from each other, or the pattern density of the filling gate layers in different filling sub-areas is different from each other.

[0026] By adopting the above-mentioned semiconductor pattern density optimization structure, by independently setting the pattern density of the filling active layer and the filling gate layer between each filling sub-area, the characteristics of the semiconductor device in each optimized sub-area are tested, and the correspondence between the pattern density of the filling active layer and the filling gate layer and the characteristics of the semiconductor device is obtained, so as to reduce the characteristic differences between the semiconductor devices of the integrated circuit.

[0027] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is apparent that the described embodiments are only a portion of the embodiments of the present invention, not all of them. The following embodiments and features thereof may be combined with each other unless there is a conflict.

[0028] refer to Figures 1 to 8 , is a schematic diagram of a semiconductor pattern density optimization structure according to an embodiment of the present application; wherein, Figure 1 It is a schematic diagram of the structure of a semiconductor substrate. Figure 2 This is a schematic diagram of the optimization area in Example 1 of the present application. Figure 3 is a schematic diagram of the semiconductor structure of an embodiment of the present application, Figure 4 yes Figure 3 The semiconductor structure in the circuit structure diagram corresponds to the following: Figure 5 This is a schematic diagram of the optimized sub-area in Example 1 of the present application. Figures 6 and 7A schematic diagram of a device filling pattern in an embodiment of the present application, Figure 8 This is a detailed distribution diagram of each test area in the embodiment of the present application.

[0029] refer to Figure 1 , is a schematic diagram of a semiconductor substrate structure, the semiconductor pattern density optimization structure includes: a substrate 100.

[0030] The substrate 100 is used to provide a process platform for forming a semiconductor pattern density optimization structure.

[0031] In this embodiment, the substrate 100 is a silicon substrate, and the material of the substrate 100 is single crystal silicon. In other embodiments, the material of the substrate 100 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. The substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates 100. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 100 can be formed on the surface of the substrate 100 to improve pattern transfer quality.

[0032] refer to Figure 2 , combined with Figure 1 The substrate 100 includes: multiple optimized areas 101.

[0033] The optimized region 101 is used to provide space for forming the semiconductor pattern density optimized structure.

[0034] The substrate 100 further includes a plurality of semiconductor device regions 102 .

[0035] The plurality of semiconductor device regions 102 are used to form semiconductor devices 112 required for an integrated circuit, ie, integrated circuit semiconductor devices.

[0036] In this embodiment, the plurality of optimized regions 101 are located outside the semiconductor device region 102 , that is, between adjacent semiconductor device regions 102 and between the semiconductor device region 102 and the edge of the substrate 100 .

[0037] The selection and setting of the optimized area 101 can be selected according to actual needs, and this does not limit the present application. In some embodiments, the entire substrate 100 is set as the optimized area 101.

[0038] Each of the plurality of optimized regions 101 includes a plurality of test regions, each of which includes an optimized sub-region and a filling sub-region surrounding the optimized sub-region.

[0039] refer to Figure 5, is a schematic diagram of an optimized sub-area in an embodiment of the present application; the optimized sub-area is used to form a semiconductor device 112, an N-type well layer 200, a P-type well layer 201, an NLDD layer 202, a PLDD layer 203, an N-type source and drain doped layer 204 and a P-type source and drain doped layer 205 and a plurality of test terminals.

[0040] The filling sub-area is used to form a plurality of filling active layers and a plurality of filling gate layers.

[0041] For the sake of clarity and convenience of description, please refer to Figure 2 , combined with Figure 1 In this embodiment, the number of the optimization areas 101 is 13, each optimization area 101 includes 9 test areas, each test area includes: 1 optimization sub-area and 1 filling sub-area, and the shapes of the optimization area 101, the test area, the optimization sub-area and the filling sub-area are all rectangular, that is, the 9 test areas are test area 103, test area 104, test area 105, test area 106, test area 107, test area 108, test area 109, test area 110, and test area 111; the test area 103 includes an optimization sub-area 103a and a filling sub-area 103b surrounding the optimization sub-area 103a, the test area 104 includes an optimization sub-area 104a and a filling sub-area 104b surrounding the optimization sub-area 104a, and the test area 105 includes an optimization sub-area The test area 106 includes the optimized sub-area 106a and the padded sub-area 106b surrounding the optimized sub-area 106a. The test area 107 includes the optimized sub-area 107a and the padded sub-area 107b surrounding the optimized sub-area 107a. The test area 108 includes the optimized sub-area 108a and the padded sub-area 108b surrounding the optimized sub-area 108a. The test area 109 includes the optimized sub-area 109a and the padded sub-area 109b surrounding the optimized sub-area 109a. The test area 110 includes the optimized sub-area 110a and the padded sub-area 110b surrounding the optimized sub-area 110a. The test area 111 includes the optimized sub-area 111a and the padded sub-area 111b surrounding the optimized sub-area 111a.

[0042] It should be noted that the shapes and numbers of the optimization area 101, the test area, the optimization sub-area and the filling sub-area can be selected according to actual needs and are not intended to limit the present application.

[0043] It should be noted that the reference Figure 2 The test areas are arranged in a regular array within the optimization area 101, but this does not limit the present application. In this embodiment, the test areas are arranged in 3 rows and 3 columns within the optimization area 101, that is, the number of test areas in each optimization area 101 is 9.

[0044] It should be noted that the area of ​​each optimized region 101 is equal, the area of ​​each test region is equal, the area of ​​each filling sub-region is equal, and the area of ​​each optimized sub-region is equal, which facilitates the calculation of the subsequent graphic density.

[0045] refer to Figures 3 to 5 ,in, Figure 4 yes Figure 3 The semiconductor structure in the circuit structure diagram corresponds to the semiconductor structure circuit diagram 112c.

[0046] The optimized sub-region 103 a includes a semiconductor device 112 .

[0047] The semiconductor device 112 is used to test the characteristics of the semiconductor device 112 under different pattern densities of the filling sub-regions. The semiconductor device 112 may also be referred to as a test semiconductor device 112 .

[0048] In this embodiment, semiconductor devices 112 are provided in the optimized sub-areas 103a to 111a, and the number of semiconductor devices 112 in each optimized sub-area is 1, and the design parameters and process parameters of the semiconductor devices 112 in each optimized sub-area are the same.

[0049] The types of the semiconductor device 112 include: P-type transistors and / or N-type transistors. In this embodiment, the type of the semiconductor device 112 is a P-type transistor.

[0050] The semiconductor device 112 includes a source doping layer 112a and a drain doping layer 112b.

[0051] The characteristics of the semiconductor device 112 include at least electrical characteristics, thermal characteristics, and reliability, as follows:

[0052] The electrical characteristics include: on-state current, threshold voltage, subthreshold swing, off-state current, breakdown voltage, cut-off frequency, and maximum oscillation frequency.

[0053] The thermal characteristics include: maximum allowable operating temperature, hot carrier effect (degradation caused by carrier injection into the gate oxide layer under high electric field).

[0054] The reliability includes: electrical properties under high temperature and high humidity, maximum breakdown voltage and radiation tolerance.

[0055] Those skilled in the art may selectively test the characteristics of the semiconductor device 112 according to actual needs, and this is not intended to limit the present application.

[0056] It should be noted that, in this embodiment, the design and manufacturing parameters of the semiconductor device 112 are exactly the same as the design and manufacturing parameters of the multiple integrated circuit semiconductor devices in the semiconductor device area 102. For example, the semiconductor device 112 and the multiple integrated circuit semiconductor devices are formed simultaneously in the same process flow, the channel carrier flow direction of the semiconductor device 112 is parallel and consistent with the channel carrier flow direction of the multiple integrated circuit semiconductor devices, the channel length and width of the semiconductor device 112 are consistent with those of the integrated circuit semiconductor device, and the size of the semiconductor device 112 is the same as that of the integrated circuit semiconductor device. That is, the semiconductor device 112 and the integrated circuit semiconductor device use the same design and manufacturing parameters.

[0057] In this embodiment, the channel carrier flow direction of the semiconductor device 112 is the second direction X, and the direction perpendicular to the second direction X and parallel to the surface of the substrate 100 is the first direction Y.

[0058] The semiconductor device 112 includes: at least one device active layer and at least one device gate layer located on the device active layer; the number of the device active layer and the device gate layer includes any one of the following:

[0059] When the number of the device active layer and the device gate layer are both one, the device active layer extends along a first direction Y, and the device gate layer extends along a second direction X to cover the device active layer, and the first direction Y and the second direction X are perpendicular to each other.

[0060] refer to Figures 6 and 7 , is a schematic diagram of the device filling pattern of an embodiment of the present application.

[0061] refer to Figure 6 As an embodiment, the number of the device active layer 113 and the device gate layer 114 in the optimized sub-region 103a is 1, the device active layer 113 extends along a first direction Y, that is, extends along the long direction of the device active layer 113, and the device gate layer 114 extends along a second direction X to cover the device active layer 113, that is, extends along the width direction of the device active layer 113. The device gate layer 114 is located on the device active layer 113, and the first direction Y and the second direction X are arranged perpendicularly; the device active layer and the device gate layer in the optimized sub-region 104a to the optimized sub-region 111a are designed according to the device active layer 113 and the device gate layer 114 in the optimized sub-region 103a.

[0062] It should be noted that Figure 6 The device active layer 113 and the device gate layer 114 in the device can be referred to as a device filling pattern 117.

[0063] The number of the device active layers is greater than or equal to 2, each device active layer is covered with a corresponding device gate layer, the device active layers extend along the first direction Y and are arranged along the second direction X, and each device gate layer extends along the second direction X and is arranged along the second direction X.

[0064] refer to Figure 7 As an embodiment, the number of the device active layers 113 in the optimized sub-region 103a is three, and the number of the device gate layers 114 is three, with each device active layer being covered with a corresponding device gate layer; the device active layers 113 all extend along the first direction Y and are arranged along the second direction X, and the three device active layers are arranged in an array of one row and three columns, that is, the three device active layers 113 extend along the length direction of the device active layer 113 and are arranged along the width direction of the device active layer 113; each device gate layer 114 extends along the second direction X and is arranged along the second direction X, that is, extends and is arranged along the width direction of the device active layer 113; along the second direction X, the spacing between adjacent device active layers 113 is equal, and the spacing between adjacent device gate layers 114 is equal; the device active layers and device gate layers in the optimized sub-regions 104a to 111a are designed according to the device active layers 113 and device gate layers 114 in the optimized sub-region 103a.

[0065] It should be noted that adjacent device gate layers are disconnected or electrically connected; the shape and size of each device active layer within each optimized sub-region are the same, and the shape and size of each device gate layer are the same. In this embodiment, within each optimized sub-region, the device active layers are all rectangular in shape and have the same size, and the device gate layers are all rectangular in shape and have the same size.

[0066] It should be noted that the active layer at least includes: a channel layer, a source doped layer, a source doped extension region, a drain doped layer and a drain doped extension region, and the active layer includes a device active layer and a filling active layer. In this embodiment, reference is made to Figure 3 The device active layer 113 includes: a channel layer 112g, a source doping layer 112a, a source doping extension region 112e, a drain doping layer 112b and a drain doping extension region 112f, and the filled active layer includes: a channel layer 112g, a source doping layer 112a, a source doping extension region 112e, a drain doping layer 112b and a drain doping extension region 112f.

[0067] like Figure 6 As shown, in this embodiment, the number of the device active layer 113 and the number of the device gate layer 114 in the optimized sub-region 103a are both 1. For relevant information about the device active layer 113 and the device gate layer 114, please refer to the above and will not be repeated here.

[0068] The filling sub-area includes: a plurality of filling active layers that are identical to the device active layer and arranged in an array; wherein the pattern density of the filling active layer of each filling sub-area is independently set; and the pattern density of the filling active layers of different filling sub-areas is different from each other.

[0069] In this embodiment, each filling active layer in each filling sub-area is the same as the device active layer, that is, the device active layer and the filling active layer have the same shape, size and thickness. Furthermore, the formation process, design and extension direction of each filling active layer are also the same as those of the device active layer.

[0070] The multiple filling active layers are arranged in an array, and the pattern density of the filling active layers in each filling sub-area is independently set. The pattern density of the filling active layers in different filling sub-areas is different from each other. Each of the multiple filling active layers arranged in the array extends along the first direction Y, and the spacing between each filling active layer along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device active layers in the second direction X.

[0071] By independently setting different pattern densities of the filling active layer between the filling sub-areas, the corresponding relationship between different pattern densities and semiconductor device characteristics is obtained, thereby reducing the characteristic differences between integrated circuit semiconductor devices.

[0072] Each of the plurality of filled active layers arranged in the array extends along the first direction Y and is also arranged along the first direction Y and the second direction X.

[0073] It should be noted that the filling active layer and the device active layer are the same, that is, the design parameters and process parameters are the same, so the filling active layer and the device active layer use the same mark, that is, Figure 6 The mark 113 of the device active layer in FIG. 1 may also represent the filled active layer 113 .

[0074] In other embodiments, the filling active layer and the device active layer may be different, that is, the design parameters and / or process parameters are different.

[0075] refer to Figure 8 , is a detailed distribution diagram of each test area in the embodiment of this application.

[0076] Each filling sub-area includes an upper filling sub-area 115a, a lower filling sub-area 115b opposite to the upper filling sub-area, a left filling sub-area 115c, and a right filling sub-area 115d opposite to the left filling sub-area; each block area 116 is correspondingly provided with a device filling pattern 117 (such as Figure 6), that is, the blocks in the upper area 115a of the filling sub-area have a total of m2 rows and m1 columns of device filling graphics 117, the blocks in the lower area 115b of the filling sub-area have a total of m4 rows and m3 columns of device filling graphics 117, the blocks in the left area 115c of the filling sub-area have a total of m6 rows and m5 columns of device filling graphics 117, and the blocks in the right area 115d of the filling sub-area have a total of m8 rows and m7 columns of device filling graphics 117, where m1 to m8 are all natural numbers.

[0077] In order to better understand the present application, in this embodiment, each filled active layer 113 is rectangular and of equal size, and the area S1 of each filled active layer 113 is 200 square nanometers (nm 2 ), the shape of each test area is rectangular, and the area S2 of each test area is 185,000 square nanometers. For example, the pattern density of the filling active layer 113 of each filling sub-area is independently set, and the pattern density of the filling active layer 113 of different filling sub-areas is different from each other.

[0078] The calculation formula for the density of the filling active layer 113 in each filling sub-area is:

[0079] (Total number of active filling layers * area of ​​each active filling layer) / (area of ​​each test area)

[0080] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 103b, m1=30, m2=11, m3=30, m4=11, m5=11, m6=11, m7=11, and m8=11, that is, there are 330 filling active layers 113 arranged in 11 rows and 30 columns in the upper filling sub-area 115a, there are 330 filling active layers 113 arranged in 11 rows and 30 columns in the lower filling sub-area 115b, and there are 121 filling active layers 113 arranged in 11 rows and 11 columns in the left filling sub-area 115c. , there are 121 filling active layers 113 arranged in 11 rows and 11 columns in the right filling sub-area 115d, that is, there are 902 filling active layers 113 in the filling sub-area 103b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 103b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing between each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device active layers in the second direction X.

[0081] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-area 103b is:

[0082] (902*S1) / S2=(902*200) / 185000≈98%

[0083] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 104b, m1=28, m2=10, m3=28, m4=10, m5=10, m6=10, m7=10, and m8=10. That is, in the upper filling sub-area 115a, there are 280 filling active layers 113 arranged in 10 rows and 28 columns, in the lower filling sub-area 115b, there are 280 filling active layers 113 arranged in 10 rows and 28 columns, and in the left filling sub-area 115c, there are 100 filling active layers 113 arranged in 10 rows and 10 columns. There are 100 filling active layers 113 arranged in 10 rows and 10 columns in the right filling sub-area 115d, that is, there are 760 filling active layers 113 in the filling sub-area 104b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 104b extends along the first direction Y and is arranged along the first direction Y and the second direction X, and the spacing between each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device active layers in the second direction X.

[0084] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 104b is:

[0085] (760*S1) / S2=(760*200) / 185000≈82%

[0086] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 105b, m1=26, m2=9, m3=26, m4=9, m5=9, m6=9, m7=9, and m8=9, that is, there are 234 filling active layers 113 arranged in 9 rows and 26 columns in the upper filling sub-area 115a, there are 234 filling active layers 113 arranged in 9 rows and 26 columns in the lower filling sub-area 115b, there are 81 filling active layers 113 arranged in 9 rows and 9 columns in the left filling sub-area 115c, and the filling There are 81 filling active layers 113 arranged in 9 rows and 9 columns in the right sub-area 115d, that is, there are 630 filling active layers 113 in the filling sub-area 105b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 105b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0087] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 105b is:

[0088] (630*S1) / S2=(630*200) / 185000=68%

[0089] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 106b, m1=24, m2=8, m3=24, m4=9, m5=8, m6=8, m7=8, and m8=8, that is, there are 192 filling active layers 113 arranged in 8 rows and 24 columns in the upper area 115a of the filling sub-area, there are 192 filling active layers 113 arranged in 8 rows and 24 columns in the lower area 115b of the filling sub-area, there are 64 filling active layers 113 arranged in 8 rows and 8 columns in the left area 115c of the filling sub-area, and the filling active layers 113 are arranged in 8 rows and 8 columns. There are 64 filling active layers 113 arranged in 8 rows and 8 columns in the right sub-area 115d, that is, there are 512 filling active layers 113 in the filling sub-area 106b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 106b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0090] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 106b is:

[0091] (512*S1) / S2=(512*200) / 185000≈55%

[0092] refer to Figure 8 , combined with Figure 2In this embodiment, in the filling sub-area 107b, m1=22, m2=7, m3=22, m4=97, m5=7, m6=7, m7=7, and m8=7. That is, there are 154 filling active layers 113 arranged in 7 rows and 22 columns in the upper filling sub-area 115a, there are 154 filling active layers 113 arranged in 7 rows and 22 columns in the lower filling sub-area 115b, there are 49 filling active layers 113 arranged in 7 rows and 7 columns in the left filling sub-area 115c, and the filling active layers 113 are arranged in 7 rows and 7 columns. There are 49 filling active layers 113 arranged in 7 rows and 7 columns in the right filling sub-area 115d, that is, there are 406 filling active layers 113 in the filling sub-area 107b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 107b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing between each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device active layers in the second direction X.

[0093] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 107b is:

[0094] (406*S1) / S2=(406*200) / 185000≈44%

[0095] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 108b, m1=20, m2=6, m3=20, m4=6, m5=6, m6=6, m7=6, and m8=6. That is, in the upper area 115a of the filling sub-area, there are 120 filling active layers 113 arranged in 6 rows and 20 columns, in the lower area 115b of the filling sub-area, there are 120 filling active layers 113 arranged in 6 rows and 20 columns, in the left area 115c of the filling sub-area, there are 36 filling active layers 113 arranged in 6 rows and 6 columns, and in the filling There are 36 filling active layers 113 arranged in 6 rows and 6 columns in the right sub-area 115d, that is, there are 312 filling active layers 113 in the filling sub-area 108b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 108b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0096] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 108b is:

[0097] (312*S1) / S2=(312*200) / 185000≈34%

[0098] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 109b, m1=18, m2=5, m3=18, m4=5, m5=5, m6=5, m7=5, and m8=5, that is, there are 90 filling active layers 113 arranged in 5 rows and 18 columns in the upper filling sub-area X721, there are 90 filling active layers 113 arranged in 5 rows and 18 columns in the lower filling sub-area X722, there are 25 filling active layers 113 arranged in 5 rows and 5 columns in the left filling sub-area X723, and the filling sub-area 109b has 25 filling active layers 113 arranged in 5 rows and 5 columns. There are 25 filling active layers 113 arranged in 5 rows and 5 columns in the right area X724, that is, there are 230 filling active layers 113 in the filling sub-area 109b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 109b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0099] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-region 109b is:

[0100] (230*S1) / S2=(230*200) / 185000≈25%

[0101] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 110b, m1=16, m2=4, m3=16, m4=4, m5=4, m6=4, m7=4, and m8=4, that is, there are 64 filling active layers 113 arranged in 4 rows and 16 columns in the upper area 115a of the filling sub-area, there are 64 filling active layers 113 arranged in 4 rows and 16 columns in the lower area 115b of the filling sub-area, there are 16 filling active layers 113 arranged in 4 rows and 4 columns in the left area 115c of the filling sub-area, and the filling sub-area 110b has 16 filling active layers 113 arranged in 4 rows and 4 columns. There are 16 filling active layers 113 arranged in 4 rows and 4 columns in the right area 115d, that is, there are 160 filling active layers 113 in the filling sub-area 110b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 110b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0102] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-area 110b is:

[0103] (160*S1) / S2=(160*200) / 185000≈17%

[0104] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 111b, m1=14, m2=3, m3=14, m4=3, m5=3, m6=3, m7=3, and m8=3. That is, there are 42 filling active layers 113 arranged in 3 rows and 14 columns in the upper filling sub-area 115a, there are 42 filling active layers 113 arranged in 3 rows and 14 columns in the lower filling sub-area 115b, there are 9 filling active layers 113 arranged in 3 rows and 3 columns in the left filling sub-area 115c, and the filling sub-area 111b has 42 filling active layers 113 arranged in 3 rows and 14 columns in total. There are 9 filling active layers 113 arranged in 3 rows and 3 columns in the right area 115d, that is, there are 102 filling active layers 113 in the filling sub-area 111b, and each filling active layer 113 is a rectangle of the same size; each filling active layer 113 in the filling sub-area 111b extends along the first direction Y, and is arranged along the first direction Y and the second direction X, and the spacing of each filling active layer 113 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing of the adjacent device active layers in the second direction X.

[0105] In this embodiment, the pattern density of the filling active layer 113 in the filling sub-area 110b is:

[0106] (102*S1) / S2=(102*200) / 185000≈11%

[0107] It should be noted that the spacing of each filled active layer 113 along the first direction Y and the spacing along the second direction X can be set according to actual needs, and the center line of each row of filled active layers 113 in the filling sub-area along the second direction X is located on the same straight line, and the center line of each column of filled active layers 113 along the first direction Y is also located on the same straight line.

[0108] The filling sub-area includes: a plurality of filling gate layers that are identical to the device gate layer and arranged in an array, and each row of the filling active layer is covered with at least one filling gate layer; wherein the pattern density of the filling gate layer of each filling sub-area is independently set; and the pattern density of the filling gate layers of different filling sub-areas is different from each other.

[0109] In this embodiment, each filling gate layer in each filling sub-area is the same as the device gate layer, that is, the device gate layer and the filling gate layer have the same shape, size and thickness. Furthermore, the formation process and extension direction of each filling gate layer are also the same as those of the device gate layer.

[0110] Each row of filled active layers is covered with at least one filled gate layer. Specifically, each row of filled active layers is covered with a filled gate layer, meaning each row of filled active layers shares a common gate. Alternatively, each filled active layer is covered with a separate filled gate layer, meaning the number of filled active layers in each test area is equal to the number of filled gate layers. The position of the filled gate layer on the filled active layers is consistent with the position of the device gate layer on the device active layers. In this embodiment, each filled active layer is covered with a separate filled gate layer.

[0111] The multiple filling gate layers are arranged in an array, and the pattern density of the filling gate layer in each filling sub-area is independently set. The pattern density of the filling gate layers in different filling sub-areas is different from each other. In addition, each of the multiple filling gate layers arranged in the array extends along the second direction X, and the spacing between each filling gate layer along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0112] By independently setting different pattern densities of the filling gate layer between the filling sub-areas, the corresponding relationship between different pattern densities and semiconductor device characteristics is obtained, thereby reducing the characteristic differences between integrated circuit semiconductor devices.

[0113] Each of the plurality of filling gate layers arranged in the array extends along the second direction X and is also arranged along the first direction Y and the second direction X.

[0114] It should be noted that the filling gate layer and the device gate layer are the same, so the filling gate layer and the device gate layer use the same mark, such as Figure 6 As shown, that is, Figure 6 The device gate layer 114 in FIG. 1 may also represent a filling gate layer 114 .

[0115] In order to better understand the present application, in this embodiment, each of the filling gate layers 114 is rectangular and has the same size, and the area S3 of each filling gate layer 114 is 150 square nanometers (nm 2 ), the shape of each test area is rectangular, and the area S2 of each test area is 185,000 square nanometers. For example, the pattern density of the filling gate layer 114 of each filling sub-area is independently set, and the pattern density of the filling gate layer 114 of different filling sub-areas is different from each other.

[0116] The calculation formula for the density of the filling gate layer in each filling sub-area is:

[0117] (Total number of filled gate layers * area of ​​each filled gate layer) / (area of ​​each test area)

[0118] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-region 103b, m1=30, m2=11, m3=30, m4=11, m5=11, m6=11, m7=11, and m8=11. That is, there are 330 filling gate layers 114 arranged in 11 rows and 30 columns in the upper filling sub-region 115a, 330 filling gate layers 114 arranged in 11 rows and 30 columns in the lower filling sub-region 115b, and 121 filling gate layers 114 arranged in 11 rows and 11 columns in the left filling sub-region 115c. , there are 121 filling gate layers 114 arranged in 11 rows and 11 columns in the right filling sub-region 115d, that is, there are 902 filling gate layers 114 in the filling sub-region 103b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-region 103b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0119] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 103b is:

[0120] (902*S3) / S2=(902*150) / 185000≈73%

[0121] refer to Figure 8 , combined with Figure 2In this embodiment, in the filling sub-region 104b, m1=28, m2=10, m3=28, m4=10, m5=10, m6=10, m7=10, and m8=10. That is, in the upper filling sub-region 115a, there are 280 filling gate layers 114 arranged in 10 rows and 28 columns, in the lower filling sub-region 115b, there are 280 filling gate layers 114 arranged in 10 rows and 28 columns, and in the left filling sub-region 115c, there are 100 filling gate layers 114 arranged in 10 rows and 10 columns. There are 100 filling gate layers 114 arranged in 10 rows and 10 columns in the right filling sub-area 115d, that is, there are 760 filling gate layers 114 in the filling sub-area 104b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-area 104b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0122] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 104b is:

[0123] (760*S3) / S2=(760*150) / 185000≈62%

[0124] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 105b, m1=26, m2=9, m3=26, m4=9, m5=9, m6=9, m7=9, and m8=9. That is, in the upper area 115a of the filling sub-area, there are 234 filling gate layers 114 arranged in 9 rows and 26 columns, in the lower area 115b of the filling sub-area, there are 234 filling gate layers 114 arranged in 9 rows and 26 columns, in the left area 115c of the filling sub-area, there are 81 filling gate layers 114 arranged in 9 rows and 9 columns, and in the filling There are 81 filling gate layers 114 arranged in 9 rows and 9 columns in the right sub-area 115d, that is, there are 630 filling gate layers 114 in the filling sub-area 105b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-area 105b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0125] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 105b is:

[0126] (630*S3) / S2=(630*150) / 185000≈51%

[0127] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 106b, m1=24, m2=8, m3=24, m4=9, m5=8, m6=8, m7=8, and m8=8. That is, in the upper area 115a of the filling sub-area, there are 192 filling gate layers 114 arranged in 8 rows and 24 columns, in the lower area 115b of the filling sub-area, there are 192 filling gate layers 114 arranged in 8 rows and 24 columns, in the left area 115c of the filling sub-area, there are 64 filling gate layers 114 arranged in 8 rows and 8 columns, and in the filling There are 64 filling gate layers 114 arranged in 8 rows and 8 columns in the right sub-area 115d, that is, there are 512 filling gate layers 114 in the filling sub-area 106b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-area 106b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0128] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 106b is:

[0129] (512*S3) / S2=(512*150) / 185000≈42%

[0130] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 107b, m1=22, m2=7, m3=22, m4=97, m5=7, m6=7, m7=7, and m8=7. That is, in the upper area 115a of the filling sub-area, there are 154 filling gate layers 114 arranged in 7 rows and 22 columns, in the lower area 115b of the filling sub-area, there are 154 filling gate layers 114 arranged in 7 rows and 22 columns, in the left area 115c of the filling sub-area, there are 49 filling gate layers 114 arranged in 7 rows and 7 columns, and in the filling There are 49 filling gate layers 114 arranged in 7 rows and 7 columns in the right filling sub-area 115d, that is, there are 406 filling gate layers 114 in the filling sub-area 107b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-area 107b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0131] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 107b is:

[0132] (406*S3) / S2=(406*150) / 185000≈33%

[0133] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 108b, m1=20, m2=6, m3=20, m4=6, m5=6, m6=6, m7=6, and m8=6. That is, in the upper area 115a of the filling sub-area, there are 120 filling gate layers 114 arranged in 6 rows and 20 columns, in the lower area 115b of the filling sub-area, there are 120 filling gate layers 114 arranged in 6 rows and 20 columns, in the left area 115c of the filling sub-area, there are 36 filling gate layers 114 arranged in 6 rows and 6 columns, and in the filling There are 36 filling gate layers 114 arranged in 6 rows and 6 columns in the right sub-area 115d, that is, there are 312 filling gate layers 114 in the filling sub-area 108b, and each filling gate layer 114 is a rectangle of the same size; in the filling sub-area 103b, each filling gate layer 114 extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0134] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 108b is:

[0135] (312*S3) / S2=(312*150) / 185000≈25%

[0136] refer to Figure 8 , combined with Figure 2In this embodiment, in the filling sub-area 109b, m1=18, m2=5, m3=18, m4=5, m5=5, m6=5, m7=5, and m8=5. That is, in the upper area 115a of the filling sub-area, there are 90 filling gate layers 114 arranged in 5 rows and 18 columns, in the lower area X7122 of the filling sub-area, there are 90 filling gate layers 114 arranged in 5 rows and 18 columns, in the left area 115c of the filling sub-area, there are 25 filling gate layers 114 arranged in 5 rows and 5 columns, and in the filling sub-area There are 25 filling gate layers 114 arranged in 5 rows and 5 columns in the right area 115d, that is, there are 230 filling gate layers 114 in the filling sub-area 109b, and each filling gate layer 114 is a rectangle of the same size; each filling gate layer 114 in the filling sub-area 109b extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0137] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 109b is:

[0138] (230*S3) / S2=(230*150) / 185000≈19%

[0139] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 110b, m1=16, m2=4, m3=16, m4=4, m5=4, m6=4, m7=4, and m8=4. That is, in the upper area 115a of the filling sub-area, there are 64 filling gate layers 114 arranged in 4 rows and 16 columns, in the lower area 115b of the filling sub-area, there are 64 filling gate layers 114 arranged in 4 rows and 16 columns, in the left area 115c of the filling sub-area, there are 16 filling gate layers 114 arranged in 4 rows and 4 columns, and in the filling sub-area There are 16 filling gate layers 114 arranged in 4 rows and 4 columns in the right area 115d, that is, there are 160 filling gate layers 114 in the filling sub-area 110b, and each filling gate layer 114 is a rectangle of the same size; in the filling sub-area 103b, each filling gate layer 114 extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0140] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 110b is:

[0141] (160*S3) / S2=(160*150) / 185000≈13%

[0142] refer to Figure 8 , combined with Figure 2 In this embodiment, in the filling sub-area 111b, m1=14, m2=3, m3=14, m4=3, m5=3, m6=3, m7=3, and m8=3. That is, in the upper area 115a of the filling sub-area, there are 42 filling gate layers 114 arranged in 3 rows and 14 columns, in the lower area 115b of the filling sub-area, there are 42 filling gate layers 114 arranged in 3 rows and 14 columns, in the left area 115c of the filling sub-area, there are 9 filling gate layers 114 arranged in 3 rows and 3 columns, and in the filling sub-area There are 9 filling gate layers 114 arranged in 3 rows and 3 columns in the right area 115d, that is, there are 102 filling gate layers 114 in the filling sub-area 111b, and each filling gate layer 114 is a rectangle of the same size; in the filling sub-area 103b, each filling gate layer 114 extends along the second direction X and is arranged along the first direction Y and the second direction X, and the spacing between each filling gate layer 114 along the first direction Y is equal, and the spacing along the second direction X is equal to the spacing between adjacent device gate layers in the second direction X.

[0143] In this embodiment, the pattern density of the filling gate layer 114 in the filling sub-region 110b is:

[0144] (102*S3) / S2=(102*150) / 185000≈8%

[0145] It should be noted that the spacing between each filling gate layer 114 along the first direction Y and the spacing along the second direction X can be set according to actual needs, and the center lines of each row of filling gate layers in the filling sub-region along the second direction X are located on the same straight line, and the center lines of each column of filling gate layers along the first direction Y are also located on the same straight line. Furthermore, the center line of each row of filling gate layers along the second direction X coincides with the center line of each row of device gate layers along the second direction X, and the center line of each row of filling active layers along the second direction X coincides with the center line of each row of device active layers along the second direction X.

[0146] It should be noted that the calculation of the graphic density of the above-mentioned filling active layer 113 and the filling gate layer 114 is only for ease of understanding. The graphic density of the filling active layer 113 and the filling gate layer 114 in each test area can be set according to actual needs, and this does not limit the present application.

[0147] It should be noted that the graphic density ratio of the filled active layer 113 and the filled gate layer 114 remains unchanged, so that each filled active layer 113 is provided with a filled gate layer 114, so that the correspondence between the graphic density and the characteristics of the semiconductor device 112 is more accurate, further reducing the characteristic differences between the integrated circuit semiconductor devices.

[0148] The graphic density ratio of the filled active layer 113 and the filled gate layer 114 remains unchanged, that is, the graphic density ratio of the filled active layer 113 to the filled gate layer 114 in each test area is equal, or the graphic density ratio of the filled active layer 113 to the filled gate in each test area is within the range of (0, 10%].

[0149] That is, the ratio of (total number of filled active layers * area of ​​each filled active layer) / (area of ​​each test area) to (total number of filled gate layers * area of ​​each filled gate layer) / (area of ​​each test area) remains unchanged, for example:

[0150] The ratio of (902*200) / 185000 to (902*150) / 185000 is about 1.33;

[0151] The ratio of (760*200) / 185000 to (760*150) / 185000 is about 1.33;

[0152] The ratio of (630*200) / 185000 to (630*150) / 185000 is about 1.33;

[0153] The ratio of (512*200) / 185000 to (512*150) / 185000 is about 1.33;

[0154] The ratio of (406*200) / 185000 to (406*150) / 185000 is about 1.33;

[0155] The ratio of (312*200) / 185000 to (312*150) / 185000 is approximately 1.33;

[0156] The ratio of (230*200) / 185000 to (230*150) / 185000 is approximately 1.33;

[0157] The ratio of (160*200) / 185000 to (160*150) / 185000 is about 1.33;

[0158] The ratio of (102*200) / 185000 to (102*150) / 185000 is approximately 1.33.

[0159] In this embodiment, the above ratios are all approximately 1.33, that is, the pattern density ratio of the filling active layer 113 and the filling gate layer 114 remains unchanged.

[0160] It should be noted that the shape, size and thickness of the device active layer 113 are the same as those of the filling active layer 113, and the shape, size and thickness of the device gate layer 114 are the same as those of the filling gate layer 114. That is, in each test area, each filling active layer 113 is the same as the shape, size and thickness of each device active layer 113, and each filling gate layer 114 is the same as the shape, size and thickness of each device gate layer 114.

[0161] It should be noted that the arrangement order of the optimized sub-areas and the filling sub-areas surrounding the optimized sub-areas can be changed as needed, that is, the graphic density of the filling active layer 113 and the filling gate layer 114 can be arranged from large to small from the optimized sub-area 103a to the optimized sub-area 111a, or from small to large, or randomly arranged, and this does not limit the present application.

[0162] In other embodiments, the filling active layer 113 and the filling gate layer 114 in the optimized area 101 can also be arranged in the following manner: the spacing between the filling active layers 113 between the filling sub-areas is arranged in an array in an increasing manner, and the spacing between the filling gate layers 114 between the filling sub-areas is arranged in an array in an increasing manner, that is, referring to Figure 2 and Figure 8 , along the first direction Y, the spacing between adjacent filling active layers 113 in each filling sub-region is equal, along the second direction X, the spacing between adjacent filling active layers 113 in each filling sub-region is equal, and along the first direction Y, the spacing between adjacent filling active layers 113 between each filling sub-region increases, along the second direction X, the spacing between adjacent filling active layers 113 between each filling sub-region increases; along the first direction Y, the spacing between adjacent filling gate layers 114 in each filling sub-region is equal, along the second direction X, the spacing between adjacent filling gate layers 114 in each filling sub-region is equal. The spacing is equal, and along the first direction Y, the spacing between adjacent filling gate layers 114 between each filling sub-region increases, and along the second direction X, the spacing between adjacent filling gate layers 114 between each filling sub-region increases, which has the following beneficial effects: the filling active layer 113 and the filling gate layer 114 in each filling sub-region can be evenly distributed, and the distribution of the blank area in each filling sub-region is more uniform, so that the correspondence between the obtained graphic density and the characteristics of the semiconductor device is more accurate, and the characteristic differences between the semiconductor devices of the integrated circuit are further reduced.

[0163] For example, in the filling sub-area 103b, along the first direction Y, the spacing between adjacent filling active layers 113 is 50 nanometers, and the spacing between adjacent filling gate layers 114 is 50 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 50 nanometers, and the spacing between adjacent filling gate layers 114 is 50 nanometers.

[0164] In the filling sub-area 104b, along the first direction Y, the spacing between adjacent filling active layers 113 is 52 nanometers, and the spacing between adjacent filling gate layers 114 is 52 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 52 nanometers, and the spacing between adjacent filling gate layers 114 is 52 nanometers.

[0165] In the filling sub-area 105b, along the first direction Y, the spacing between adjacent filling active layers 113 is 54 nanometers, and the spacing between adjacent filling gate layers 114 is 54 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 54 nanometers, and the spacing between adjacent filling gate layers 114 is 54 nanometers.

[0166] In the filling sub-area 106b, along the first direction Y, the spacing between adjacent filling active layers 113 is 56 nanometers, and the spacing between adjacent filling gate layers 114 is 56 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 56 nanometers, and the spacing between adjacent filling gate layers 114 is 56 nanometers.

[0167] In the filling sub-area 107b, along the first direction Y, the spacing between adjacent filling active layers 113 is 58 nanometers, and the spacing between adjacent filling gate layers 114 is 58 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 58 nanometers, and the spacing between adjacent filling gate layers 114 is 58 nanometers.

[0168] In the filling sub-area 108b, along the first direction Y, the spacing between adjacent filling active layers 113 is 60 nanometers, and the spacing between adjacent filling gate layers 114 is 60 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 60 nanometers, and the spacing between adjacent filling gate layers 114 is 60 nanometers.

[0169] In the filling sub-area 109b, along the first direction Y, the spacing between adjacent filling active layers 113 is 62 nanometers, and the spacing between adjacent filling gate layers 114 is 62 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 56 nanometers, and the spacing between adjacent filling gate layers 114 is 62 nanometers.

[0170] In the filling sub-area 110b, along the first direction Y, the spacing between adjacent filling active layers 113 is 64 nanometers, and the spacing between adjacent filling gate layers 114 is 64 nanometers. Along the second direction X, the spacing between adjacent filling active layers 113 is 64 nanometers, and the spacing between adjacent filling gate layers 114 is 64 nanometers.

[0171] In the filling sub-area 111b, along the first direction Y, the distance between adjacent filling active layers 113 is 68 nanometers, and the distance between adjacent filling gate layers 114 is 64 nanometers. Along the second direction X, the distance between adjacent filling active layers 113 is 54 nanometers, and the distance between adjacent filling gate layers 114 is 64 nanometers.

[0172] It should be noted that, along the direction perpendicular to the substrate surface, one or more film layers can be designed on each filling gate layer 114 in each filling sub-area, and between each filling active layer 113 and the filling gate layer 114, so that the highest height in each filling sub-area is equal to or close to the highest height in the semiconductor device 112. Taking the surface of the substrate 100 as a reference, the highest height is the maximum distance between the surface of the topmost film layer in the filling sub-area and the surface of the substrate 100, and the maximum distance between the surface of the topmost film layer in the semiconductor device 112 and the surface of the substrate 100. This has the following beneficial effects: it can make the correspondence between the pattern density and the characteristics of the semiconductor device more accurate, and further reduce the characteristic differences between the semiconductor devices of the integrated circuit.

[0173] It should be noted that the size of the semiconductor device 112 , the size, shape, thickness, etc. of the filled active layer 113 and the filled gate layer 114 can be designed according to actual needs and are not intended to limit this application.

[0174] refer to Figure 5 , combined with Figure 8 The semiconductor pattern density optimization structure and the optimized sub-area further include: an N-type well layer 200 , a P-type well layer 201 , an NLDD layer 202 , a PLDD layer 203 , an N-type source and drain doping layer 204 and a P-type source and drain doping layer 205 .

[0175] The N-type well layer 200 is used to test the resistance of the N-type well layer 200 when filling sub-regions with different pattern densities.

[0176] The P-type well layer 201 is used to test the resistance of the P-type well layer 201 when filling sub-regions with different pattern densities.

[0177] The NLDD layer 202 is used to test the resistance of the NLDD layer 202 when filling sub-regions with different pattern densities.

[0178] The PLDD layer 203 is used to test the resistance of the PLDD layer 203 when filling sub-areas with different pattern densities.

[0179] The N-type source / drain doped layer 204 is used to test the resistance of the N-type source / drain doped layer 204 when filling sub-regions with different pattern densities.

[0180] The P-type source-drain doped layer 205 is used to test the resistance of the P-type source-drain doped layer 205 when each filling sub-region has different pattern densities.

[0181] In this embodiment, the N-type well layer 200 , the P-type well layer 201 , the NLDD layer 202 , the PLDD layer 203 , the N-type source / drain doping layer 204 and the P-type source / drain doping layer 205 have the same manufacturing process and process parameters as the integrated circuit semiconductor device in the semiconductor device region 102 .

[0182] In this embodiment, the number of N-type well layers 200, P-type well layers 201, NLDD layers 202, PLDD layers 203, N-type source and drain doping layers 204, and P-type source and drain doping layers 205 in each optimized sub-area is one. That is, the number of N-type well layers 200, P-type well layers 201, NLDD layers 202, PLDD layers 203, N-type source and drain doping layers 204, and P-type source and drain doping layers 205 in the optimized sub-area 103a is one. The number of N-type well layers 200, P-type well layers 201, NLDD layers 202, PLDD layers 203, N-type source and drain doping layers 204, and P-type source and drain doping layers 205 in the optimized sub-area 104a to the optimized sub-area 111a can be designed according to the number of corresponding layers in the optimized sub-area 103a.

[0183] The N-type well layer 200 , the P-type well layer 201 , the NLDD layer 202 , the PLDD layer 203 , the N-type source / drain doping layer 204 and the P-type source / drain doping layer 205 are of the same shape and size, and the spacing between adjacent layers is equal.

[0184] In this embodiment, the N-type well layer 200, the P-type well layer 201, the NLDD layer 202, the PLDD layer 203, the N-type source and drain doping layer 204, and the P-type source and drain doping layer 205 in the optimized sub-region 103a are all rectangular in shape, and the sizes of the rectangles are equal, and the spacing between adjacent layers in the optimized sub-region 103a is equal, that is, the spacing between the N-type well layer 200 and the P-type well layer 201 is equal to the spacing between the P-type well layer 201 and the NLDD layer 202, the spacing between the P-type well layer 201 and the NLDD layer 202 is equal to the spacing between the NLDD layer 202 and the PLDD layer 203, and the spacing between the NLDD layer 202 and the PLDD layer 203 is equal. The spacing between the PLDD layers 203 is equal to the spacing between the PLDD layer 203 and the N-type source-drain doped layer 204, and the spacing between the PLDD layer 203 and the N-type source-drain doped layer 204 is equal to the spacing between the N-type source-drain doped layer 204 and the P-type source-drain doped layer 205. The shapes, sizes, and spacings between adjacent layers of the N-type well layer 200, P-type well layer 201, NLDD layer 202, PLDD layer 203, N-type source-drain doped layer 204, and P-type source-drain doped layer 205 in the optimized sub-area 104a to the optimized sub-area 111a are designed according to the shapes, sizes, and spacings between adjacent layers of the corresponding layers in the optimized sub-area 103a.

[0185] The N-type well layer 200 , the P-type well layer 201 , the NLDD layer 202 , the PLDD layer 203 , the N-type source / drain doping layer 204 , and the P-type source / drain doping layer all extend along the first direction Y.

[0186] In this embodiment, the N-type well layer 200 in the optimized sub-region 103a extends along the first direction Y, the P-type well layer 201 extends along the first direction Y, the NLDD layer 202 extends along the first direction Y, the PLDD layer 203 extends along the first direction Y, the N-type source and drain doping layer 204 extends along the first direction Y, and the P-type source and drain doping layer 205 extends along the first direction Y. That is, the N-type well layer 200, the P-type well layer 201, the NLDD layer 202, the PLDD layer 203, the N-type source and drain doping layer 204 and the P-type source and drain doping layer 205 in the optimized sub-region 103a all extend in their respective longitudinal directions; the extension directions of the N-type well layer 200, the P-type well layer 201, the NLDD layer 202, the PLDD layer 203, the N-type source and drain doping layer 204 and the P-type source and drain doping layer 205 from the optimized sub-region 104a to the optimized sub-region 111a are all designed according to the extension directions of the corresponding layers in the optimized sub-region 103a.

[0187] In this embodiment, the extension directions of the N-type well layer 200 , the P-type well layer 201 , the NLDD layer 202 , the PLDD layer 203 , the N-type source / drain doping layer 204 and the P-type source / drain doping layer 205 are consistent with the extension directions of the corresponding layers in the integrated circuit semiconductor device.

[0188] In this embodiment, surfaces of the NLDD layer 202 , the PLDD layer 203 , the N-type source / drain doped layer 204 , and the P-type source / drain doped layer 205 are all covered with metal silicide.

[0189] The material of the metal silicide includes one or more of nickel silicide (NiSi), titanium silicide (TiSi) and cobalt silicide (CoSi). In this embodiment, the material of the metal silicide is nickel silicide (NiSi).

[0190] It should be noted that the surfaces of the NLDD layer 202, the PLDD layer 203, the N-type source and drain doped layer 204 and the P-type source and drain doped layer 205 are all covered with metal silicide, which is formed using the same process as the corresponding layers in the integrated circuit semiconductor device are covered with metal silicide, so as to improve the accuracy of the resistance test of each layer.

[0191] refer to Figure 5 and Figure 8 The semiconductor pattern density optimization structure includes: a gate terminal 300 connected to the device gate layer; a source terminal 301 connected to the source doped layer 112a; a drain terminal 302 connected to the drain doped layer 112b; an N-type well first terminal 200a connected to one end of the N-type well layer 200, an N-type well second terminal 200b connected to the other end of the N-type well layer 200; a P-type well first terminal 201a connected to one end of the P-type well layer 201, a P-type well second terminal 201b connected to the other end of the P-type well layer 201; an NLDD first terminal 202a connected to the NLDD layer 202 One end is connected, the NLDD second terminal 202b is connected to the other end of the NLDD layer 202; the PLDD first terminal 203a is connected to one end of the PLDD layer 203, and the PLDD second terminal 203b is connected to the other end of the PLDD layer 203; the N-type doped first terminal 204a is connected to one end of the N-type source and drain doped layer 204, and the N-type doped second terminal 204b is connected to the other end of the N-type source and drain doped layer 204; the P-type doped first terminal 205a is connected to one end of the P-type source and drain doped layer 205, and the P-type doped second terminal 205b is connected to the other end of the P-type source and drain doped layer 205.

[0192] In this embodiment, in the optimized sub-region 103a, the gate terminal 300 is electrically connected to the gate layer; the source terminal 301 is electrically connected to the source doped layer 112a; the drain terminal 302 is electrically connected to the drain doped layer 112b; the N-type well first terminal 200a is electrically connected to one end of the N-type well layer 200, and the N-type well second terminal 200b is electrically connected to the other end of the N-type well layer 200; the P-type well first terminal 201a is electrically connected to one end of the P-type well layer 201, and the P-type well second terminal 201b is electrically connected to the other end of the P-type well layer 201; the NLDD first terminal 202a is electrically connected to one end of the NLDD layer 202 The NLDD second terminal 202b is electrically connected to the other end of the NLDD layer 202; the PLDD first terminal 203a is electrically connected to one end of the PLDD layer 203, and the PLDD second terminal 203b is electrically connected to the other end of the PLDD layer 203; the N-type doped first terminal 204a is electrically connected to one end of the N-type source-drain doped layer 204, and the N-type doped second terminal 204b is electrically connected to the other end of the N-type source-drain doped layer 204; the P-type doped first terminal 205a is electrically connected to one end of the P-type source-drain doped layer 205, and the P-type doped second terminal 205b is electrically connected to the other end of the P-type source-drain doped layer 205.

[0193] The material of each terminal in the optimized sub-region 103a includes: one or more combinations of copper, aluminum, tungsten, titanium, and indium tin oxide. In this embodiment, the material of each terminal in the optimized sub-region 103a is copper.

[0194] In some embodiments, each terminal in the optimized sub-area 103a is electrically connected to each corresponding layer through a via (not shown). In other embodiments, each terminal in the optimized sub-area 103a is directly electrically connected to each corresponding layer.

[0195] In this embodiment, the shape, size and thickness of each terminal in the optimized sub-area 103a are the same.

[0196] It should be noted that the gate terminal 300, source terminal 301, drain terminal 302, N-type well first terminal 200a, N-type well second terminal 200b, P-type well first terminal 201a, P-type well second terminal 201b, NLDD first terminal 202a, NLDD second terminal 202b, PLDD first terminal 203a, PLDD second terminal 203b, N-type doped first terminal 204a, N-type doped second terminal 204b, P-type doped first terminal 205a, and P-type doped second terminal 205b within the optimized sub-region 104a to the optimized sub-region 111a can all be designed according to the corresponding terminals of the optimized sub-region 103a.

[0197] It should be noted that the optimized sub-areas in each test area all adopt the same design, that is, the corresponding structures in the optimized sub-areas 103a to 111a are all the same.

[0198] It should be noted that along the first direction Y means parallel to the first direction Y, and along the second direction X means parallel to the second direction X. The first direction Y is the column direction, and the second direction X is the row direction, which is not intended to limit the present application.

[0199] It should be noted that semiconductor devices 112 of different sizes can also be set in the optimized sub-area, for example, semiconductor devices 112 with semiconductor channel width-to-length ratios of 10 / 10, 10 / 0.06, 0.12 / 10, and 0.12 / 0.06, so as to test the characteristics of semiconductor devices 112 with different semiconductor channel width-to-length ratios at different densities, and the units of the width and length of the semiconductor channel are both nanometers.

[0200] It should be noted that the optimized sub-area 104a to the optimized sub-area 111a and Figure 8 The optimized sub-area 103a in FIG. 1 adopts the same design.

[0201] In order to better understand the present application, the present application provides a method for optimizing semiconductor pattern density, which is applied to any of the aforementioned semiconductor pattern density optimization structures.

[0202] Figure 9 It is a flow chart of a method for optimizing semiconductor pattern density according to an embodiment of the present application.

[0203] The semiconductor pattern density optimization method includes: calculating the pattern density of each filled sub-area, wherein the pattern density includes: the pattern density of the filled active layer and / or the pattern density of the filled gate layer; testing the semiconductor device characteristics of each optimized sub-area, and obtaining the corresponding relationship between the semiconductor device characteristics of each test area and the pattern density, so as to establish a semiconductor device characteristic pattern density query table.

[0204] By adopting the above-mentioned semiconductor pattern density optimization method, by independently setting the pattern density of the filling active layer and the filling gate layer between each filling sub-area, the characteristics of the semiconductor device in each optimized sub-area are tested, and the correspondence between the pattern density of the filling active layer and the filling gate layer and the semiconductor device characteristics is obtained, so as to reduce the characteristic differences between the semiconductor devices of the integrated circuit.

[0205] The method for optimizing semiconductor pattern density mainly comprises the following steps:

[0206] Step S11: Calculating the pattern density of each filling sub-area, wherein the pattern density includes: the pattern density of the filling active layer and / or the pattern density of the filling gate layer.

[0207] In this embodiment, the pattern density of the filled active layer 113 and the pattern density of the filled gate layer 114 in the test area 103 to the test area 111 are calculated respectively.

[0208] Regarding the calculation method of the pattern density of the filled active layer 113 and the pattern density of the filled gate layer 114, reference may be made to the calculation method of the pattern density of the filled active layer 113 and the pattern density of the filled gate layer 114 in the aforementioned semiconductor pattern density optimization structure, which will not be repeated here.

[0209] In this embodiment, in the calculation of the graphic density of the filled active layer 113 and the graphic density of the filled gate layer 114, the area of ​​the filled active layer 113 and the filled gate layer 114 can be the area after the filled active layer 113 and the filled gate layer 114 are etched on the semiconductor device layout, or it can be the area of ​​the filled active layer 113 and the filled gate layer 114 after the actual process etching on the substrate 100. The calculation method can be selected according to actual needs, and this does not limit the present application.

[0210] Step S12: testing the semiconductor device characteristics of each optimized sub-area, obtaining the corresponding relationship between the semiconductor device characteristics of each test area and the pattern density, and establishing a semiconductor device characteristic pattern density lookup table.

[0211] The characteristics of the semiconductor device 112 in each optimized sub-area are tested by a semiconductor parameter analyzer and a probe station. In this embodiment, the on-state current Ion and the leakage current Ioff of the semiconductor device 112 are tested by a semiconductor parameter analyzer, but this is not intended to limit the present application.

[0212] In this embodiment, the on-state current Ion of the semiconductor device 112 in the optimized sub-region 103a is I11 and the leakage current Ioff is I21, the on-state current Ion of the semiconductor device 112 in the optimized sub-region 104a is I12 and the leakage current Ioff is I22, the on-state current Ion of the semiconductor device 112 in the optimized sub-region 105a is I13 and the leakage current Ioff is I23, the on-state current Ion of the semiconductor device 112 in the optimized sub-region 106a is I14 and the leakage current Ioff is I24, and the semiconductor device 112 in the optimized sub-region 107a is I15. 12 The on-state current Ion is I15 and the leakage current Ioff is I25, the on-state current of the semiconductor device 112 in the optimized sub-area 108a is I16 and the leakage current Ioff is I26, the on-state current Ion of the semiconductor device 112 in the optimized sub-area 109a is I17 and the leakage current Ioff is I27, the on-state current Ion of the semiconductor device 112 in the optimized sub-area 110a is I18 and the leakage current Ioff is I28, and the on-state current Ion of the semiconductor device 112 in the optimized sub-area 111a is I19 and the leakage current Ioff is I29.

[0213] According to the pattern density of the filled active layer 113, the pattern density of the filled gate layer 114 and the on-state current Ion and leakage current Ioff of the semiconductor device 112 in each filled sub-area in step S11, a characteristic pattern density query table of the semiconductor device 112 is established, as shown in Table 1.0.

[0214]

[0215] Wherein, M represents the pattern density of the active layer, N represents the pattern density of the gate layer, Ion represents the on-state current (unit: microampere), and Ion represents the leakage current (unit: microampere).

[0216] Step S13: testing the resistance of the N-type well layer, P-type well layer, NLDD layer, PLDD layer, N-type source and drain doped layer and P-type source and drain doped layer in each optimized sub-area, and obtaining the relationship between the resistance of each layer in each test area and the pattern density to establish a resistance pattern density lookup table for each layer.

[0217] The resistance of the N-type well layer 200, P-type well layer 201, NLDD layer 202, PLDD layer 203, N-type source and drain doped layer 204 and P-type source and drain doped layer 205 in each optimized sub-area is tested using a resistance tester (such as a multimeter or a four-probe tester).

[0218] According to the pattern density of the filled active layer 113 and the pattern density of the filled gate layer 114 in each filled sub-area in step S11 and the resistance of each film layer in each optimized sub-area, a lookup table of the pattern density of each layer resistance is established, as shown in Table 2.0.

[0219]

[0220] Among them, R1 represents the N-type well layer resistance, R2 represents the P-type well layer resistance, R3 represents the NLDD layer resistance, R4 represents the PLDD layer resistance, R5 represents the N-type source and drain doping layer resistance, and R6 represents the P-type source and drain doping layer resistance.

[0221] It should be noted that, for example, when designing the characteristics of integrated circuit semiconductor devices, the blank area outside the semiconductor device region 102 on the substrate can be set with a graphic density corresponding to the on-state current and leakage current of the integrated circuit semiconductor device according to the above-mentioned Tables 1.0 and 2.0, so as to reduce the characteristic differences between the integrated circuit semiconductor devices in the semiconductor device region 102.

[0222] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to make possible changes, modifications and combinations of the technical solutions of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor pattern density optimization structure, characterized in that: include: A substrate, comprising: a plurality of optimized regions; Each optimization area includes a plurality of test areas, and each test area includes an optimization sub-area and a filling sub-area surrounding the optimization sub-area; The optimized sub-region includes: a semiconductor device, wherein the semiconductor device includes: at least one device active layer and at least one device gate layer located on the device active layer; The filling sub-area includes: a plurality of filling active layers that are identical to the device active layers and arranged in an array, and a plurality of filling gate layers that are identical to the device gate layers and arranged in an array, and each row of the filling active layers is covered with at least one filling gate layer; The pattern densities of the filling active layer and the filling gate layer of each filling sub-region are independently set, and the pattern density ratio of the filling active layer and the filling gate layer remains unchanged; The pattern densities of the filled active layers in different filled sub-regions are different from each other, or the pattern densities of the filled gate layers in different filled sub-regions are different from each other.

2. The semiconductor pattern density optimization structure according to claim 1, wherein: The number of the device active layer and the device gate layer includes any one of the following: When the number of the device active layer and the number of the device gate layer are both one, the device active layer extends along a first direction, and the device gate layer extends along a second direction to cover the device active layer, and the first direction and the second direction are perpendicular to each other; The number of the device active layers is greater than or equal to 2, each device active layer is covered with a corresponding device gate layer, the device active layers extend along the first direction and are arranged along the second direction, and each device gate layer extends along the second direction and is arranged along the second direction.

3. The semiconductor pattern density optimization structure according to claim 2, wherein: Each of the plurality of filled active layers arranged in the array extends along a first direction, and the spacing between each filled active layer along the first direction is equal, and the spacing between the filled active layers along the second direction is equal to the spacing between adjacent device active layers in the second direction; Each of the plurality of filled gate layers arranged in the array extends along the second direction, and each filled gate layer has equal spacing along the first direction and the same spacing along the second direction as the spacing of adjacent device gate layers in the second direction.

4. The semiconductor pattern density optimization structure according to claim 1, wherein: The device active layer and the filling active layer have the same shape and size, and the device gate layer and the filling gate layer have the same shape and size; The area of ​​each optimized region is equal, the area of ​​each test region is equal, the area of ​​each filling sub-region is equal, and the area of ​​each optimized sub-region is equal.

5. The semiconductor pattern density optimization structure according to claim 1, wherein: The optimized sub-area further includes: an N-type well layer, a P-type well layer, an NLDD layer, a PLDD layer, an N-type source and drain doping layer, and a P-type source and drain doping layer; The N-type well layer, the P-type well layer, the NLDD layer, the PLDD layer, the N-type source-drain doped layer and the P-type source-drain doped layer all extend along a first direction; The N-type well layer, the P-type well layer, the NLDD layer, the PLDD layer, the N-type source / drain doping layer and the P-type source / drain doping layer have the same shape and size, and the spacing between adjacent layers is equal.

6. The semiconductor pattern density optimization structure according to claim 1, wherein: The types of the semiconductor devices include: P-type transistors and / or N-type transistors.

7. The semiconductor pattern density optimization structure according to claim 5, wherein: The surfaces of the NLDD layer, the PLDD layer, the N-type source-drain doped layer and the P-type source-drain doped layer are all covered with metal silicide.

8. The semiconductor pattern density optimization structure according to claim 5, wherein: The active layer at least includes: a channel layer, a source doping layer, a source doping extension region, a drain doping layer and a drain doping extension region; The semiconductor device comprises: a source doping layer and a drain doping layer; The semiconductor pattern density optimization structure comprises: a gate terminal connected to the device gate layer; a source terminal connected to the source doping layer; a drain terminal connected to the drain doping layer; An N-type well first terminal is connected to one end of the N-type well layer, and an N-type well second terminal is connected to the other end of the N-type well layer; A P-type well first terminal is connected to one end of the P-type well layer, and a P-type well second terminal is connected to the other end of the P-type well layer; An NLDD first terminal is connected to one end of the NLDD layer, and an NLDD second terminal is connected to the other end of the NLDD layer; A PLDD first terminal is connected to one end of the PLDD layer, and a PLDD second terminal is connected to the other end of the PLDD layer; An N-type doped first terminal is connected to one end of the N-type source-drain doped layer, and an N-type doped second terminal is connected to the other end of the N-type source-drain doped layer; The P-type doped first terminal is connected to one end of the P-type source-drain doped layer, and the P-type doped second terminal is connected to the other end of the P-type source-drain doped layer.

9. A method for optimizing semiconductor pattern density, characterized in that: The semiconductor pattern density optimization structure according to any one of claims 1 to 8 comprises: Calculating the pattern density of each filling sub-area, wherein the pattern density includes: the pattern density of the filling active layer and / or the pattern density of the filling gate layer; The semiconductor device characteristics of each optimized sub-area are tested to obtain a corresponding relationship between the semiconductor device characteristics of each test area and the pattern density, so as to establish a semiconductor device characteristic pattern density lookup table.

10. The optimization method according to claim 9, wherein: Also includes: The resistance of the N-type well layer, P-type well layer, NLDD layer, PLDD layer, N-type source and drain doped layer and P-type source and drain doped layer in each optimized sub-area is tested, and the relationship between the resistance of each layer in each test area and the pattern density is obtained to establish a resistance pattern density lookup table for each layer.

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