Image sensor and method of manufacturing the same, electronic device
By utilizing the difference in etching rate between the sacrificial layer and the device wafer, and through a polishing process, a wavy light-trapping layer is formed, which solves the problems of high manufacturing cost and low light absorption efficiency of traditional BSI image sensors, achieving more efficient light capture and lower power consumption.
Patent Information
- Application Number
- CN202511173598.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-21
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2045-08-21
AI Technical Summary
Traditional BSI image sensors face limitations in performance improvement during the back-end manufacturing process due to their low full-well limit, limited light absorption efficiency, and high manufacturing cost of light-trapping structures.
By utilizing the difference in etching rates between the sacrificial layer and the device wafer, and combining it with a polishing process to form a light-trapping layer, the light-trapping layer is formed, avoiding additional photomasks and photolithography processes. This integrates thinning and light-trapping layer fabrication, forming a wavy light-trapping layer to increase the full-well capacity of the photodiode.
This reduces the fabrication cost of light-trapping structures, improves light absorption efficiency, simplifies the process, reduces interface damage, and enhances the imaging performance and signal-to-noise ratio of image sensors.
Smart Images
Figure CN120659404B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to an image sensor, a preparation method thereof, and an electronic device. BACKGROUND
[0002] An image sensor is a photoelectric conversion device widely used in many fields such as consumer electronics, security monitoring, automotive electronics, and machine vision. A backside illuminated (BSI) image sensor has higher sensitivity, better wiring layout, and allows high-speed recording, and is often used in fields with high requirements for image sensor pixel performance.
[0003] However, in the conventional BSI back-end-of-line process, the silicon substrate is thinned by combining a grinding and wet etching process, and then a metal grid process is performed, which results in a low full-well capacity, limited light absorption efficiency, and a separate light trapping structure mask, thereby hindering further improvement of the performance of the BSI image sensor. SUMMARY
[0004] Therefore, it is necessary to provide an image sensor, a preparation method thereof, and an electronic device, which can at least reduce the preparation cost of the light trapping structure, in view of the technical problems in the prior art.
[0005] In a first aspect, the present application provides a preparation method of an image sensor, comprising:
[0006] providing a device wafer, the device wafer comprising grooves extending into the device wafer via a first surface of the device wafer and spaced apart along a first direction parallel to the first surface;
[0007] forming a sacrificial layer and an isolation structure arranged in sequence in a direction away from the device wafer, which fill the grooves;
[0008] forming a photodiode between adjacent isolation structures along the first direction, and bonding the first surface to a bonding surface of a carrier wafer, the device wafer comprising a second surface facing away from each other at the first surface;
[0009] etching and removing part of the device wafer via the second surface to obtain an initial groove between adjacent sacrificial layers;
[0010] simultaneously etching and removing the sacrificial layer and part of the device wafer at the bottom of the initial groove in the same process step to form a target groove;
[0011] forming a light trapping layer filling at least the target groove and having a wavy bottom surface.
[0012] In the preparation method of the above embodiment, the device wafer is formed with photodiodes and isolation structures arranged alternately along the first direction, and the isolation structures are provided with a sacrificial layer on the side away from the first surface. After the bonding and flipping, the sacrificial layer is used to thin the device wafer while forming a plurality of target grooves between adjacent isolation structures. After the target grooves are filled, the preparation of the light-trapping layer is completed. In this preparation method, the position and shape of the light-trapping layer are defined by the sacrificial layer formed in the device wafer, which can avoid the use of extra masks and photolithography processes in the preparation of the light-trapping structure, thereby reducing the preparation cost. Thinning the device wafer and preparing the light-trapping layer at the same time can improve the integration of the process and reduce the processing difficulty.
[0013] In addition, the formed light-trapping layer can increase the full well capacity of the photodiode and improve the light absorption efficiency.
[0014] In some embodiments, the sacrificial layer includes a first sacrificial layer and a second sacrificial layer stacked along the direction away from the device wafer.
[0015] The sacrificial layer and the isolation structure are formed in the direction away from the device wafer in sequence, including:
[0016] Performing an ion implantation process on the device wafer at the bottom of the trench to form the first sacrificial layer.
[0017] Forming a second sacrificial layer and an isolation structure in the trench in the direction away from the device wafer in sequence.
[0018] In some embodiments, forming the second sacrificial layer and the isolation structure includes:
[0019] Using a deposition process to form a sacrificial material layer covering the top surface of the first sacrificial layer and the first surface.
[0020] Forming an isolation material layer that at least fills the trench; wherein the isolation material layer covers the top surface of the sacrificial material layer.
[0021] Removing part of the sacrificial material layer and the isolation material layer above the first surface, and the remaining sacrificial material layer is used to constitute the second sacrificial layer, and the isolation material layer is used to constitute the isolation structure.
[0022] In some embodiments, forming the initial groove includes:
[0023] Using a first grinding process to remove part of the device wafer above the first sacrificial layer.
[0024] Using a first etching solution to etch the device wafer between adjacent first sacrificial layers to obtain an initial groove with a bottom surface lower than the first sacrificial layer and higher than the bottom surface of the second sacrificial layer.
[0025] In some embodiments, forming the target groove includes:
[0026] The first sacrificial layer is removed by a second grinding process;
[0027] The second sacrificial layer and the device wafer between the adjacent second sacrificial layers are etched synchronously by using a second etching solution.
[0028] In some embodiments, a plurality of metal gratings are formed on the top surface of the light-trapping layer and are arranged in the first direction at intervals; the plurality of metal gratings are located directly above the plurality of isolation structures.
[0029] In some embodiments, before the first surface is bonded to the bonding surface of the carrier wafer, the method further comprises:
[0030] After the circuit layer is formed on the first surface, an isolation layer is formed to cover the circuit layer; the isolation layer comprises a first surface corresponding to the first surface of the device wafer.
[0031] The first surface of the isolation layer is bonded to the bonding surface of the carrier wafer.
[0032] In a second aspect, the present application also provides an image sensor prepared by the preparation method of any one of the above embodiments, and the image sensor further comprises:
[0033] The device wafer, the light-trapping layer, and the metal gratings and the insulating layers arranged alternately in parallel to the first direction on the top surface of the light-trapping layer;
[0034] The device wafer comprises the photodiodes and the isolation structures extending into the device wafer through the top surface of the device wafer and arranged alternately in the first direction; the isolation structures are located directly below the metal gratings arranged one-to-one.
[0035] The light-trapping layer extends to the photodiodes in a direction towards the device wafer; the contact surfaces of the light-trapping layer, the insulating layers, and the photodiodes are wavy; and the top surface of the light-trapping layer is lower than the bottom surface of the metal gratings.
[0036] In the above embodiments, the wavy interface of the light-trapping layer effectively reduces the risk of light escape, improves the light absorption efficiency, and enables the image sensor to maintain high signal-to-noise ratio imaging in a weak light environment; the isolation structures and the photodiodes arranged alternately can suppress the crosstalk between adjacent pixels. The above structures work together to lay a foundation for the image sensor to achieve better imaging, lower power consumption, and more compact design.
[0037] In some embodiments, the image sensor further comprises: a carrier wafer, and the isolation layer and the circuit layer arranged in sequence on the top surface of the carrier wafer and in a direction away from the carrier wafer.
[0038] In a third aspect, the present application provides an electronic device comprising the image sensor prepared by the preparation method of any one of the above embodiments, or the image sensor of any one of the above embodiments. Since the electronic device of the above embodiments and the image sensor and the preparation method thereof provided by the present application are based on the same inventive concept, the electronic device has all the advantages of the image sensor and the preparation method thereof provided by the present application, and thus repeated description is omitted here.
[0039] The image sensor and the preparation method thereof, and the electronic device provided by the present application have the following unexpected technical effects:
[0040] The preparation method provided by the present application uses the pre-prepared sacrificial layer for positioning, forms the light trapping layer by using the difference in etching rate between the sacrificial layer and the device wafer and the different film grinding selectivity, does not need an additional photolithography step, effectively reduces the risk of multi-mask alignment deviation, greatly simplifies the process flow, and compared with the traditional separate process of step-by-step thinning and structure etching, the method integrates the device wafer thinning and the light trapping layer morphology shaping together, reduces the interface damage and improves the yield.
[0041] In addition, the light trapping layer and the wavy contact surface of the photodiode naturally form a refractive index transition structure, which can significantly increase the light absorption rate compared with the flat stacking design, and effectively improve the performance of the electronic device based on the preparation method and structure in the dynamic range expansion and extreme light environment. BRIEF DESCRIPTION OF DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0043] Figure 1 A flowchart of the preparation method of the image sensor provided in an embodiment;
[0044] Figure 2 A cross-sectional schematic view of the structure obtained after the step S102 of forming a groove in the preparation method provided in an embodiment;
[0045] Figure 3a A cross-sectional schematic view of the structure obtained after the step S301 of forming a first sacrificial layer in the preparation method provided in an embodiment;
[0046] Figure 3b A cross-sectional schematic view of the structure obtained after the step S302 of forming a sacrificial material layer and an isolation material layer in the preparation method provided in an embodiment;
[0047] Figure 3cA cross-sectional view of the structure obtained after forming the sacrificial layer and the isolation structure in step S303 of the preparation method provided in an embodiment;
[0048] Figure 4 A cross-sectional view of the structure obtained after bonding with the carrier wafer in step S106 of the preparation method provided in an embodiment;
[0049] Figure 5a A cross-sectional view of the structure obtained after performing the first polishing process in step S501 of the preparation method provided in an embodiment;
[0050] Figure 5b A cross-sectional view of the structure obtained after forming the initial groove in step S502 of the preparation method provided in an embodiment;
[0051] Figure 6a A cross-sectional view of the structure obtained after performing the second polishing process in step S601 of the preparation method provided in an embodiment;
[0052] Figure 6b A cross-sectional view of the structure obtained after forming the target groove in step S602 of the preparation method provided in an embodiment;
[0053] Figure 7 A cross-sectional view of the structure obtained after forming the light-trapping layer in step S112 of the preparation method provided in an embodiment;
[0054] Figure 8 A cross-sectional view of the structure obtained after forming the metal grid and the insulating layer in step S113 of the preparation method provided in an embodiment. Figure 7
[0055] Legend of reference signs:
[0056] 10, device wafer; 11, circuit layer; 12, isolation layer; 20, trench; 21, sacrificial layer; 211, first sacrificial layer; 212, second sacrificial layer; 22, isolation structure; 30, carrier wafer; 401, initial groove; 40, target groove; 50, light-trapping layer; 60, insulating layer; 70, metal grid; 71, first grid layer; 72, second grid layer; 73, third grid layer. DETAILED DESCRIPTION
[0057] In order to facilitate the understanding of the present application, a more comprehensive description will be made below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.
[0059] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type, and, similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.
[0060] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the included spatial description terminology is interpreted accordingly.
[0061] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" as used herein is intended to mean that the composition or method "comprises" the recited features, integers, steps, operations, elements, or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0062] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.
[0063] Referring now to the drawings, wherein like reference numerals refer to similar Figure 1 The present application provides a method for manufacturing an image sensor, comprising: steps S102-S112.
[0064] It should be understood that, although Figure 1 The steps in the flowchart of FIG. 1 are not necessarily performed in the order indicated by the arrows. Unless specifically stated, the order of performance of the steps can be modified, and the steps can be performed in an order other than that depicted in the figure. Also, Figure 1 At least some of the steps in the flowchart of FIG. 1 can include multiple steps or stages, which can be performed in different orders, at different times, or in an overlapping manner. Also,
[0065] The steps described above are described in detail with reference to the accompanying drawings:
[0066] Referring now to the drawings, wherein like reference numerals refer to similar Figure 2 Step S102: A device wafer 10 is provided, the device wafer 10 including trenches 20 extending into the device wafer 10 via a first surface 10a of the device wafer 10 and spaced apart along a first direction parallel to the first surface 10a.
[0067] For example, the device wafer 10 comprises a bulk semiconductor substrate. Other semiconductor materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc. can also be used. The semiconductor material can be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. or other types of substrates, as long as the semiconductor material is suitable for the process requirements or is easy to integrate. In this embodiment, the substrate is a silicon substrate.
[0068] For example, the first surface 10a of the device wafer 10 is coated with photoresist. After exposure based on a predetermined mask and development, a deep trench is formed by etching, denoted as trench 20.
[0069] Step S104: forming a sacrificial layer 21 and an isolation structure 22 arranged in sequence in a direction away from the device wafer 10, which fill the trench 20.
[0070] Further, please refer to Figure 3a , Figure 3b and Figure 3c In some embodiments, step S104 further comprises:
[0071] Please refer to Figure 3a Step S301: performing an ion implantation process on the device wafer 10 at the bottom of the trench 20 to form a first sacrificial layer 211.
[0072] Specifically, the first sacrificial layer 211 has the same conductivity type as the device wafer 10 but different doping concentration.
[0073] Please refer to Figure 3b Step S302: forming a sacrificial material layer and an isolation material layer stacked in sequence in a direction away from the device wafer 10 within the trench 20.
[0074] In an alternative embodiment, the sacrificial material layer covering the top surface of the first sacrificial layer 211 and the first surface 10a is formed by a deposition process.
[0075] The isolation material layer is formed to fill at least the trench 20; wherein the isolation material layer covers the top surface of the sacrificial material layer.
[0076] Please refer to Figure 3c Step S303: removing part of the sacrificial material layer and the isolation material layer above the first surface 10a, and the remaining sacrificial material layer is used to form a second sacrificial layer 212, and the isolation material layer is used to form an isolation structure 22.
[0077] For example, the deposition process can include one or more of a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a high density plasma (HDP) process, a plasma enhanced deposition process, a spin-on dielectric (SOD) process, etc. A portion of the sacrificial material layer and the isolation material layer can be removed using a chemical mechanical polishing (CMP) process.
[0078] The second sacrificial layer 212 includes silicon nitride, and together with the first sacrificial layer 211 forms a sacrificial layer 21 as shown in Figure 3c for defining the position and shape of the light trapping layer in subsequent processes.
[0079] The isolation structure 22 includes an insulating material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or a combination thereof, for isolating adjacent photodiodes and reducing the risk of optical / electrical cross-talk in adjacent pixel regions.
[0080] In the above embodiments, the sacrificial layer 21 and the isolation structure 22, which have different functions, are formed based on the same trench 20, thereby avoiding the need to design and manufacture masks for different structures in conventional processes and reducing the number of masks used.
[0081] Referring to Figure 4 , at step S106, after forming the photodiodes between the adjacent isolation structures 22 in the first direction, the first surface 10a is bonded to the bonding surface of the carrier wafer 30, and the device wafer 10 includes a second surface 10b opposite the first surface 10a.
[0082] In an alternative embodiment, in an extension of step S106, before the first surface 10a is bonded to the bonding surface 30a of the carrier wafer 30, the method further includes:
[0083] After forming the circuit layer 11 on the first surface 10a, an isolation layer 12 is formed covering the circuit layer 11.
[0084] The first surface 12a of the isolation layer 12 is bonded to the bonding surface 30a of the carrier wafer 30.
[0085] For example, the photodiodes are formed between the adjacent isolation structures 22 using an ion implantation process.
[0086] For example, the device wafer 10 is flipped by a film rewinder so that the second surface 10b of the device wafer 10 faces upward and the first surface 10a faces downward. The photodiode process and the bonding process are well known to those skilled in the art, and thus are not described in detail.
[0087] The circuit layer 11 includes metal wires and dielectric material wrapping the metal wires.
[0088] The isolation layer 12 includes oxide such as SiO2, which is used for isolation and binding the binding section of the binding wafer 30.
[0089] Step S108: etching and removing part of the device wafer 10 via the second surface 10b to obtain the initial groove 401 between the adjacent sacrificial layers 21.
[0090] Further, referring to Figure 5a - Figure 5b In some embodiments, step S108 includes:
[0091] Referring to Figure 5a Step S501: removing part of the device wafer 10 above the first sacrificial layer 211 by a first grinding process.
[0092] The first grinding process is a grind process, which is used for preliminary flattening and thinning of the device wafer 10.
[0093] Referring to Figure 5b Step S502: etching the device wafer 10 between the adjacent first sacrificial layers 211 by a first etching solution to obtain the initial groove 401 between the bottom surface lower than the first sacrificial layer 211 and the bottom surface higher than the bottom surface of the second sacrificial layer 212.
[0094] The first etching solution includes hydrofluoric acid (HF), nitric acid (HNO3) and acetic acid (CH3COOH), denoted as HNA.
[0095] In the above embodiments, since the first sacrificial layer 211 is formed based on an ion implantation process, in the case where the material of the first sacrificial layer 211 and the device wafer 10 has different nitrogen doping concentrations, the first etching solution, i.e. the HNA (HF / HNO3 / CH3COOH) etching solution, is used for selective etching of silicon with different doping concentrations, which preferentially etches the device wafer 10 with higher doping concentration, avoiding additional masks or complex processes. Since the etching of silicon by HNA is isotropic, the inner surface of the initial groove 401 is smooth, effectively reducing stress concentration in subsequent processes.
[0096] Step S110: etching and removing part of the device wafer 10 at the bottom of the initial groove 401 at the same process step to form the target groove 40.
[0097] Further referring to Figure 6a - Figure 6b , step S110 further comprises:
[0098] Referring to Figure 6a , step S601: removing the first sacrificial layer 211 by a second grinding process.
[0099] The second grinding process is a silicon CMP process, which is used to remove the first sacrificial layer 211 selectively. At this time, the second sacrificial layer 212 can be used as a grinding stop layer to protect the initial groove 401 and other structures of the device wafer 10.
[0100] Referring to Figure 6b , step S602: synchronously etching the second sacrificial layer 212 and the device wafer 10 between adjacent second sacrificial layers by a second etching solution.
[0101] The second etching solution includes tetramethylammonium hydroxide (TMAH).
[0102] In the above embodiment, the first sacrificial layer is removed preferentially by using the selection ratio of the CMP process, and then the second sacrificial layer 212 (silicon nitride) and the device wafer 10 are synchronously etched by TMAH. This process does not need to switch equipment or process, which can simplify the process and reduce the cost, and effectively deepen the initial groove 401 to obtain the target groove 40.
[0103] Referring to Figure 7 , step S112: forming a light-trapping layer 50 which at least fills the target groove 40 and has a wavy bottom surface.
[0104] For example, the above structure can be formed by using any one of CVD process, plasma CVD process or molecular beam epitaxy (MBE) process.
[0105] The material of the light-trapping layer 50 includes high-K material such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).
[0106] In the above embodiment, the light-trapping layer 50 can effectively improve the light absorption efficiency without increasing the thickness of the device wafer 10, reduce the escape of photons, and improve the light capture capability, so that the image sensor based on the light-trapping layer 50 can generate more photo-generated carriers under the same light conditions.
[0107] It should be understood that, in order to facilitate the understanding of the present application, Figure 7The image sensor is an example prepared by the preparation method of the present application, and other suitable examples can also be prepared by the image sensor of the present application, which are not limited herein.
[0108] Please refer to Figure 8 In some embodiments, step S112 further includes:
[0109] The metal grating 70 and the insulating layer 60 are formed on the top surface of the light trapping layer 50.
[0110] The metal grating 70 includes the first grating layer 71, the second grating layer 72 and the third grating layer 73 arranged in sequence in the direction away from the device wafer 10.
[0111] The material of the first grating layer 71 can include but is not limited to one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3); the material of the second grating layer 72 can include but is not limited to cobalt (Co), nickel (Ni), titanium (Ti), aluminum (Al) and other metal materials; and the material of the third grating layer 73 can include titanium nitride (TiN).
[0112] The material of the insulating layer includes silicon oxide (SiO2).
[0113] Please continue to refer to Figure 8 The present application also provides an image sensor prepared by the preparation method of any one of the above embodiments, further comprising:
[0114] The device wafer 10, the light trapping layer 50, and the metal grating 70 and the insulating layer 60 arranged alternately in parallel to the first direction on the top surface of the light trapping layer 50;
[0115] The device wafer 10 includes the photodiode and the isolation structure 22 extending into the device wafer 10 through the top surface of the device wafer 10 and arranged alternately in the first direction; the isolation structure 22 is located directly below the metal grating 70 arranged one-to-one;
[0116] The light trapping layer 50 extends to the photodiode in the direction toward the device wafer 10; the contact surface of the light trapping layer 50 with the insulating layer 60 and the photodiode is wavy; and the top surface of the light trapping layer 50 is lower than the bottom surface of the metal grating.
[0117] In some embodiments, the image sensor further includes the carrier wafer 30, and the isolation layer 12 and the circuit layer 11 arranged in sequence on the top surface of the carrier wafer 30 in the direction away from the carrier wafer 30.
[0118] In the above embodiments, the photodiode is used for light sensing; the isolation structures are arranged alternately on both sides of the photodiode to form a lateral potential barrier, which is used for preventing optical / electrical crosstalk between pixels and improving signal-to-noise ratio; the light trapping layer is used for increasing light absorption, and the wavy contact surface helps to scatter light, prolong the light path, and improve the absorption efficiency.
[0119] In addition, the light trapping layer extends to the photodiode, and the wavy contact surface and the like design not only reduces the interface reflection loss, but also guides the light to focus precisely on the light sensing area, enhances the effective photon absorption, and improves the quantum efficiency.
[0120] In some embodiments, the present application also provides an electronic device comprising the image sensor prepared by the preparation method of any one of the above embodiments; or the image sensor of any one of the above embodiments.
[0121] In the above embodiments, thanks to the synergistically optimized process design, the process complexity of the electronic device based on the image sensor is effectively reduced, thereby accelerating the mass production process and compressing the research and development cycle. In addition, the light trapping layer with the wavy surface can greatly suppress the interface reflection loss, increase the capture efficiency of incident light, so that the image sensor can still accurately restore details in backlight or high-contrast scenes, while reducing edge artifacts and improving overall imaging uniformity.
[0122] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features of the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.
[0123] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.
Claims
1. A method for fabricating an image sensor, characterized in that, include: A device wafer is provided, the device wafer including trenches extending into the device wafer via a first surface and spaced apart along a first direction parallel to the first surface; A sacrificial layer and an isolation structure are formed to fill the trench and are arranged sequentially in a direction away from the device wafer; the sacrificial layer includes a first sacrificial layer and a second sacrificial layer stacked in a direction away from the device wafer; After forming a photodiode between adjacent isolation structures along the first direction, the first surface is bonded to the bonding surface of a carrier wafer, the device wafer including a second surface opposite to the first surface; A portion of the device wafer is removed by etching the second surface to obtain an initial groove located between adjacent first sacrificial layers; After removing the first sacrificial layer, the second sacrificial layer and a portion of the device wafer at the bottom of the initial groove are simultaneously etched away in the same process step to form the target groove; A light-trapping layer is formed that at least fills the target groove and has a wavy bottom surface.
2. The preparation method according to claim 1, characterized in that, A sacrificial layer and an isolation structure are formed sequentially along a direction away from the device wafer, including: An ion implantation process is performed on the device wafer at the bottom of the trench to form the first sacrificial layer; The second sacrificial layer and the isolation structure are formed sequentially in the trench along the direction away from the device wafer.
3. The preparation method according to claim 2, characterized in that, The formation of the second sacrificial layer and the isolation structure includes: A sacrificial material layer covering the top surface of the first sacrificial layer and the first surface is formed using a deposition process; An insulating material layer is formed that at least fills the trench; wherein the insulating material layer covers the top surface of the sacrificial material layer; The portion of the sacrificial material layer and the insulating material layer above the first surface is removed, and the remaining sacrificial material layer is used to form the second sacrificial layer, and the insulating material layer is used to form the insulating structure.
4. The preparation method according to claim 2, characterized in that, Forming the initial groove includes: The portion of the device wafer whose top surface is above the first sacrificial layer is removed using a first grinding process; Using a first etching solution, the device wafers between adjacent first sacrificial layers are etched to obtain an initial groove between the bottom surface of the first sacrificial layer and the bottom surface of the second sacrificial layer.
5. The preparation method according to claim 3, characterized in that, Forming the target groove includes: The first sacrificial layer is removed using a second grinding process; The second sacrificial layer and the device wafer between adjacent second sacrificial layers are simultaneously etched using a second etching solution.
6. The preparation method according to any one of claims 1-5, characterized in that, Also includes: A plurality of metal grilles are formed on the top surface of the light trapping layer and spaced apart along the first direction; the plurality of metal grilles are located directly above the plurality of isolation structures.
7. The preparation method according to any one of claims 1-5, characterized in that, Before the first surface is bonded to the bonding surface of the supporting wafer, it further includes: After forming a circuit layer on the first surface, an isolation layer is formed to cover the circuit layer; The first surface of the isolation layer is bonded to the bonding surface of the carrier wafer.
8. An image sensor, characterized in that, The image sensor fabricated by the method described in any one of claims 1-7 further includes: a device wafer, a light-trapping layer, and a metal grid and an insulating layer arranged alternately on the top surface of the light-trapping layer and parallel to the first direction; The device wafer includes photodiodes and isolation structures that extend from the top surface of the device wafer into the device wafer and are alternately arranged along the first direction; the isolation structures are located directly below the metal grids that are set one-to-one. The light-trapping layer extends toward the photodiode along the direction toward the device wafer; wherein the contact surface between the light-trapping layer and the insulating layer and the photodiode is wavy; the top surface of the light-trapping layer is lower than the bottom surface of the metal grid.
9. The image sensor according to claim 8, characterized in that, Also includes: A carrier wafer, and an isolation layer and a circuit layer arranged sequentially on the top surface of the carrier wafer in a direction away from the carrier wafer.
10. An electronic device, characterized in that, include: An image sensor prepared by the preparation method according to any one of claims 1-7; or The image sensor as described in any one of claims 8-9.
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