Semiconductor device, image sensor, and layout design method

Abstract

The invention relates to a semiconductor device, an image sensor and a layout design method. The semiconductor device includes: a first substrate; a first device isolation portion surrounding a first active region extending in a first direction in the first substrate; a plurality of sub-transistors connected to form a logic transistor; and a common node region at a center of the first active region, where the common node region is shared by the plurality of sub-transistors, where each sub-transistor includes: at least three gate electrodes crossing the first active region in a second direction crossing the first direction; and a plurality of source regions and a plurality of drain regions disposed in the first active region adjacent sidewalls of the at least three gate electrodes, where the plurality of source regions and the plurality of drain regions are alternately arranged in a first direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an image sensor, and a layout design method. Background Art

[0002] Semiconductor devices are important components in the electronics industry due to their small size, multifunctional capabilities, and relatively low cost. Consequently, there is a growing demand for semiconductor devices with high integration density. To increase the integration density of semiconductor devices, it may be beneficial to reduce the line width of patterns included in the semiconductor devices.

[0003] An image sensor is a semiconductor device configured to convert an optical image into an electrical signal. Image sensors can be of the charge-coupled device (CCD) type or the complementary metal oxide semiconductor (CMOS) type. A CMOS image sensor (CIS) may include multiple pixels arranged in a two-dimensional pattern. Each pixel may include a photodiode (PD), which may be used to convert incident light into an electrical signal. Summary of the Invention

[0004] A semiconductor device with increased integration density is provided.

[0005] An image sensor having increased integration density is also provided.

[0006] A method for designing a layout of an interconnection structure in a semiconductor device that can increase the integration density of the semiconductor device and simplify the layout of the interconnection structure in the semiconductor device is also provided.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: a first substrate; a first device isolation portion, which surrounds a first active area extending in a first direction in the first substrate; a plurality of sub-transistors, which are adjacently arranged on the first active area in the first direction, wherein the plurality of sub-transistors are connected to form a logic transistor; and a common node area in the first active area, wherein the common node area is shared by the plurality of sub-transistors and is positioned at the center of the first active area, wherein each of the plurality of sub-transistors includes: at least three gate electrodes, which cross the first active area in a second direction and are spaced apart in the first direction, wherein the second direction intersects the first direction; and a plurality of source regions and a plurality of drain regions, which are arranged in the first active area adjacent to side walls of the at least three gate electrodes, wherein the plurality of source regions and the plurality of drain regions are alternately arranged in the first direction.

[0009] According to one aspect of the present disclosure, an image sensor includes: a first substrate including an analog-to-digital converter (ADC) circuit area, the ADC circuit area including a plurality of ADC column areas; a device isolation portion in the first substrate surrounding a plurality of active areas in each of the plurality of ADC column areas; a plurality of logic transistors in the plurality of active areas; a plurality of interconnection lines connecting the plurality of logic transistors; a first interlayer insulating layer on the plurality of logic transistors, the plurality of interconnection lines, and the first substrate; a second interlayer insulating layer on the first interlayer insulating layer; a second substrate on the second interlayer insulating layer, wherein the second substrate includes a plurality of photoelectric conversion areas; a deep isolation portion in the second substrate, wherein the deep isolation portion separates the plurality of photoelectric conversion areas; and a color filter array and a microlens array sequentially stacked on the second substrate, wherein the plurality of ADC column areas are arranged in a first direction, wherein the plurality of ADC Each ADC column region in the column region and each active region of the plurality of active regions extend in a second direction intersecting the first direction, wherein, in each ADC column region, the plurality of active regions are arranged in the second direction to form a column, wherein each logic transistor of the plurality of logic transistors includes M sub-transistors arranged on a corresponding active region among the plurality of active regions in the second direction, wherein M is an integer greater than or equal to two (2), wherein each sub-transistor includes N unit transistors arranged in the second direction, wherein N is an integer greater than or equal to three (3), wherein each of the N unit transistors includes a gate electrode and a source region and a drain region adjacent to the gate electrode, wherein at least one of the source region and the drain region between adjacent unit transistors is shared by the adjacent unit transistors, and wherein a common node region is arranged in the corresponding active region to connect the M sub-transistors.

[0010] According to one aspect of the present disclosure, a semiconductor device includes: a first substrate; a first device isolation portion, which surrounds a first active area extending in a first direction in the first substrate; a plurality of sub-transistors, which are arranged on the first active area in the first direction, wherein the plurality of sub-transistors are connected to form a logic transistor; a common node area between the plurality of sub-transistors in the first active area, wherein the common node area is shared by the plurality of sub-transistors; and a first contact plug and a second contact plug on the common node area, wherein the first contact plug is spaced apart from the second contact plug in a second direction intersecting the first direction.

[0011] According to one aspect of the present disclosure, a layout design method includes: dividing a logic transistor having a first gate width and a first gate length into a plurality of unit transistors, the plurality of unit transistors being arranged to form M rows and N columns, wherein M is an integer greater than or equal to two (2), and N is an integer greater than or equal to three (3), wherein each unit transistor of the plurality of unit transistors has a second gate length and a second gate width, wherein the first gate length is M times the second gate length, wherein the first gate width is N times the second gate width, and wherein in each of the M rows, N unit transistors are connected in parallel to form a sub-transistor, and M sub-transistors are connected in series to form a logic transistor; arranging the plurality of unit transistors along a first direction on an active region extending along the first direction, wherein a width of the active region in a second direction intersecting the first direction is equal to the second gate width, wherein each unit transistor includes a gate electrode and a source region and a drain region adjacent to the gate electrode. , wherein the plurality of unit transistors are mirror-symmetric in a first direction, wherein the gate electrode crosses the active region in a second direction, wherein at least one of the source region and the drain region between adjacent unit transistors is shared by the adjacent unit transistors, and wherein a common node region is between the M sub-transistors; a gate connection line is formed to connect the gate electrode of each unit transistor in the first direction; a source connection line is formed to connect some source regions included in the M sub-transistors in the first direction; a drain connection line is formed to connect some drain regions included in the M sub-transistors in the first direction; and a common node line is formed to connect the common node region to the remaining source regions or the remaining drain regions included in the M sub-transistors, wherein the source connection line and the drain connection line or the common node line are arranged along a first straight line where the drain connection line or the common node line is located, wherein the drain connection line and the common node line are arranged along a second straight line, and wherein the first straight line is spaced apart from the second straight line in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a diagram illustrating a layout design method according to an embodiment;

[0014] Figure 2A and Figure 2B is a diagram illustrating a layout design method according to an embodiment;

[0015] Figure 3A and Figure 3B is a diagram illustrating a layout design method according to an embodiment;

[0016] Figure 4is a diagram illustrating a layout design method according to an embodiment;

[0017] Figure 5A and Figure 5B 1 is a diagram showing a layout of a logic transistor according to an embodiment;

[0018] 6A to 6D It shows that according to the embodiment Figure 5A or Figure 5B Circuit diagram of logic transistor;

[0019] Figure 7 is a diagram showing a device having Figure 5A A perspective view of a layout of logic transistors;

[0020] Figure 8A and Figure 8B 1 is a diagram showing a layout of a logic transistor according to an embodiment;

[0021] Figure 9A and Figure 9B is a layout of a sub-transistor including four unit transistors according to an embodiment;

[0022] Figure 9C According to the implementation method Figure 9A or Figure 9B The circuit diagram of the sub-transistor;

[0023] Figure 10A and Figure 10B 1 is a diagram showing a layout of a logic transistor according to an embodiment;

[0024] Figures 10C to 10F According to the implementation method Figure 10A or Figure 10B Circuit diagram of logic transistor;

[0025] Figure 11A and Figure 11B 1 is a diagram showing a layout of a logic transistor according to an embodiment;

[0026] Figure 12 According to the implementation method Figure 11A or Figure 11B Circuit diagram of logic transistor;

[0027] Figure 13 is a layout of a sub-transistor including five unit transistors according to an embodiment;

[0028] Figure 14 1 is a diagram showing a layout of a logic transistor according to an embodiment;

[0029] Figure 15 is a layout of a sub-transistor including eight unit transistors according to an embodiment;

[0030] Figure 16 is a block diagram illustrating an image sensor according to an embodiment;

[0031] Figure 17 is a circuit diagram illustrating an active pixel sensor array of an image sensor according to an embodiment;

[0032] Figure 18 is a cross-sectional view showing an image sensor according to an embodiment;

[0033] Figure 19 is a top view schematically showing an ADC circuit area according to an embodiment;

[0034] Figure 20A shows a portion of an ADC circuit according to an embodiment;

[0035] Figure 20B According to the implementation method Figure 20A Detailed circuit diagram of the comparator;

[0036] Figure 21 is a schematic top view of an ADC column area according to an embodiment;

[0037] Figure 22 is a cross-sectional view showing an image sensor according to an embodiment; DETAILED DESCRIPTION

[0038] Example embodiments are described below with reference to the accompanying drawings, some of which are shown in the accompanying drawings. In the present disclosure, the term "source region" may be referred to as a "source node", "first impurity region", "first doped region", "first node" or "first node region". The term "drain region" may be referred to as a "drain node", "second impurity region", "second doped region", "second node" or "second node region". In the present disclosure, terms such as first, second, etc. indicating an order may be used to distinguish elements that perform the same or similar functions from each other, and their numbers may change according to the order mentioned.

[0039] As demand for scaled semiconductor manufacturing processes increases, it may be desirable to reduce the geometric features of a transistor's gate electrode (e.g., gate width and / or gate length). For some circuits, to achieve desired characteristics in terms of noise and size matching, the minimum feature size of the transistor's gate electrode may be kept within a range greater than a specific value. Therefore, embodiments may provide a method for connecting several unit transistors of limited size to form a single logic transistor.

[0040] When a plurality of unit transistors are provided, a complex interconnect structure may be used to connect the unit transistors to each other, and the area of ​​the interconnect structure may be increased. This may make it difficult to increase the integration density of the semiconductor device. However, according to an embodiment, a layout design method can be provided to form the unit transistors in a manner that meets the growing demand for scaled-down semiconductor manufacturing processes and to reduce the area occupied by the interconnect structure of the logic transistor.

[0041] In the present disclosure, the term "logic transistor" may refer to a transistor that may be provided as part of a logic circuit for driving a transfer transistor and a pixel transistor (e.g., a reset transistor, a select transistor, a source follower transistor, a dual conversion transistor, etc.) in a pixel array of an image sensor. However, in embodiments, it may refer to a transistor that is provided as part of a logic circuit for driving a memory cell transistor in a memory cell array of a memory device.

[0042] Figure 1 FIG. 1 is a diagram illustrating a layout design method according to an embodiment from a layout perspective.

[0043] refer to Figure 1 The layout design method may include selecting a logic transistor LTR to be designed. The logic transistor LTR may be disposed on a first active area ACT1, which may be confined within a substrate. The logic transistor LTR may include a first gate electrode G1 and may also include a first source region S1 and a first drain region D1. The first source region S1 and the first drain region D1 may be disposed in the substrate and on either side of the first gate electrode G1. The first source region S1 and the first drain region D1 may be spaced apart from each other in a first direction X1. The first gate electrode G1 may intersect the first active area ACT1 in a second direction X2. A gate insulating layer Gox (e.g., as shown in FIG. 6 ) may be interposed between the first gate electrode G1 and the substrate. The logic transistor LTR may have a first gate length L1 and a first gate width W1. The first gate length L1 may correspond to the length of the first gate electrode G1 that may overlap with the first active area ACT1 in the first direction X1. The first gate width W1 may correspond to the width of the first gate electrode G1 that may overlap with the first active area ACT1 in the second direction X2. If the first gate length L1 and the first gate width W1 are set within a range that can be used to obtain an output signal having a desired level from the logic transistor LTR, it may be difficult to achieve a scaled-down semiconductor manufacturing process or reduce noise issues.

[0044] Therefore, in the layout design method according to the embodiment, in order to realize the logic transistor LTR, the logic transistor LTR can be divided into unit transistors UTR, and the unit transistors UTR can be arranged to form M rows and N columns that can be connected to each other. Here, M can represent a natural number greater than or equal to two (2), and N can represent a natural number greater than or equal to three (3). For example, each unit transistor UTR can be set on the second active area ACT2. Each unit transistor UTR may include a second gate electrode G2 and a second source region S2 and a second drain region D2, and the second source region S2 and the second drain region D2 can be set in the substrate and on both sides of the second gate electrode G2. The second source region S2 and the second drain region D2 can be spaced apart from each other in the first direction X1. The second gate electrode G2 can intersect the second active area ACT2 in the second direction X2. A gate insulating layer Gox (for example, as shown in FIG. 6 ) can be interposed between the second gate electrode G2 and the substrate. Each unit transistor UTR can have a second gate length L2 and a second gate width W2.

[0045] In the present disclosure, the second gate electrode G2 may be referred to as a "unit gate electrode," the second source region S2 may be referred to as a "unit source region," and the second drain region D2 may be referred to as a "unit drain region." The second gate length L2 may be referred to as a "unit gate length." The second gate width W2 may be referred to as a "unit gate width."

[0046] The second gate length L2 may correspond to the length of the second gate electrode G2 that may overlap with the second active area ACT2 in the first direction X1. The second gate width W2 may correspond to the width of the second gate electrode G2 that may overlap with the second active area ACT2 in the second direction X2. The second gate length L2 and the second gate width W2 may be achieved by a scaled-down semiconductor manufacturing process. For example, M times the second gate length L2 may correspond to the first gate length L1, and N times the second gate width W2 may correspond to the first gate width W1.

[0047] Figure 1 The layout can be changed by Figure 2A and Figure 2B The circuit diagram is used to describe it.

[0048] Figure 2A and Figure 2B FIG. 1 is a diagram illustrating a layout design method according to an embodiment from a circuit perspective. Figure 2A depicts an n-type field effect transistor (FET) or n-type metal oxide semiconductor field effect transistor (NMOSFET), and Figure 2B A p-type FET or PMOSFET is depicted.

[0049] refer to Figure 1、 Figure 2A and Figure 2B , N unit transistors UTR (e.g., transistor UTR (1) to transistor UTR (N)) can be arranged in the second direction X2 to form a row and can be connected in parallel to form a single sub-transistor STR. In an embodiment, M sub-transistors STR (e.g., sub-transistor STR (1) to sub-transistor STR (M)) can be arranged in the first direction X1 to form a column and can be connected in series to form a logic transistor LTR. The second gate electrodes G2 of the unit transistors UTR can be electrically connected to each other via the gate connection line GL. Within each sub-transistor STR, the second source regions S2 of the unit transistors UTR included in the sub-transistor STR can be connected to each other through the source connection line SL. Within each sub-transistor STR, the second drain regions D2 of the unit transistors UTR included in the sub-transistor STR can be connected to each other through the drain connection line DL. The common node region DS can connect adjacent sub-transistors STR to each other. For example, the drain connection line DL in one of the sub-transistors STR can be connected to the source connection line SL in the adjacent sub-transistor STR in the first direction X1 through the common node region DS. In Figure 2A and Figure 2B In the example shown in , (M-1) common node regions DS may be provided. The common node regions DS may include, for example, a first common node region DS(1) to an (M-1)th common node region DS(M-1).

[0050] Figure 3A and Figure 3B FIG. 1 is a diagram illustrating a layout design method according to an embodiment from a circuit perspective.

[0051] refer to Figure 3A In the layout design method, the unit transistors UTR included in each sub-transistor STR may be arranged to form a line in the first direction X1. The sub-transistors STR may be arranged to form a line in the first direction X1, as shown in FIG. Figure 3A As shown in . Interconnection lines may be provided to connect the sub-transistors STR to form a logic transistor LTR.

[0052] exist Figure 2A and Figure 2B In the matrix arrangement of the unit transistors UTR shown in , the first row of unit transistors UTR parallel to the horizontal direction X2 may be arranged in the first direction X1, the next row of unit transistors UTR parallel to the horizontal direction X2 may be arranged in the first direction X1, and the process may be sequentially repeated until the Mth row of unit transistors UTR is arranged. For example, the unit transistors UTR may be arranged in Figure 2A and Figure 2B The matrix arrangement shown in FIG is placed in a "Z" shape sequence to form Figure 3Aand Figure 3B arrangement.

[0053] refer to Figure 3A , the second gate electrodes G2 of all the unit transistors UTR included in the logic transistor LTR can be connected to each other through the gate connection line GL. The gate connection line GL can extend in the first direction X1. Within each sub-transistor STR, the second source regions S2 of the unit transistors UTR included in the sub-transistor STR can be connected to each other through the source connection line SL. Within each sub-transistor STR, the second drain regions D2 of the unit transistors UTR included in the sub-transistor STR can be connected to each other through the drain connection line DL. The common node area DS can connect the sub-transistors STR adjacent to each other. For example, the drain connection line DL in one of the sub-transistors STR can be connected to the source connection line SL in the adjacent sub-transistor STR in the first direction X1 through the common node area DS. Figure 3A In the example shown in , the source connection line SL can be arranged along a straight line parallel to the first direction X1. The drain connection line DL can be arranged along another straight line parallel to the first direction X1. The source connection line SL, the drain connection line DL, and the gate connection line GL can be spaced apart from each other in the second direction X2. Figure 3A The arrangement can be applied to the following reference Figure 5A and Figure 8A Describes the layout design method.

[0054] like Figure 3B As shown in , the even sub-transistors in the sub-transistor STR may be provided to be symmetrical with respect to the odd sub-transistors in the sub-transistor STR in the second direction X2. For example, the source connection lines SL in the odd sub-transistors in the sub-transistor STR and the drain connection lines DL in the even sub-transistors in the sub-transistor STR may be arranged along a first straight line. According to an embodiment, when one or more elements are described as being “arranged along” a straight line, this may mean that one or more elements are located on or set according to a straight line, which may be, for example, a dotted line or an imaginary line. The source connection lines SL in the even sub-transistors in the sub-transistor STR and the drain connection lines DL in the odd sub-transistors in the sub-transistor STR may be arranged along a second straight line different from the first straight line. The common node area DS may be provided to have a zigzag shape. Figure 3B The arrangement can be applied to the following reference Figure 5B and Figure 8B Describes the layout design method.

[0055] exist Figure 2A or Figure 2B The arrangement of the unit transistor UTR is changed to Figure 3A or Figure 3BIn the case of the arrangement of the gate connection line GL, the source connection line SL, and the drain connection line DL can be reduced in number and placed along three straight lines. This can reduce the complexity and difficulty of placing the gate connection line GL, the source connection line SL, and the drain connection line DL, which can be used to connect the unit transistors UTR to each other.

[0056] Furthermore, it is possible to reduce the area occupied by the gate connection line GL, the source connection line SL, and the drain connection line DL, and reduce the width of the region of the logic transistor LTR in the second direction X2 (eg, Figure 19 ). Therefore, a semiconductor device with increased integration density can be achieved.

[0057] Figure 4 is a diagram illustrating a layout design method according to an embodiment.

[0058] Figure 4 A process 400 for designing a layout of a sub-transistor STR including three unit transistors UTR connected in parallel is shown. For example, at operation 410, the first to third unit transistors UTR (1) to UTR (3) may be alternately positioned to form a row in a first direction X1 and have mirror symmetry with respect to each other. For example, in the first unit transistor UTR (1) and the third unit transistor UTR (3), the second source region S2 may be located to the left of the second gate electrode G2, and the second drain region D2 may be located to the right of the second gate electrode G2. In the second unit transistor UTR (2), the second source region S2 may be located to the right of the second gate electrode G2, and the second drain region D2 may be located to the left of the second gate electrode G2.

[0059] At operation 420, the first to third unit transistors UTR (1) to UTR (3) may be connected so that they overlap with each other in the first direction X1. Here, the second drain region D2 of the second unit transistor UTR (2) may overlap or share the second drain region D2 of the first unit transistor UTR (1). The second source region S2 of the second unit transistor UTR (2) may overlap or share the second source region S2 of the third unit transistor UTR (3). The first to third unit transistors UTR (1) to UTR (3) included in the sub-transistor STR may be arranged in a finger-type arrangement.

[0060] At operation 430, interconnection lines may be placed to connect the first to third unit transistors UTR (1) to UTR (3) to each other. First contact plugs CT1 may be respectively disposed on the second drain region D2. Drain connection lines DL may connect the first contact plugs CT1 to each other. Second contact plugs CT2 may be disposed on the second source region S2. Source connection lines SL may connect the second contact plugs CT2 to each other. Third contact plugs CT3 may be disposed on the second gate electrode G2. Gate connection lines GL may connect the third contact plugs CT3. The source connection lines SL, the drain connection lines DL, and the gate connection lines GL may extend in the first direction X1 and may be spaced apart from each other in the second direction X2. At operation 430, the sub-transistor STR may have the same circuit structure as that shown in operation 440, and the sub-transistor STR is completed at operation 440.

[0061] Figure 5A and Figure 5B 2 is a diagram showing a layout of a logic transistor according to an embodiment.

[0062] Figure 5A 1 shows a layout of a logic transistor LTR constructed by connecting two sub-transistors STR in a first direction X1, each sub-transistor STR having a corresponding Figure 4 4. For example, the first sub-transistor STR (1) and the second sub-transistor STR (2) may be arranged side by side in the first direction X1 to form one logic transistor LTR. The logic transistor LTR may be arranged in the third active region ACT3. The third active region ACT3 may have a shape obtained by connecting two second active regions ACT2 in the first direction X1, the two second active regions ACT2 being provided to have a shape corresponding to Figure 4 The third active region ACT3 may have a second width W2 in the second direction X2.

[0063] Each of the first sub-transistor STR (1) and the second sub-transistor STR (2) may have a value corresponding to Figure 4 Here, the layout of the first sub-transistor STR (1) and the second sub-transistor STR (2) may be connected so that the rightmost second drain region D2 in the first sub-transistor STR (1) contacts or overlaps the leftmost second source region S2 in the second sub-transistor STR (2).

[0064] An overlapping region between the first sub-transistor STR (1) and the second sub-transistor STR (2) may serve as a common node region DS. The common node region DS may correspond to the rightmost second drain region D2 of the first sub-transistor STR (1), and may correspond to the leftmost second source region S2 of the second sub-transistor STR (2). The first sub-transistor STR (1) and the second sub-transistor STR (2) may share the common node region DS therebetween.

[0065] In the first sub-transistor STR (1), the drain connection line DL (for example, as shown in FIG. 1 ) connected to the second drain region D2 is connected to the drain connection line DL (for example, as shown in FIG. 1 ). Figure 4 As shown in FIG, at operation 430 ) can be used as Figure 5A and Figure 5B For example, the first common node line DSL1 may connect the second drain region D2 of the first sub-transistor STR(1) to the common node region DS.

[0066] In the second sub-transistor STR (2), the source connection line SL (eg, Figure 4 As shown in FIG, at operation 430 ) can be used as Figure 5A and Figure 5B For example, the second common node line DSL2 may connect the second source region S2 of the second sub-transistor STR(2) to the common node region DS.

[0067] A first contact plug CT1 connectable to a first common node line DSL1 and a second contact plug CT2 connectable to a second common node line DSL2 may be disposed on the common node region DS. The second contact plug CT2 may be spaced apart from the first contact plug CT1 in the second direction X2. The common node region DS may connect the first common node line DSL1 to the second common node line DSL2. As a result, there may be no need to place an additional line connecting the first common node line DSL1 to the second common node line DSL2, thereby simplifying the layout.

[0068] The second gate electrodes G2 of the first sub-transistor STR (1) and the second sub-transistor STR (2) may be connected to each other by a gate connection line GL extending in the first direction X1. The gate connection line GL may be arranged along a first straight line IS1. The source connection line SL of the first sub-transistor STR (1) and the second common node line DSL2 of the second sub-transistor STR (2) may be arranged along a second straight line IS2. The first common node line DSL1 of the first sub-transistor STR (1) and the drain connection line DL of the second sub-transistor STR (2) may be arranged along a third straight line IS3. The first to third straight lines IS2, IS2 and IS3 may be spaced apart from each other in the second direction X2.

[0069] exist Figure 5A During operation of the logic transistor LTR, the same gate voltage may be applied to the second gate electrode G2 at the same time. A source voltage may be applied to the source connection line SL of the first sub-transistor STR (1), and a drain voltage may be applied to the drain connection line DL of the second sub-transistor STR (2). The gate voltage, the source voltage, and the drain voltage may not be applied to the first common node line DSL1 and the second common node line DSL2. A voltage may be applied to the first common node line DSL1 and the second common node line DSL2 through the common node region DS.

[0070] exist Figure 5A In the layout of the second sub-transistor STR (2), the drain connection line DL and the second common node line DSL2 can be placed to have mirror symmetry in the second direction X2. In this case, it is possible to form Figure 5B For example, refer to Figure 5B , Figure 5A The first contact plug CT1 on the common node region DS in the embodiment may be merged with the second contact plug CT2 to form a common contact plug CTT. The first common node line DSL1 and the second common node line DSL2 on the common contact plug CTT may be connected to each other to form a common node line DSL. Figure 5B In the logic transistor LTR, the source connection line SL of the first sub-transistor STR (1) and the drain connection line DL of the second sub-transistor STR (2) can be arranged along the second straight line IS2. The common node line DSL can be arranged along the third straight line IS3. The gate voltage, source voltage and drain voltage may not be applied to the common node line DSL. The voltage may be applied to the common node line DSL through the common node region DS. The other parts may have the same Figure 5A The structural features in the examples shown in FIG. 1 are the same or similar structural features.

[0071] 6A to 6D It shows Figure 5A or Figure 5B Circuit diagram of a logic transistor.

[0072] Figure 5A or Figure 5B The logic transistor LTR can be made of 6A to 6D For example, the first sub-transistor STR (1) and the second sub-transistor STR (2) may be connected in series, and each of the sub-transistors STR (1) and STR (2) may include three unit transistors UTR connected in parallel. Figure 5A The logic transistor LTR can have Figure 6A or Figure 6B The circuit structure is similar to the circuit structure. Figure 5BThe logic transistor LTR can have Figure 6C or Figure 6D The circuit structure is similar to the circuit structure.

[0073] Figure 7 It shows that Figure 5A A perspective view of the layout of logic transistors.

[0074] refer to Figure 7 , a device isolation portion STI may be provided in the substrate 1 to define a third active region ACT3. The substrate 1 may be a semiconductor substrate (e.g., a silicon wafer). The device isolation portion STI may be formed of or include an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The third active region ACT3 may have a shape that is elongated or extended in the first direction X1. The third active region ACT3 may have a first sidewall SW1 and a second sidewall SW2, and the first sidewall SW1 and the second sidewall SW2 may be opposite to each other in the first direction X1. The third active region ACT3 may have a second width W2 in a second direction X2 that is not parallel to the first direction X1.

[0075] Six second gate electrodes G2, which may be arranged in a 2×3 configuration, may be disposed on the third active area ACT3 to intersect the third active area ACT3 in the second direction X2. The second gate electrodes G2 may be formed of or include at least one of doped polysilicon and / or a metal material (e.g., tungsten and aluminum). Each second gate electrode G2 may have a third length L3 in the second direction X2. The third length L3 may be greater than the second width W2 of the third active area ACT3. A gate insulating layer Gox may be interposed between the second gate electrodes G2 and the substrate 1. The gate insulating layer Gox may be formed of or include at least one of silicon oxide, silicon nitride, or a metal oxide material and may have a single-layer or multi-layer structure.

[0076] Seven impurity regions S2, D2, and DS may be disposed in the third active region ACT3 and proximate the sidewalls of the second gate electrode G2. The impurity regions S2, D2, and DS may be doped with n-type impurities (e.g., phosphorus or arsenic) or p-type impurities (e.g., boron). The impurity regions S2, D2, and DS may include a second source region S2, a second drain region D2, and a common node region DS. The second source regions S2 and the second drain regions D2 may be alternately arranged in the first direction X1. The common node region DS may be arranged to overlap the center of the third active region ACT3. First contact plugs CT1 may be disposed on the second drain regions D2, respectively. Second contact plugs CT2 may be disposed on the second source regions S2, respectively. Third contact plugs CT3 may be disposed on the second gate electrode G2, respectively. The first contact plugs CT1 and the second contact plugs CT2 may be disposed on the common node region DS.

[0077] The source connection line SL may connect the first and second source regions and the third second source region in the second source region S2 to each other in the first direction X1. For example, the source connection line SL may connect the first and third impurity regions S2 in order away from the first sidewall SW1 of the third active region ACT3.

[0078] The drain connection line DL may connect the first and second drain regions in the second drain region D2 to each other in a direction opposite to the first direction X1 (e.g., the negative direction X1). For example, the drain connection line DL may connect the first and third impurity regions D2 and D2, which are located first and third in this order moving away from the second sidewall SW2 of the third active region ACT3.

[0079] The first common node line DSL1 may connect the first and second drain regions in the second drain region D2 to the common node region DS in the first direction X1. For example, the first common node line DSL1 may connect the first impurity region D2 to the impurity region DS in an order away from the first sidewall SW1 of the third active region ACT3.

[0080] The second common node line DSL2 may connect the first and second source regions in the second source region S2 to the common node region DS in a direction opposite to the first direction X1. For example, the second common node line DSL2 may connect the first impurity region S2 to the impurity region DS in an order moving away from the second sidewall SW2 of the third active region ACT3.

[0081] The gate connection line GL, the source connection line SL, the drain connection line DL, the first common node line DSL1, and the second common node line DSL2 may cross the second gate electrode G2 in the first direction X1 and may overlap the third active area ACT3.

[0082] Each of the gate connection line GL, the source connection line SL, the drain connection line DL, the first common node line DSL1, the second common node line DSL2, and the first and second contact plugs CT1 and CT2 may be formed of or include at least one of metal materials (e.g., titanium, tantalum, tungsten, aluminum, and copper).

[0083] Figure 8A and Figure 8B 2 is a diagram showing a layout of a logic transistor according to an embodiment.

[0084] Figure 8A and Figure 8B Each of the layouts of the logic transistors LTR shown in FIG. 1 can be realized by connecting four sub-transistors STR (each of which can correspond to Figure 4 For example, the first sub-transistor STR (1) to the fourth sub-transistor STR (4) may be arranged in the first direction X1 to form one logic transistor LTR. Each of the first sub-transistor STR (1) to the fourth sub-transistor STR (4) may have a value corresponding to Figure 4 The layout of operation 430. Here, the layout of the first sub-transistor STR (1) to the fourth sub-transistor STR (4) may be connected so that the edge impurity regions (e.g., S2 or D2) of the first sub-transistor STR (1) to the fourth sub-transistor STR (4) are in contact with each other. The overlapping region between each adjacent pair of the first sub-transistor STR (1) to the fourth sub-transistor STR (4) may be used as a common node region DS. The sub-transistors STR (1) to STR (4) may be configured to share the common node region DS therebetween. In Figure 8A and Figure 8B In the example shown in , the logic transistor LTR may include three common node regions DS( 1 ) to DS( 3 ).

[0085] Corresponding to Figure 4 The drain connection lines DL of operation 430 (which may be used to connect the second drain regions D2 to each other) may be used as Figure 8A The first common node line DSL1 of the first sub-transistor STR (1) is connected to the first common node area DS (1). For example, the first common node line DSL1 can connect the second drain area D2 of the first sub-transistor STR (1) to the first common node area DS (1).

[0086] The second source region S2 of the first sub-transistor STR (1) that may be closest to the first side wall SW1 of the third active area ACT3 may be connected to the source connection line SL. The second drain region D2 of the fourth sub-transistor STR (4) that may be closest to the second side wall SW2 of the third active area ACT3 may be connected to the drain connection line DL.

[0087] exist Figure 8A , the second common node line DSL2 may connect the first common node region DS (1) to the second source region S2 of the second sub-transistor STR (2). The third common node line DSL3 may connect the second drain region D2 of the second sub-transistor STR (2) to the second common node region DS (2). The fourth common node line DSL4 may connect the second common node region DS (2) to the second source region S2 of the third sub-transistor STR (3). The fifth common node line DSL5 may connect the second drain region D2 of the third sub-transistor STR (3) to the third common node region DS (3). The sixth common node line DSL6 may connect the third common node region DS (3) to the second source region S2 of the fourth sub-transistor STR (4). The first to sixth common node lines DSL1 to DSL6 may be arranged in a zigzag shape (e.g., an alternating shape) to connect two adjacent impurity regions in the impurity regions S2, D2, or DS to each other, as shown in FIG. Figure 8A Other parts may have structural features that are the same as or similar to those in one of the above embodiments.

[0088] like Figure 8B As shown in , the first common node line DSL1 can connect the second drain region D2 of the first sub-transistor STR (1), the first common node region DS (1), and the second source region S2 of the second sub-transistor STR (2) to each other. The second common node line DSL2 can connect the second drain region D2 of the second sub-transistor STR (2), the second common node region DS (2), and the second source region S2 of the third sub-transistor STR (3) to each other. The third common node line DSL3 can connect the second drain region D2 of the third sub-transistor STR (3), the third common node region DS (3), and the second source region S2 of the fourth sub-transistor STR (4) to each other. The first common node line DSL1 to the third common node line DSL3 can be arranged in a zigzag shape to connect three impurity regions S2, D2, or DS that can be spaced apart from each other, as shown in FIG. Figure 8B As shown in .

[0089] In the case where the sub-transistor STR includes three or more odd-numbered unit transistors UTR, the interconnection and arrangement of the sub-transistors STR may be the same as that of the reference Figures 5A to 8B The interconnections and arrangements in one of the described embodiments are the same or similar.

[0090] Figure 9A and Figure 9B is a layout of a sub-transistor including four unit transistors according to an embodiment. Figure 9C yes Figure 9A or Figure 9B Circuit diagram of a sub-transistor.

[0091] refer to Figure 9A and Figure 9B , in the case where the sub-transistor STR includes four unit transistors UTR connected in parallel, the four second gate electrodes G2 can be arranged side by side in the first direction X1 on the third active region ACT3. Five impurity regions S2 and D2 can be arranged in the third active region ACT3. The impurity regions S2 and D2 can include second source regions S2 and second drain regions D2 that can be arranged alternately. The arrangement order of the second source regions S2 and the second drain regions D2 can be changed. For example, the impurity regions S2 and D2 can be arranged in the second sub-transistor STR (2) in the order of S2 / D2 / S2 / D2 / S2 (as shown in FIG. Figure 9B ), or may be arranged in the first sub-transistor STR (1) in the order of D2 / S2 / D2 / S2 / D2 (as shown in Figure 9A ). Figure 9B In the second sub-transistor STR (2), the source connection line SL can connect the three second source regions S2 to each other. Figure 9A In the first sub-transistor STR (1), the drain connection line DL can connect the three second drain regions D2 to each other. Figure 9A and Figure 9B The sub-transistor STR can have Figure 9C The circuit structure shown in .

[0092] Figure 10A and Figure 10B 2 is a diagram showing a layout of a logic transistor according to an embodiment. Figure 10A and Figure 10B Two example layouts of a logic transistor LTR that can be constructed by connecting two sub-transistors STR to each other in a first direction X1 are shown, each sub-transistor STR including four unit transistors UTR.

[0093] refer to Figure 10A and Figure 10B , Figure 9A The first sub-transistor STR (1) and Figure 9B The second sub-transistors STR (2) can be connected to each other in the first direction X1 or in a direction opposite to the first direction X1 to form a logic transistor LTR.

[0094] The layout of the first sub-transistor STR (1) and the second sub-transistor STR (2) can be connected so that the rightmost second source region S2 of the second sub-transistor STR (2) contacts or overlaps with the leftmost second drain region D2 of the first sub-transistor STR (1).

[0095] An overlapping region between the first sub-transistor STR (1) and the second sub-transistor STR (2) may serve as a common node region DS. The common node region DS may correspond to the rightmost second source region S2 of the second sub-transistor STR (2), and may correspond to the leftmost second drain region D2 of the first sub-transistor STR (1). The first sub-transistor STR (1) and the second sub-transistor STR (2) may share the common node region DS therebetween.

[0096] The logic transistor LTR may include eight second gate electrodes G2 and nine impurity regions S2 , D2 , and D5 , which may be arranged side by side on the third active region ACT3 in the first direction X1 .

[0097] Can be used to connect the second source region S2 in the second sub-transistor STR (2) Figure 9B The source connection line SL can be used as Figure 10A and Figure 10B For example, the first common node line DSL1 may connect the second source region S2 of the second sub-transistor STR (2) to the common node region DS.

[0098] Can be used to connect the second drain region D2 in the first sub-transistor STR (1) Figure 9A The drain connection line DL can be used as Figure 10A and Figure 10B For example, the second common node line DSL2 may connect the second drain region D2 in the first sub-transistor STR(1) to the common node region DS.

[0099] The common node region DS may connect the first common node line DSL1 to the second common node line DSL2. As a result, there may be no need to form an additional line connecting the first common node line DSL1 to the second common node line DSL2, and thus the layout may be simplified.

[0100] like Figure 10A As shown in , the second common node line DSL2 may be spaced apart from the first common node line DSL1. Figure 10B As shown in FIG, the first common node line DSL1 and the second common node line DSL2 may be connected to each other to form the common node line DSL.

[0101] Figures 10C to 10F yes Figure 10A or Figure 10B Circuit diagram of a logic transistor.

[0102] Can be based on Figures 10C to 10F The circuit diagram is used to describe Figure 10A or Figure 10B For example, the first sub-transistor STR (1) and the second sub-transistor STR (2) may be connected in series, and each of the sub-transistors STR (1) and STR (2) may include four unit transistors UTR connected in parallel. Figure 10A The logic transistor LTR can have Figure 10C or Figure 10D Similar circuit structure in . Figure 10B The logic transistor LTR can have Figure 10E or Figure 10F Similar circuit structure in .

[0103] Figure 11A and Figure 11B 2 is a diagram showing a layout of a logic transistor according to an embodiment. Figure 12 yes Figure 11A or Figure 11B Circuit diagram of a logic transistor.

[0104] Figure 11A and Figure 11B Two example layouts of a logic transistor LTR are shown, which may be constructed by connecting four sub-transistors STR, each including four unit transistors UTR, to one another in a first direction X1 or in a direction opposite to the first direction X1 .

[0105] refer to Figure 11A 、 Figure 11B and Figure 12 , the first sub-transistor STR (1) to the fourth sub-transistor STR (4) can be connected to each other in the first direction X1 or in a direction opposite to the first direction X1 to form a logic transistor LTR. The first sub-transistor STR (1) and the second sub-transistor STR (2) can be arranged on the fourth active region ACT4. The third sub-transistor STR (3) and the fourth sub-transistor STR (4) can be arranged on the third active region ACT3 spaced apart from the fourth active region ACT4. The logic transistor LTR may include sixteen second gate electrodes G2 and eighteen impurity regions S2, D2 and D5, which can be arranged side by side in the first direction X1 or in a direction opposite to the first direction X1.

[0106] Each of the first sub-transistor STR (1) and the third sub-transistor STR (3) may have Figure 9AThe first sub-transistor STR (1) has the same layout as the first sub-transistor STR (1). Each of the second sub-transistor STR (2) and the fourth sub-transistor STR (4) may have the same Figure 9B The connection between the first sub-transistor STR (1) and the second sub-transistor STR (2) can be the same as Figure 10A or Figure 10B The connections in the layout of the logic transistor LTR are the same or similar. The connection between the third sub-transistor STR (3) and the fourth sub-transistor STR (4) can be the same as Figure 10A or Figure 10B The connections in the layout of the logic transistor LTR are the same or similar. Figure 11A and Figure 11B In the example shown, the logic transistor LTR may further include a node connection line CCL. The node connection line CCL may connect the source connection line SL of the third sub-transistor STR (3) to the drain connection line DL of the second sub-transistor STR (2). When viewed in a top view, the node connection line CCL may have a curved shape (e.g., Figure 11A ), or may have a straight shape (as Figure 11B ). The source voltage and the drain voltage may not be applied to the node connection line CCL.

[0107] Figures 9A to 11B An example is shown in which the sub-transistor STR includes four unit transistors UTR, but the embodiment is not limited to this example. The sub-transistor STR may include four or more even-numbered unit transistors UTR. In the case where the sub-transistor STR includes four or more even-numbered unit transistors UTR4 and the four or more sub-transistors STR are connected to form a row parallel to the first direction X1, the active area ACT3 for the first sub-transistor STR (1) and the second sub-transistor STR (2) may be separated from the active area ACT4 for the third sub-transistor STR (3) and the fourth sub-transistor STR (4), as shown in FIG. Figure 11A and Figure 11B As shown in .

[0108] In the present disclosure, each unit transistor UTR may have a planar FET shape, but the embodiment is not limited to this example. Each unit transistor UTR may be provided in the form of a FinFET, a vertical FET, a multi-bridge channel FET (MBCFET), or a gate-all-around FET (GAAFET).

[0109] Figure 13 is a layout of a sub-transistor including five unit transistors according to an embodiment.

[0110] refer to Figure 13The sub-transistor STR may include five unit transistors UTR connected in parallel. Five second gate electrodes G2 may be arranged side by side on the third active region ACT3 in the first direction X1. Six impurity regions S2 and D2 may be arranged in the third active region ACT3. The impurity regions S2 and D2 may include second source regions S2 and second drain regions D2 that may be arranged alternately. The arrangement order of the second source regions S2 and second drain regions D2 may be changed. A source connection line SL may connect the three second source regions S2 to each other. A drain connection line DL may connect the three second drain regions D2 to each other.

[0111] Figure 14 2 is a diagram showing a layout of a logic transistor according to an embodiment. Figure 14 An example layout of a logic transistor LTR that may be constructed by connecting two sub-transistors STR to each other in a first direction X1 is shown, each sub-transistor STR including five unit transistors UTR.

[0112] refer to Figure 14 , the logic transistor LTR may include ten second gate electrodes G2 and eleven impurity regions S2 , D2 , and DS arranged side by side in the first direction X1 on the third active region ACT3 . Figure 14 In the example shown in FIG, the common node region DS can connect the first common node line DSL1 to the second common node line DSL2. Therefore, there is no need to form an additional line connecting the first common node line DSL1 to the second common node line DSL2, so the layout can be simplified. Other parts can be the same as those in reference Figures 5A to 8B The same or similar to those in one of the described embodiments.

[0113] Figure 15 is a layout of a sub-transistor including eight unit transistors according to an embodiment.

[0114] refer to Figure 15 The sub-transistor STR may include eight unit transistors UTR connected in parallel. Eight second gate electrodes G2 may be arranged side by side on the third active region ACT3 in the first direction X1. Nine impurity regions S2 and D2 may be arranged in the third active region ACT3. The impurity regions S2 and D2 may include second source regions S2 and second drain regions D2 that may be arranged alternately. The arrangement order of the second source regions S2 and second drain regions D2 may be changed. A source connection line SL may connect the five second source regions S2 to each other. A drain connection line DL may connect the four second drain regions D2 to each other. Figure 15 The connection structure between the unit transistors UTR in the sub-transistor STR can be Figure 10A and Figure 10B The connection structure is different from the example shown in . Figure 15A plurality of sub-transistors having the same structure as the sub-transistor STR may be arranged in the first direction X1 and may be arranged in a manner similar to that of the sub-transistor STR. Figures 10A to 11B are connected to each other in the same manner in one embodiment.

[0115] The layout of the logic transistor can be designed in the above manner. The number of sub-transistors and the number of unit transistors included in each sub-transistor may not be limited to Figures 4 to 15 The number of sub-transistors included in the logic transistor may be greater than or equal to 2, and the number of unit transistors included in each sub-transistor may be greater than or equal to 3.

[0116] The logic transistor LTR, which can be manufactured to have a layout structure designed using the above-described layout design method, can be applied to various semiconductor devices. For example, the logic transistor LTR can be applied to image sensors or various memory devices (e.g., DRAM devices). The logic transistor LTR can be used as part of an image sensor circuit (e.g., an analog-to-digital converter (ADC), a row driver, or a column decoder). In some embodiments, the logic transistor LTR can be used as part of a DRAM device circuit (e.g., a sub-wordline driver or a sense amplifier) ​​or as part of a NAND flash memory device circuit (e.g., a decoder or a page buffer).

[0117] Below, an example of an image sensor including logic transistors is described in more detail.

[0118] Figure 16 is a block diagram illustrating an image sensor according to an embodiment.

[0119] refer to Figure 16 The image sensor 1000 may be a semiconductor configured to convert an optical image into an electrical signal. The image sensor 1000 may be configured to generate a digital signal based on light incident from the outside. In an electronic device including the image sensor 1000, the digital signal may be used to display an image on a display panel. In an embodiment, the electronic device including the image sensor 1000 may be implemented as one of various electronic devices including a smartphone, a tablet personal computer, a laptop personal computer, a wearable device, and the like.

[0120] The image sensor 1000 may include an active pixel sensor array 1001 , a row driver 1002 , a row decoder 1003 , a column decoder 1007 , a timing generator 1005 , an analog-to-digital converter (ADC) 1006 , and an input / output (I / O) buffer 1008 .

[0121] The active pixel sensor array 1001 may include a plurality of pixels that may be arranged two-dimensionally and may be configured to convert optical signals into electrical signals. The active pixel sensor array 1001 may be driven by a plurality of drive signals (such as pixel selection signals, reset signals, and charge transfer signals) sent from a row driver 1002. The converted electrical signals may be provided to a correlated double sampler.

[0122] The row driver 1002 may be configured to generate a driving signal for driving the unit pixel based on the information decoded by the row decoder 1003, and then transmit such a driving signal to the active pixel sensor array 1001. In the case where the unit pixels are arranged in a matrix shape (e.g., in rows and columns), the driving signal may be provided to the corresponding row.

[0123] The timing generator 1005 may be configured to provide timing signals and control signals to the row decoder 1003 and the column decoder 1007 .

[0124] The ADC 1006 can be configured to function as a correlated double sampler (CDS). The correlated double sampler can be configured to receive an electrical signal that may be generated in the active pixel sensor array 1001 and perform operations to hold and sample the received electrical signal. For example, the correlated double sampler can perform a double sampling operation (wherein a specific noise level and signal level of the electrical signal may be used) and then output a difference level corresponding to the difference between the noise level and the signal level. In an embodiment, the ADC 1006 can be configured to convert an analog signal into a digital signal and output the converted digital signal. The analog signal may include information about the difference level output from the correlated double sampler.

[0125] The I / O buffer 1008 may be configured to latch digital signals and then sequentially output the latched signals to the image signal processing unit based on information decoded by the column decoder 1007 .

[0126] Figure 17 is a circuit diagram illustrating an active pixel sensor array of an image sensor according to an embodiment.

[0127] refer to Figure 16 and Figure 17 The active pixel sensor array 1001 may include a plurality of unit pixels PX arranged in a matrix. Each unit pixel PX may include a transfer transistor TX. Each unit pixel PX may also include a pixel transistor, such as a reset transistor RX, a select transistor SX, or a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each unit pixel PX may also include a photoelectric conversion region PD and a floating diffusion region FD. In an embodiment, the pixel transistor may be shared by at least two unit pixels PX.

[0128] The photoelectric conversion region PD can be configured to generate an amount of photocharge proportional to the amount of light incident from the outside and store the photocharge. The photoelectric conversion region PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, or any combination thereof. The transfer transistor TX can be configured to transfer the charge generated in the photoelectric conversion region PD to the floating diffusion region FD. The floating diffusion region FD can be configured to receive and cumulatively store the charge generated in the photoelectric conversion region PD. The source follower transistor DX can be controlled based on the amount of photocharge stored in the floating diffusion region FD.

[0129] The reset transistor RX can be configured to periodically discharge or reset photocharge accumulated in the floating diffusion area FD. The reset transistor RX can include a drain electrode and a source electrode, and the drain electrode and the source electrode can be connected to the floating diffusion area FD and a power supply voltage VDD, respectively. When the reset transistor RX is turned on, the power supply voltage VDD, which can be connected to the source electrode of the reset transistor RX, can be applied to the floating diffusion area FD. Therefore, if the reset transistor RX is turned on, the charge accumulated in the floating diffusion area FD can be discharged; for example, the floating diffusion area FD can be reset.

[0130] The source follower transistor DX including the source follower gate electrode SF may function as a source follower buffer amplifier. The source follower transistor DX may be configured to amplify a potential change of the floating diffusion area FD and output the amplified signal to the output line Vout.

[0131] The selection transistor SX including the selection gate electrode SEL may be used to select one of the rows of unit pixels PX during a read operation. When the selection transistor SX is turned on, the power supply voltage VDD may be applied to the drain electrode of the source follower transistor DX.

[0132] Figure 17 An example of a unit pixel PX in which a transfer transistor TX, a reset transistor RX, a select transistor SX, and a source follower transistor DX are provided is shown, but embodiments are not limited to this example. For example, at least one of the reset transistor RX, the select transistor SX, and the source follower transistor DX may be shared by a plurality of unit pixels PX.

[0133] Figure 18 is a cross-sectional view illustrating an image sensor according to an embodiment.

[0134] refer to Figure 18The image sensor 1000 according to the embodiment may include a first semiconductor chip CH1 and a second semiconductor chip CH2 stacked sequentially. The first semiconductor chip CH1 may include a first substrate 11, a lower interconnection layer 223, and a first interlayer insulating layer IL1. A first device isolation portion STI1 may be provided on the first substrate 11 to define an active region. Figure 16 The circuits of the row driver 1002, the row decoder 1003, the column decoder 1007, the timing generator 1005, the ADC 1006, and the I / O buffer 1008 may be provided on the first substrate 11. The peripheral transistor PTR, the logic transistor LTR, and the lower interconnection layer 223 may be provided on the first substrate 11 of the first semiconductor chip CH1 to form the circuits such as the row driver 1002, the row decoder 1003, the column decoder 1007, the timing generator 1005, the ADC 1006, and the I / O buffer 1008. However, the embodiment is not limited to Figure 18 , and the logic transistor LTR may be provided in the second semiconductor chip CH2.

[0135] Figure 19 FIG. 1 is a top view schematically showing an ADC circuit area according to an embodiment.

[0136] refer to Figure 19 According to the present embodiment, the ADC circuit area 1006a may include a plurality of ADC column areas AC (e.g., AC(1), AC(2), ..., AC(K-1), AC(K)). The ADC circuit area 1006a is an area where the ADC 1006 is provided. The ADC column area AC is an area where the ADC columns are provided. The ADC column areas AC may be provided to have a structure elongated in the first direction X1 and may be arranged side by side in the second direction X2. In an embodiment, K ADC column areas AC may be included in the ADC circuit area 1006a. The number K of K ADC column areas AC may be equal to the number of columns of pixels PX included in the active pixel sensor array 1001. Each of the ADC column areas AC may have a third width W3 in the second direction X2. This means that the ADC circuit area 1006a may have a fourth width W4 in the second direction X2, and the fourth width W4 is K times the third width W3.

[0137] Figure 20A A portion of the ADC circuit is shown. Figure 20B yes Figure 20A Detailed circuit diagram of the comparator.

[0138] refer to Figure 19 、 Figure 20A and Figure 20B , the comparator 100 can be set in each ADC column area AC, such as Figure 20AAs shown in FIG. 1 , the comparator 100 may include a first logic transistor LTR1, a second logic transistor LTR2, a third logic transistor LTR3, a fourth logic transistor LTR4 and a current source CS. Figure 20B As shown in . The first logic transistor LTR1 and the second logic transistor LTR2 can be load transistors and can be, for example, p-type MOSFETs. The power supply voltage VDD can be applied to the ends of the first logic transistor LTR1 and the second logic transistor LTR2. The gate electrodes of the first logic transistor LTR1 and the second logic transistor LTR2 can be connected to each other. The third logic transistor LTR3 and the fourth logic transistor LTR4 can be input transistors and can be, for example, n-type MOSFETs. The ramp voltage VRamp can be applied to the gate electrode of the third logic transistor LTR3. The pixel voltage VPix can be applied to the gate electrode of the fourth logic transistor LTR4. The current source CS can be provided between the third logic transistor LTR3 and the fourth logic transistor LTR4 and connected to the third logic transistor LTR3 and the fourth logic transistor LTR4. The output node Vout can be provided between the second logic transistor LTR2 and the fourth logic transistor LTR4 and connected to the second logic transistor LTR2 and the fourth logic transistor LTR4.

[0139] Figure 21 It is a schematic top view of the ADC column area.

[0140] refer to Figure 21 , Figure 19 Each of the ADC column regions AC may include J transistor regions RN (e.g., RN(1), RN(2), ..., RN(J-1), RN(J)), where J is a natural number greater than or equal to 5. The transistor regions RN may be arranged side by side in the first direction X1. The transistor regions RN arranged to form a row in the first direction X1 may be provided in each ADC column region AC, such as Figure 21 However, the embodiment is not limited to this example, and the transistor regions RN in each ADC column region AC may be arranged to form a plurality of rows in the first direction X1.

[0141] Figure 20BThe first to fourth logic transistors LTR1 to LTR4 may be provided in at least one of the transistor regions RN. For example, the first logic transistor LTR1 may be provided in the first transistor region RN(1). The second logic transistor LTR2 may be provided in the second transistor region RN(2). The third logic transistor LTR3 may be provided in the (J-1)th transistor region RN(J-1). The fourth logic transistor LTR4 may be provided in the Jth transistor region RN(J). The arrangement of the first to fourth logic transistors LTR1 to LTR4 is not limited to this example and may be variously modified.

[0142] According to an embodiment of the present disclosure, each of the first to fourth logic transistors LTR1 to LTR4 may have a reference Figures 3A to 15 The layout or structure of the logic transistor LTR described above can be reduced. Therefore, the width W3 of each ADC column region AC in the second direction X2 and the width W4 of the ADC circuit region 1006a in the second direction X2 can be reduced, and in this case, the size of the image sensor 1000 can be reduced. Therefore, the integration density of the image sensor 1000 can be increased.

[0143] Reference again Figure 18 , the second semiconductor chip CH2 disposed on the first semiconductor chip CH1 may include a second substrate 1 having a main area APS, an optical black area OB, and a pad area PAD. The upper interconnect layer 221 and the second interlayer insulating layer IL2 may be disposed on the front surface 1a of the second substrate 1. The main area APS may include a plurality of pixels PX. A deep isolation portion DTI may be disposed in the second substrate 1 to separate the photoelectric conversion regions PD of the pixels PX from each other. When viewed in a top view, the deep isolation portion DTI may have a grid shape. The deep isolation portion DTI may include an isolation conductive pattern spaced apart from the second substrate 1 and an isolation insulating pattern interposed between the isolation conductive pattern and the second substrate 1. A second device isolation portion STI2 may be disposed in the second substrate 1 to define an active area. The deep isolation portion DTI may penetrate the second device isolation portion STI2. No interface may be observed between the deep isolation portion DTI and the second device isolation portion STI2.

[0144] In each pixel PX, a photoelectric conversion region PD may be provided in the second substrate 1. In each pixel PX, a transfer gate TG and a floating diffusion region FD may be provided on and in the front surface 1a of the second substrate 1. A color filter array, which may include a color filter CF1, may be provided on the rear surface 1b of the second substrate 1. A microlens array, which includes microlenses ML, may be provided on the color filter array.

[0145] At least one of the first to fourth logic transistors LTR1 to LTR4 may overlap at least one of the pixel PX, the photoelectric conversion region PD, the transfer gate TG, and the floating diffusion region FD.

[0146] In the optical black area OB, a light blocking pattern WG, a first connection structure 120, a first conductive pad 81, and a bulk color filter 90 may be provided on the second substrate 1. The first connection structure 120 may include a first connection line 121, an insulating pattern 123, and a first capping pattern 125.

[0147] A portion of the first connection line 121 may be provided on the rear surface 1b of the second substrate 1 and may conformally cover the inner surfaces of the third trench TR3 and the fourth trench TR4. A light-blocking pattern WG may cover the rear surface 1b. The first connection line 121 may be provided to penetrate the photoelectric conversion layer 150 and the upper interconnect layer 221 and connect the photoelectric conversion layer 150 to the interconnect layer 200. More specifically, the first connection line 121 may contact the interconnect lines provided in the upper interconnect layer 221 and the lower interconnect layer 223, as well as the isolation conductive pattern of the pixel isolation portion DTI provided in the photoelectric conversion layer 150. Thus, the first connection structure 120 may be electrically connected to the interconnect lines in the interconnect layer 200. The first connection line 121 may be formed of or include at least one metal material (e.g., tungsten). The light-blocking pattern WG may prevent light from entering the optical black area OB.

[0148] A first conductive pad 81 may be provided in the third trench TR3 to fill the remaining portion of the third trench TR3. The first conductive pad 81 may be formed of or include at least one metal material (e.g., aluminum). The first conductive pad 81 may contact the isolation conductive pattern of the deep isolation portion DTI. A negative bias voltage may be applied to the isolation conductive pattern provided in the deep isolation portion DTI via the first conductive pad 81. In this manner, white spot issues or dark current issues may be prevented or suppressed.

[0149] The insulating pattern 123 may fill the remaining portion of the fourth trench TR4. The insulating pattern 123 may be provided to penetrate all or at least a portion of the interconnection layer 200 and the photoelectric conversion layer 150. The first capping pattern 125 may be provided on the top surface of the insulating pattern 123. The first capping pattern 125 may be provided on the insulating pattern 123.

[0150] A bulk color filter 90 may be provided on the first conductive pad 81, the light blocking pattern WG, and the first capping pattern 125. The bulk color filter 90 may cover the first conductive pad 81, the light blocking pattern WG, and the first capping pattern 125. A first protective layer 71 may be provided on the bulk color filter 90 to hermetically seal the bulk color filter 90.

[0151] The photoelectric conversion region PD' and the dummy region PD'' may be provided in the optical black area OB of the second substrate 1. In an embodiment, the photoelectric conversion region PD' may be doped with impurities of a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, n-type. The photoelectric conversion region PD' may have a structure similar to that of the photoelectric conversion region PD, but may not be used to perform the operations performed by the photoelectric conversion region PD (e.g., generating an electrical signal from incident light). The dummy region PD'' may not be doped with impurities. The signal generated in the dummy region PD'' may be used as information for removing process noise.

[0152] In the pad area PAD, a second connection structure 130 , a second conductive pad 83 , and a second protection layer 73 may be provided on the second substrate 1 . The second connection structure 130 may include a second connection line 131 , an insulating pattern 133 , and a second capping pattern 135 .

[0153] The second connection line 131 may be provided on the rear surface 1b of the second substrate 1. For example, the second connection line 131 may cover the rear surface 1b and may conformally cover the inner surfaces of the fifth trench TR5 and the sixth trench TR6. The second connection line 131 may be provided to penetrate the photoelectric conversion layer 150 and the upper interconnect layer 221 and connect the photoelectric conversion layer 150 to the interconnect layer 200. For example, the second connection line 131 may contact the interconnect line in the lower interconnect layer 223. Thus, the second connection structure 130 may be electrically connected to the interconnect line in the interconnect layer 200. The second connection line 131 may be formed of or include at least one metal material (e.g., tungsten).

[0154] A second conductive pad 83 may be provided in the fifth trench TR5 to fill the remaining portion of the fifth trench TR5. The second conductive pad 83 may be formed of or include at least one metal material (e.g., aluminum). The second conductive pad 83 may serve as a conductive path for electrical connection to the outside of the image sensor. An insulating pattern 133 may fill the remaining portion of the sixth trench TR6. The insulating pattern 133 may be provided to penetrate the entirety or at least a portion of the interconnect layer 200 and the photoelectric conversion layer 150. A second capping pattern 135 may be provided on the insulating pattern 133.

[0155] Figure 22 is a cross-sectional view illustrating an image sensor according to an embodiment.

[0156] refer to Figure 22, the image sensor 1000a may include a third semiconductor chip CH3 inserted between the first semiconductor chip CH1 and the second semiconductor chip CH2. The third semiconductor chip CH3 may include a third substrate 21, and may further include an intermediate interconnect layer 225 and a third interlayer insulating layer IL3 provided on the third substrate 21. The first chip connection pad CP1 may be provided in the lower portion of the second semiconductor chip CH2. The second chip connection pad CP2 may be provided in the upper portion of the third semiconductor chip CH3. The second chip connection pad CP2 may be in contact with the first chip connection pad CP1. The source follower gate SF and the selection gate SEL may be provided on the third substrate 21. The third semiconductor chip CH3 may be connected to the first semiconductor chip CH1 through a penetration via TSV. The logic transistor LTR may be integrated on the first semiconductor chip CH1. However, the embodiment is not limited to this example, and the logic transistor LTR may be provided on the second semiconductor chip CH2 and / or the third semiconductor chip CH3. In an embodiment, as Figure 22 As shown in , at least one of the source follower gate SF and the select gate SEL may overlap with at least one of the logic transistors LTR. Other portions may have structural features that are the same as or similar to those in one of the above embodiments.

[0157] In this specification, the concept of a single semiconductor chip may be defined as a stacked structure formed by multiple different semiconductor wafers. The interface between the semiconductor chips may not be clearly observed due to the bonding shape, bonding method, or bonding material between the semiconductor chips, and a stacked structure with a blurred interface is not excluded from the concept of a single semiconductor chip.

[0158] In the layout design method according to the embodiment, the logic transistor can be divided into multiple logic transistors, which can be placed in a finger shape. In this case, the width of the active area of ​​the logic transistor can be reduced, the area occupied by the interconnection line can be reduced, and the complexity and difficulty of the process of placing the interconnection structure can be reduced.

[0159] Furthermore, when the logic transistor has a layout designed by the above-described layout design method, the width of the active region can be reduced and the area occupied by the connection line can be reduced, which can increase the integration density of semiconductor devices such as image sensors.

[0160] While example embodiments have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims. Figures 3A to 22 At least two of the examples described.

[0161] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2024-0036068 filed on March 14, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device comprising: a first substrate; a first device isolation portion surrounding a first active region extending in a first direction in the first substrate; a plurality of sub-transistors disposed adjacently on the first active region in the first direction, wherein the plurality of sub-transistors are connected to form a logic transistor; as well as a common node region in the first active region, wherein the common node region is shared by the plurality of sub-transistors, Each of the plurality of sub-transistors comprises: at least three gate electrodes crossing the first active region in a second direction and spaced apart in the first direction, wherein the second direction intersects the first direction; as well as a plurality of source regions and a plurality of drain regions disposed in the first active region adjacent to sidewalls of the at least three gate electrodes, wherein the plurality of source regions and the plurality of drain regions are alternately arranged in the first direction, and The common node region is disposed at the center of the first active region.

2. The semiconductor device according to claim 1 , wherein the plurality of sub-transistors include a plurality of first sub-transistors and a plurality of second sub-transistors adjacently arranged in the first direction, The semiconductor device further comprises: a gate connection line connecting gate electrodes of the plurality of first sub-transistors and the plurality of second sub-transistors, wherein the gate connection line extends in the first direction; a source connection line, connecting the source regions of the plurality of first sub-transistors; a drain connection line, connecting the drain regions of the plurality of second sub-transistors; a first common node line connecting the drain regions of the plurality of first sub-transistors to the common node region; as well as A second common node line connects the source regions of the plurality of second sub-transistors to the common node region.

3. The semiconductor device according to claim 2 , wherein a gate voltage is applied to the gate electrode, wherein a source voltage is applied to the source connection line, wherein a drain voltage is applied to the drain connection line, and The source voltage and the drain voltage are not applied to the first common node line and the second common node line.

4. The semiconductor device according to claim 2 , wherein the source connection line and the second common node line are arranged along a first straight line, wherein the first common node line and the drain connection line are arranged along a second straight line, and The first straight line is spaced apart from the second straight line in the second direction.

5. The semiconductor device according to claim 2, wherein the source connection line and the drain connection line are arranged along a first straight line, wherein the first common node line and the second common node line are arranged along a second straight line and connected to each other, and The first straight line is spaced apart from the second straight line in the second direction.

6. The semiconductor device according to claim 2, further comprising: a first contact plug connecting the common node region to the first common node line; as well as a second contact plug connecting the common node region to the second common node line, The first contact plug is spaced apart from the second contact plug in the second direction.

7. The semiconductor device according to claim 1 , wherein the first active region has a first width in the second direction, wherein each of the at least three gate electrodes has a second width in the second direction, wherein the second width is greater than the first width, Each gate electrode has a third width in the first direction, The at least three gate electrodes are spaced apart by a first distance.

8. An image sensor comprising: A first substrate includes an analog-to-digital converter circuit area, wherein the analog-to-digital converter circuit area includes a plurality of analog-to-digital converter column areas; a device isolation portion surrounding a plurality of active regions in each of the plurality of analog-to-digital converter column regions in the first substrate; a plurality of logic transistors in the plurality of active regions; a plurality of interconnect lines connecting the plurality of logic transistors; a first interlayer insulating layer on the plurality of logic transistors, the plurality of interconnect lines, and the first substrate; a second interlayer insulating layer on the first interlayer insulating layer; a second substrate on the second interlayer insulating layer, wherein the second substrate includes a plurality of photoelectric conversion regions; a deep isolation portion in the second substrate, wherein the deep isolation portion separates the plurality of photoelectric conversion regions; as well as a color filter array and a microlens array sequentially stacked on the second substrate, wherein the plurality of analog-to-digital converter column areas are arranged in a first direction, wherein each of the plurality of analog-to-digital converter column regions and each of the plurality of active regions extends in a second direction intersecting the first direction, wherein, in each of the analog-to-digital converter column regions, the plurality of active regions are arranged in the second direction to form a column, wherein each of the plurality of logic transistors includes M sub-transistors disposed on a corresponding active region among the plurality of active regions in the second direction, wherein M is an integer greater than or equal to two (2), wherein each of the sub-transistors includes N unit transistors arranged in the second direction, wherein N is an integer greater than or equal to three (3), Each of the N unit transistors includes a gate electrode and a source region and a drain region adjacent to the gate electrode. wherein at least one of the source region and the drain region between adjacent unit transistors is shared by the adjacent unit transistors, and The common node region is arranged in the corresponding active region to connect the M sub-transistors.

9. The image sensor according to claim 8, wherein: In each of the unit transistors, the gate electrode crosses the corresponding active region in the first direction, and The gate electrode of each unit transistor has a unit gate width and a unit gate length.

10. The image sensor according to claim 8, wherein the plurality of active regions include a first active region, wherein the first active region includes a first sidewall and a second sidewall opposite to the first sidewall in the second direction, wherein a first logic transistor among the plurality of logic transistors is on the first active area, and wherein the M sub-transistors included in the first logic transistor include a first sub-transistor closest to the first sidewall and a second sub-transistor closest to the second sidewall, and The image sensor further comprises: a gate connection line connecting the gate electrode of each of the unit transistors included in the first logic transistor in the second direction; a source connection line connected to the source region of each unit transistor included in the first sub-transistor; a drain connection line connecting the drain region of each unit transistor included in the second sub-transistor; a first common node line connecting the drain region of each unit transistor included in the first sub-transistor to the common node region; as well as A second common node line connects the source region of each unit transistor included in the second sub-transistor to the common node region.

11. The image sensor according to claim 10, wherein a source voltage is applied to the source connection line, wherein a drain voltage is applied to the drain connection line, and The source voltage and the drain voltage are not applied to the first common node line and the second common node line.

12. The image sensor according to claim 10 , wherein the source connection line and the second common node line are arranged along a first straight line, wherein the first common node line and the drain connection line are arranged along a second straight line, and The first straight line is spaced apart from the second straight line in the first direction.

13. The image sensor according to claim 10, wherein the source connection line and the drain connection line are arranged along a first straight line, wherein the first common node line and the second common node line are arranged along a second straight line and connected to each other, and The first straight line is spaced apart from the second straight line in the first direction.

14. The image sensor according to claim 10, further comprising: a first contact plug connecting the common node region to the first common node line; as well as a second contact plug connecting the common node region to the second common node line, The first contact plug is spaced apart from the second contact plug in the first direction. 15 . The image sensor according to claim 8 , wherein at least one pixel in the plurality of photoelectric conversion regions overlaps with at least one analog-to-digital converter column region in the plurality of analog-to-digital converter column regions.

16. The image sensor according to claim 8, further comprising: a transfer gate electrode, located below the second substrate; a floating diffusion region, disposed in the second substrate; a third substrate between the first interlayer insulating layer and the second interlayer insulating layer; a source follower gate electrode on the third substrate and connected to the floating diffusion region; as well as A select gate electrode is provided on the third substrate.

17. A semiconductor device comprising: a first substrate; a first device isolation portion surrounding a first active region extending in a first direction in the first substrate; a plurality of sub-transistors disposed on the first active region in the first direction, wherein the plurality of sub-transistors are connected to form a logic transistor; a common node region in the first active region, wherein the common node region is shared by the plurality of sub-transistors; as well as a first contact plug and a second contact plug on the common node region, wherein the first contact plug is spaced apart from the second contact plug in a second direction intersecting the first direction, The common node region is located at the center of the first active region.

18. The semiconductor device according to claim 17, wherein each of the plurality of sub-transistors comprises: at least three gate electrodes crossing the first active region in the second direction and spaced apart in the first direction; as well as a plurality of source regions and a plurality of drain regions disposed in the first active region adjacent to sidewalls of the at least three gate electrodes, wherein the plurality of source regions and the plurality of drain regions are alternately arranged in the first direction, wherein the first active region has a first width in the second direction, wherein each of the at least three gate electrodes has a second width in the second direction, wherein the second width is greater than the first width, wherein each of the gate electrodes has a third width in the first direction, and The at least three gate electrodes are spaced apart by a first distance.

19. The semiconductor device according to claim 18, wherein the first active region includes a first sidewall and a second sidewall opposite to the first sidewall in the first direction, and wherein the plurality of sub-transistors include a first sub-transistor closest to the first sidewall and a second sub-transistor closest to the second sidewall, The semiconductor device further comprises: a gate connection line connecting the at least three gate electrodes in the first direction; a source connection line connected to the source region of the first sub-transistor; a drain connection line connected to the drain region of the second sub-transistor; a first common node line connecting the drain region of the first sub-transistor to the common node region; as well as A second common node line connects the source region of the second sub-transistor to the common node region.

20. The semiconductor device according to claim 19, wherein a source voltage is applied to the source connection line, wherein a drain voltage is applied to the drain connection line, and The source voltage and the drain voltage are not applied to the first common node line and the second common node line.

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