Control method and device of single photon avalanche diode, and electronic equipment

Abstract

The invention relates to the technical field of integrated circuits, in particular to a control method and device of a single photon avalanche diode and electronic equipment. The control method of the single-photon avalanche diodes comprises the following steps: controlling a target register so that the plurality of single-photon avalanche diodes are switched to work in a first array mode or a second array mode; acquiring output values of the plurality of single photon avalanche diodes in the first array mode or the second array mode; based on the output values, output information of the plurality of single photon avalanche diodes is determined. The single-photon avalanche diode has the first array mode and the second array mode, so that the single-photon avalanche diode can adapt to various application scenes. Furthermore, according to the invention, the enabling signal of the target register is controlled, so that the single photon avalanche diode is switched to work in the first array mode and the second array mode, and the flexibility of the single photon avalanche diode is further improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a control method, device and electronic equipment for a single-photon avalanche diode. Background Art

[0002] With the rapid development of Direct Time-of-Flight (Dtof) technology, Single Photon Avalanche Diode (SPAD) devices are increasingly used in various fields.

[0003] Existing SPAD control solutions still have certain deficiencies in flexibility and precision. For example, in Dtof applications, the SPAD array needs to be controlled according to different scenario requirements. However, in traditional technologies, the control method of the SPAD array is relatively fixed, and the control mode cannot be flexibly switched according to actual needs, which limits the application scenarios of SPAD devices.

[0004] Therefore, at present, there is an urgent need for a solution that can flexibly control the SPAD array to meet the demand for flexible control of the SPAD array. Summary of the Invention

[0005] Based on this, it is necessary to provide a control method, device and electronic equipment for a single photon avalanche diode that can flexibly control the single photon avalanche diode in order to address the above technical problems.

[0006] In one aspect, a method for controlling a single-photon avalanche diode is provided, the method comprising:

[0007] Controlling the target register to switch the plurality of single-photon avalanche diodes to operate in a first array mode or a second array mode;

[0008] Obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode;

[0009] Based on the output values, output information of the plurality of single photon avalanche diodes is determined.

[0010] In one embodiment, the first array pattern includes a dot matrix pattern, the plurality of single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

[0011] In one embodiment, obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode includes:

[0012] Performing a first logic gate operation on the single photon avalanche diodes located in two adjacent even-numbered rows in each column to obtain a first-level output;

[0013] A second logic gate operation is performed on the plurality of first-stage outputs to obtain a second-stage output, and the second-stage output is determined as an output value of the plurality of single-photon avalanche diodes in the first array mode.

[0014] In one embodiment, performing a first logic gate operation on the single photon avalanche diodes located in two adjacent even-numbered rows in each column to obtain a first-level output includes:

[0015] The first stage output is subjected to a third logic gate operation with 1 or 0.

[0016] In one embodiment, the second array mode includes a linear array mode, the multiple single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

[0017] In one embodiment, obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode includes:

[0018] determining the single photon avalanche diodes located in the same row as a target group;

[0019] The target group is subjected to a third logic gate operation to obtain an output value.

[0020] In one embodiment, controlling the target register to switch the plurality of single-photon avalanche diodes to operate in the first array mode or the second array mode includes:

[0021] Obtaining a target enable signal of the target register;

[0022] Based on the target enable signal, the multiple single-photon avalanche diodes are controlled to switch between the first array mode and the second array mode.

[0023] In one embodiment, after obtaining the output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode, the method further comprises:

[0024] Acquiring the target enable signal;

[0025] determining an inverse signal of the target enable signal;

[0026] The output value and the inverted signal are subjected to a second logic gate operation, and then the first logic gate operation is performed.

[0027] In one aspect, a control device for a single-photon avalanche diode is provided, the device comprising:

[0028] A control module, configured to control a target register so that the plurality of single-photon avalanche diodes switch to operate in a first array mode or a second array mode;

[0029] an acquisition module, configured to acquire output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode;

[0030] A determination module is configured to determine output information of the plurality of single photon avalanche diodes based on the output values.

[0031] In one aspect, an electronic device is provided, which executes any of the aforementioned methods for controlling a single-photon avalanche diode.

[0032] The control method, device and electronic device of the above-mentioned single-photon avalanche diode, by setting the single-photon avalanche diode to have a first array mode and a second array mode, enables the single-photon avalanche diode to adapt to a variety of application scenarios. Furthermore, in the present application, by controlling the enable signal of the target register, the single-photon avalanche diode is switched to work in the first array mode and the second array mode, thereby increasing the flexibility of the single-photon avalanche diode. Specifically, in the first array mode (lattice mode), column switching is supported. In the second array mode (linear array mode), row switching is supported to achieve batch control. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic flow chart of a control method for a single-photon avalanche diode provided in one embodiment;

[0034] Figure 2 A schematic diagram of a dot matrix pattern provided in one embodiment;

[0035] Figure 3 A schematic diagram of a linear array mode provided in one embodiment;

[0036] Figure 4 A flow chart of single-photon avalanche diode mode switching provided in one embodiment;

[0037] Figure 5 A schematic diagram of a circuit principle of a control method for a single-photon avalanche diode provided in one embodiment;

[0038] Figure 6 A schematic diagram of a control method for a single-photon avalanche diode in a lattice mode provided in one embodiment;

[0039] Figure 7A schematic diagram of the circuit principle of a method for controlling a single-photon avalanche diode in a lattice mode provided in one embodiment;

[0040] Figure 8 A schematic diagram of a control method for a single-photon avalanche diode in a linear array mode provided in one embodiment;

[0041] Figure 9 A schematic diagram of the circuit principle of a single-photon avalanche diode in a linear array mode provided in one embodiment;

[0042] Figure 10 A schematic flow chart of a method for preventing crosstalk in a single-photon avalanche diode provided in one embodiment;

[0043] Figure 11 A schematic diagram of a circuit for preventing crosstalk in a single-photon avalanche diode provided in one embodiment;

[0044] Figure 12 A schematic diagram of a circuit for preventing crosstalk in a single-photon avalanche diode provided in another embodiment;

[0045] Figure 13 A schematic diagram of a control device for a single-photon avalanche diode provided in one embodiment. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0047] In one embodiment, Figure 1 As shown, a control method for a single-photon avalanche diode is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0048] Step S100: controlling a target register to enable a plurality of single-photon avalanche diodes to switch to operate in a first array mode or a second array mode.

[0049] Step S200: obtaining output values ​​of a plurality of single-photon avalanche diodes in a first array mode or a second array mode.

[0050] Step S400: Determine output information of a plurality of single photon avalanche diodes based on the output values.

[0051] In step S100, the first array pattern may include a dot pattern. For example, Figure 2As shown in FIG, in a dot matrix mode, multiple single photon avalanche diodes can be arranged in vertical and horizontal directions to form a single photon avalanche diode array. Figure 3 As shown, the second array mode may include a linear array mode. As an example, in the linear array mode, a plurality of single photon avalanche diodes may be arranged along a straight line.

[0052] In addition, this embodiment may also include a third array mode, a fourth array mode, etc.

[0053] The target register can be electrically connected to a plurality of single-photon avalanche diodes. Furthermore, the target register can control the enabling of the dot array mode and the linear array mode respectively according to the use environment requirements, so that the plurality of single-photon avalanche diodes can switch to work in the first array mode or the second array mode. Figure 4 Specifically, step S100 may include:

[0054] Step S110: Acquire a target enable signal of a target register.

[0055] Step S120: Based on the target enable signal, control the multiple single-photon avalanche diodes to switch between the first array mode and the second array mode.

[0056] In steps S110 to S120, the target enable signal of the target register may be reg_point_en or reg_line_en. Specifically, when the target enable signal is reg_point_en, the multiple single-photon avalanche diodes operate in a first array mode (lattice mode). When the target enable signal is reg_line_en, the multiple single-photon avalanche diodes operate in a second array mode (lattice mode).

[0057] Of course, in this embodiment, it is possible to control the two modes so that only one of them can be enabled at the same time, thereby ensuring the stability of the output information of the multiple single-photon avalanche diodes.

[0058] In step S200, Figure 2As shown, in a possible example, when multiple single-photon avalanche diodes are in the first array mode (lattice mode), the multiple single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n (columns) × 2n (rows) single-photon avalanche diodes, where n is a positive integer. Further, each single-photon avalanche diode can be marked. Specifically, the marking can be incremented starting from the lower left corner of the single-photon avalanche diode array and finally ending at the upper right corner of the single-photon avalanche diode array. Each single-photon avalanche diode can have an output value, and the same number represents a first logic gate (AND gate) generating a 1-bit signal (output value). For example, all single-photon avalanche diodes with a number of 0 generate spad_out[0] through a fixed logic gate (and / or / not) operation.

[0059] In another possible example, Figure 3 As shown, when multiple single-photon avalanche diodes are in the second array mode (linear array mode), multiple single-photon avalanche diodes are configured as a single-photon avalanche diode array, and multiple single-photon avalanche diodes located in the same row (for example, n single-photon avalanche diodes) can generate a 1-bit signal (output value).

[0060] In step S400, Figure 5 As shown, the output values ​​can be sent to a time-to-digital converter (TDC) to generate output information of multiple single-photon avalanche diodes. As an example, in this case, in the first array mode (dot matrix mode) and the second array mode (line matrix mode), 2n output values ​​are generated, and the output values ​​can be output in the form of spad_out[2n-1:0].

[0061] In this embodiment, by setting the single-photon avalanche diode to have a first array mode and a second array mode, the single-photon avalanche diode can adapt to a variety of application scenarios. Furthermore, in this embodiment, by controlling the enable signal of the target register, the single-photon avalanche diode is switched between the first array mode and the second array mode, thereby increasing the flexibility of the single-photon avalanche diode. Specifically, in the first array mode (lattice mode), column switching is supported. In the second array mode (line array mode), row switching is supported to achieve batch control.

[0062] In one possible example, Figure 6 and Figure 7 As shown, in the first array mode (lattice mode), step S200 includes:

[0063] Step S210: performing a first logic gate operation on the single photon avalanche diodes in two adjacent even-numbered rows in each column to obtain a first-level output.

[0064] Step S211: performing a second logic gate operation on the plurality of first-stage outputs to obtain second-stage outputs, and determining the second-stage outputs as output values ​​of the plurality of single-photon avalanche diodes in the first array mode.

[0065] In step S210 to step S211 , the first logic gate may include an AND gate, and the second logic gate may include an OR gate.

[0066] In this example, first, the single-photon avalanche diodes in two adjacent even-numbered rows in each column can be subjected to a first-level logic gate (AND) operation to obtain the first-level output, thereby avoiding overlapping operations and ensuring that each single-photon avalanche diode participates in a first-level logic gate operation, ensuring that the number of logic gates passed by each pixel signal is exactly the same. Secondly, in this example, by performing the first logic gate (AND) operation on the single-photon avalanche diodes, the noise resistance of the single-photon avalanche diodes is increased, suppressing random noise.

[0067] In addition, after step S210, the following steps may be included:

[0068] Step S2101: Perform a third logic gate operation on the first stage output and 1 or 0.

[0069] This step balances the paths, ensuring that all signals pass through the same number of logic gates before reaching the final output. Specifically, for example, when the value "1" is selected, the third logic gate can be an AND gate. When the value "0" is selected, the third logic gate can be an OR gate. This adds one level of logic delay without changing the first-stage output, ensuring that all signals pass through the same number of logic gates before reaching the final output.

[0070] In another possible example, Figure 8 and Figure 9 As shown, in the second array mode (linear array mode), step S200 includes:

[0071] Step S220: determining the single photon avalanche diodes located in the same row as a target group.

[0072] Step S221: performing a third logic gate operation on the target group to obtain an output value.

[0073] In steps S220 and S221, for an n×2n array, all single-photon avalanche diodes in the same row are grouped into a target group, resulting in 2n target groups, each containing n single-photon avalanche diodes. In this case, each target group has equal-length circuits, simplifying wiring.

[0074] The third logic gate may include an AND gate or an OR gate. Specifically, when the third logic gate is an AND gate, the noise immunity of the single-photon avalanche diode can be increased. When the third logic gate is an OR gate, the sensitivity of the single-photon avalanche diode can be increased.

[0075] In one embodiment, Figure 10 、 Figure 11 and Figure 12 As shown, after step S200, the following steps are included:

[0076] Step S300: Acquire a target enable signal.

[0077] Step S310: Determine the inverse signal of the target enable signal.

[0078] Step S320 : performing a second logic gate operation on the output value and the inverted signal, and then performing a first logic gate operation.

[0079] In steps S300 to S320 , as an example, if the target enable signal of the first array mode or the second array mode is 1, the inverted signal of the target enable signal is 0. The first logic gate may include an AND gate, and the second logic gate may include an OR gate.

[0080] In this embodiment, the output value and the inverted signal are subjected to a second logic gate operation, and then the first logic gate operation is performed, so that the first array mode and the second array mode are mutually exclusive, that is, it is ensured that "reg_point_en" and "reg_line_en" are not 1 at the same time, thereby improving the accuracy of the output value and preventing crosstalk.

[0081] The following is an exemplary description of the control method of the single-photon avalanche diode provided by the present application.

[0082] In the first embodiment, during configuration of the first array mode (dot matrix mode), the dot matrix enable signal a is set to 1, and the control register signal b for the second array mode (line matrix mode) is set to 0. Afterward, the first array mode (dot matrix mode) is entered. Register configuration is performed via an external I2C master, fully enabling n columns of single-photon avalanche diodes. All single-photon avalanche diodes are fully enabled, ultimately outputting a 2n-bit signal. Alternatively, following the "0 if 0" principle, n single-photon avalanche diodes in the same position in alternate rows can generate a 1-bit signal.

[0083] In a second embodiment, during configuration of the second array mode (linear mode), the enable signal a of the first array mode (dot matrix mode) is set to 0, and the control register signal b of the second array mode (linear mode) is set to 1, thereby entering the second array mode (linear mode). Register configuration is performed via an external I2C master, enabling all 2n rows of single-photon avalanche diodes to fully activate, ultimately outputting a 2n-bit signal. Alternatively, the principle of "0 if there is 0, 0 if there is 0" can be followed, with each row of n single-photon avalanche diodes generating a 1-bit signal.

[0084] In a third embodiment, during crosstalk detection, the second array mode (linear array mode) can be entered, and single-photon avalanche diode_crosstalk1, single-photon avalanche diode_crosstalk2, and single-photon avalanche diode_crosstalk0 can all be configured to 1 via I2C. The crosstalk value is then calculated using C2, C1, and C0 to achieve crosstalk detection and control in the single-photon avalanche diode array.

[0085] It should be understood that although the steps in the flowcharts in the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The order of execution of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0086] In one embodiment, Figure 13 As shown, a control device for a single-photon avalanche diode is provided, comprising: a control module, an acquisition module and a determination module, wherein:

[0087] The control module is used to control the target register so that the multiple single-photon avalanche diodes switch to operate in the first array mode or the second array mode.

[0088] An acquisition module is used to acquire output values ​​of the multiple single-photon avalanche diodes in the first array mode or the second array mode.

[0089] A determination module is configured to determine output information of the plurality of single photon avalanche diodes based on the output values.

[0090] In one embodiment, the first array mode includes a dot matrix mode, the plurality of single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

[0091] In one embodiment, the acquisition module is used to perform a first logic gate operation on the single-photon avalanche diodes located in two adjacent even rows in each column to obtain a first-level output; perform a second logic gate operation on multiple first-level outputs to obtain a second-level output, and determine the second-level output as the output value of multiple single-photon avalanche diodes in the first array mode.

[0092] In one embodiment, the acquisition module is configured to perform a third logic gate operation on the first stage output and 1 or 0.

[0093] In one embodiment, the second array mode includes a linear array mode, the plurality of single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

[0094] In one embodiment, the acquisition module is used to determine the single photon avalanche diodes located in the same row as a target group; perform a third logic gate operation on the target group to obtain an output value.

[0095] In one embodiment, the control module is configured to obtain a target enable signal from a target register; and based on the target enable signal, control the plurality of single-photon avalanche diodes to switch between operating in a first array mode or a second array mode.

[0096] In one embodiment, the control device for a single-photon avalanche diode further includes a second acquisition module, a second determination module, and an operation module. The second acquisition module is configured to acquire a target enable signal, and the second determination module is configured to determine an inverse signal of the target enable signal, and to perform a second logic gate operation on the output value and the inverse signal before performing the first logic gate operation.

[0097] The specific definition of the control device of the single-photon avalanche diode can be found in the definition of the control method of the single-photon avalanche diode above, and will not be repeated here. The various modules in the above-mentioned control device of the single-photon avalanche diode can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of the above-mentioned modules.

[0098] In one embodiment, an electronic device is provided, which executes the control method of the single-photon avalanche diode provided in one or more embodiments of the present application.

[0099] As an example, electronic devices may include smartphones / tablets, AR / VR devices, medical diagnostic equipment, industrial detection equipment, etc. For example, in an embodiment, the mismatch between different SPADs can be controlled within 50ps, and crosstalk detection is supported.

[0100] In one embodiment, a computer device is provided, which may be a server. The computer device includes a processor, a memory, and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store control data of a single-photon avalanche diode. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a control method for a single-photon avalanche diode is implemented.

[0101] In one embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal via wired or wireless communication, where the wireless communication may be achieved via Wi-Fi, a mobile cellular network, NFC (near field communication), or other technologies. When the computer program is executed by the processor, a method for controlling a single-photon avalanche diode is implemented. The display screen of the computer device may be a liquid crystal display or an electronic ink display screen, and the input device of the computer device may be a touch layer covering the display screen, or may be a key, trackball, or touchpad provided on the computer device housing, or may be an external keyboard, touchpad, or mouse.

[0102] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0103] Step S100: controlling a target register to enable a plurality of single-photon avalanche diodes to switch to operate in a first array mode or a second array mode.

[0104] Step S200: obtaining output values ​​of a plurality of single-photon avalanche diodes in a first array mode or a second array mode.

[0105] Step S400: Determine output information of a plurality of single photon avalanche diodes based on the output values.

[0106] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0107] Step S110: Acquire a target enable signal of a target register.

[0108] Step S120: Based on the target enable signal, control the multiple single-photon avalanche diodes to switch between the first array mode and the second array mode.

[0109] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0110] Step S210: performing a first logic gate operation on the single photon avalanche diodes in two adjacent even-numbered rows in each column to obtain a first-level output.

[0111] Step S211: performing a second logic gate operation on the plurality of first-stage outputs to obtain second-stage outputs, and determining the second-stage outputs as output values ​​of the plurality of single-photon avalanche diodes in the first array mode.

[0112] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0113] Step S2101: Perform a third logic gate operation on the first stage output and 1 or 0.

[0114] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0115] Step S220: determining the single photon avalanche diodes located in the same row as a target group.

[0116] Step S221: performing a third logic gate operation on the target group to obtain an output value.

[0117] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0118] Step S300: Acquire a target enable signal.

[0119] Step S310: Determine the inverse signal of the target enable signal.

[0120] Step S320 : performing a second logic gate operation on the output value and the inverted signal, and then performing a first logic gate operation.

[0121] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0122] Step S100: controlling a target register to enable a plurality of single-photon avalanche diodes to switch to operate in a first array mode or a second array mode.

[0123] Step S200: obtaining output values ​​of a plurality of single-photon avalanche diodes in a first array mode or a second array mode.

[0124] Step S400: Determine output information of a plurality of single photon avalanche diodes based on the output values.

[0125] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0126] Step S110: Acquire a target enable signal of a target register.

[0127] Step S120: Based on the target enable signal, control the multiple single-photon avalanche diodes to switch between the first array mode and the second array mode.

[0128] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0129] Step S210: performing a first logic gate operation on the single photon avalanche diodes in two adjacent even-numbered rows in each column to obtain a first-level output.

[0130] Step S211: performing a second logic gate operation on the plurality of first-stage outputs to obtain second-stage outputs, and determining the second-stage outputs as output values ​​of the plurality of single-photon avalanche diodes in the first array mode.

[0131] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0132] Step S2101: Perform a third logic gate operation on the first stage output and 1 or 0.

[0133] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0134] Step S220: determining the single photon avalanche diodes located in the same row as a target group.

[0135] Step S221: performing a third logic gate operation on the target group to obtain an output value.

[0136] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0137] Step S300: Acquire a target enable signal.

[0138] Step S310: Determine the inverse signal of the target enable signal.

[0139] Step S320 : performing a second logic gate operation on the output value and the inverted signal, and then performing a first logic gate operation.

[0140] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0141] Step S100: controlling a target register to enable a plurality of single-photon avalanche diodes to switch to operate in a first array mode or a second array mode.

[0142] Step S200: obtaining output values ​​of a plurality of single-photon avalanche diodes in a first array mode or a second array mode.

[0143] Step S400: Determine output information of a plurality of single photon avalanche diodes based on the output values.

[0144] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0145] Step S110: Acquire a target enable signal of a target register.

[0146] Step S120: Based on the target enable signal, control the multiple single-photon avalanche diodes to switch between the first array mode and the second array mode.

[0147] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0148] Step S210: performing a first logic gate operation on the single photon avalanche diodes in two adjacent even-numbered rows in each column to obtain a first-level output.

[0149] Step S211: performing a second logic gate operation on the plurality of first-stage outputs to obtain second-stage outputs, and determining the second-stage outputs as output values ​​of the plurality of single-photon avalanche diodes in the first array mode.

[0150] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0151] Step S2101: Perform a third logic gate operation on the first stage output and 1 or 0.

[0152] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0153] Step S220: determining the single photon avalanche diodes located in the same row as a target group.

[0154] Step S221: performing a third logic gate operation on the target group to obtain an output value.

[0155] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0156] Step S300: Acquire a target enable signal.

[0157] Step S310: Determine the inverse signal of the target enable signal.

[0158] Step S320 : performing a second logic gate operation on the output value and the inverted signal, and then performing a first logic gate operation.

[0159] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0160] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A control method for a single-photon avalanche diode, characterized in that: The method comprises: Controlling the target register to switch the plurality of single-photon avalanche diodes to operate in a first array mode or a second array mode; Obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode; Based on the output values, output information of the plurality of single photon avalanche diodes is determined.

2. The control method of the single photon avalanche diode according to claim 1, characterized in that: The first array mode includes a dot matrix mode, the plurality of single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

3. The control method of the single photon avalanche diode according to claim 2, characterized in that: The obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode includes: Performing a first logic gate operation on the single photon avalanche diodes located in two adjacent even-numbered rows in each column to obtain a first-level output; A second logic gate operation is performed on the plurality of first-stage outputs to obtain a second-stage output, and the second-stage output is determined as an output value of the plurality of single-photon avalanche diodes in the first array mode.

4. The control method of a single photon avalanche diode according to claim 2, characterized in that: After performing a first logic gate operation on the single photon avalanche diodes located in two adjacent even-numbered rows in each column to obtain a first-level output, the method includes: The first stage output is subjected to a third logic gate operation with 1 or 0.

5. The control method of a single photon avalanche diode according to claim 1, characterized in that: The second array mode includes a linear array mode, the plurality of single-photon avalanche diodes are configured as a single-photon avalanche diode array, and the single-photon avalanche diode array includes n×2n single-photon avalanche diodes, where n is a positive integer.

6. The control method of the single photon avalanche diode according to claim 5, characterized in that: The obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode includes: determining the single photon avalanche diodes located in the same row as a target group; The target group is subjected to a third logic gate operation to obtain an output value.

7. The control method of a single photon avalanche diode according to claim 1, characterized in that: The controlling target register so that the plurality of single-photon avalanche diodes switch to operate in the first array mode or the second array mode includes: Obtaining a target enable signal of the target register; Based on the target enable signal, the multiple single-photon avalanche diodes are controlled to switch between the first array mode and the second array mode.

8. The control method of a single photon avalanche diode according to claim 7, characterized in that: After obtaining output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode, the method further comprises: Acquiring the target enable signal; determining an inverse signal of the target enable signal; The output value and the inverted signal are subjected to a second logic gate operation, and then the first logic gate operation is performed.

9. A control device for a single-photon avalanche diode, characterized in that: The device comprises: A control module, configured to control a target register so that the plurality of single-photon avalanche diodes switch to operate in a first array mode or a second array mode; an acquisition module, configured to acquire output values ​​of the plurality of single-photon avalanche diodes in the first array mode or the second array mode; A determination module is configured to determine output information of the plurality of single photon avalanche diodes based on the output values.

10. An electronic device, characterized in that: The electronic device executes the control method of the single-photon avalanche diode according to any one of claims 1 to 8.

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