Display device

Abstract

The display device includes: a first region and a second region each including a plurality of pixels; and a plurality of wirings connected to the plurality of pixels, respectively, to transmit signals; wherein the number of pixels per unit area in the second region is less than the number of pixels per unit area in the first region, and the number of wirings per unit area in the second region is less than the number of wirings per unit area in the first region.

Description

[0001] This application is a divisional application of the patent application with application number 202011244799.0 and title “Display Device” filed on November 10, 2020.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2020-0024388, filed on February 27, 2020, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0004] The present disclosure relates to a display device. Background Art

[0005] A display device is a device for displaying images and includes a liquid crystal display ("LCD"), an organic light emitting diode ("OLED") display, etc. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, and various terminals.

[0006] A display device may include a plurality of pixels, and within each pixel, various elements such as transistors and capacitors and various wirings capable of supplying signals to these elements may be positioned. It may not be easy to ensure transmittance through these elements and wirings.

[0007] In display devices, components such as cameras may be placed in areas surrounding the area where the screen is displayed. Generally, pixels are not formed in the areas where these components are placed, and thus the screen may not be displayed. Therefore, black holes may be visible in some areas of the screen, which may cause interference when viewing images. Summary of the Invention

[0008] Exemplary embodiments will provide a display device in which a screen can be displayed in some areas of the display device in which components such as a camera are arranged.

[0009] In addition, exemplary embodiments are to provide a display device that can increase transmittance of a corresponding region so as not to affect the function of a component and have high brightness so that the corresponding region is not distinguished from other adjacent regions.

[0010] According to an exemplary embodiment, a display device includes: a first area and a second area, each including a plurality of pixels; and a plurality of wirings, respectively connected to the plurality of pixels to transmit signals, wherein the number of pixels per unit area in the second area is smaller than the number of pixels per unit area in the first area, and the number of wirings per unit area in the second area is smaller than the number of wirings per unit area in the first area.

[0011] The plurality of wirings may include: a plurality of first initialization voltage supply lines that supply a first initialization voltage; and a plurality of second initialization voltage supply lines that supply a second initialization voltage, and the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the second region may be less than the sum of the number of the first initialization voltage supply lines and the second initialization voltage supply lines per unit area in the first region.

[0012] The number of pixels per unit area in the second region may be more than one-sixth and less than half of the number of pixels per unit area in the first region, and the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the second region may be more than one-sixth of the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region and less than the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region.

[0013] The number of pixels per unit area in the second region may be one quarter of the number of pixels per unit area in the first region, and the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the second region may be half of the sum of the number of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region.

[0014] Each of the multiple pixels may include: a light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; a third transistor connected between a second electrode of the driving transistor and a gate electrode of the driving transistor, wherein the second electrode of the driving transistor is connected to the light emitting diode; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; and a seventh transistor connected between the light emitting diode and a second initialization voltage line to which a second initialization voltage is applied.

[0015] The number of pixels per unit area in the second region may be one-fourth the number of pixels per unit area in the first region, the number of first initialization voltage supply lines per unit area in the second region may be one-fourth the sum of the numbers of first initialization voltage supply lines and second initialization voltage supply lines per unit area in the first region, and the second initialization voltage supply line may not be arranged in the second region.

[0016] Each of the multiple pixels in the first area may include: a light emitting diode, connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor, connected between the driving voltage line and the light emitting diode; a second transistor, connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; a third transistor, connected between a second electrode of the driving transistor and a gate electrode of the driving transistor, wherein the second electrode of the driving transistor is connected to the light emitting diode; a fourth transistor, connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; and a seventh transistor, connected between the light emitting diode and the second initialization voltage line to which a second initialization voltage is applied, and each of the multiple pixels in the second area may include: a light emitting diode, a driving transistor, a second transistor, a third transistor, a fourth transistor; and a seventh transistor, connected between the light emitting diode and the first initialization voltage line.

[0017] The display device according to an exemplary embodiment may further include at least one of a camera, a proximity sensor, an illumination sensor, a gesture sensor, a motion sensor, a fingerprint sensor, and a biometric sensor, or a combination thereof, arranged in the second area.

[0018] A display device according to an exemplary embodiment includes: a plurality of pixels; a plurality of first scan lines connected to the plurality of pixels to transmit first scan signals; a plurality of second scan lines connected to the plurality of pixels to transmit second scan signals; a plurality of initialization control lines connected to the plurality of pixels to transmit initialization control signals; and a connection wiring connecting at least one initialization control line of the plurality of initialization control lines and at least one second scan line of the plurality of second scan lines.

[0019] The plurality of pixels may be arranged in a matrix along row and column directions, and the second scan line connected to the pixels of the first row of the matrix may be connected to the initialization control line connected to the pixels of the nth row of the matrix.

[0020] The display device according to an exemplary embodiment may further include: a scan driver that generates a first scan signal to be transmitted through a first scan line; and an initialization drive circuit that generates an initialization control signal to be transmitted through an initialization control line, and the initialization drive circuit may transmit the initialization control signal to the second scan line as a second scan signal, and the second scan signal applied to the second scan line connected to the pixels of the first row may have the same timing as the initialization control signal applied to the initialization control line connected to the pixels of the nth row.

[0021] The second scan signal applied to the second scan line connected to the pixels of the first row may have the same timing as the initialization control signal applied to the initialization control line connected to the pixels of the ninth row in the matrix form.

[0022] The second scan line connected to the pixels of the first row can be connected to the second scan line connected to the pixels of the second row in matrix form, and the initialization control line connected to the pixels of the first row can be connected to the initialization control line connected to the pixels of the second row.

[0023] The display device may further include: a first region and a second region, each including a plurality of pixels, wherein the number of pixels per unit area in the second region may be smaller than the number of pixels per unit area in the first region, and the number of second scan lines per unit area in the second region may be smaller than the number of second scan lines per unit area in the first region.

[0024] The number of second scan lines per unit area in the second region may be half the number of second scan lines per unit area in the first region.

[0025] The number of initialization control lines per unit area in the second region may be smaller than the number of initialization control lines per unit area in the first region.

[0026] The plurality of pixels may be arranged in a matrix along row and column directions, pixels of two adjacent rows of the matrix may be connected to the same initialization control line, and the pixels of the two adjacent rows may be vertically symmetrical with respect to the initialization control line.

[0027] A display device according to an exemplary embodiment includes: a first region and a second region, each including a plurality of pixels, and the number of pixels per unit area in the second region is smaller than the number of pixels per unit area in the first region, wherein each of the plurality of pixels includes: a light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; and a storage capacitor connected between the driving voltage line and a gate electrode of the driving transistor, and a width-to-length ratio of a channel of the driving transistor in the second region is different from a width-to-length ratio of a channel of the driving transistor in the first region.

[0028] A ratio of a width to a length of a channel of the driving transistor in the second region may be greater than a ratio of a width to a length of the channel of the driving transistor in the first region.

[0029] A ratio of a width to a length of a channel of the driving transistor in the second region may be 155% or more and 206% or less of a ratio of a width to a length of the channel of the driving transistor in the first region.

[0030] The display device according to an exemplary embodiment may further include: a substrate arranged in the first region and the second region; and a light blocking member arranged on the substrate, wherein the light blocking member may not be arranged in the first region.

[0031] The multiple pixels may include: a first pixel representing red, a second pixel representing green, and a third pixel representing blue, the capacitance of the storage capacitor of the first pixel in the second region may be greater than 86% and less than 140% of the capacitance of the storage capacitor of the first pixel in the first region, and the capacitance of the auxiliary capacitor of the first pixel in the second region may be greater than 27% and less than 37% of the capacitance of the storage capacitor of the first pixel in the first region.

[0032] The capacitance of the storage capacitor of the second pixel in the second region may be greater than 63% and less than 90% of the capacitance of the storage capacitor of the second pixel in the first region, and the capacitance of the auxiliary capacitor of the second pixel in the second region may be greater than 27% and less than 33% of the capacitance of the storage capacitor of the second pixel in the first region.

[0033] The capacitance of the storage capacitor of the third pixel in the second region may be greater than 81% and less than 137% of the capacitance of the storage capacitor of the third pixel in the first region, and the capacitance of the auxiliary capacitor of the third pixel in the second region may be greater than 26% and less than 37% of the capacitance of the storage capacitor of the third pixel in the first region.

[0034] According to an exemplary embodiment, a display device includes: a first area and a second area, each including a plurality of pixels; a substrate arranged in the first area and the second area; and a light shielding member arranged in the second area, wherein the number of pixels per unit area in the second area is smaller than the number of pixels per unit area in the first area, and each of the plurality of pixels includes: a light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between a first electrode of the driving transistor and a data line to which a data voltage is applied, wherein the first electrode of the driving transistor is connected to the driving voltage line; and a storage capacitor connected between the driving voltage line and a gate electrode of the driving transistor, and the light shielding member is arranged between the substrate and the gate electrode of the driving transistor in the second area to form an auxiliary capacitor.

[0035] According to exemplary embodiments, a screen may be displayed in some areas of a display device in which components such as a camera are arranged.

[0036] In addition, the transmittance of the corresponding area may be increased so as not to affect the function of the component, or the brightness of the corresponding area may be increased so as not to be distinguished from other adjacent areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a top plan view schematically illustrating a display device according to an exemplary embodiment.

[0038] Figure 2 is a top plan view illustrating some pixels arranged in a first area of ​​a display device according to an exemplary embodiment.

[0039] Figure 3 is a circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0040] Figure 4 is a top plan view illustrating some pixels arranged in a second area of ​​a display device according to an exemplary embodiment.

[0041] Figure 5 is a top plan view illustrating some pixels arranged in a second area of ​​a display device according to an exemplary embodiment.

[0042] Figure 6 is a circuit diagram of a pixel arranged in the second area of ​​a display device according to an exemplary embodiment.

[0043] Figure 7 is a view illustrating a connection relationship of some pixels and wirings of a display device according to an exemplary embodiment.

[0044] Figure 8 is a signal timing diagram illustrating a plurality of signals applied to two adjacent pixel rows of a display device according to an exemplary embodiment.

[0045] Figure 9 is a signal timing diagram illustrating a relationship of signals applied to some pixels of a display device according to an exemplary embodiment.

[0046] Figure 10 is a view illustrating a connection relationship of some pixels and wirings of a display device according to another exemplary embodiment.

[0047] Figure 11 is a top plan view of some pixels of a first area of ​​a display device according to an exemplary embodiment.

[0048] Figure 12 It is along Figure 11 A cross-sectional view taken along line XII-XII'.

[0049] Figure 13 It is along Figure 11 A cross-sectional view taken along line XIII-XIII'.

[0050] Figures 14 to 19 1 and 2 are top views sequentially illustrating some pixels of a first region in a manufacturing order of a display device according to an exemplary embodiment.

[0051] Figure 20 is a top plan view illustrating some pixels of a first area of ​​a display device according to an exemplary embodiment.

[0052] Figure 21 is a top plan view illustrating some pixels of a second area of ​​a display device according to an exemplary embodiment.

[0053] Figure 22 It is along Figure 21 A cross-sectional view taken along line XXII-XXII'.

[0054] Figure 23 It is along Figure 21 A cross-sectional view taken along line XXIII-XXIII'.

[0055] Figures 24 to 291 and 2 are top views sequentially illustrating some pixels of a second region in a manufacturing order of a display device according to an exemplary embodiment.

[0056] Figure 30 is a top plan view illustrating some pixels of a second area of ​​a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0057] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

[0058] Parts irrelevant to the description will be omitted to clearly describe the present invention, and the same elements will be denoted by the same reference numerals throughout the specification.

[0059] Furthermore, the sizes and thicknesses of the components shown in the drawings are arbitrarily given for better understanding and ease of description, and the present invention is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0060] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present. Furthermore, in this specification, the terms "on" or "above" refer to being located above or below an object part, and do not necessarily refer to being located on the upper side of an object part based on the direction of gravity.

[0061] In addition, unless explicitly described to the contrary, the term “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0062] Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross section obtained by vertically cutting the object portion is viewed from the side.

[0063] The terms used herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include plural forms including "at least one." "At least one" should not be interpreted as limited to "one." "Or" means "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] It will be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0065] First, refer to Figure 1 A display apparatus 1000 according to an exemplary embodiment is described.

[0066] Figure 1 is a top view schematically illustrating a display apparatus 1000 according to an exemplary embodiment.

[0067] like Figure 1 As shown in , the display device 1000 according to an exemplary embodiment may include a display area DA in which an image is displayed and a peripheral area PA in which a driving circuit for driving the display area DA is installed and in which no image is displayed.

[0068] The display area DA may have a generally rectangular shape with relatively long sides and relatively short sides, and the corners of the display area DA may have a shape with chamfered curved surfaces. However, the shape of the display area DA is merely an example and may be modified to various shapes. A plurality of pixels PX are arranged in the display area DA to display an image. Some areas around the edge of the display area DA may not have pixels PX arranged therein and may not display an image.

[0069] A plurality of pixels PX may be arranged in a matrix along row and column directions and may receive image signals to display images accordingly. However, the arrangement of the plurality of pixels PX is not limited thereto and may be variously modified in another exemplary embodiment. Although not shown, the display device 1000 may further include a plurality of wirings. The wirings may be composed of a plurality of scan lines, a plurality of control lines, a plurality of data lines, and a plurality of drive voltage lines, etc. These wirings may transmit scan signals, control signals, data signals, and drive voltages. The plurality of wirings may be positioned to intersect each other in the row direction or the column direction.

[0070] In addition, each pixel PX may include a capacitor connected to a plurality of wirings, a plurality of transistors, and at least one light emitting diode (LED). That is, the display device 1000 may be an organic light emitting display device. However, the type of the display device 1000 is not limited thereto, and in another exemplary embodiment, it may be made of various types of display devices. For example, the display device 1000 may be a liquid crystal display device, an electrophoretic display device, or an electrowetting display device. In addition, the display device 1000 according to the exemplary embodiment may also be a next generation display device such as a micro light emitting diode (LED) (Micro LED) display device, a quantum dot light emitting diode ("QLED") display device, and a quantum dot organic light emitting diode ("QD-OLED") display device.

[0071] The display area DA may include a first area DA1 and a second area DA2. The first area DA1 and the second area DA2 may each include a plurality of pixels PX. The density of the pixels PX arranged in the first area DA1 may differ from the density of the pixels PX arranged in the second area DA2. As used herein, the density of the pixels PX refers to the number of pixels PX per unit area. That is, the number of pixels PX per unit area in the first area DA1 may differ from the number of pixels PX per unit area in the second area DA2. The number of pixels PX per unit area in the second area DA2 may be less than the number of pixels PX per unit area in the first area DA1. In addition, the density of the wiring arranged in the first area DA1 may differ from the density of the wiring arranged in the second area DA2. As used herein, the density of the wiring refers to the number of wirings per unit area. That is, the number of wirings per unit area in the first area DA1 may differ from the number of wirings per unit area in the second area DA2. The number of wirings per unit area in the second area DA2 may be less than the number of wirings per unit area in the first area DA1.

[0072] The second area DA2 may be surrounded by the first area DA1. The area of ​​the first area DA1 may be relatively larger than the area of ​​the second area DA2. The first area DA1 may mainly play the role of displaying images emitted from the pixels PX in the first area DA1, and the second area DA2 may have other functions and the role of displaying images. For example, a camera may be further arranged in the second area DA2. The camera may include a plurality of non-emitting elements, and these non-emitting elements may be arranged under the pixel PX. In the second area DA2, in addition to the camera, at least one of a proximity sensor, an illumination sensor, a posture sensor, a motion sensor, a fingerprint recognition sensor, and a biometric sensor, or a combination thereof may be arranged. In addition, other parts with various functions may be arranged in the second area DA2. In Figure 1, the display area DA is shown as including one second area DA2, but in another exemplary embodiment, a plurality of second areas DA2 may be included.

[0073] The peripheral area PA may be arranged adjacent to one edge of the display area DA. For example, the peripheral area PA may be connected to the lower edge of the display area DA. However, in another exemplary embodiment, the position of the peripheral area PA may be variously changed. For example, the peripheral area PA may be arranged at both edges of the display area DA. The driver circuit chip IC may be arranged in the peripheral area PA. The driver circuit chip IC is connected to the plurality of pixels PX arranged in the display area DA via wiring, thereby transmitting various signals to the plurality of pixels PX. For example, the driver circuit chip IC may supply scan signals, control signals, data signals, drive voltages, and the like.

[0074] Although not shown, a flexible circuit board may be further disposed in the peripheral area PA. A circuit for controlling driving of the display device 1000 may be designed on the flexible circuit board and may be attached to the peripheral area PA.

[0075] Next, refer to Figure 2 The first area DA1 of the display apparatus 1000 according to an exemplary embodiment is described.

[0076] Figure 2 is a top plan view illustrating some pixels PX arranged in the first area DA1 of the display device 1000 according to an exemplary embodiment.

[0077] like Figure 2 As shown in FIG, in the first area DA1, a plurality of pixels PX and a plurality of wirings 127, 128, 171, 1127, and 1128 connected to the plurality of pixels PX to transmit signals may be arranged.

[0078] Figure 2 The pixels PX of the first area DA1 shown in FIG are arranged in a matrix along four rows and sixteen columns, and the number of pixels PX and the number of rows and columns are merely examples, and the present invention is not limited thereto. The plurality of pixels PX may include a first pixel PX1 that displays a first color, a second pixel PX2 that displays a second color, and a third pixel PX3 that displays a third color. For example, the first color may be red, the second color may be green, and the third color may be blue. The colors displayed by the plurality of pixels PX are not limited thereto, and in another exemplary embodiment, at least one of cyan, magenta, yellow, and a white-based color may be displayed. Here, one first pixel PX1, two second pixels PX2, and one third pixel PX3 may form a pixel group PXGr.

[0079] The plurality of wirings may include a plurality of data lines 171 supplying a data voltage DATA, a plurality of first initialization voltage supply lines 1127 and a plurality of first initialization voltage lines 127 supplying a first initialization voltage VINT, and a plurality of second initialization voltage supply lines 1128 and a plurality of second initialization voltage lines 128 supplying a second initialization voltage AINT.

[0080] The data line 171 is arranged for each pixel column and connected to each pixel PX in the pixel column. That is, the pixels PX arranged in the same column can be connected to the same data line 171 to receive the data voltage DATA.

[0081] The first initialization voltage supply line 1127 may be arranged every four pixel columns. The first initialization voltage line 127 may connect the first initialization voltage supply line 1127 and each pixel PX. That is, the first initialization voltage VINT supplied by the first initialization voltage supply line 1127 may be transmitted to each pixel PX through the first initialization voltage line 127. For example, the first initialization voltage supply line 1127 may be arranged between the second pixel column and the third pixel column, between the sixth pixel column and the seventh pixel column, between the tenth pixel column and the eleventh pixel column, and between the fourteenth pixel column and the fifteenth pixel column, respectively. However, this is merely an example, and in another exemplary embodiment, the arrangement of the first initialization voltage supply line 1127 may be variously changed. A plurality of first initialization voltage lines 127 are connected to the first initialization voltage supply line 1127, and a plurality of pixels PX are connected to the first initialization voltage line 127.

[0082] The second initialization voltage supply line 1128 can be arranged every four pixel columns. The second initialization voltage line 128 can connect the second initialization voltage supply line 1128 and each pixel PX. That is, the second initialization voltage AINT supplied by the second initialization voltage supply line 1128 can be transmitted to each pixel PX through the second initialization voltage line 128. For example, the second initialization voltage supply line 1128 can be arranged between the fourth pixel column and the fifth pixel column, between the eighth pixel column and the ninth pixel column, between the twelfth pixel column and the thirteenth pixel column, and between the sixteenth pixel column and the seventeenth pixel column, respectively. However, this is merely an example, and in another exemplary embodiment, the arrangement of the second initialization voltage supply line 1128 can be variously changed. Multiple second initialization voltage lines 128 are connected to the second initialization voltage supply line 1128, and multiple pixels PX are connected to the second initialization voltage line 128.

[0083] In the following, reference Figure 3 Describe the connection relationship between a pixel PX and each wiring.

[0084] Figure 3is a circuit diagram of a pixel PX of the display device 1000 according to an exemplary embodiment.

[0085] like Figure 3 As shown in , one pixel PX of the display device 1000 according to an exemplary embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741, a storage capacitor Cst, a boosting capacitor Cboost, and a light emitting diode LED.

[0086] A plurality of wirings 127, 128, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of wirings include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, a light emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0087] The first scan line 151 is connected to a gate driver (not shown) and transmits a first scan signal GW to the second transistor T2. The second scan line 152 may be applied with a voltage having a polarity opposite to that of a voltage applied to the first scan line 151 as a signal of the first scan line 151. For example, when a high voltage is applied to the first scan line 151, a low voltage may be applied to the second scan line 152. The second scan line 152 transmits a second scan signal GC to the third transistor T3.

[0088] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. The bypass control line 154 transmits the bypass signal GB to the seventh transistor T7. The bypass control line 154 may correspond to the first scan line 151 of the next stage. The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0089] The data line 171 is a wiring that transmits a data voltage DATA generated from a data driver (not shown), and the brightness emitted by the light emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0090] The driving voltage line 172 transmits a driving voltage ELVDD. The first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage AINT. The common voltage line 741 applies a common voltage ELVSS to the cathode of the light-emitting diode LED. In this exemplary embodiment, the voltages applied to the driving voltage line 172, the first and second initialization voltage lines 127 and 128, and the common voltage line 741 may each be a constant voltage.

[0091] Next, the structures and connection relationships of the plurality of transistors are described in detail.

[0092] The driving transistor T1 may have p-type transistor characteristics and may include a polycrystalline semiconductor. It is a transistor for adjusting the magnitude of the current output to the anode of the light-emitting diode LED based on the data voltage DATA applied to the gate electrode of the driving transistor T1. Since the brightness of the light-emitting diode LED is adjusted based on the magnitude of the driving current output to the anode of the light-emitting diode LED, the brightness of the light-emitting diode LED can be adjusted based on the data voltage DATA applied to the pixel PX. To this end, the first electrode of the driving transistor T1 is arranged to receive the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode of the driving transistor T1 is connected to the second electrode of the second transistor T2, thereby also receiving the data voltage DATA. The second electrode of the driving transistor T1 is arranged to output current to the light-emitting diode LED and is connected to the anode of the light-emitting diode LED via the sixth transistor T6. In addition, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. The gate electrode of the driving transistor T1 is connected to one electrode of the storage capacitor Cst (hereinafter also referred to as the second storage electrode). Therefore, the voltage of the gate electrode of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and accordingly, the driving current output by the driving transistor T1 changes. In addition, the storage capacitor Cst is also used to keep the voltage of the gate electrode of the driving transistor T1 constant within one frame.

[0093] The second transistor T2 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The second transistor T2 is a transistor in the pixel PX that receives the data voltage DATA. The gate electrode of the second transistor T2 is connected to the first scan line 151 and the first electrode of the boost capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. When the second transistor T2 is turned on by the low voltage of the first scan signal GW transmitted via the first scan line 151, the data voltage DATA transmitted via the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0094] The third transistor T3 may have n-type transistor characteristics and may include an oxide semiconductor. The third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1. Therefore, it is a transistor that transmits the compensation voltage, which is a result of the data voltage DATA being changed by the driving transistor T1, to the second storage electrode of the storage capacitor Cst. The gate electrode of the third transistor T3 is connected to the second scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boost capacitor Cboost. The third transistor T3 is turned on by the high voltage of the second scan signal GC transmitted via the second scan line 152, connecting the gate electrode of the driving transistor T1 to the second electrode of the driving transistor T1, so that the voltage applied to the first electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst for storage in the storage capacitor Cst.

[0095] The fourth transistor T4 may have n-type transistor characteristics and may include an oxide semiconductor. The fourth transistor T4 is used to initialize the gate electrode of the drive transistor T1 and the second storage electrode of the storage capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the drive transistor T1, and the second electrode of the boost capacitor Cboost via the second electrode of the third transistor T3. The fourth transistor T4 is turned on by the high voltage of the initialization control signal GI transmitted through the initialization control line 153, and in this case, the first initialization voltage VINT is transmitted to the gate electrode of the drive transistor T1 and the second storage electrode of the storage capacitor Cst. Accordingly, the voltage of the gate electrode of the drive transistor T1 and the storage capacitor Cst is initialized.

[0096] The fifth transistor T5 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the light emission control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0097] The sixth transistor T6 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The sixth transistor T6 is used to transmit the driving current output from the driving transistor T1 to the light-emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the light emission control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode of the light-emitting diode LED.

[0098] The seventh transistor T7 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The seventh transistor T7 is used to initialize the anode of the light-emitting diode LED. The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the anode of the light-emitting diode LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. When the seventh transistor T7 is turned on by the low voltage of the bypass signal GB, the second initialization voltage AINT is applied to the anode of the light-emitting diode LED to be initialized.

[0099] It is described above that one pixel PX includes seven transistors (T1 to T7), one storage capacitor Cst, and one boost capacitor Cboost, however the present invention is not limited thereto, and in another exemplary embodiment, the number of transistors, the number of capacitors, and their connection relationship may be variously changed.

[0100] In this exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor. In addition, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. However, the present invention is not limited thereto, and in another exemplary embodiment, at least one of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor.

[0101] In this exemplary embodiment, since the third transistor T3 and the fourth transistor T4 may include a semiconductor material different from that of the driving transistor T1, driving can be performed more stably and reliability can be improved. However, the present invention is not limited thereto, and in another exemplary embodiment, all transistors included in one pixel PX may include polycrystalline semiconductors. In addition, in yet another exemplary embodiment, all transistors included in one pixel PX may include oxide semiconductors.

[0102] As described above, when a high voltage is applied to the first scan line 151, a low voltage is applied to the second scan line 152, and when a low voltage is applied to the first scan line 151, a high voltage is simultaneously applied to the second scan line 152. That is, since the second scan signal GC applied to the second scan line 152 is a signal of opposite phase to the first scan signal GW applied to the first scan line 151, the gate voltage of the driving transistor T1 is lowered after data is written. Conversely, the first scan signal GW raises the gate voltage of the driving transistor T1. Therefore, when writing the black voltage, the black voltage may be lowered. In this exemplary embodiment, since the boost capacitor Cboost is arranged between the first scan line 151, to which the first scan signal GW is applied, and the gate electrode of the driving transistor T1, the gate voltage of the driving transistor T1 is raised, allowing the black voltage to be stably output. As the capacitance of the boost capacitor Cboost increases, the gate voltage of the driving transistor T1 can be increased. By adjusting the capacitance of the boost capacitor Cboost, the gate voltage of the driving transistor T1 can be controlled.

[0103] Next, refer to Figure 4 The second area DA2 of the display apparatus 1000 according to an exemplary embodiment is described.

[0104] Figure 4 is a top plan view illustrating some pixels PX arranged in the second area DA2 of the display device 1000 according to an exemplary embodiment.

[0105] like Figure 4 As shown in FIG, in the second area DA2, a plurality of pixels PX and a plurality of wirings 127, 128, 171, 1127, and 1128 connected to the plurality of pixels PX to transmit signals may be arranged.

[0106] Figure 4Some pixels PX in the second area DA2 shown in FIG are arranged along two rows and eight columns, and the number of pixels PX and the number of rows and columns are merely examples, and the present invention is not limited thereto. For comparison with the arrangement of the pixels PX in the first area DA1, the dotted lines corresponding to the pixels PX indicate areas in the second area DA2 where no pixels PX are actually arranged. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Four pixels PX (e.g., one first pixel PX1, two second pixels PX2, and one third pixel PX3) may form a pixel group PXGr. The two pixel groups PXGr may be positioned adjacent to each other, and two other pixel groups PXGr may be arranged to be spaced apart from the two pixel groups PXGr. That is, the two pixel groups PXGr may be surrounded by an area where no pixels PX are arranged. However, in another exemplary embodiment, the arrangement of the pixels PX in the second area DA2 may be variously changed.

[0107] Within the same area, the first area DA1 may include sixteen pixel groups PXGr, and the second area DA2 may include four pixel groups PXGr. Accordingly, within the same area, the first area DA1 may include sixty-four pixels PX, and the second area DA2 may include sixteen pixels PX. That is, the number of pixels PX per unit area in the second area DA2 is less than the number of pixels PX per unit area in the first area DA1. In this case, the number of pixels PX per unit area in the second area DA2 may be greater than approximately one-sixth and less than approximately one-half of the number of pixels PX per unit area in the first area DA1. For example, the number of pixels PX per unit area in the second area DA2 may be approximately one-quarter of the number of pixels PX per unit area in the first area DA1. As described above, by reducing the number of pixels PX arranged in the second area DA2, the transmittance of the second area DA2 can be increased compared to the first area DA1. Therefore, the influence exerted by the pixels PX on other portions arranged in the second area DA2 can be reduced.

[0108] The plurality of wirings may include a plurality of data lines 171 , a plurality of first initialization voltage lines 127 , a plurality of first initialization voltage supply lines 1127 , a plurality of second initialization voltage lines 128 , and a plurality of second initialization voltage supply lines 1128 .

[0109] A data line 171 is arranged for each pixel column and is connected to each pixel PX in the pixel column. Even if no pixel PX is arranged, a data line 171 may be arranged. In the same area, the first area DA1 may include sixteen data lines 171, and the second area DA2 may also include sixteen data lines 171. That is, the number of data lines 171 per unit area in the second area DA2 may be substantially the same as the number of data lines 171 per unit area in the first area DA1.

[0110] The first initialization voltage supply line 1127 may be arranged every eight pixel columns. The first initialization voltage line 127 may connect the first initialization voltage supply line 1127 and each pixel PX. That is, the first initialization voltage VINT supplied by the first initialization voltage supply line 1127 may be transmitted to each pixel PX through the first initialization voltage line 127. For example, the first initialization voltage supply line 1127 may be arranged between the second pixel column and the third pixel column and between the tenth pixel column and the eleventh pixel column. However, this is merely an example, and in another exemplary embodiment, the arrangement of the first initialization voltage supply line 1127 may be variously changed. A plurality of first initialization voltage lines 127 are connected to the first initialization voltage supply line 1127, and a plurality of pixels PX are connected to the first initialization voltage line 127.

[0111] Within the same area, four first initialization voltage supply lines 1127 may be arranged in the first area DA1, and two first initialization voltage supply lines 1127 may be arranged in the second area DA2. That is, the number of first initialization voltage supply lines 1127 per unit area in the second area DA2 is less than the number of first initialization voltage supply lines 1127 per unit area in the first area DA1. In this case, the number of first initialization voltage supply lines 1127 per unit area in the second area DA2 may be approximately one-sixth or more and less than approximately one-times the number of first initialization voltage supply lines 1127 per unit area in the first area DA1. For example, the number of first initialization voltage supply lines 1127 per unit area in the second area DA2 may be approximately half the number of first initialization voltage supply lines 1127 per unit area in the first area DA1.

[0112] Furthermore, within the same area, sixteen first initialization voltage lines 127 may be arranged in the first area DA1, and four first initialization voltage lines 127 may be arranged in the second area DA2. That is, the number of first initialization voltage lines 127 per unit area in the second area DA2 is smaller than the number of first initialization voltage lines 127 per unit area in the first area DA1. For example, the number of first initialization voltage lines 127 per unit area in the second area DA2 may be approximately one-fourth the number of first initialization voltage lines 127 per unit area in the first area DA1.

[0113] The second initialization voltage supply line 1128 may be arranged every eight pixel columns. The second initialization voltage line 128 may connect the second initialization voltage supply line 1128 and each pixel PX. That is, the second initialization voltage AINT supplied by the second initialization voltage supply line 1128 may be transmitted to each pixel PX through the second initialization voltage line 128. For example, the second initialization voltage supply line 1128 may be arranged between the fourth pixel column and the fifth pixel column and between the twelfth pixel column and the thirteenth pixel column, respectively. However, this is merely an example, and in another exemplary embodiment, the arrangement of the second initialization voltage supply line 1128 may be variously changed. A plurality of second initialization voltage lines 128 are connected to the second initialization voltage supply line 1128, and a plurality of pixels PX are connected to the second initialization voltage line 128.

[0114] Within the same area, four second initialization voltage supply lines 1128 may be arranged in the first area DA1, and two second initialization voltage supply lines 1128 may be arranged in the second area DA2. That is, the number of second initialization voltage supply lines 1128 per unit area in the second area DA2 is less than the number of second initialization voltage supply lines 1128 per unit area in the first area DA1. In this case, the number of second initialization voltage supply lines 1128 per unit area in the second area DA2 may be approximately one-sixth or more and less than approximately one-times the number of second initialization voltage supply lines 1128 per unit area in the first area DA1. For example, the number of second initialization voltage supply lines 1128 per unit area in the second area DA2 may be approximately half the number of second initialization voltage supply lines 1128 per unit area in the first area DA1.

[0115] Furthermore, within the same area, sixteen second initialization voltage lines 128 may be arranged in the first area DA1, and four second initialization voltage lines 128 may be arranged in the second area DA2. That is, the number of second initialization voltage lines 128 per unit area in the second area DA2 is smaller than the number of second initialization voltage lines 128 per unit area in the first area DA1. For example, the number of second initialization voltage lines 128 per unit area in the second area DA2 may be approximately one-fourth the number of second initialization voltage lines 128 per unit area in the first area DA1.

[0116] That is, the number of wirings per unit area in the second area DA2 is smaller than the number of wirings per unit area in the first area DA1. The sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the second area DA2 may be greater than approximately one-sixth and less than approximately one-time the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the first area DA1. For example, the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the second area DA2 may be approximately half the sum of the number of first initialization voltage supply lines 1127 and the number of second initialization voltage supply lines 1128 per unit area in the first area DA1. As described above, by reducing the number of wirings arranged in the second area DA2, the transmittance of the second area DA2 can be increased compared to the first area DA1. Therefore, the influence exerted by the pixel PX on other portions arranged in the second area DA2 can be reduced.

[0117] Next, refer to Figure 5 and Figure 6 A display apparatus 1000 according to an exemplary embodiment is described.

[0118] Because according to Figure 5 and Figure 6 The display device 1000 of the exemplary embodiment shown in FIG. 1 has the same Figures 1 to 4 The display device 1000 of the exemplary embodiment shown in FIG has many parts in common, so descriptions of the same parts are omitted. Figures 1 to 4 The previous exemplary embodiment is different from that in that the second initialization voltage line 128 and the second initialization voltage supply line 1128 are not arranged in the second area DA2, and this is further described.

[0119] Figure 5is a top plan view showing some pixels PX arranged in the second area DA2 of the display device 1000 according to an exemplary embodiment, and Figure 6 is a circuit diagram of a pixel PX arranged in the second area DA2 of the display device 1000 according to an exemplary embodiment.

[0120] like Figure 5 As shown in FIG, in the second area DA2, a plurality of pixels PX and a plurality of wirings 127, 171, and 1127 connected to the plurality of pixels PX to transmit signals may be arranged.

[0121] In this exemplary embodiment, the arrangement of the pixels PX in the first and second areas DA1 and DA2 may be substantially the same as that in the previous exemplary embodiment. Therefore, the number of pixels PX per unit area in the second area DA2 is smaller than the number of pixels PX per unit area in the first area DA1. For example, the number of pixels PX per unit area in the second area DA2 may be approximately one-fourth the number of pixels PX per unit area in the first area DA1.

[0122] The plurality of wirings may include a plurality of data lines 171, a plurality of first initialization voltage lines 127, and a plurality of first initialization voltage supply lines 1127. In the previous exemplary embodiment, the plurality of second initialization voltage lines 128 and the plurality of second initialization voltage supply lines 1128 were arranged in the first area DA1 and the second area DA2. However, in the present exemplary embodiment, the second initialization voltage lines 128 and the second initialization voltage supply lines 1128 are not arranged in the second area DA2. That is, in the present exemplary embodiment, the second initialization voltage lines 128 and the second initialization voltage supply lines 1128 are located in the first area DA1 rather than in the second area DA2.

[0123] The number of wirings per unit area in the second area DA2 is smaller than the number of wirings per unit area in the first area DA1. The number of first initialization voltage supply lines 1127 per unit area in the second area DA2 may be greater than or equal to about one-sixth and less than one time the sum of the number of first initialization voltage supply lines 1127 and second initialization voltage supply lines 1128 per unit area in the first area DA1.

[0124] For example, the number of first initialization voltage supply lines 1127 per unit area in the second area DA2 may be approximately one-fourth the sum of the number of first initialization voltage supply lines 1127 and second initialization voltage supply lines 1128 per unit area in the first area DA1. As described above, by further reducing the number of wirings arranged in the second area DA2, the transmittance of the second area DA2 can be further increased compared to the first area DA1. Therefore, the influence exerted by the pixel PX on other portions arranged in the second area DA2 can be reduced.

[0125] Since the second initialization voltage line 128 and the second initialization voltage supply line 1128 are not arranged in the second area DA2, the circuit of the pixel PX arranged in the second area DA2 may be different from the circuit of the pixel PX positioned in the first area DA1. Figure 6 A connection relationship between one pixel PX arranged in the second area DA2 and each wiring is described.

[0126] like Figure 6 As shown in , one pixel PX of the display device 1000 according to an exemplary embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to several wirings 127, 151, 152, 153, 154, 155, 171, 172, and 741, a storage capacitor Cst, a boosting capacitor Cboost, and a light emitting diode LED.

[0127] A plurality of wirings 127, 151, 152, 153, 154, 155, 171, 172, and 741 are connected to one pixel PX. The plurality of wirings include a first initialization voltage line 127, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, a light emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0128] The pixels PX arranged in the first area DA1 are connected to the second initialization voltage line 128, but the pixels PX arranged in the second area DA2 are not connected to the second initialization voltage line 128. Therefore, the seventh transistor T7 of the pixel PX arranged in the first area DA1 is connected to the second initialization voltage line 128, but the seventh transistor T7 of the pixel PX arranged in the second area DA2 is not connected to the second initialization voltage line 128. The second electrode of the seventh transistor T7 of the pixel PX arranged in the second area DA2 can be connected to the first initialization voltage line 127. If the seventh transistor T7 is turned on by the low voltage of the bypass signal GB, the first initialization voltage VINT is applied to the anode of the light emitting diode LED to be initialized.

[0129] Next, refer to Figures 7 to 9 A display apparatus 1000 according to an exemplary embodiment is described.

[0130] according to Figures 7 to 9 The display device 1000 of the exemplary embodiment shown in FIG. Figures 1 to 6 Most of the display device 1000 of the exemplary embodiment shown in FIG is the same, so that descriptions of the same parts are omitted. This exemplary embodiment is different from the previous exemplary embodiment in that the initialization control line 153 can be connected to the second scan line 152, and this is further described.

[0131] First, refer to Figure 7 Connections of pixels PX and wirings of the display device 1000 according to an exemplary embodiment are described.

[0132] Figure 7 1 is a view illustrating a connection relationship of some pixels PX and wirings of the display device 1000 according to an exemplary embodiment.

[0133] like Figure 7 As shown in FIG, a display device 1000 according to an exemplary embodiment includes a plurality of pixels PX and a plurality of wirings 151, 152, 153, and 155 connected to the plurality of pixels PX to transmit signals. Figure 7 Only some of the plurality of wirings connected to each pixel PX are shown, and the connection relationship between one pixel PX and each wiring of the display device 1000 according to the present exemplary embodiment may have Figure 3 or Figure 6 In the form of the circuit diagram shown in .

[0134] The display area DA may include a first area DA1 and a second area DA2. The first area DA1 and the second area DA2 may each include a plurality of pixels PX. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3, and four pixels PX (e.g., one first pixel PX1, two second pixels PX2, and one third pixel PX3) may form a pixel group PXGr.

[0135] In the present exemplary embodiment, the arrangement of the pixels PX in the first and second areas DA1 and DA2 may be substantially the same as that in the previous exemplary embodiment. Therefore, the number of pixels PX per unit area in the second area DA2 is smaller than that in the first area DA1. Figure 7Some pixel columns arranged in the first area DA1 and some pixel columns arranged in the second area DA2 are shown side by side. Pixels PX may not be arranged in the second area DA2 corresponding to the third and fourth pixel rows of the first area DA1, and pixels PX may not be arranged in the second area DA2 corresponding to the seventh and eighth pixel rows of the first area DA1.

[0136] The plurality of wirings may include a first scan line 151 , a second scan line 152 , an initialization control line 153 , and a light emitting control line 155 .

[0137] The first scan line 151 is arranged for each pixel row and is connected to each pixel PX in the pixel row. That is, the pixels PX arranged in the same row are connected to the same first scan line 151 to receive the first scan signals GW[1] to GW

[10] . The display device 1000 according to the exemplary embodiment may further include a scan driver GWD that generates the first scan signals GW[1] to GW

[10] to be transmitted through the first scan line 151. The scan driver GWD may include a plurality of stages GW_1 to GW_10. Each of the stages GW_1 to GW_10 of the scan driver GWD may correspond to each pixel row. Each of the stages GW_1 to GW_10 of the scan driver GWD is connected to each pixel PX through the first scan line 151, thereby transmitting the first scan signals GW[1] to GW

[10] to each pixel PX. The first scan signals GW[1] to GW

[10] may be sequentially applied to each pixel row.

[0138] The light emitting control line 155 is arranged for each pixel row and connected to each pixel PX. That is, the pixels PX arranged in the same row are connected to the same light emitting control line 155 to receive the light emitting control signals EM[1] to EM

[10] . The display device 1000 according to the exemplary embodiment may further include a light emitting driver EMD that generates the light emitting control signals EM[1] to EM

[10] to be transmitted through the light emitting control line 155. The light emitting driver EMD may include a plurality of stages EM_1 to EM_10. Each of the stages EM_1 to EM_10 of the light emitting driver EMD may correspond to each pixel row. Each of the stages EM_1 to EM_10 of the light emitting driver EMD may be connected to each pixel PX through the light emitting control line 155 to transmit the light emitting control signals EM[1] to EM

[10] to each pixel PX.

[0139] The initialization control line 153 is connected to each pixel PX. The pixels PX arranged in the same row can be connected to the same initialization control line 153 and transmit initialization control signals GI[1 / 2] to GI[9 / 10]. The same initialization control signal GI[1 / 2] to GI[9 / 10] can be applied to two adjacent pixel rows. Therefore, the initialization control line 153 connected to the pixel PX in the first row can be connected to the initialization control line 153 connected to the pixel PX in the second row. Similarly, the initialization control lines 153 connected to the pixels PX in the third and fourth rows can be connected to each other, and the initialization control lines 153 connected to the pixels PX in the fifth and sixth rows can be connected to each other. In the case of the third and fourth rows, the pixels PX are arranged in the first area DA1, however, the pixels PX are not arranged in the second area DA2. Therefore, in the second area DA2, a single initialization control line 153 can pass between the third and fourth rows.

[0140] The display device 1000 according to an exemplary embodiment may further include an initialization drive circuit GID that generates initialization control signals GI[1 / 2] to GI[9 / 10] to be transmitted through the initialization control line 153. The initialization drive circuit GID may include a plurality of stages GI_1 / 2 to GI_9 / 10. Each of the stages GI_1 / 2 to GI_9 / 10 of the initialization drive circuit GID may correspond to every two pixel rows. Each of the stages GI_1 / 2 to GI_9 / 10 of the initialization drive circuit GID is connected to each pixel PX through the initialization control line 153, thereby transmitting the initialization control signals GI[1 / 2] to GI[9 / 10] to each pixel PX.

[0141] The second scan line 152 is connected to each pixel PX. The pixels PX arranged in the same row are connected to the same second scan line 152, thereby receiving the second scan signals GC[1 / 2] to GC[9 / 10] through the second scan line 152. In this case, the same second scan signal GC[1 / 2] to GC[9 / 10] can be applied to two adjacent pixel rows. Therefore, the second scan line 152 connected to the pixels PX in the first row can be connected to the second scan line 152 connected to the pixels PX in the second row. Similarly, the second scan lines 152 connected to the pixels PX in the third and fourth rows can be connected to each other. The second scan lines 152 connected to the pixels PX in the fifth and sixth rows can be connected to each other. In the case of the third and fourth rows, the pixels PX are arranged in the first area DA1, but the pixels PX are not arranged in the second area DA2. In this case, the second scan line 152 is not arranged in the portion of the second area DA2 corresponding to the third and fourth rows. Therefore, the number of second scan lines 152 per unit area in the second area DA2 is less than the number of second scan lines 152 per unit area in the first area DA1. For example, the number of second scan lines 152 per unit area in the second area DA2 may be approximately half the number of second scan lines 152 per unit area in the first area DA1. As described above, by reducing the number of wirings arranged in the second area DA2, the transmittance of the second area DA2 can be increased compared to the first area DA1. Therefore, the influence of the pixel PX on other portions arranged in the second area DA2 can be reduced.

[0142] The display device 1000 according to this exemplary embodiment may not include a separate driving unit for generating the second scan signals GC[1 / 2] to GC[9 / 10]. Instead, the display device 1000 according to the exemplary embodiment may include a connection wiring CL that connects at least one of the plurality of initialization control lines 153 and at least one of the plurality of second scan lines 152. For example, the connection wiring CL may connect a second scan line 152 connected to pixels PX in the first row among the plurality of second scan lines 152 and an initialization control line 153 connected to pixels PX in the ninth row among the plurality of initialization control lines 153. This is merely an example, and in another exemplary embodiment, the second scan line 152 connected to pixels PX in the first row may be connected to an initialization control line 153 connected to pixels PX in rows other than the ninth row. In other words, the second scan line 152 connected to pixels PX in the first row among the plurality of second scan lines 152 may be connected to the initialization control line 153 connected to pixels PX in the nth row among the plurality of initialization control lines 153, and the value of n may be variously set. The second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX in the first row via the connection wiring CL can have the same timing as the initialization control signal GI[9 / 10] applied to the initialization control line 153 connected to the pixels PX in the ninth row. That is, the second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX in the first row can have the same timing as the initialization control signal applied to the initialization control line 153 connected to the pixels PX in the nth row, and the value of n can be variously set. Therefore, the initialization drive circuit GID can transmit the initialization control signals GI[1 / 2] to GI[9 / 10] as the second scan signals GC[1 / 2] to GC[9 / 10] to the second scan line 152.

[0143] Next, refer to Figure 8 and Figure 9 Describes the signal applied to each trace.

[0144] Figure 8 is a signal timing diagram illustrating a plurality of signals applied to two adjacent pixel rows of the display device 1000 according to an exemplary embodiment, and Figure 9 is a signal timing diagram illustrating a relationship of signals applied to some pixels PX of the display device 1000 according to an exemplary embodiment.

[0145] like Figure 8 and Figure 9As shown in , after the high-voltage light-emitting control signals EM[1] and EM[2] are applied to the pixels PX in the first and second rows, the high-voltage initialization control signal GI[1 / 2] may be applied to the pixels PX in the first and second rows. Next, the initialization control signal GI[1 / 2] may be changed to a low voltage, and the low-voltage first scan signals GW[1] and GW[2] may be sequentially applied to the pixels PX in the first and second rows. In addition, the high-voltage second scan signal GC[1 / 2] may be applied to the pixels PX in the first and second rows. At this time, the time for which the initialization control signal GI[1 / 2] is maintained at a high voltage is similar to the time for which the second scan signal GC[1 / 2] is maintained at a high voltage, but there is a difference in the timing of applying the signals. That is, when the initialization control signal GI[1 / 2] has been shifted for a predetermined time, the second scan signal GC[1 / 2] may be obtained. The initialization control signal GI[1 / 2] applied to the pixels PX in the third and fourth rows may have a value that is shifted from the initialization control signal GI[1 / 2] applied to the pixels PX in the first and second rows. The second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX in the first and second rows may have substantially the same timing as the initialization control signal GI[9 / 10] applied to the initialization control line 153 connected to the pixels PX in the ninth and tenth rows. However, this is merely an example, and depending on the design of each pixel PX, the second scan signal GC[1 / 2] applied to the second scan line 152 connected to the pixels PX in the first and second rows may have substantially the same timing as the initialization control signal GC[1 / 2] applied to the initialization control line 153 connected to the pixels PX in the eleventh and twelfth rows.

[0146] Next, refer to Figure 10 A display apparatus 1000 according to another exemplary embodiment is described.

[0147] according to Figure 10 The display device 1000 of the exemplary embodiment shown in FIG. Figures 7 to 9 Most of the display device 1000 of the exemplary embodiment shown in FIG is the same, so that descriptions of the same parts are omitted. This exemplary embodiment is different from the previous exemplary embodiment in that the number of initialization control lines 153 in the second area DA2 is further reduced, and this is further described below.

[0148] Figure 10 1 is a view illustrating a connection relationship of some pixels PX and wirings of the display device 1000 according to an exemplary embodiment.

[0149] like Figure 10As shown in FIG, a display device 1000 according to an exemplary embodiment includes a plurality of pixels PX and a plurality of wirings 151, 152, 153, and 155 connected to the plurality of pixels PX to transmit signals.

[0150] The display area DA may include a first area DA1 and a second area DA2 , and the number of pixels PX per unit area in the second area DA2 is smaller than the number of pixels PX per unit area in the first area DA1 .

[0151] The plurality of wirings may include a first scan line 151 , a second scan line 152 , an initialization control line 153 , and a light emitting control line 155 .

[0152] An initialization control line 153 is connected to each pixel PX. In the case of the previous exemplary embodiment, in the second area DA2, the pixels PX in the first row and the pixels PX in the second row can be connected to different initialization control lines 153, and the initialization control line 153 connected to the pixels PX in the first row can be connected to the initialization control line 153 connected to the pixels PX in the second row. In the case of the present exemplary embodiment, in the second area DA2, the pixels PX in the first row and the pixels PX in the second row are connected to the same initialization control line 153. In this case, the initialization control line 153 can be arranged between the pixels PX in the first row and the pixels PX in the second row. Similarly, in the second area DA2, the pixels PX in the fifth row and the pixels PX in the sixth row are connected to the same initialization control line 153. In this case, the initialization control line 153 can be arranged between the pixels PX in the fifth row and the pixels PX in the sixth row. In other words, the pixels PX in two adjacent rows in the second area DA2 can be connected to the same initialization control line 153. Therefore, the number of initialization control lines 153 per unit area in the second area DA2 is less than the number of initialization control lines 153 per unit area in the first area DA1. For example, the number of initialization control lines 153 per unit area in the second area DA2 may be approximately half the number of initialization control lines 153 per unit area in the first area DA1. In this case, the pixels PX of two adjacent rows in the second area DA2 may have a flip structure that is symmetrical up and down based on the initialization control lines 153.

[0153] Next, refer to Figures 11 to 30 A display apparatus 1000 according to an exemplary embodiment is described.

[0154] according to Figures 11 to 30 The display device 1000 of the exemplary embodiment shown in FIG. Figures 1 to 10Most of the display device 1000 of the exemplary embodiment shown in FIG is identical, so that descriptions of the identical parts are omitted. This exemplary embodiment differs from the previous exemplary embodiment in that the channel length of the driving transistor T1 and the capacitances of the storage capacitors Cst1 and Cst2 are different in the first and second areas DA1 and DA2, and this is further described below.

[0155] First, refer to Figures 11 to 19 The pixels PX of the first area DA1 of the display apparatus 1000 according to an exemplary embodiment are described.

[0156] Figure 11 is a top plan view of some pixels PX of the first area DA1 of the display device 1000 according to an exemplary embodiment, Figure 12 It is along Figure 11 A cross-sectional view taken along line XII-XII', Figure 13 It is along Figure 11 A cross-sectional view taken along line XIII-XIII', and Figures 14 to 19 1000 are top plan views sequentially illustrating some pixels PX of the first area DA1 in a manufacturing order of the display device 1000 according to an exemplary embodiment.

[0157] Figures 11 to 19 Two adjacent pixels PX among a plurality of pixels PX arranged in the first area DA1 of the display device 1000 according to an exemplary embodiment are shown, and Figure 3 However, this exemplary embodiment is not limited thereto, and may have a configuration modified to correspond to the circuit diagram shown in FIG. Figure 6 The pixel structure corresponds to the circuit diagram shown in FIG. 1 , or may be variously changed in another exemplary embodiment.

[0158] like Figures 11 to 19 As shown in , a polycrystalline semiconductor including a channel 1132 , a first electrode 1131 , and a second electrode 1133 of a driving transistor T1 may be disposed on a substrate 110 . Figure 14 In addition to the channel 1132 , the first electrode 1131 , and the second electrode 1133 of the driving transistor T1 , the polycrystalline semiconductor may further include channels, first electrodes, and second electrodes of the second, fifth, sixth, and seventh transistors T2 , T5 , T6 , and T7 .

[0159] The channel 1132 of the driving transistor T1 can be formed into a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto, and various changes can be made in another exemplary embodiment. For example, the channel 1132 of the driving transistor T1 can be bent into a different shape, or can be formed into a rod shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 can be arranged on both sides of the channel 1132 of the driving transistor T1. The first electrode 1131 of the driving transistor T1 extends up and down on a plane, so that the downward extending portion can be connected to the second electrode of the second transistor T2, and the upward extending portion can be connected to the second electrode of the fifth transistor T5. The second electrode 1133 of the driving transistor T1 extends upward on a plane and can be connected to the first electrode of the sixth transistor T6.

[0160] The buffer layer 111 may be disposed between the substrate 110 and the polycrystalline semiconductor including the channel 1132, the first electrode 1131, and the second electrode 1133 of the driving transistor T1. The buffer layer 111 may have a single-layer or multi-layer structure and may include an organic insulating material or an inorganic insulating material.

[0161] The first gate insulating layer 141 may be disposed on the polycrystalline semiconductor including the channel 1132 of the driving transistor T1, the first electrode 1131, and the second electrode 1133. The first gate insulating layer 141 may include silicon nitride, silicon oxide, or the like.

[0162] A first gate conductor including a gate electrode 1151 of the driving transistor T1 may be disposed on the first gate insulating layer 141 . Figure 15 The polycrystalline semiconductor and the first gate conductor are shown together. In addition to the gate electrode 1151 of the driving transistor T1, the first gate conductor may further include respective gate electrodes of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0163] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1.

[0164] The first gate conductor may further include a first scan line 151 and a light emission control line 155. The first scan line 151 and the light emission control line 155 may extend approximately in a horizontal direction. The first scan line 151 may be connected to the gate electrode of the second transistor T2 and the first electrode of the boost capacitor Cboost. The first scan line 151 may be connected to the gate electrode of the seventh transistor T7 arranged at the pixel of the next stage. In other words, the bypass control line 154 connected to the seventh transistor T7 may be composed of the first scan line 151 of the previous stage. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be connected to the light emission control line 155.

[0165] A doping process may be performed after forming the first gate conductor including the gate electrode 1151 of the driver transistor T1. The polycrystalline semiconductor covered by the first gate conductor is not doped, and the portion of the polycrystalline semiconductor not covered by the first gate conductor is doped to have the same characteristics as a conductor. In this case, a doping process using a p-type dopant may be performed, and the driver transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including the polycrystalline semiconductor may have p-type transistor characteristics.

[0166] The second gate insulating layer 142 may be disposed on the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the first gate insulating layer 141. The second gate insulating layer 142 may include silicon nitride, silicon oxide, or the like.

[0167] On the second gate insulating layer 142 , a second gate conductor including a first storage electrode 1153 of the storage capacitor Cst1 , a light shielding layer 3155 of the third transistor T3 , and a light shielding layer 4155 of the fourth transistor T4 may be disposed. Figure 16 The polycrystalline semiconductor, the first gate conductor, and the second gate conductor are shown together.

[0168] The first storage electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1, thereby forming a storage capacitor Cst1. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst1. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst1 may overlap with the gate electrode 1151 of the driving transistor T1. The light shielding layer 3155 of the third transistor T3 may overlap with the channel 3137 and gate electrode 3151 of the third transistor T3. The light shielding layer 4155 of the fourth transistor T4 may overlap with the channel 4137 and gate electrode 4151 of the fourth transistor T4.

[0169] The second gate conductor may further include a lower second scan line 152a, a lower initialization control line 153a, and an initialization voltage line 127. The lower second scan line 152a, the lower initialization control line 153a, and the initialization voltage line 127 may extend approximately in a horizontal direction. The lower second scan line 152a may be connected to the light shielding layer 3155 of the third transistor T3.

[0170] The lower initialization control line 153 a may be connected to the light shielding layer 4155 of the fourth transistor T4 .

[0171] A first interlayer insulating layer 161 may be disposed on the second gate conductor including the first storage electrode 1153 of the storage capacitor Cst1 , the light shielding layer 3155 of the third transistor T3 , and the light shielding layer 4155 of the fourth transistor T4 .

[0172] The first interlayer insulating layer 161 may include silicon nitride, silicon oxide, or the like.

[0173] On the first interlayer insulating layer 161 , an oxide semiconductor including a channel 3137 , a first electrode 3136 , and a second electrode 3138 of the third transistor T3 and a channel 4137 , a first electrode 4136 , and a second electrode 4138 of the fourth transistor T4 may be disposed. Figure 17 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, and an oxide semiconductor are shown together.

[0174] The oxide semiconductor may include at least one of the following: a main metal oxide such as indium oxide (In), tin oxide (Sn) or zinc oxide (Zn); a binary metal oxide such as an In-Zn-based oxide, a Sn-Zn-based oxide, an Al-Zn-based oxide, a Zn-Mg-based oxide, a Sn-Mg-based oxide, an In-Mg-based oxide or an In-Ga-based oxide; an oxide such as an In-Ga-Zn-based oxide, an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, an Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, an Sn-Al-Zn-based oxide, an In-Hf-Zn-based oxide, an In-La-Zn-based oxide, an In-Ce-Zn-based oxide, an In-Pr-Zn-based oxide; The oxide semiconductor may include an In-Nd-Zn-based oxide, an In-Sm-Zn-based oxide, an In-Eu-Zn-based oxide, an In-Gd-Zn-based oxide, an In-Tb-Zn-based oxide, an In-Dy-Zn-based oxide, an In-Ho-Zn-based oxide, an In-Er-Zn-based oxide, an In-Tm-Zn-based oxide, an In-Yb-Zn-based oxide, or an In-Lu-Zn-based oxide; and a quaternary metal oxide such as an In-Sn-Ga-Zn-based oxide, an In-Hf-Ga-Zn-based oxide, an In-Al-Ga-Zn-based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide. For example, the oxide semiconductor may include indium-gallium-zinc oxide ("IGZO") in an In-Ga-Zn-based oxide.

[0175] The channel 3137, first electrode 3136, and second electrode 3138 of the third transistor T3, and the channel 4137, first electrode 4136, and second electrode 4138 of the fourth transistor T4 may be connected to one another as a single body. The first electrode 3136 and second electrode 3138 of the third transistor T3 may be arranged on either side of the channel 3137 of the third transistor T3. The first electrode 4136 and second electrode 4138 of the fourth transistor T4 may be arranged on either side of the channel 4137 of the fourth transistor T4. The second electrode 3138 of the third transistor T3 may be connected to the second electrode 4138 of the fourth transistor T4. The channel 3137 of the third transistor T3 may overlap with the light shielding layer 3155. The channel 4137 of the fourth transistor T4 may overlap with the light shielding layer 4155.

[0176] The oxide semiconductor may further include a second electrode of a boost capacitor Cboost. The second electrode of the boost capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3. The second electrode of the boost capacitor Cboost may be connected to the second electrode 4138 of the fourth transistor T4. The second electrode of the boost capacitor Cboost may overlap with the first electrode of the boost capacitor Cboost. The capacitance of the boost capacitor Cboost may be determined by the overlapping area of ​​the first and second electrodes of the boost capacitor Cboost and the thickness of the second gate insulating layer 142 and the first interlayer insulating layer 161 disposed between the first and second electrodes.

[0177] The third gate insulating layer 143 may be disposed on the oxide semiconductor including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3, and the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. The third gate insulating layer 143 may be disposed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. Accordingly, the third gate insulating layer 143 may cover the upper and side surfaces of the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3, and the upper and side surfaces of the channel 4137, the first electrode 4136, and the second electrode 4138 of the fourth transistor T4. However, the present exemplary embodiment of the present invention is not limited thereto, and the third gate insulating layer 143 may not be disposed on the entire surface of the oxide semiconductor and the first interlayer insulating layer 161. For example, the third gate insulating layer 143 may overlap with the channel 3137 of the third transistor T3, but may not overlap with the first electrode 3136 and the second electrode 3138. In addition, the third gate insulating layer 143 may overlap with the channel 4137 of the fourth transistor T4 , but may not overlap with the first electrode 4136 and the second electrode 4138 .

[0178] On the third gate insulating layer 143 , a third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be disposed. Figure 18 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor are shown together.

[0179] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may overlap with the light shielding layer 3155 of the third transistor T3.

[0180] The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4. The gate electrode 4151 of the fourth transistor T4 may overlap with the light shielding layer 4155 of the fourth transistor T4.

[0181] The third gate conductor may further include a second initialization voltage line 128, an upper second scan line 152b, and an upper initialization control line 153b. The second initialization voltage line 128, the upper second scan line 152b, and the upper initialization control line 153b may extend approximately in a horizontal direction. The upper second scan line 152b and the lower second scan line 152a together form a second scan line 152. The upper second scan line 152b may be connected to the gate electrode 3151 of the third transistor T3. The upper initialization control line 153b and the lower initialization control line 153a together form the initialization control line 153. The upper initialization control line 153b may be connected to the gate electrode 4151 of the fourth transistor T4.

[0182] After forming the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4, a doping process may be performed. The portion of the oxide semiconductor covered by the third gate conductor is undoped, and the portion of the oxide semiconductor not covered by the third gate conductor is doped to have the same characteristics as a conductor. The channel 3137 of the third transistor T3 may be arranged below the gate electrode 3151 to overlap with the gate electrode 3151. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 4137 of the fourth transistor T4 may be arranged below the gate electrode 4151 to overlap with the gate electrode 4151. The first electrode 4136 and the second electrode 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151. The doping process of the oxide semiconductor may be performed using an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor may have n-type transistor characteristics.

[0183] The second interlayer insulating layer 162 may be disposed on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. The second interlayer insulating layer 162 may have a first opening 1165, a second opening 1166, a third opening 3165, a fourth opening 3166, a fifth opening 4165, and a sixth opening 4166.

[0184] The first opening 1165 may overlap at least a portion of the gate electrode 1151 of the driving transistor T1. The first opening 1165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. The first opening 1165 may overlap with the opening 1152 of the first storage electrode 1153. The first opening 1165 may be arranged inside the opening 1152 of the first storage electrode 1153. The second opening 1166 may overlap at least a portion of the boosting capacitor Cboost. The second opening 1166 may be further formed in the third gate insulating layer 143.

[0185] The third opening 3165 may overlap at least a portion of the second electrode 1133 of the driving transistor T1. The third opening 3165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141. The fourth opening 3166 may overlap at least a portion of the first electrode 3136 of the third transistor T3. The fourth opening 3166 may be further formed in the third gate insulating layer 143.

[0186] The fifth opening 4165 may overlap at least a portion of the first electrode 4136 of the fourth transistor T4. The fifth opening 4165 may be further formed in the third gate insulating layer 143. The sixth opening 4166 may overlap at least a portion of the first initialization voltage line 127. The sixth opening 4166 may be further formed in the third gate insulating layer 143 and the first interlayer insulating layer 161.

[0187] On the second interlayer insulating layer 162 , a first data conductor including a first connection electrode 1175 , a second connection electrode 3175 , and a third connection electrode 4175 may be disposed. Figure 19 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, a third gate conductor, and a first data conductor are shown together.

[0188] The first connection electrode 1175 may overlap with the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 1165 and the opening 1152 of the first storage electrode 1153. The first connection electrode 1175 may overlap with the boost capacitor Cboost. The first connection electrode 1175 may be connected to the second electrode of the boost capacitor Cboost through the second opening 1166. Accordingly, the gate electrode 1151 of the driving transistor T1 and the second electrode of the boost capacitor Cboost may be connected by the first connection electrode 1175. In this case, the gate electrode 1151 of the driving transistor T1 may also be connected to the second electrode 3138 of the third transistor T3 and the second electrode 4138 of the fourth transistor T4 by the first connection electrode 1175.

[0189] The second connection electrode 3175 may overlap with the second electrode 1133 of the driving transistor T1. The second connection electrode 3175 may be connected to the second electrode 1133 of the driving transistor T1 through the third opening 3165. The second connection electrode 3175 may overlap with the first electrode 3136 of the third transistor T3. The second connection electrode 3175 may be connected to the first electrode 3136 of the third transistor T3 through the fourth opening 3166. Accordingly, the second electrode 1133 of the driving transistor T1 and the first electrode 3136 of the third transistor T3 may be connected by the second connection electrode 3175.

[0190] The third connection electrode 4175 may overlap with the first electrode 4136 of the fourth transistor T4. The third connection electrode 4175 may be connected to the first electrode 4136 of the fourth transistor T4 through the fifth opening 4165. The third connection electrode 4175 may overlap with the first initialization voltage line 127. The third connection electrode 4175 may be connected to the first initialization voltage line 127 through the sixth opening 4166. Accordingly, the first electrode 4136 of the fourth transistor T4 and the first initialization voltage line 127 may be connected by the third connection electrode 4175.

[0191] The first data conductor may further include a second initialization voltage supply line 1128. The second initialization voltage supply line 1128 may extend approximately in a vertical direction and may be arranged between two adjacent pixels PX. The second initialization voltage supply line 1128 may branch left and right at an intersection with the first initialization voltage line 128. The second initialization voltage supply line 1128 may be connected to the first initialization voltage line 128 to transmit a second initialization voltage AINT.

[0192] A third interlayer insulating layer 180 may be disposed on the first data conductor including the first connection electrode 1175 , the second connection electrode 3175 , and the third connection electrode 4175 .

[0193] The data line 171 and the driving voltage line 172 may be arranged on the third interlayer insulating layer 180. The data line 171 and the driving voltage line 172 may extend approximately in a vertical direction. The data line 171 may be connected to the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5.

[0194] Although not shown, a passivation layer may be arranged on the data line 171 and the drive voltage line 172, and an anode may be arranged on the passivation layer. The anode may be connected to the sixth transistor T6 and may receive the output current of the drive transistor T1. A partition wall may be arranged above the anode. An opening may be formed in the partition wall, and the opening of the partition wall may overlap with the anode. The light-emitting element layer may be arranged in the opening of the partition wall. The cathode may be arranged on the light-emitting element layer and the partition wall. The anode, the light-emitting element layer, and the cathode constitute a light-emitting diode LED.

[0195] As described above, in the display device 1000 according to the exemplary embodiment, the driving transistor T1 may include a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. As described above, by forming the third transistor T3 and the fourth transistor T4 to include a semiconductor material different from that of the driving transistor T1, driving can be performed more stably and reliability can be improved.

[0196] In the above, reference Figure 11 and Figure 19 The first connection electrode 1175 is described as being connected to the second electrode 3138 of the third transistor T3, the second electrode 4138 of the fourth transistor T4, and the second electrode of the boost capacitor Cboost through the second opening 1166. In this exemplary embodiment, the shape of the first connection electrode 1175 and the position of the second opening 1166 may be changed, and reference may be made to FIG. Figure 20 Describe this.

[0197] Figure 20 is a top plan view illustrating some pixels PX of the first area DA1 of the display device 1000 according to an exemplary embodiment.

[0198] like Figure 20 As shown in , similar to Figure 11 In the exemplary embodiment, the first connection electrode 1175 is connected to the second electrode 3138 of the third transistor T3, the second electrode 4138 of the fourth transistor T4, and the second electrode of the boost capacitor Cboost through the second opening 1166. The width of both ends of the first connection electrode 1175 is wider than that of the other parts. Figure 11 In the embodiment, one of the two ends of the first connection electrode 1175 may overlap with the first scan line 151. That is, the first scan line 151, the second electrode of the boosting capacitor Cboost, and the first connection electrode 1175 overlap. Figure 20 In the embodiment, one end of the first connection electrode 1175 is bent to be arranged between the first scan line 151 and the second scan line 152. The first connection electrode 1175 and the first scan line 151 partially overlap, but the overlapping area of ​​the first connection electrode 1175 and the first scan line 151 is less than 1%. Figure 11 Therefore, the influence of the signal applied to the first scan line 151 on the connection path of the driving transistor T1 and the third transistor T3 can be minimized.

[0199] In the above description, the first connection electrode 1175 partially overlaps the first scan line 151 , but the present exemplary embodiment of the present invention is not limited thereto. In some cases, the first connection electrode 1175 may not overlap the first scan line 151 at all.

[0200] Next, refer to Figures 21 to 29 The pixels PX of the second area DA2 of the display apparatus 1000 according to an exemplary embodiment are described.

[0201] Figure 21 is a top plan view illustrating some pixels PX of the second area DA2 of the display device 1000 according to an exemplary embodiment. Figure 22 It is along Figure 21 A cross-sectional view taken along line XXII-XXII', Figure 23 It is along Figure 21 A cross-sectional view taken along line XXIII-XXIII', and Figures 24 to 29 1 and 2 are top plan views of some pixels PX of the second area DA2 sequentially illustrating a manufacturing order of the display device 1000 according to an exemplary embodiment.

[0202] Figures 21 to 29 Four adjacent pixels PX among a plurality of pixels PX arranged in the second area DA2 of the display device 1000 according to an exemplary embodiment are shown, and they are aligned with Figure 3 However, the present exemplary embodiment is not limited thereto, and may have a modified pixel structure to correspond to the circuit diagram of FIG. Figure 6 The circuit diagram may correspond to the circuit diagram shown in FIG. 1 , or various changes may be made in another exemplary embodiment.

[0203] In the first and second regions DA1 and DA2 of the display device 1000 according to an exemplary embodiment, each layer may be formed in the same process and may have a substantially similar pixel structure. However, designs may be made to differentiate the specifications of some layers, and specifically, the width and length of the channel 1132 of the driving transistor T1 may be designed differently. This will be further described below.

[0204] like Figure 22As shown in FIG, the light shielding member 500 may be arranged on the substrate 110. The light shielding member 500 may be arranged as a whole in the second area DA2. The light shielding member 500 may not be arranged in the first area DA1. That is, after the light shielding member 500 is formed as a whole on the substrate 110, the light shielding member 500 positioned in the first area DA1 may be patterned so as to be removed. Although not shown, a separate insulating layer, buffer layer, etc. may be arranged between the substrate 110 and the light shielding member 500.

[0205] A polycrystalline semiconductor including the channel 1132 , the first electrode 1131 , and the second electrode 1133 of the driving transistor T1 may be disposed on the light blocking member 500 . Figure 24 A polycrystalline semiconductor is shown.

[0206] The channel 1132 of the driving transistor T1 may be formed in a rod-like shape in a planar manner. However, the shape of the channel 1132 of the driving transistor T1 according to the present invention is not limited thereto and may be variously modified in another exemplary embodiment. The planar shape of the channel 1132 of the driving transistor T1 may be different in the first area DA1 and the second area DA2. For example, the planar shape of the channel 1132 of the driving transistor T1 may be formed in a curved shape in the first area DA1 and in a rod-like shape in the second area DA2.

[0207] A buffer layer 111 may be disposed between the light blocking member 500 and the polycrystalline semiconductor. A first gate insulating layer 141 may be disposed on the polycrystalline semiconductor.

[0208] A first gate conductor including a gate electrode 1151 of the driving transistor T1 may be disposed on the first gate insulating layer 141 . Figure 25 The polycrystalline semiconductor and the first gate conductor are shown together.

[0209] The gate electrode 1151 of the driving transistor T1 may overlap with the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1. The overlapping area between the gate electrode 1151 of the driving transistor T1 and the polycrystalline semiconductor in the first area DA1 and the overlapping area between the gate electrode 1151 of the driving transistor T1 and the polycrystalline semiconductor in the second area DA2 may be different. In addition, the width W1 of the channel 1132 of the driving transistor T1 in the first area DA1 (see Figure 11 and Figure 20 ) and the width W2 of the channel 1132 of the driving transistor T1 in the second area DA2 (see Figure 21 ) can be different. Further, the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1 (see Figure 12) and the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 (see Figure 22 In addition, a ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1 and a ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be different.

[0210] The gate electrode 1151 of the driving transistor T1 overlaps with the light shielding member 500 to form an auxiliary capacitor Cas. The light shielding member 500 may be disposed between the substrate 110 and the gate electrode 1151 of the driving transistor T1. A buffer layer 111 and a first gate insulating layer 141 may be disposed between the light shielding member 500 and the gate electrode 1151. Since the light shielding member 500 is disposed throughout the second area DA2, it overlaps not only with the driving transistor T1 but also with the gate electrodes of the second to seventh transistors T2, T3, T4, T5, T6, and T7 to form the auxiliary capacitor Cas. The capacitance of the auxiliary capacitor Cas may be determined by the overlapping area between the light shielding member 500 and the gate electrode 1151 of the driving transistor T1, as well as the thickness of the buffer layer 111 and the first gate insulating layer 141 disposed between the light shielding member 500 and the gate electrode 1151 of the driving transistor T1.

[0211] The first gate conductor may further include a first scan line 151, a light emitting control line 155, and a bypass control line 154. A second gate insulating layer 142 may be disposed on the first gate conductor and the first gate insulating layer 141.

[0212] A second gate conductor including the first storage electrode 1153 of the storage capacitor Cst2 , the light shielding layer 3155 of the third transistor T3 , and the light shielding layer 4155 of the fourth transistor T4 may be disposed on the second gate insulating layer 142 . Figure 26 The polycrystalline semiconductor, the first gate conductor, and the second gate conductor are shown together.

[0213] The first storage electrode 1153 overlaps with the gate electrode 1151 of the drive transistor T1 to form a storage capacitor Cst2. The capacitance of the storage capacitor Cst2 may be determined by the overlapping area between the gate electrode 1151 of the drive transistor T1 and the first storage electrode 1153, and the thickness of the second gate insulating layer 142 between the gate electrode 1151 of the drive transistor T1 and the first storage electrode 1153. The overlapping area between the gate electrode 1151 of the drive transistor T1 and the first storage electrode 1153 in the first area DA1 and the overlapping area between the gate electrode 1151 of the drive transistor T1 and the first storage electrode 1153 in the second area DA2 may be different. Accordingly, the capacitance of the storage capacitor Cst1 in the first area DA1 and the capacitance of the storage capacitor Cst2 in the second area DA2 may be different.

[0214] In this exemplary embodiment, the number of pixels PX per unit area in the second area DA2 is smaller than the number of pixels PX per unit area in the first area DA1. Accordingly, when the pixels PX arranged in the first area DA1 and the pixels PX positioned in the second area DA2 have the same structure and are driven by the same voltage, the brightness of the second area DA2 can be lower than the brightness of the first area DA1. Accordingly, the boundary between the first area DA1 and the second area DA2 can be identified. In this exemplary embodiment, the pixels PX arranged in the second area DA2 have a brightness similar to that of the pixels PX arranged in the first area DA1 by distinguishing the structures of the pixels PX arranged in the first area DA1 and the second area DA2, so that the boundary between the first area DA1 and the second area DA2 is not identified and the image can be displayed naturally. Next, the difference in the length and width of the channel 1132 of the driving transistor T1 and the capacitance of the storage capacitors Cst1 and Cst2 and the auxiliary capacitor Cas between the first area DA1 and the second area DA2 is described.

[0215] Table 1 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the brightness of the second area DA2 to the brightness of the first area DA1 in the first pixel PX1 representing red is 60%, 80%, and 100%, respectively.

[0216] In the first and second areas DA1 and DA2 , widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 micrometers (μm).

[0217] (Table 1)

[0218]

[0219]

[0220] When the first pixel PX1 represents red, a ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be greater than a ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. A ratio of the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 to the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1 may be approximately 168% or more and approximately 185% or less. Considering the error range, when considering the numerical range described in parentheses, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 can be greater than or equal to approximately 155% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1, and can be less than or equal to approximately 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. When the first pixel PX1 displays red, the capacitance of the storage capacitor Cst2 in the second area DA2 can be greater than or equal to approximately 86% and less than or equal to approximately 140% of the capacitance of the storage capacitor Cst1 in the first area DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second area DA2 can be greater than or equal to approximately 27% and less than or equal to the capacitance of the storage capacitor Cst1 in the first area DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second area DA2 may be approximately 113% or more and approximately 177% or less of the capacitance of the storage capacitor Cst1 in the first area DA1 .

[0221] Table 2 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the luminance of the second area DA2 to the luminance of the first area DA1 is 60%, 80%, and 100%, respectively, in the second pixel PX2 representing green. In the first area DA1 and the second area DA2, the widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 μm.

[0222] (Table 2)

[0223]

[0224] When the second pixel PX2 represents green, a ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be greater than a ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. The ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be greater than or equal to about 168% and less than or equal to about 185% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. Considering the error range, when considering the numerical range described in parentheses, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 can be greater than or equal to approximately 155% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1, and can be less than or equal to approximately 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. When the second pixel PX2 displays green, the capacitance of the storage capacitor Cst2 in the second area DA2 can be greater than or equal to approximately 63% and less than or equal to approximately 90% of the capacitance of the storage capacitor Cst1 in the first area DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second area DA2 can be greater than or equal to approximately 27% and less than or equal to the capacitance of the storage capacitor Cst1 in the first area DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second area DA2 may be approximately 90% or more and 123% or less of the capacitance of the storage capacitor Cst1 in the first area DA1.

[0225] Table 3 shows the channel lengths L1 and L2 of the driving transistor T1, the capacitances of the storage capacitors Cst1 and Cst2, and the capacitance of the auxiliary capacitor Cas when the ratio of the luminance of the second area DA2 to the luminance of the first area DA1 is 60%, 80%, and 100%, respectively, in the third pixel PX3 representing blue. In the first area DA1 and the second area DA2, the widths W1 and W2 of the channel 1132 of the driving transistor T1 are both set to 3.5 μm.

[0226] (Table 3)

[0227]

[0228] When the third pixel PX3 represents blue, a ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be greater than a ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. The ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 may be approximately 185% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. Considering the error range, when considering the numerical range described in parentheses, the ratio W2 / L2 of the width W2 to the length L2 of the channel 1132 of the driving transistor T1 in the second area DA2 can be greater than or equal to approximately 168% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1, and can be less than or equal to approximately 206% of the ratio W1 / L1 of the width W1 to the length L1 of the channel 1132 of the driving transistor T1 in the first area DA1. When the third pixel PX3 displays blue, the capacitance of the storage capacitor Cst2 in the second area DA2 can be greater than or equal to approximately 81% and less than or equal to approximately 137% of the capacitance of the storage capacitor Cst1 in the first area DA1. In addition, the capacitance of the auxiliary capacitor Cas in the second area DA2 can be greater than or equal to approximately 26% and less than or equal to the capacitance of the storage capacitor Cst1 in the first area DA1. Therefore, the sum of the capacitances of the storage capacitor Cst2 and the auxiliary capacitor Cas in the second area DA2 may be approximately 107% or more and 174% or less of the capacitance of the storage capacitor Cst1 in the first area DA1.

[0229] The second gate conductor may further include a lower second scan line 152a, a lower initialization control line 153a, and an initialization voltage line 127. A first interlayer insulating layer 161 may be disposed on the second gate conductor.

[0230] On the first interlayer insulating layer 161 , an oxide semiconductor including a channel 3137 , a first electrode 3136 , and a second electrode 3138 of the third transistor T3 and a channel 4137 , a first electrode 4136 , and a second electrode 4138 of the fourth transistor T4 may be disposed. Figure 27 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, and an oxide semiconductor are shown together.

[0231] The oxide semiconductor may further include a second electrode of a boosting capacitor Cboost, and the second electrode of the boosting capacitor Cboost may be connected to the second electrode 3138 of the third transistor T3 and the second electrode 4138 of the fourth transistor T4. A third gate insulating layer 143 may be disposed on the oxide semiconductor.

[0232] On the third gate insulating layer 143 , a third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be disposed. Figure 28 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, and a third gate conductor are shown together.

[0233] The third gate conductor may further include a second initialization voltage line 128, an upper second scan line 152b, and an upper initialization control line 153b. A second interlayer insulating layer 162 may be disposed on the third gate conductor.

[0234] On the second interlayer insulating layer 162 , a first data conductor including a first connection electrode 1175 , a second connection electrode 3175 , and a third connection electrode 4175 may be disposed. Figure 29 A polycrystalline semiconductor, a first gate conductor, a second gate conductor, an oxide semiconductor, a third gate conductor, and a first data conductor are shown together.

[0235] The first connection electrode 1175 may connect the gate electrode 1151 of the driving transistor T1, the second electrode 3138 of the third transistor T3, the second electrode 4138 of the fourth transistor T4, and the second electrode of the boost capacitor Cboost. The second connection electrode 3175 may connect the second electrode 1133 of the driving transistor T1 and the first electrode 3136 of the third transistor T3. The third connection electrode 4175 may connect the first electrode 4136 of the fourth transistor T4 and the first initialization voltage line 127.

[0236] The first data conductor may further include a driving voltage line 172 , a first initialization voltage supply line 1127 , and a second initialization voltage supply line 1128 .

[0237] The driving voltage line 172 may extend approximately in the vertical direction and transmit the driving voltage ELVDD. The driving voltage line 172 may be connected to the fifth transistor T5 and the first storage electrode 1153 of the storage capacitor Cst2. The first storage electrodes 1153 of the storage capacitors Cst2 of four adjacent pixels PX may be connected to each other. Therefore, it is not necessary to arrange a driving voltage line 172 for each pixel column. For example, the driving voltage line 172 may be arranged one for every two pixel columns or one for every four pixel columns.

[0238] The first initialization voltage supply line 1127 may extend approximately in a vertical direction and may transmit a first initialization voltage VINT. The first initialization voltage supply line 1127 may be connected to the first initialization voltage line 127. The first initialization voltage line 127 is connected to each pixel PX to transmit the first initialization voltage VINT. The first initialization voltage supply line 1127 may be arranged one for every four pixel columns.

[0239] The second initialization voltage supply line 1128 may extend approximately in a vertical direction and may transmit a second initialization voltage AINT. The second initialization voltage supply line 1128 may be connected to the second initialization voltage line 128. The second initialization voltage line 128 is connected to each pixel PX to transmit the second initialization voltage AINT. The second initialization voltage supply line 1128 may be arranged one for every four pixel columns.

[0240] A third interlayer insulating layer 180 may be disposed on the first data conductor. A data line 171 may be disposed on the third interlayer insulating layer 180. The data line 171 may extend substantially in a vertical direction and may be connected to the second transistor T2 of each pixel PX.

[0241] Although not shown, a passivation layer, an anode, a partition wall, a light emitting element layer, a cathode, etc. may be positioned on the data line 171 .

[0242] According to an exemplary embodiment, two adjacent rows of pixels PX in the second area DA2 of the display device 1000 may have a vertically symmetrical structure. Figure 30 Describe this.

[0243] Figure 30 is a top plan view illustrating some pixels PX of the second area DA2 of the display device 1000 according to an exemplary embodiment. Figure 30 is shown together Figure 21 1 is a view of four pixels PX and four pixels PX adjacent thereto shown in FIG.

[0244] According to an exemplary embodiment, pixels PX in two adjacent rows in the second area DA2 of the display device 1000 may have a flip structure that is symmetrical up and down based on the first initialization voltage line 127. Therefore, eight adjacent pixels PX are connected to the same initialization voltage line 127 to receive the first initialization voltage VINT. As described above, the number of wirings arranged in the second area DA2 is reduced compared to the first area DA1 to increase the transmittance of the second area DA2.

[0245] This is merely an example, and the pixels PX of two adjacent rows may be symmetrical based on other wiring instead of the first initialization voltage line 127. For example, the pixels PX of two adjacent rows may be symmetrical based on the second initialization voltage line 128.

[0246] While the present disclosure has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0247] <Description of Symbols>

[0248] DA1: First area DA2: Second area

[0249] 127: first initialization voltage line 128: second initialization voltage line

[0250] 151: First scan line 152: Second scan line

[0251] 153: Initialization control line 154: Bypass control line

[0252] 155: Lighting control line 171: Data line

[0253] 172: driving voltage line 500: light shielding member

[0254] 741: Common voltage line

[0255] 1127: First initialization voltage supply line 1128: Second initialization voltage supply line

[0256] PX: Pixel

[0257] Cst: Storage capacitor Cas: Auxiliary capacitor.

Claims

1. A display device, comprising: substrate; a polycrystalline semiconductor layer on the substrate, the polycrystalline semiconductor layer including a channel, a first electrode, and a second electrode of a first transistor, and a channel, a first electrode, and a second electrode of a second transistor; a first gate conductor layer comprising a gate electrode of the first transistor overlapping with the channel of the first transistor and a gate electrode of the second transistor overlapping with the channel of the second transistor; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including a channel of a third transistor, a first electrode, and a second electrode; a second gate conductor layer, comprising a lower gate electrode of the third transistor overlapping the channel of the third transistor; a third gate conductor layer, comprising an upper gate electrode of the third transistor overlapping the channel of the third transistor; a first data conductor layer including a first initialization voltage supply line electrically connected to the second transistor, a second initialization voltage supply line, and a first connection electrode electrically connected to the second electrode of the third transistor and the gate electrode of the first transistor; as well as a fourth transistor connected to the second initialization voltage supply line, The second initialization voltage supply line and the first initialization voltage supply line are arranged on the same layer.

2. The display device according to claim 1, wherein The fourth transistor is connected between the second initialization voltage supply line and the third transistor, and The first initialization voltage supply line and the first connection electrode are provided in the same layer.

3. The display device according to claim 2, wherein The oxide semiconductor layer further includes a channel, a first electrode, and a second electrode of the fourth transistor, The second gate conductor layer further includes a lower gate electrode of the fourth transistor overlapping the channel of the fourth transistor, and The third gate conductor layer further includes an upper gate electrode of the fourth transistor overlapping the channel of the fourth transistor.

4. The display device according to claim 2, further comprising: A light emitting diode is connected between the driving voltage line and the common voltage line; a fifth transistor connected between the first electrode of the first transistor and a data line, wherein the first electrode of the first transistor is connected to the driving voltage line; as well as A storage capacitor is connected between the driving voltage line and the gate electrode of the first transistor.

5. The display device according to claim 4, wherein The polycrystalline semiconductor layer further includes a channel, a first electrode, and a second electrode of the fifth transistor, and The first gate conductor layer further includes a gate electrode of the fifth transistor. The display device according to claim 5 , wherein: The first electrode of the first transistor extends to the second electrode of the fifth transistor.

7. The display device according to claim 5, wherein The second gate conductor further includes a first storage electrode of the storage capacitor, and The first storage electrode overlaps the gate electrode of the first transistor.

8. The display device according to claim 4, further comprising: a sixth transistor connected between the driving voltage line and the first electrode of the first transistor; as well as A seventh transistor is connected between the second electrode of the first transistor and the light emitting diode.

9. The display device according to claim 8, wherein The polycrystalline semiconductor layer further includes a channel, a first electrode, and a second electrode of the sixth transistor, and The first gate conductor layer further includes a gate electrode of the sixth transistor.

10. The display device according to claim 9, wherein The first electrode of the sixth transistor is connected to the driving voltage line, and The second electrode of the sixth transistor extends to the first electrode of the first transistor.

11. The display device according to claim 9, wherein The polycrystalline semiconductor layer further includes a channel, a first electrode, and a second electrode of the seventh transistor, and The first gate conductor layer further includes a gate electrode of the seventh transistor.

12. The display device according to claim 11, wherein The first electrode of the seventh transistor extends to the second electrode of the first transistor, and The second electrode of the seventh transistor is connected to the anode of the light emitting diode.

13. The display device according to claim 1, further comprising: a light shielding member provided on the substrate, The light shielding member is provided between the substrate and the gate electrode of the first transistor.

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