Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display, the display panel comprises a light emitting element and a pixel driving circuit located on a driving circuit layer, the pixel driving circuit comprises a driving transistor, a grid electrode of the driving transistor is electrically connected with a first node, and a first pole and a second pole are electrically connected with a second node and a third node respectively; wherein the second node is coupled with a data voltage signal line in the driving circuit layer. The driving circuit layer further comprises a shielding wire, and the shielding wire is located between the first node and the data voltage signal line; the shielding wire and the second node are at least partially overlapped, and the shielding wire is connected with a fixed potential signal. When signal jump occurs in the data voltage signal line, coupling between the data voltage signal line and the first node can be reduced through the shielding routing, the crosstalk problem between the first node and the data voltage signal line can be improved, the display problems of uneven display, ghost shadow and the like are further improved, and the display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the advancement of display technology, various industries are placing increasingly stringent demands on display products. Display panels contain multiple traces, which can generate coupling capacitance between different traces. When a signal in one trace changes, it can affect the potential of other traces, causing crosstalk and adversely affecting the display panel's performance.

[0003] Therefore, how to improve the above problems has become one of the technical problems that need to be solved urgently at this stage. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device for improving the crosstalk problem in display products and enhancing the display effect.

[0005] In one aspect, the present disclosure provides a display panel comprising a plurality of light-emitting elements and a pixel driving circuit for driving the light-emitting elements;

[0006] The display panel further includes a base substrate and a driving circuit layer stacked along a first direction, the driving circuit layer being located on one side of the base substrate, and the pixel driving circuit being located on the driving circuit layer, and the first direction being perpendicular to the plane where the display panel is located;

[0007] The pixel driving circuit includes a driving transistor, wherein the gate of the driving transistor is electrically connected to the first node, and the first electrode and the second electrode are electrically connected to the second node and the third node respectively;

[0008] The driving circuit layer further includes a data voltage signal line, the second node is coupled to the data voltage signal line, the data voltage signal line extends along a second direction, and the second direction is parallel to the plane where the display panel is located;

[0009] The driving circuit layer further includes a shielding line, and the shielding line is located between the first node and the data voltage signal line along a third direction, and the third direction is parallel to the plane where the display panel is located and perpendicular to the second direction;

[0010] Along the first direction, the shielding line at least partially overlaps with the second node, and the shielding line is connected to a fixed potential signal.

[0011] In another aspect, the present disclosure provides a display device including the display panel as described above.

[0012] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0013] The present disclosure provides a display panel and a display device, comprising a light-emitting element and a pixel driving circuit located in a driving circuit layer, wherein the pixel driving circuit comprises a driving transistor, wherein the gate of the driving transistor is electrically connected to a first node, and the first electrode and the second electrode are electrically connected to a second node and a third node, respectively; wherein the second node is coupled to a data voltage signal line in the driving circuit layer. The driving circuit layer further comprises a shielding trace, wherein the shielding trace is located between the first node and the data voltage signal line; the shielding trace at least partially overlaps with the second node, and the shielding trace is connected to a fixed potential signal. When a signal jump occurs in the data voltage signal line, the shielding trace forms an "electrostatic shielding layer" between the first node and the data voltage signal line, reducing the influence of the coupled signal on the first node. Therefore, the shielding trace can reduce the coupling between the data voltage signal line and the first node, which is beneficial to reducing the influence on the gate potential of the driving transistor, and thus is beneficial to improving the crosstalk problem between the first node and the data voltage signal line, thereby improving display problems such as uneven display and ghosting, and improving the display effect. In addition, the present disclosure sets the shielding line to at least partially overlap with the second node, which is beneficial to increase the capacitance of the second node, thereby increasing the charge storage capacity of the second node, slowing down the voltage decay of the second node, and thus helping to reduce image retention and ghosting caused by voltage decay, and further helping to improve the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0015] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 FIG2 is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0017] Figure 2 FIG2 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure;

[0019] Figure 4 Shown Figure 3 A schematic diagram of a layout structure of a pixel driving circuit;

[0020] Figure 5 FIG2 is a schematic diagram showing a connection between a driving transistor and a light-emitting unit provided in an embodiment of the present disclosure;

[0021] Figure 6 Shown Figure 3 Another schematic diagram of the layout structure of the pixel driving circuit;

[0022] Figure 7 FIG2 is another structural schematic diagram of a pixel driving circuit provided in the disclosed embodiment;

[0023] Figure 8 FIG2 is a schematic diagram of another film layer of a display panel provided by an embodiment of the present disclosure;

[0024] Figure 9 FIG. 1 is a schematic diagram of another film layer of a display panel provided by an embodiment of the present disclosure;

[0025] Figure 10 Shown is a planar schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0028] Figure 1 FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit provided by an embodiment of the present disclosure. Figure 4 Shown Figure 3 A schematic diagram of the layout structure of the pixel driving circuit, please refer to Figures 1 to 4 The present disclosure provides a display panel 100, including a plurality of light-emitting elements 10 and a pixel driving circuit 20 for driving the light-emitting elements 10; the display panel 100 also includes a base substrate 00 and a driving circuit layer 30 stacked along a first direction F1, the driving circuit layer 30 is located on one side of the base substrate 00, and the pixel driving circuit 20 is located on the driving circuit layer 30, and the first direction F1 is perpendicular to the plane where the display panel 100 is located.

[0029] It should be noted that this disclosure Figure 1 The rectangular display panel 100 is used as an example for illustration, but the invention is not limited thereto. The display panel 100 may also be any feasible shape such as a circle or a rounded rectangle. The display panel 100 includes a plurality of pixel driving circuits 20 arranged in a matrix. Figure 1 The circuit structure of the pixel driving circuit 20 is only for illustration and does not represent its actual structure. Figure 1 The number of light-emitting elements 10 and pixel driving circuits 20 does not represent the actual number. Optionally, the display panel 100 provided in this embodiment may be a display panel using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel. Figure 5 FIG. 1 is a schematic diagram showing a connection between a driving transistor and a light-emitting unit provided in an embodiment of the present disclosure. Figure 5 FIG1 shows a connection relationship between the driving transistor M0 and the light emitting unit 10 in an OLED display panel. Figure 5 The basic structure of the light-emitting element 10 includes an anode 201, a light-emitting material layer 202 and a cathode 203. When the power supply supplies an appropriate voltage, the holes in the anode 201 and the electrons in the cathode 203 will combine in the light-emitting material layer to generate bright light. Compared with thin-film field-effect transistor liquid crystal displays, OLED display devices have the characteristics of high visibility and high brightness, and are more power-saving, lightweight and thin. Of course, in some other embodiments of the present invention, the display panel 100 can also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a MiniLED display panel, etc. The present disclosure is only described by this example and is not limited to this.

[0030] Please continue to refer to Figures 1 to 4 The pixel driving circuit 20 includes a driving transistor M0, whose gate is electrically connected to a first node N1, and whose first and second electrodes are electrically connected to a second node N2 and a third node N3, respectively. The driving circuit layer 30 also includes a data voltage signal line DATA, to which the second node N2 is coupled. The data voltage signal line DATA extends along a second direction F2, which is parallel to the plane of the display panel 100. The driving circuit layer 30 also includes a shielding trace 40. The shielding trace 40 is located between the first node N1 and the data voltage signal line DATA along a third direction F3, which is parallel to the plane of the display panel 100 and perpendicular to the second direction F2. The shielding trace 40 at least partially overlaps with the second node N2 along the first direction F1, and the shielding trace 40 is connected to a fixed potential signal.

[0031] It should be noted that the present disclosure marks the signal line and the signal transmitted on the signal line the same. For example, the reference mark of the data voltage signal line is DATA, and the reference mark of the data voltage signal is also DATA. The marking method of other signal lines and signals is also the same, and will not be repeated later.

[0032] Please refer to Figures 1 to 4 The pixel driving circuit 20 includes a driving transistor M0 for driving the light-emitting element 10 to emit light. The gate, first electrode, and second electrode of the driving transistor M0 are connected to a first node N1, a second node N2, and a third node N3, respectively. The second node N2 is coupled to a data voltage signal line DATA. The data voltage signal line DATA is located in the driving circuit layer 30 and is used to transmit a data voltage signal DATA to the pixel driving circuit 20. The driving circuit layer 30 also includes a first power supply voltage signal line PVDD. The first power supply voltage signal line PVDD is used to transmit a first power supply voltage signal PVDD to the pixel driving circuit 20. The first power supply voltage signal line PVDD and the data voltage signal line DATA both extend along a second direction F2. A coupling capacitor exists between the first power supply voltage signal line PVDD and the data voltage signal line DATA. When the data voltage signal DATA transmitted by the data voltage signal line DATA changes, the first power supply voltage signal PVDD transmitted by the first power supply voltage signal line PVDD is also affected and changes, thereby affecting the voltage of the first node N1, that is, affecting the gate voltage of the driving transistor M0, resulting in crosstalk. When the gate voltage of the driving transistor M0 changes, it will affect the conduction of the driving transistor M0, and then affect the current flowing through the light-emitting element 10, causing the actual brightness of the light-emitting element 10 to be inconsistent with the display brightness it should achieve, thereby causing display problems such as uneven brightness and afterimages, affecting the display effect.

[0033] Please combine Figure 4 As shown, Figure 4 Indicated in Figure 3 The layout structure of the pixel driving circuit 20 is shown in FIG. Figure 3The layout shown in is for illustration only and does not represent the actual structure. The present disclosure sets a shielding line 40, which is located between the first node N1 and the data voltage signal line DATA. The shielding line 40 is connected to a fixed potential signal. When a signal jump occurs in the data voltage signal line DATA, the shielding line 40 forms an "electrostatic shielding layer" between the first node N1 and the data voltage signal line DATA. The coupling signal generated by the data voltage signal line DATA will preferentially flow into the shielding line 40, reducing the influence of the coupling signal on the first node N1. Therefore, the shielding line 40 can reduce the coupling between the data voltage signal line DATA and the first node N1, which is beneficial to reducing the influence on the gate potential of the driving transistor M0 (the potential of the first node N1), thereby improving the crosstalk problem between the first node N1 and the data voltage signal line DATA, and further improving display problems such as uneven display and ghosting, thereby improving the display effect. In addition, the second node N2 is coupled to the data voltage signal line DATA, and is at least used to receive the data voltage signal DATA transmitted by the data voltage signal line DATA. The present disclosure sets the shielding line 40 to at least partially overlap with the second node N2. This is beneficial to increasing the capacitance of the second node N2. The increase in the capacitance of the second node N2 is beneficial to increasing the charge storage capacity of the second node N2, slowing down the voltage attenuation of the second node N2, thereby helping to reduce image retention and ghosting caused by voltage attenuation, and further helping to improve the display effect.

[0034] Please refer to Figures 1 to 4 In an optional embodiment of the present disclosure, the driving circuit layer 30 further includes a first power supply voltage signal line PVDD, the second node N2 is coupled to the first power supply voltage signal line PVDD; the shielding trace 40 is electrically connected to the first power supply voltage signal line PVDD.

[0035] Specifically, the present disclosure reduces the coupling between the first node N1 and the data voltage signal line DATA by providing a shielding trace 40. The shielding trace 40 is connected to a fixed potential signal. Optionally, the shielding trace 40 can be electrically connected to the first power supply voltage signal line PVDD, which is a fixed potential signal. The shielding trace 40 forms an "electrostatic shielding layer" between the first node N1 and the data voltage signal line DATA. The coupled signal generated by the data voltage signal line DATA will preferentially flow into the shielding trace 40, reducing the impact of the coupled signal on the first node N1. This helps to improve the crosstalk problem between the first node N1 and the data voltage signal line DATA, thereby improving display problems such as image retention and smearing, and enhancing the display effect. In addition, the shielding trace 40 is connected to the first power supply voltage signal line PVDD, eliminating the need to add a new signal to the display panel 100, which helps to simplify the structure of the display panel 100.

[0036] Please continue to refer to Figures 1 to 4In an optional embodiment of the present disclosure, the first power supply voltage signal line PVDD includes a first sub-segment PVDD1 and a second sub-segment PVDD2, the first sub-segment PVDD1 extends along the second direction F2, and the second sub-segment PVDD2 extends along the third direction F3; the second sub-segment PVDD2 is electrically connected to the first sub-segment PVDD1 and the shielding trace 40 through vias.

[0037] Specifically, in this embodiment, the first power supply voltage signal line PVDD includes a first sub-segment PVDD1 and a second sub-segment PVDD2 extending in different directions. Optionally, the first sub-segment PVDD1 and the second sub-segment PVDD2 are located on different metal layers and connected via vias, forming a multi-layer, multi-directional power supply wiring structure. In some medium-to-large display products, if the power supply voltage signal line is too long, its resistance can cause a significant voltage drop (IR drop), resulting in a lower voltage received by the remote light-emitting element 10 than at the near end. The multi-layer, intersecting sub-segments and via connections can effectively reduce the overall impedance of the power supply voltage signal line, thereby reducing voltage drop and facilitating a more uniform and stable power supply voltage across all regions of the display panel 100. The shielding trace 40 is electrically connected to the second sub-segment PVDD2 via vias, facilitating a stable fixed-potential signal and preventing the shielding trace 40 from becoming a new noise source due to impedance or parasitic effects. Furthermore, the primary function of the shielding trace 40 is to suppress crosstalk between adjacent signal lines. When shielding trace 40 is connected to a more stable power supply voltage signal, it can more effectively absorb and guide noise current, thereby improving shielding effectiveness and further alleviating display image retention and smearing, thereby enhancing the display quality. Furthermore, connecting shielding trace 40 to the first power supply voltage signal line PVDD via the second sub-segment PVDD2 further enhances wiring flexibility.

[0038] Figure 6 Shown Figure 3 Another layout diagram of the pixel driving circuit, please refer to Figures 1 to 3 as well as Figure 6 In an optional embodiment of the present disclosure, the driving circuit layer 30 further includes a first reset signal line VREF1, the first node N1 is coupled to the first reset signal line VREF1; and the shielding trace 40 is electrically connected to the first reset signal line VREF1.

[0039] It should be noted that Figure 6The first reset signal line VREF1 and the second reset signal line VREF2 are illustrated as a single trace. In practice, the first reset signal line VREF1 and the second reset signal line VREF2 can be separate traces. The figures in this disclosure illustrate that the shielding trace 40 can be connected to either the first reset signal line VREF1 or the second reset signal line VREF2 and do not limit the actual location and direction of the traces. In some other embodiments, the first reset signal line VREF1 and the second reset signal line VREF2 can further include sub-segments extending in two directions to form a mesh structure, which helps improve the stability of the transmitted signal.

[0040] Specifically, the first reset signal line VREF1 is at least used to transmit a first reset signal VREF1 to the pixel driving circuit 20. Optionally, the first reset signal line VREF1 is coupled to the first node N1. The first reset signal VREF1 transmitted by the first reset signal line VREF1 is used to set the initial voltage of the driving transistor M0 to eliminate the residual charge of the previous frame, which is beneficial to prevent display abnormalities (such as uneven brightness, color deviation, flicker, etc.) caused by the uncleared residual charge, thereby improving the uniformity and accuracy of the display. The present disclosure reduces the coupling between the first node N1 and the data voltage signal line DATA by setting a shielding line 40. The shielding line 40 is connected to a fixed potential signal. In this embodiment, the shielding line 40 is electrically connected to the first reset signal line VREF1. The first reset signal VREF1 transmitted by the first reset signal line VREF1 is a fixed potential signal. The first reset signal is used to provide a shielding signal for the shielding line 40, thereby avoiding the introduction of a new signal source in the display panel 100, which is beneficial to simplifying the structure of the display panel 100.

[0041] Please continue to refer to Figures 1 to 3 as well as Figure 6 In an optional embodiment of the present disclosure, the driving circuit layer 30 further includes a second reset signal line VREF2, and the first electrode of the light-emitting element 10 is coupled to the second reset signal line VREF2; the shielding trace 40 is electrically connected to the second reset signal line VREF2.

[0042] Specifically, the second reset signal line VREF2 is used to transmit at least a second reset signal VREF2 to the first electrode of the light-emitting element 10. The second reset signal VREF2 is used to reset the first electrode of the light-emitting element 10 before the light-emitting element 10 displays new data, thereby eliminating residual charge and reducing the impact of residual charge from the previous frame on the new data. This helps to avoid light leakage, improve display issues such as smearing, and thus improve the display effect. The present disclosure provides a shielding line 40 to reduce the coupling capacitance between the first node N1 and the data voltage signal line DATA. The shielding line 40 needs to receive a fixed potential signal to reduce the impact of the coupling signal on the first node N1, which helps to improve the crosstalk problem between the first node N1 and the data voltage signal line DATA. In this embodiment, the shielding line 40 is electrically connected to the second reset signal line VREF2. The second reset signal transmitted by the second reset signal line VREF2 is a fixed potential signal. In this configuration, the second reset signal is used as a shielding signal for the shielding line 40, avoiding the introduction of a new signal source in the display panel 100, which helps to simplify the structure of the display panel 100.

[0043] Figure 7 FIG2 is another structural diagram of a pixel driving circuit provided in the disclosed embodiment. Please refer to FIG2 Figures 1 to 4 ,as well as Figure 6 and Figure 7 In an optional embodiment of the present disclosure, the driving circuit layer 30 further includes a bias signal line DVH, the second node N2 or the third node N3 is coupled to the bias signal line DVH; the shielding trace 40 is electrically connected to the bias signal line DVH.

[0044] It should be noted that Figure 4 and Figure 6 In the layout shown, the bias signal line DVH is not shown. Figure 7 In the circuit structure diagram of the pixel driving circuit shown in FIG, a bias signal line DVH is shown. The specific position of the bias signal line DVH transmitting the bias signal DVH in the layout is not specifically limited in this disclosure, and reference may be made to FIG. Figure 6 The setting method of the first reset signal line VREF1 and the second reset signal line VREF2.

[0045] Specifically, the bias signal line DVH is used to provide a bias signal to the pixel driving circuit 20. The bias signal is generally a constant DC voltage. Optionally, the bias signal line DVH is connected to the second node N2 or the third node N3 to set the bias point of the first electrode or the second electrode of the driving transistor M0 so that it operates in the desired region (such as the saturation region, the linear region, or the cutoff region). The provision of the bias signal line DVH is conducive to the driving transistor M0 being able to stably and accurately output current or voltage within the display area and service life, thereby ensuring the uniformity of the brightness of the light-emitting element 10 and the accuracy of the grayscale, reducing display defects caused by changes in the characteristics of the driving transistor M0, and improving the stability of the display panel 100. In the present disclosure, the shielding line 40 is electrically connected to the bias signal line DVH, that is, the shielding line 40 receives the bias signal, which is a fixed potential signal. Such a provision provides a stable potential reference for the shielding line 40, thereby enhancing the effectiveness of the shielding line 40 as an anti-interference barrier, further helping to improve the anti-crosstalk capability of the driving circuit layer 30.

[0046] Please refer to Figures 1 to 4 as well as Figure 7 In an optional embodiment of the present disclosure, the pixel driving circuit 20 further includes a switching transistor and a storage capacitor Cst. The switching transistor includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The gate of the first transistor M1 is electrically connected to the first scan signal line SP1, and the first electrode and the second electrode are electrically connected to the data voltage signal line DATA and the second node N2 respectively; the gate of the second transistor M2 is connected to the second scan signal line SP2, the first electrode is electrically connected to the bias signal line DVH, and the second electrode is electrically connected to the second node N2 or the third node N3; the gate of the third transistor M3 is electrically connected to the light emitting control signal line EMIT, the first electrode and the second electrode are electrically connected to the first power supply voltage signal line PVDD and the second node N2 respectively; the gate of the fourth transistor M4 is electrically connected to the first control signal line S1N, and the first electrode and the second electrode are electrically connected to the first node N1 and the third node N3; the gate of the fifth transistor M5 is electrically connected to the second control signal line S2N, and the first electrode and the second electrode are electrically connected to the first reset signal line VREF1 and the first node N1 respectively; the gate of the sixth transistor M6 is electrically connected to the light emitting control signal line EMIT, and the first electrode and the second electrode are electrically connected to the third node N3 and the first electrode of the light emitting element 10 respectively; the gate of the seventh transistor M7 is electrically connected to the third control signal line S3, and the first electrode and the second electrode are electrically connected to the second reset signal line VREF2 and the first electrode of the light emitting element 10 respectively; the storage capacitor Cst is electrically connected between the first node N1 and the first electrode of the first transistor M1.

[0047] Specifically, this embodiment provides an embodiment of a pixel driving circuit 20, which includes a driving transistor M0, seven switching transistors, and a storage capacitor Cst. The driving transistor M0 is the core of the pixel driving circuit 20, and accurately controls the current flowing through the light-emitting element 10 based on its gate voltage (the voltage of the first node N1), thereby determining the brightness of the light-emitting element 10. The storage capacitor Cst is electrically connected between the first node N1 and the first electrode of the first transistor M1. After the data writing phase is completed, the storage capacitor Cst can maintain the voltage of the gate of the driving transistor M0 (i.e., the voltage of the first node N1), thereby stabilizing the gate voltage of the driving transistor M0, maintaining the brightness of the light-emitting element 10, and eliminating smear and flicker. The first scanning signal line SP1 transmits the first scanning signal SP1, and the first transistor M1 is turned on or off under the control of the first scanning signal SP1. When the first transistor M1 is turned on, the data voltage signal DATA transmitted by the data voltage signal line DATA is written to the second node N2. The second scan signal line SP2 transmits a second scan signal SP2, and the second transistor M2 is turned on or off under the control of the second scan signal SP2. When the second transistor M2 is turned on, the bias signal transmitted by the bias signal line DVH is written to the second node N2 or the third node N3, which is used to set the bias point of the first electrode or the second electrode of the driving transistor M0 so that it operates in the desired range. The light-emitting control signal line EMIT transmits the light-emitting control signal EMIT, and the third transistor M3 is turned on or off under the control of the light-emitting control signal EMIT. When the third transistor M3 is turned on, the first power supply voltage signal PVDD transmitted by the first power supply voltage signal line PVDD can be transmitted to the second node N2 to provide operating power for the driving transistor M0 and the light-emitting element 10. The first control signal line S1N transmits a first control signal S1N, and the fourth transistor M4 is turned on or off under the control of the first control signal S1N. The first electrode and the second electrode of the fourth transistor M4 are respectively connected to the gate and the second electrode of the driving transistor M0. When the fourth transistor M4 is turned on, it can perform threshold compensation for the driving transistor M0. The second control signal line S2N transmits a second control signal S2N, and the fifth transistor M5 is turned on or off under the control of the second control signal S2N. When the fifth transistor M5 is turned on, it transmits the first reset signal VREF1 transmitted by the first reset signal line VREF1 to the first node N1, which is used to reset the gate potential of the drive transistor M0 and eliminate the influence of residual charge from the previous frame on the new data. The sixth transistor M6 and the third transistor M3 are both turned on or off under the control of the light-emitting control signal. When the sixth transistor M6 and the third transistor M3 are turned on, current can flow to the first electrode of the light-emitting element 10.The third control signal line S3 transmits the third control signal S3, and the seventh transistor M7 is turned on or off under the control of the third control signal S3. When the seventh transistor M7 is turned on, the second reset signal VREF2 transmitted by the second reset signal line VREF2 can be transmitted to the first electrode of the light-emitting element 10, so as to eliminate the residual charge of the light-emitting element 10 when displaying the previous frame of the picture, and ensure that it is completely turned off during the non-light-emitting time, which is beneficial to avoid display problems such as light leakage or afterimage.

[0048] Figure 8 FIG. 1 is another schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure, please refer to FIG. Figure 1 、 Figure 7 and Figure 8 In an optional embodiment of the present disclosure, the fourth transistor M4 and the fifth transistor M5 are oxide thin film transistors 02; and the other switching transistors are low-temperature polysilicon thin film transistors 01.

[0049] It should be noted that the low-temperature polycrystalline silicon thin film transistor 01 (LTPS transistor) has advantages such as small size and high mobility. High mobility means that the transistor can provide a larger current when it is turned on. The oxide thin film transistor 02 has the advantage of extremely low leakage current in the off state. In this embodiment, the fourth transistor M4 and the fifth transistor M5 are set as oxide thin film transistors 02. The fourth transistor M4 and the fifth transistor M5 are both closely connected to the gate (first node N1) of the driving transistor M0 or its related compensation path. Their low leakage current characteristics are conducive to maintaining the gate voltage of the driving transistor M0. In this way, the current transmitted by the driving transistor M0 to the light-emitting element 10 is more stable, which is conducive to achieving a display effect with no smear and uniform brightness. The extremely low leakage current of the oxide thin film transistor 02 is also conducive to stabilizing the voltage of the storage capacitor Cst. Even when displaying a static image for a long time, it is conducive to stabilizing the brightness of the display screen and improving problems such as brightness attenuation or drift. In addition, the low leakage current characteristic of the fourth transistor M4 is conducive to accurately storing the captured threshold voltage information of the driving transistor M0 on the storage capacitor Cst, thereby achieving more accurate threshold voltage compensation, which is further conducive to improving brightness uniformity. The other switching transistors are low-temperature polysilicon thin-film transistors 01, the first transistor M1 is a data voltage write switch, the third transistor M3 is a first power supply voltage supply switch, the sixth transistor M6 is a light-emitting control switch, and the seventh transistor M7 is a reset switch for the light-emitting element 10. Setting the other switching transistors except the fourth transistor M4 and the fifth transistor M5 as low-temperature polysilicon thin-film transistors 01 is conducive to the rapid conduction of the switching transistors, providing sufficient current, and efficient switching. In addition, the size of the low-temperature polysilicon thin-film transistor 01 is small, which is conducive to improving the pixel aperture ratio and thus improving the display effect. Optionally, the oxide thin-film transistor 02 is an IGZO (Indium Gallium Zinc Oxide) transistor.

[0050] Please continue to refer to Figure 1 、 Figure 7 and Figure 8In an optional embodiment of the present disclosure, along the first direction F1, the driving circuit layer 30 includes a semiconductor layer 31, a first metal layer 32, an oxide layer 33 and a second metal layer 34; the semiconductor layer 31 is located on one side of the substrate 00, the first metal layer 32 is located on the side of the semiconductor layer 31 away from the substrate 00, the oxide layer 33 is located on the side of the first metal layer 32 away from the substrate 00, and the second metal layer 34 is located on the side of the oxide layer 33 away from the substrate 00; the low-temperature polycrystalline silicon active layer 011 of the low-temperature polycrystalline silicon thin film transistor 01 is located in the semiconductor layer 31, and at least part of the gate 012 of the low-temperature polycrystalline silicon thin film transistor 01 is located in the first metal layer 32; the gate 022 of the oxide thin film transistor 02 is located in the second metal layer 34, and the oxide active layer 021 is located in the oxide layer 33.

[0051] Specifically, this embodiment provides a method for arranging different film layers when a driving circuit layer 30 includes both a low-temperature polysilicon thin-film transistor 01 and an oxide thin-film transistor 02. The driving circuit layer 30 includes a semiconductor layer 31, a first metal layer 32, an oxide layer 33, and a second metal layer 34 stacked along a first direction F1. The gate 012 of the low-temperature polysilicon thin-film transistor 01 can be located in the first metal layer 32, the low-temperature polysilicon active layer 011 can be located in the semiconductor layer 31, the gate 022 of the oxide thin-film transistor 02 can be located in the second metal layer 34, and the oxide active layer 021 can be located in the oxide layer 33.

[0052] It should be noted that both the low-temperature polysilicon thin-film transistor 01 and the oxide thin-film transistor 02 further include a source electrode s and a drain electrode d. The source electrode s and the drain electrode d may be located on other metal layers above the second metal layer 34, but the present disclosure is not limited thereto and may be designed according to actual conditions. The accompanying drawings of the present disclosure are only illustrated by the example of the source and drain electrodes of the low-temperature polysilicon thin-film transistor 01 and the oxide thin-film transistor 02 being arranged on the same layer, and are not limited thereto. The semiconductor layer 31 includes a source region and a drain region, and the source region and the drain region are formed by doping N-type impurity ions or P-type impurity ions. The source electrode s of the transistor is electrically connected to the source region of the semiconductor layer 31 through a contact hole, and the drain electrode d of the transistor is electrically connected to the drain region of the semiconductor layer 31 through a contact hole.

[0053] Please refer to Figures 1 to 4 as well as Figure 8 In an optional embodiment of the present disclosure, the shielding trace 40 overlaps with the semiconductor layer 31. Specifically, the second node N2 overlaps with the semiconductor layer 31, and capacitance exists between the second node N2 and the semiconductor layer 31. When the shielding trace 40 overlaps with the semiconductor layer 31, the capacitance of the second node N2 is increased, reducing image retention and smearing caused by voltage decay, further improving the display effect.

[0054] Please continue to refer to Figures 1 to 4 、 Figure 7 as well as Figure 8 In an optional embodiment of the present disclosure, the light emitting control signal line EMIT, the first scanning signal line SP1, the second scanning signal line SP2 and the third control signal line S3 are located in the first metal layer 32; the first control signal line S1N and the second control signal line S2N are located in the second metal layer 34.

[0055] Specifically, the light control signal line EMIT transmits the light control signal EMIT for controlling the on / off switching of the third transistor M3 and the sixth transistor M6; the first scan signal line SP1 transmits the first scan signal SP1 for controlling the on / off switching of the first transistor M1; the second scan signal line SP2 transmits the second scan signal SP2 for controlling the on / off switching of the second transistor M2; the third control signal line S3 transmits the third control signal S3 for controlling the on / off switching of the seventh transistor M7; the first control signal line S1N transmits the first control signal S1N for controlling the on / off switching of the fourth transistor M4; and the second control signal line S2N transmits the second control signal S2N for controlling the on / off switching of the fifth transistor M5. In this embodiment, the control signal lines for controlling the on / off switching of each transistor are arranged through multiple metal layers, which is beneficial for increasing the physical distance and dielectric isolation between different signal lines, thereby reducing parasitic capacitance coupling between each other, effectively suppressing mutual interference between different signal lines, and beneficial for avoiding various display defects in the display image.

[0056] Please continue to refer to Figures 1 to 4 as well as Figure 8 In an optional embodiment of the present disclosure, the shielding trace 40 is located in the second metal layer 34. The second metal layer 34 is located on the side of the first metal layer 32 away from the base substrate 00. The first metal layer 32 includes multiple traces. The side of the second metal layer 34 away from the base substrate 00 may also include other metal layers, also including multiple traces. Providing the shielding trace 40 in the second metal layer 34 is beneficial for shielding the vertical coupling between the first metal layer 32 and the second metal layer 34, and is also beneficial for shielding the vertical coupling between the second metal layer 34 and the metal layer located above it, which is more beneficial for improving the shielding effect, reducing coupling and crosstalk in the drive circuit layer 30, and improving the anti-crosstalk capability of the drive circuit layer 30.

[0057] Figure 9 FIG. 1 is another schematic diagram of a film layer of a display panel provided by an embodiment of the present disclosure, please refer to FIG. Figures 1 to 4 as well as Figure 9In an optional embodiment of the present disclosure, the driving circuit layer 30 further includes a third metal layer 35 and a fourth metal layer 36, the third metal layer 35 is located on the side of the second metal layer 34 away from the substrate 00, and the fourth metal layer 36 is located on the side of the third metal layer 35 away from the substrate 00; the first power supply voltage signal line PVDD includes a first sub-segment PVDD1 and a second sub-segment PVDD2, the first sub-segment PVDD1 extends along the second direction F2, and the second sub-segment PVDD2 extends along the third direction F3; the first sub-segment PVDD1 is located in the third metal layer 35, the second sub-segment PVDD2 is located in the fourth metal layer 36, and the first sub-segment PVDD1 and the second sub-segment PVDD2 are electrically connected.

[0058] Specifically, in this embodiment, different sub-segments of the first power supply voltage signal line PVDD are arranged on two independent metal layers, and the first sub-segment PVDD1 and the second sub-segment PVDD2 are connected by vias, which is equivalent to connecting multiple power lines in parallel, which is beneficial to reducing the total resistance of the power supply network composed of the first sub-segment PVDD1 and the second sub-segment PVDD2, and improving signal transmission efficiency. In addition, different sub-segments of the first power supply voltage signal line are arranged in multiple layers and form a grid, which is beneficial to each area of ​​the display panel 100 to obtain a uniform and stable power supply voltage, and is more beneficial to improving the brightness uniformity of the display product.

[0059] Based on the same inventive concept, the present disclosure provides a display device, Figure 10 FIG2 is a schematic diagram of a plan view of a display device provided by an embodiment of the present disclosure, please refer to FIG2 Figure 10 The display device 200 includes a display panel 100 , and the display panel 100 is any one of the display panels 100 provided in the present disclosure.

[0060] It should be noted that the embodiment of the display device 200 provided in the present disclosure can refer to the embodiment of the display panel 100 described above, and will not be repeated here. The display device 200 provided in the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a touch controller, a laptop computer, a navigation system, or the like.

[0061] It can be seen from the above embodiments that the display panel and display device provided by the present disclosure achieve at least the following beneficial effects:

[0062] The present disclosure provides a display panel and a display device, comprising a light-emitting element and a pixel driving circuit located in a driving circuit layer, wherein the pixel driving circuit comprises a driving transistor, wherein the gate of the driving transistor is electrically connected to a first node, and the first electrode and the second electrode are electrically connected to a second node and a third node, respectively; wherein the second node is coupled to a data voltage signal line in the driving circuit layer. The driving circuit layer further comprises a shielding trace, wherein the shielding trace is located between the first node and the data voltage signal line; the shielding trace at least partially overlaps with the second node, and the shielding trace is connected to a fixed potential signal. When a signal jump occurs in the data voltage signal line, the shielding trace forms an "electrostatic shielding layer" between the first node and the data voltage signal line, reducing the influence of the coupled signal on the first node. Therefore, the shielding trace can reduce the coupling between the data voltage signal line and the first node, which is beneficial to reducing the influence on the gate potential of the driving transistor, and thus is beneficial to improving the crosstalk problem between the first node and the data voltage signal line, thereby improving display problems such as uneven display and ghosting, and improving the display effect. In addition, the present disclosure sets the shielding line to at least partially overlap with the second node, which is beneficial to increase the capacitance of the second node, thereby increasing the charge storage capacity of the second node, slowing down the voltage decay of the second node, and thus helping to reduce image retention and ghosting caused by voltage decay, and further helping to improve the display effect.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0064] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: comprising a plurality of light emitting elements and a pixel driving circuit for driving the light emitting elements; The display panel further includes a base substrate and a driving circuit layer stacked along a first direction, the driving circuit layer being located on one side of the base substrate, and the pixel driving circuit being located on the driving circuit layer, and the first direction being perpendicular to the plane where the display panel is located; The pixel driving circuit includes a driving transistor, wherein the gate of the driving transistor is electrically connected to the first node, and the first electrode and the second electrode are electrically connected to the second node and the third node respectively; The driving circuit layer further includes a data voltage signal line, the second node is coupled to the data voltage signal line, the data voltage signal line extends along a second direction, and the second direction is parallel to the plane where the display panel is located; The driving circuit layer further includes a shielding line, and the shielding line is located between the first node and the data voltage signal line along a third direction, and the third direction is parallel to the plane where the display panel is located and perpendicular to the second direction; Along the first direction, the shielding line at least partially overlaps with the second node, and the shielding line is connected to a fixed potential signal.

2. The display panel according to claim 1, wherein: The driving circuit layer further includes a first power supply voltage signal line, and the second node is coupled to the first power supply voltage signal line; The shielding wiring is electrically connected to the first power supply voltage signal line.

3. The display panel according to claim 2, wherein: The first power supply voltage signal line includes a first sub-segment and a second sub-segment, the first sub-segment extends along the second direction, and the second sub-segment extends along the third direction; The second sub-segment is electrically connected to the first sub-segment and the shielding trace through vias.

4. The display panel according to claim 1, wherein: The driving circuit layer further includes a first reset signal line, and the first node is coupled to the first reset signal line; The shielding wiring is electrically connected to the first reset signal line.

5. The display panel according to claim 1, wherein: The driving circuit layer further includes a second reset signal line, and the first electrode of the light emitting element is coupled to the second reset signal line; The shielding wiring is electrically connected to the second reset signal line.

6. The display panel according to claim 1, wherein: The driving circuit layer further includes a bias signal line, and the second node or the third node is coupled to the bias signal line; The shielding trace is electrically connected to the bias signal line.

7. The display panel according to claim 1, wherein: The pixel driving circuit further includes a switching transistor and a storage capacitor, wherein the switching transistor includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The gate of the first transistor is electrically connected to the first scan signal line, and the first electrode and the second electrode are electrically connected to the data voltage signal line and the second node respectively; The gate of the second transistor is connected to the second scan signal line, the first electrode is electrically connected to the bias signal line, and the second electrode is electrically connected to the second node or the third node; The gate of the third transistor is electrically connected to the light emitting control signal line, and the first electrode and the second electrode are electrically connected to the first power supply voltage signal line and the second node respectively; The gate of the fourth transistor is electrically connected to the first control signal line, and the first electrode and the second electrode are electrically connected to the first node and the third node respectively; The gate of the fifth transistor is electrically connected to the second control signal line, and the first electrode and the second electrode are electrically connected to the first reset signal line and the first node respectively; The gate of the sixth transistor is electrically connected to the light emitting control signal line, and the first electrode and the second electrode are electrically connected to the third node and the first electrode of the light emitting element respectively; The gate of the seventh transistor is electrically connected to the third control signal line, and the first electrode and the second electrode are electrically connected to the second reset signal line and the first electrode of the light emitting element respectively; The storage capacitor is electrically connected between the first node and the first electrode of the first transistor.

8. The display panel according to claim 7, wherein: The fourth transistor and the fifth transistor are oxide thin film transistors; the other switch transistors are low-temperature polysilicon thin film transistors.

9. The display panel according to claim 8, wherein: Along the first direction, the driving circuit layer includes a semiconductor layer, a first metal layer, an oxide layer and a second metal layer; The semiconductor layer is located on one side of the substrate, the first metal layer is located on a side of the semiconductor layer away from the substrate, the oxide layer is located on a side of the first metal layer away from the substrate, and the second metal layer is located on a side of the oxide layer away from the substrate; The low-temperature polysilicon active layer of the low-temperature polysilicon thin film transistor is located in the semiconductor layer, and at least part of the gate of the low-temperature polysilicon thin film transistor is located in the first metal layer; The gate of the oxide thin film transistor is located in the second metal layer, and the oxide active layer is located in the oxide layer.

10. The display panel according to claim 9, wherein: The shielding trace overlaps the semiconductor layer.

11. The display panel according to claim 9, wherein The light emitting control signal line, the first scanning signal line, the second scanning signal line and the third control signal line are located in the first metal layer; The first control signal line and the second control signal line are located in the second metal layer.

12. The display panel according to claim 9, wherein: The shielding trace is located on the second metal layer.

13. The display panel according to claim 12, wherein: The driving circuit layer further includes a third metal layer and a fourth metal layer, wherein the third metal layer is located on a side of the second metal layer away from the base substrate, and the fourth metal layer is located on a side of the third metal layer away from the base substrate; The first power supply voltage signal line includes a first sub-segment and a second sub-segment, the first sub-segment extends along the second direction, and the second sub-segment extends along the third direction; The first sub-segment is located in the third metal layer, the second sub-segment is located in the fourth metal layer, and the first sub-segment is electrically connected to the second sub-segment.

14. A display device, characterized in that: A display panel comprising the display panel according to any one of claims 1 to 13.

Images