A multi-cycle modulation driving component, method, system, and product

Abstract

This invention proposes a multi-cycle modulation driving component, method, system, and product. The multi-cycle modulation driving component includes a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component. The state division component performs functional decoding based on the device's functional mode and generates timing-matched trigger signals according to the specific functional mode. The synchronous multi-cycle configuration component generates various types of periodic / aperiodic enable signals at different clock frequencies based on configuration information, realizing multi-cycle timing drive. The single-cycle modulation component can serve as a general-purpose modulation unit; each unit can generate periodic composite on-chip timing drive signals based on configuration information and multi-cycle drive signals, thereby meeting the driving requirements of digital and analog readout units of different device chips. This invention can greatly simplify the overall timing structure of the driving chip.

Description

Technical Field

[0001] This invention proposes a multi-cycle modulation driving component, driving method, driving system, and product, belonging to the field of digital integrated circuits. Background Technology

[0002] Modern, complex device chips inevitably require driving multiple cycles and complex timing sequences. This places high demands on the timing interfacing between upstream and downstream modules in the hardware circuit. For pipelined operation modes, the timing becomes even more complex. Therefore, it is often necessary to design complex driver circuits for multiple cycles to drive sequential digital and analog readouts, thereby meeting the driving and readout requirements of complex functional device chips.

[0003] Currently, the mainstream design approach for driver and readout circuits of device chips is a top-down approach. This involves first planning the timing requirements at the top level, and then designing the preceding and following stages based on those timings. This approach requires first determining the hardware structure of the overall chip's array driver and readout circuits, then designing the timing, and finally designing the control logic that generates the timing. The circuits typically employ complex counter modules, using external trigger signals and timing configuration information to output drive signals that meet the chip's driving requirements. This approach results in complex on-chip circuit design, large area footprint, and long design cycles, often requiring customization for specific driving needs. Timing adjustments are limited to fine-tuning the duration of states, making it impossible to change the overall drive timing. The waveform adjustability is low, and subsequent verification requires significant manpower and integration costs. Summary of the Invention

[0004] This invention proposes a multi-period modulation driving component, driving method, driving system, and product. Utilizing technologies such as Software-Defined Networking (SDN), the control plane is decoupled from the hardware. A remote controller can configure storage unit data and program circuit logic devices for different controlled devices based on device coding, providing various periodic / aperiodic timing drive signals required by multiple controlled device chips, and is compatible with the timing requirements of driving and data reading from different device chip arrays. Using a software-generated programmable interconnect array of sub-modules, the remote controller can batch-produce multi-periodic modulation drive signal outputs. This eliminates the need for additional custom designs, meeting the flexible configuration and real-time switching requirements of periodic and aperiodic drive signals for different devices in multiple modes, reducing design complexity and design and verification costs, and enabling flexible configuration of drive signals across multiple devices and modes. This driving component, driving method, driving system, and product, while meeting the driving requirements of different device chips, also provide a driving solution for current satellite equipment programming and cloud device control. By converting digital drive signals into control signals, microprocessors and microcontrollers of different devices can drive various functions of electronic devices, such as controlling mechanical motion, processing data, and managing communications.

[0005] The technical solution adopted by the circuit of this invention is as follows:

[0006] A multi-cycle modulation driving component and its driving method are characterized by separating the control plane from the hardware using technologies such as SDN, utilizing a logically centralized remote controller, and configuring the parameters of the multi-cycle modulation driven numerical control circuit based on device coding information through a communication data interface between the control plane and the hardware plane implemented via protocols such as OpenFlow. The driving component simultaneously feeds data back to the controller in real time via a data feedback link, enabling flexible and effective configuration of the hardware circuit. The software-generated programmable interconnection sub-module array circuit includes a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component connected in sequence. The state division component is used for functional decoding according to the functional mode, generating trigger signals that meet timing requirements based on the specific functional mode. The synchronous multi-cycle configuration component is used to generate various types of periodic / aperiodic enable signals at different clock frequencies based on configuration information, realizing multi-cycle timing drive. The single-cycle modulation component, as a general-purpose modulation unit, can generate periodic compound on-chip timing drive signals based on configuration information and multi-cycle drive signals, thereby meeting the driving requirements of different device chips.

[0007] Furthermore, the remote controller can be a host computer or a cloud device. The multi-cycle modulation drive component based on SDN technology abstracts the underlying hardware devices into a virtualized resource pool, decoupling control from the hardware. Hardware engineers can utilize the remote controller through, for example, OpenFlow, Serial Peripheral Interface (SPI), or Inter-Integrated Circuit (I2C) interfaces. 2 C) Matching of communication data interfaces between the control plane and hardware plane implemented by protocols such as C) Reorganizing data streams and data packets so that the feedback link can adjust the data packets and transmit them after receiving information, thereby realizing the data configuration of storage units and programming of circuit logic devices for different controlled devices.

[0008] Furthermore, the state division component is adapted to at least one digital input signal and one digital output signal for functional decoding according to the functional mode of the device chip, and for generating a timing-matching trigger signal based on the specific functional mode; wherein the one digital input signal is data configuration information Config_Data1, including chip operating mode information and configuration parameters under different functional modes, the chip operating mode information including TriggerBegin request information requiring the controlled device to start; the configuration parameters under different functional modes may include at least one of the state durations, such as reset state, exposure state, readout state, and programming state; the one digital output signal is a timing-matching trigger signal MatchTriggerBegin transmitted to the synchronous multi-cycle configuration component;

[0009] Furthermore, the state division component includes a mode judgment logic module and a trigger delay module. The mode judgment logic module, ModeJudge_Logic, performs combinational logic judgment and configures, for example, a delay storage unit, MatchNum, based on the data configuration information Config_Data1. The trigger delay module, TriggerDelay, modulates the delay time of external trigger signals and periodic enable drive signals under different functional modes based on the configuration information of the delay storage unit and the request information TriggerBegin requiring the controlled device to start, and outputs the timing-matched trigger signal MatchTriggerBegin to the synchronous multi-cycle configuration component.

[0010] Furthermore, the synchronous multi-cycle configuration component adapts to two digital input signals and two digital output signals, used to generate various types of periodic / aperiodic enable signals at different clock frequencies based on off-chip configuration information, simultaneously implementing multi-cycle timing drive on-chip. The two digital input signals are the trigger signal MatchTriggerBegin from the state division component and the data configuration information Config_Data2, respectively. The two digital output signals are a set of one-dimensional array drive enable signals PeriodValid and one-dimensional array end signals ModeEnd, which can characterize various cycle types of the chip. The drive enable signal PeriodValid and end signal ModeEnd are preferably one-dimensional array signals, but this is not a limitation. In fact, the drive enable signal PeriodValid and end signal ModeEnd can also be two-dimensional arrays, for example, to combine multiple related data for input, output, and processing.

[0011] Furthermore, the synchronous multi-cycle configuration component includes a decoding module, k clock reset generation submodules, and k configuration submodules to achieve multi-cycle enable modulation under the same clock frequency group, where k is the number of enable signal generation and k is a positive integer. The remote controller can instantiate multiple synchronous multi-cycle configuration components via data communication, and each component can operate independently. These multiple synchronous multi-cycle configuration components can generate drive signals under different frequency groups, such as Hz frequency groups, KHz frequency groups, etc. In a synchronous multi-cycle configuration component, the decoding module decodes and outputs the data configuration information Config_Data2 to internal sub-modules, configuring and strobing the sub-modules. Sub-modules that are not strobed are in standby mode. The internal k sub-modules generate drive signals at different main frequencies within the same frequency group. The clock reset generation sub-module provides stable and reliable clock signals and synchronous reset signals of different frequencies to the configuration sub-module and the single-cycle modulation component within the same clock frequency group, ensuring that each module operates at a specific main frequency. The configuration sub-module performs combinational logic judgment and configures the corresponding storage units PeriodNum, EnableNum, and RepeatNum based on its data configuration information Config_Data2. It implements the timing configuration of periodic and non-periodic drive signals through counters PeriodCounter and RepeatCounter, achieving the timing configuration of periodic and non-periodic drive signals at a specific clock main frequency. The output is the multi-cycle drive enable signal PeriodValid and the end signal ModeEnd of the single-cycle modulation component.

[0012] Furthermore, the single-cycle modulation component adapts to at least four digital input signals and at least one digital output signal as a modulation unit. Each modulation unit generates a periodic composite on-chip timing drive signal based on the off-chip signal type encoding and configuration information, as well as the multi-cycle drive enable signal and end signal, thereby driving all subsequent digital and analog readout units. The four digital input signals are the signal type encoding Config_Type, the corresponding signal timing data configuration information Config_Data3, the drive enable signal PeriodValid, and the end signal ModeEnd. The one digital output signal is the complex on-chip timing drive signal DriverSignal required by the chip's digital and analog readout units.

[0013] Furthermore, the single-cycle modulation component includes n driver submodules responsible for generating multiple complex on-chip timing drive signals, where n is the number of drive signals generated and is a positive integer. Each driver submodule, based on the input signal type encoding Config_Type, uses combinational logic to determine the type of the drive signal and the number of high / low level transitions. Upon receiving the input drive enable signal PeriodValid, it begins operation and modulates and generates the drive signal DriverSignal via the state machine submodule. Based on the device encoding DeviceType in the data configuration information, a selector is used to output either the modulated drive signal DriverSignal or the enable signal PeriodValid directly.

[0014] The present invention employs various storage units, such as delay storage units, enable signal period storage units, high-level duration storage units within a single cycle, and single-cycle repetition count storage units. The storage units involved can be general-purpose memory units, but registers are preferred. This has been confirmed by the research and simulation phases of the product of this invention.

[0015] The term "composite" in the context of composite on-chip timing drive signals, composite timing, and composite multi-cycle drive signals in this invention refers to both multiple parallel timing signals and the required multiple compound drive signals, as well as a single timing signal with a complex timing pattern and signal waveform.

[0016] The present invention also provides a driving method for the driving component utilizing the above-described multi-cycle modulation, the driving method comprising, for example, the following steps:

[0017] S1, data configuration writing is performed. Hardware technicians can send instructions to network devices through programming languages. After receiving the instructions, the remote controller selects the storage unit configuration information according to the device encoding information. The controller realizes data communication with the hardware circuit through protocols such as OpenFlow, adjusts the data transmission according to the information received from the feedback link, and realizes the storage unit data configuration and circuit logic device programming of the CNC circuit driven by multi-cycle modulation for different devices.

[0018] S2, Perform functional state division: The state division component receives the target device working mode code, corresponding functional mode timing and data configuration information Config_Data1, and the mode judgment logic module is set to the configuration delay storage unit MatchNum; The trigger delay module is set to start working under the trigger of the TriggerBegin signal, which is based on the request information TriggerBegin signal from the outside that requires the controlled device to start. When its built-in counter counts to MatchNum, it outputs the timing-matched trigger signal MatchTriggerBegin signal, and the signal is high for at least one clock cycle.

[0019] S3 involves configuring multi-cycle enable signals. The remote controller can instantiate multiple synchronous multi-cycle configuration components via data communication. Upon receiving data configuration information Config_Data2, which includes submodule selection signals, main frequency selection signals, operating status encoding information, timing configuration information, and drive switching enable, the synchronous multi-cycle configuration component uses a combinational logic decoder to select and configure the submodules. Submodules not selected remain in standby mode. The clock reset generation submodule selects the operating main frequency based on the data configuration information, providing stable and reliable clock signals and synchronous reset signals of different frequencies for the configuration submodules and single-cycle modulation components, ensuring that each module operates at a specific main frequency. The configuration submodule, based on the data configuration information, determines and configures the enable signal period storage unit PeriodNum, the high-level duration storage unit EnableNum within a single cycle, and the repeat count storage unit RepeatNum within a single cycle through combinational logic. The k submodules instantiated by the synchronous multi-cycle configuration component start working after receiving the timing-matched trigger signal MatchTriggerBegin. The counter PeriodCounter starts counting and outputs the enable signal PeriodValid with a single cycle duration of PeriodNum and a high-level duration of EnableNum within the cycle. After the counter RepeatCounter counts the single-cycle repetition count of the enable signal to EnableNum, it outputs the mode end signal ModeEnd, thus simultaneously enabling the multi-cycle drive of the subsequent k single-cycle modulation submodules on-chip.

[0020] S4 generates the modulation signal within a single cycle. The single-cycle modulation component receives the external configuration information Config_Type and Config_Data3, determines the type and timing information of the drive signal through combinational logic, and configures the corresponding storage unit. The n sub-modules instantiated by the single-cycle modulation component operate under the same drive enable signal PeriodValid. When PeriodValid is high, the built-in counter and sub-state machine modulate PeriodValid into n periodic, complex on-chip timing drive signals DriverSignal. Based on the device code DeviceType in the data configuration information, the module uses a selector to output the modulation drive signal DriverSignal or directly output the enable signal PeriodValid, ultimately achieving timing drive for all on-chip digital and analog readout units.

[0021] This invention proposes a multi-cycle modulation driving component and its driving method. Specifically, for example, SDN technology is used to decouple the control plane from the hardware. A remote controller configures the storage unit data and programs the circuit logic devices of different controlled devices based on the device code. A programmable interconnect array of sub-modules is connected using software-generated programs, and the remote controller can output multi-cycle modulation driving signals in batches. This numerical control circuit decouples the originally complex on-chip driving signal generation module and divides it into three hardware components: a status division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component. By dividing the hardware functions and software programming, each module is flexibly adjustable. It can be combined to flexibly configure and switch the periodic / aperiodic driving signals of different device chips, meeting the complex driving needs of digital and analog readout units in multiple devices and modes. Since the three hardware components can all be configured and programmed based on the data configuration of the remote controller, the driving module can be designed in advance without determining the timing, and is compatible with the timing requirements of driving and reading data from different device chip arrays. The synchronous multi-cycle configuration component and single-cycle modulation component have low hardware complexity, and their internal sub-modules can be repeatedly instantiated in batches, greatly reducing the complexity of the driver module. Subsequent circuit design, circuit verification, and back-end design can all be carried out in batches, significantly reducing design and verification costs. Accordingly, the driving method of this invention includes data configuration writing, functional state partitioning, synchronous multi-cycle enable configuration, and single-cycle drive configuration. This driving method can flexibly and efficiently configure complex drive signal timing.

[0022] In summary, this invention, based on SDN technology, provides flexible and reliable digital drives for different device chips through data configuration from a remote controller. This improves the fault tolerance and flexibility of chip timing design. Compared to traditional solutions, this invention, through off-chip flexibility and reusability of multiple modules, shortens the design cycle while meeting complex drive requirements. Furthermore, it reduces the difficulty of chip design and verification. By converting digital drive signals into control signals, microprocessors and microcontrollers in different devices can drive various functions of electronic devices, such as controlling mechanical motion, processing data, and managing communication. Simultaneously, the programmable characteristics and flexible data configuration of this numerical control circuit also provide a drive solution for current satellite equipment programming and cloud device control.

[0023] According to another aspect of the present invention, a system is also disclosed for multiple multi-cycle, multi-time sequence operating processes, including various multi-cycle modulation drive components described in the present invention, for generating composite multi-cycle drive signals for multiple controlled devices controlling the system. Attached Figure Description

[0024] Figure 1 This is a block diagram of the numerical control circuit of the multi-cycle modulation driving component in an embodiment of the present invention;

[0025] Figure 2 This is a functional configuration and hardware circuit programming block diagram of the multi-cycle modulation driving component in this embodiment of the invention;

[0026] Figure 3 This is a flowchart of the driving method for the multi-cycle modulation driving component in an embodiment of the present invention;

[0027] Figure 4 This is a timing diagram of the synchronous multi-cycle enable configuration in an embodiment of the present invention;

[0028] Figure 5 This is the truth table of the driving signal modulation in a single cycle in this embodiment of the invention (taking 4 bits as an example);

[0029] Figure 6 This is a state timing diagram of the sub-state machine of the single-cycle modulation component in an embodiment of the present invention;

[0030] Figure 7 This is a timing diagram of timing modulation and periodic / aperiodic drive signal switching within a single cycle in an embodiment of the present invention;

[0031] Figure 8 This is the multi-cycle modulation driving system disclosed in this invention.

[0032] Figure 9 It is the driver program for multi-cycle modulation disclosed in this invention. Detailed Implementation

[0033] This embodiment provides a multi-cycle modulation driving component and its driving method. The circuit utilizes SDN technology to configure storage unit data and program circuit logic devices for different devices via a remote controller based on device codes. Using a software-generated programmable interconnect array of sub-modules, the remote controller can batch-output multi-cycle modulation driving signals at different clock frequencies. This driving component decouples the originally complex on-chip driving signal generation module, dividing it into three components: a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component. The state division component performs functional decoding based on the functional mode and generates timing-matched trigger signals according to the specific functional mode. The synchronous multi-cycle configuration component generates various types of periodic / aperiodic enable signals at different clock frequencies based on configuration information, achieving multi-cycle timing drive. The single-cycle modulation component, as a general-purpose modulation unit, can generate periodic composite on-chip timing drive signals based on configuration information and multi-cycle driving signals, thereby meeting the driving requirements of different device chips.

[0034] This embodiment provides a multi-cycle modulation driving method, the steps of which are shown in the flowchart below. Figure 1 As shown ( Figure 1 In this array, MatchTriggerBegin is the trigger signal for timing matching; PeriodValid is the enable signal for the single-cycle modulation component, which is usually an array; ModeEnd is the end signal for the single-cycle modulation component, which is usually an array; and DriverSignal is the final output drive signal, which is usually an array.

[0035] Figure 2 The functional configuration and hardware circuit programming block diagram of the drive component are shown. Hardware technicians utilize TopControl (e.g., a remote controller, host computer, etc.) through communication data interfaces between the control layer and hardware layer implemented via protocols such as OpenFlow. Based on information received from the feedback link, they adjust the transmitted data to configure storage unit data and program circuit logic devices for different controlled devices. The software-generated programmable interconnection submodule array circuit includes a state division component 120, a synchronous multi-cycle configuration component 121, and a single-cycle modulation component 122 connected in sequence. This meets the needs of different devices for flexible configuration and real-time switching of periodic and aperiodic drive signals in multiple modes.

[0036] Reference Figure 2The functional configuration and hardware circuit programming block diagram of the drive component are as follows: First, the remote controller 110, through the control layer and hardware layer communication data interface implemented by protocols such as OpenFlow, configures the parameters of the multi-cycle modulation drive component 111 (including: state division component 120, synchronous multi-cycle configuration component 121, and single-cycle modulation component 122) according to the encoded information Device_fN (N = 0, 1, ..., K-1, K is a positive integer) of the controlled device 123. Simultaneously, the numerical control circuit of the drive component 111 sends data back to the remote controller 110 in real time through the data feedback link, realizing flexible and effective configuration of the hardware circuit. Then, functional state decoding is performed. (Refer to...) Figure 3 The state division component 120 receives the data configuration signal Config_Data1 as input. The mode judgment logic module 130 (ModeJudge_Logic) performs functional decoding based on the Config_Data1 signal, then performs combinational logic judgment and configures a delay storage unit. The delay value in the configured delay storage unit is represented by MatchNum to meet the synchronous triggering requirements between modules in different modes. The trigger delay module 131 (TriggerDelay) starts working after receiving the TriggerBegin signal, a request message from the external configuration information Config_Data1 requesting the controlled device to start. After its built-in counter counts to MatchNum, it outputs a timing-matched trigger signal MatchTriggerBegin, whose high-level duration is typically at least greater than a predetermined value (e.g., one clock cycle), to ensure that the synchronous triggering process can proceed normally. It should be noted that the high-level duration of the timing-matched trigger signal MatchTriggerBegin does not necessarily have to be absolutely greater than one clock cycle; it can be longer or relatively shorter, as long as the synchronous triggering process can proceed normally.

[0037] Then, the multi-cycle enable signal is configured. The synchronous multi-cycle configuration component 121 generates various types of periodic / aperiodic drive enable signals at different clock frequencies based on the external configuration information, thus simultaneously implementing multi-cycle timing drive on-chip. The inputs of the synchronous multi-cycle configuration component 121 are the MatchTriggerBegin signal and the Config_Data2 signal, which contains external data configuration information. In the synchronous multi-cycle configuration component 121, the decoding module 132 (Decoder) decodes the data according to its data configuration information Config_Data2 and outputs the decoded data to internal sub-modules (such as clock reset generation sub-module 133 (CRG) and configuration sub-module 134 (ConfigureBlock)) to configure and select the sub-modules. Sub-modules that are not selected are in standby mode. The internal k sub-modules realize the generation of drive signals under different main frequencies in the same frequency group. Each sub-module performs combinational logic judgment and configures the enable signal period storage unit (the configured value is represented by PeriodNum), the high level duration storage unit in a single cycle (the configured value is represented by EnableNum), and the number of repetitions in a single cycle storage unit (the configured value is represented by RepeatNum) according to the external configuration information (such as the data configuration information Config_Data2 mentioned above). The submodule starts working after receiving the trigger signal MatchTriggerBegin. The counter PeriodCounter starts counting and outputs an enable signal PeriodValid with a single cycle duration of PeriodNum and a high-level duration of EnableNum within the cycle. The counter RepeatCounter counts the number of times the enable signal repeats in a single cycle until EnableNum is reached, and then outputs a mode end signal ModeEnd. Based on the switching enable of periodic drive and non-periodic drive, the switching between periodic drive and non-periodic drive can be flexibly controlled. The output PeriodValid signal serves as the enable signal for subsequent single-cycle modulation components. Only the selected ConfigureBlock will work; the unselected ConfigureBlock will remain in standby mode. The output ModeEnd signal is the end signal for the controlled device's working mode. It is fed back to the state division component and output to the single-cycle modulation component to perform a Clear operation on the component's internal storage unit and to turn off the output drive signal.

[0038] Finally, a single-cycle drive signal modulation is generated. The single-cycle modulation component 122 can instantiate n drive sub-modules 135, all operating under the same drive enable signal PeriodValid. The single-cycle modulation component 122 receives external configuration information Config_Type and Config_Data3, determines the type and timing information of the drive signal through combinational logic, and configures the corresponding storage units. The n sub-modules operate when the enable signal PeriodValid is high, and the built-in counter and sub-state machine modulate PeriodValid into n periodic composite on-chip timing drive signals DriverSignal. The built-in selector in each sub-module can select modulated or unmodulated output based on the device type DeviceType, ultimately realizing the timing drive of the digital and analog readout units of the controlled device chip.

[0039] The specific module block diagram of the CNC circuit of the drive component provided in this embodiment is as follows: Figure 3 As shown, in Figure 3 In this code, Config_Data1, Config_Data2, Config_Data3, and Config_Type are external configuration parameters; ModeJudge_Logic is the mode judgment logic module; TriggerDelay is the trigger delay module; MatchNum is the delay value configured in the delay storage unit; MatchTriggerBegin is the timing matching trigger signal; Decorder is the decoding module; CRG is the clock reset generation submodule; ConfigureBlock is the configuration submodule; PeriodValid is the single-cycle modulation component enable signal; ModeEnd is the mode end signal; ClockSwitch is the clock switching module; Synchronous is the synchronizer; Period... dCounter is the period duration counter module; RepeatCounter is the repetition count counter module; PeriodNum is the value configured in the enable signal period storage unit; EnableNum is the value configured in the high-level duration storage unit within a single cycle; RepeatNum is the value configured in the single-cycle repetition count storage unit, which can be used to indicate the number of times the enable signal cycle repeats; DriverBlock is the single-cycle driver submodule; Judge_Logic is the combinational logic judgment module; Modulate_Counter is the high / low level delay time counter; State_Counter is the signal toggle count counter; FSM is the sub-state machine; DeviceType is the device chip number; DriverSignal is the drive signal.

[0040] The state division component includes one digital input signal and one digital output signal. The digital input signal is the data configuration information Config_Data1, and the digital output signal is the timing matching trigger signal MatchTriggerBegin. The data configuration information Config_Data1 includes the operating mode information of the controlled device chip and configuration parameters for different functional modes. The operating mode information of the device chip includes the request information TriggerBegin requesting the controlled device chip to start and chip operating mode information, such as at least one of gradient mode, grayscale mode, programming mode, and color image mode. The configuration parameters for different functional modes include the duration of at least one of the states such as reset state, exposure state, readout state, and programming state. The state division component 120 includes a mode judgment logic module 130 and a trigger delay module 131. The mode judgment logic module 130, based on the off-chip data configuration information Config_Data1, determines the current operating mode of the device chip through combinational logic, and configures the delay storage unit (such as the value MatchNum) according to the configuration parameters of different functional modes. The trigger delay module 131 starts working after receiving the TriggerBegin request signal requiring the controlled device to start, and generates timing-matching trigger signals for different functional modes through a counter. After the counter counts to MatchNum, it outputs the timing-matching trigger signal MatchTriggerBegin for the synchronous multi-cycle configuration component.

[0041] The synchronous multi-cycle configuration component includes two digital input signals and two digital output signals. The two digital input signals are a trigger signal MatchTriggerBegin and data configuration information Config_Data2, respectively. The two digital output signals are a set of drive enable signals PeriodValid and end signals ModeEnd, which can characterize various cycle types of the controlled device chip. The drive enable signal PeriodValid and end signal ModeEnd are preferably one-dimensional array signals, but this is not a limitation. The MatchTriggerBegin signal is a trigger signal that meets timing requirements. The Config_Data2 signal includes configuration parameters for the corresponding mode, such as at least one of the mode information including full sampling, downsampling, windowing, and windowing position; information such as single cycle time and high-level delay time; switching enable for cycle drive and non-cycle drive; submodule selection information; and clock frequency selection signal. The synchronous multi-cycle configuration component 121 includes a decoding module 132, a k clock reset generation submodule 133, and a k configuration submodule 134, where k is a positive integer. For example, a remote controller can communicate data using multiple synchronous multi-cycle configuration groups. Each component can operate independently, generating drive signals under different clock frequency groups, such as Hz frequency groups and KHz frequency groups. In a synchronous multi-cycle configuration component, the decoding module 132 configures and selects k sub-modules (such as clock reset generation sub-module 133 (CRG) and configuration sub-module 134 (ConfigureBlock)) based on the data configuration information Config_Data2. Sub-modules that are not selected are in standby mode. The k clock reset generation sub-modules can flexibly select the operating clock frequency of the configuration sub-modules and the single-cycle modulation component based on the clock frequency selection information, realizing the generation of drive signals under different clock frequencies within the same frequency group. The ClockSwitch module selects the operating frequency based on the clock frequency selection information. The reset and trigger signals are synchronized by the Synchronous module and then input to the subsequent configuration sub-modules and the single-cycle modulation component. Each of the k configuration sub-modules can be independently configured with different periodic / aperiodic modulation enable signals by external configuration parameters. The ConfigureBlock submodule includes a combinational logic judgment module and two key counters, PeriodCounter and RepeatCounter. The combinational logic judgment module is responsible for configuring the storage unit, while the PeriodCounter and RepeatCounter are responsible for driving the cycle count and cycle count, respectively.The specific driving flow of the configuration submodule is as follows: The external adjustable Config_Data2 signal input combinational logic judgment module, based on the configuration parameters of the current device mode, such as full sampling, downsampling, windowing, windowing position, etc., configures key storage units for the two counters PeriodCounter and RepeatCounter to store the enable signal period duration (PeriodNum), the high level duration within the period (EnableNum), and the number of repetitions (RepeatNum). RepeatCounter is a line counter. For example, for full resolution, this counter needs to count to n, while for downsampling 2x, it needs to count to n / 2. PeriodCounter is a signal period counter. This module calculates the corresponding drive signal period based on the enable signal period duration. When the counter reaches the predetermined value, it will be cleared and RepeatCounter will be incremented by one. After the ConfigureBlock module receives the trigger signal MatchTriggerBegin, the PeriodCounter starts working, the PeriodValid signal goes high, and when the counter reaches the predetermined value EnableNum, the PeriodValid signal goes low and continues counting. When the counter reaches the predetermined value PeriodNum, the counter is reset to zero and RepeatCounter is incremented. The PeriodValid signal will remain active throughout the entire mode operation until RepeatCounter counts to RepeatNum. The external input period / non-periodic switching enable can control the selection of the submodule drive signal, enabling flexible switching between periodic drive enable and non-periodic drive enable. The synchronous multi-period configuration component can instantiate multiple submodules to achieve, for example... Figure 4 The multi-period type drive signal PeriodValid is shown.

[0042] Reference Figure 4 The synchronous multi-cycle configuration component, based on the configuration data of the controlled device, selects the operating clock frequency CLK_0, CLK_1, etc., of the corresponding configuration sub-modules through multiple CRG modules. The configuration sub-modules utilize a period counter (PeriodCounter) to count the cycles of the drive enable signals, such as Period1, Period2, Period3, etc. The high-level duration (EnableNum) within a cycle controls the high level of the drive enable signal, and the low-level duration is obtained by subtracting the enable signal cycle duration (PeriodNum) from the high-level duration (EnableNum). The repeat counter (RepeatCounter) counts the cycles of the drive enable signals; when the count reaches RepeatNum, it outputs the end signal ModeEnd.

[0043] The single-cycle modulation component includes four digital input signals and one digital output signal. The four digital input signals are the signal type code Config_Type, the corresponding signal timing data configuration information Config_Data3, the drive enable signal PeriodValid, and the end signal ModeEnd. The one digital output signal is the DriverSignal signal, which is the composite on-chip timing drive required by the digital and analog readout unit of the controlled device chip. The single-cycle modulation component 122 contains n drive modulation submodules 135. Individual submodules can be batch instantiated, and each submodule can be independently configured by external configuration parameters to implement composite on-chip timing drive within a single cycle, where n is the number of drive signal generation, and n is a positive integer. The DriverBlock submodule includes a combinational logic judgment module, a sub-state machine FSM, a high / low level delay time counter Modulate_Counter, and a signal toggle count counter State_Counter. Based on the input signal type code Config_Type, the submodule uses combinational logic to determine the type of the generated drive signal and the number of high / low level toggle counts, and configures the corresponding storage units. The highest bit of the input signal type encoding Config_Type is processed by a first-level selector in the Judge_Logic combinational judgment logic to determine the initial level of the drive signal. If the value is 1, the initial level is high; if it is 0, the initial level is low. The other bits are processed by a second-level selector in the Judge_Logic combinational judgment logic to determine the number of high-low level toggles. The submodule's built-in selector can select modulated or unmodulated output based on the DeviceType, ultimately meeting the complex drive requirements of different device chips' digital and analog readout units at different clock frequencies.

[0044] Figure 5 The diagram illustrates the modulation truth table for a single cycle of the drive signal, using a 4-bit example. The highest bit of Config_Type determines the initial level, while the remaining bits determine the driving signal's toggle. Config_Type is not limited to 4 bits and can be any other data with any number of bits. The sub-state machine modulates and generates the drive signal DriverSignal based on the input enable signal PeriodValid and the configured storage unit. Upon receiving PeriodValid, the sub-state machine starts counting with Modulate_Counter. Once the counter reaches a predetermined value, it is reset to zero, the state machine outputs a state transition, and State_Counter is incremented by 1. After State_Counter reaches the predetermined value, the next cycle begins, and the drive signal DriverSignal output by the state machine will continue throughout the entire operating phase of the mode.

[0045] The sub-state machine module is as follows: Figure 6As shown, there are four states: S0 (standby state), S1 (high level state), S2 (low level state), and S3 (end state). The state transitions need to be based on the signal type and the number of high / low level toggles. To achieve a periodic drive signal output with a low starting level and four toggles within a cycle, a state loop from S0 to S2 to S1 to S2 to S1 to S3 needs to be implemented. The drive signal generation is as follows... Figure 7 In DriverSignal2, to switch from a periodic signal to a non-periodic drive signal, with the non-periodic drive signal starting at a high level and then toggling between high and low levels three times, an external input switch enable signal SwitchEnable is needed. This enables a state cycle from S0 to S1 to S2 to S1 to S3, and the generation of the drive signal is as described in the non-periodic stage of DriverSignal2 in section 7. The timing data configuration information Config_Data3 corresponding to the input signal is used to generate state machine transition trigger signals CounterDone and EndStateValid through the built-in counter of the single-period modulation component, thereby achieving the periodic composite on-chip timing drive signal output.

[0046] Figure 7 The timing diagram for timing modulation and periodic / aperiodic drive signal switching within a single cycle is shown. (Refer to...) Figure 7 The enable signal PeriodValid_0 from the synchronous multi-cycle configuration component is used as the drive enable for the single-cycle modulation component, configuring a timing diagram for generating periodic composite on-chip timing drive signals. The single-cycle modulation component can start operating when the enable signal is high, based on the external configuration information Config_Data3 and Config_Type. It modulates the drive signal to achieve constant high level, constant low level, and complex timing within a single cycle, creating the drive signal DriverSignal. For example, when Config_Type is 3'b101, the single-cycle modulation component modulates PeriodValid_0 into DriverSignal_0 based on the high and low level durations in Config_Data3 using a sub-state machine. When Config_Type is 3'b111, PeriodValid_0 is modulated into DriverSignal_1. (Refer to...) Figure 7 The single-cycle modulation component can flexibly modulate periodic and aperiodic driving based on the external input signal SwitchEnable. The drive enable time of the aperiodic drive can be configured independently. If no modulation is performed, the timing of the DriverSignal_0 drive signal in the aperiodic phase is output. If modulation is performed, the timing of DriverSignal_1, DriverSignal_2, etc. in the aperiodic phase is output.

[0047] Figure 8 A multi-cycle modulation drive system is illustrated. The drive system includes a remote controller (e.g., a host computer), a cloud, a software-defined network (SDN), and controlled devices. The SDN-based multi-cycle modulation drive component abstracts the underlying hardware devices into a virtualized resource pool. Hardware technicians can leverage the matching of control-level and hardware-level communication data interfaces implemented through the cloud or peripheral interfaces of the remote controller to achieve storage unit data configuration and circuit logic device programming for different controlled devices. The SDN-based drive component includes one state partitioning component, k multi-cycle configuration components, and n single-cycle modulation components. (See reference...) Figure 8 A state partitioning component can trigger k multi-cycle configuration components based on configuration information, enabling modulation of the delay time between the external trigger signal and the cycle enable drive signal under different clock frequencies and functional modes. (See reference...) Figure 8 In this context, a multi-cycle configuration component _k-1 can drive n single-cycle modulation components to generate n modulation drive signals, thereby enabling the driving of multiple device chips.

[0048] Figure 9 This demonstrates a multi-cycle modulation driver (i.e., a computer program product). Hardware technicians, based on the driving requirements of different device chips, can utilize a remote controller to achieve communication between the control and hardware layers via protocols such as OpenFlow through a cloud or peripheral interface. Based on feedback data received through a feedback link, the transmitted data is adjusted to configure the storage unit data (Config_Data1, Config_Data2, Config_Data3, and Config_Type) and program the circuit logic devices for different controlled devices. The software-generated hardware circuit includes a state partitioning component, a synchronous multi-cycle configuration component, and a single-cycle modulation component connected in sequence. Upon receiving the TriggerBegin signal, a request for the controlled device to start, contained in Config_Data1, the state partitioning component starts its built-in counter and outputs a MatchTriggerBegin signal that meets the timing requirements to the synchronous multi-cycle configuration component. The synchronous multi-cycle configuration component implements the timing configuration of periodic and aperiodic drive signals at a specific clock frequency, outputting the multi-cycle drive enable signal PeriodValid and the end signal ModeEnd from the single-cycle modulation component. Finally, the single-cycle modulation component modulates the PeriodValid signal using the configuration information, outputting complex drive signals for multiple device chips. The computer program product includes a computer program. The computer program can be executed by a processor to implement the multi-cycle modulation driving method as described above.

Claims

1. A multi-cycle modulation driving circuit for generating a multi-cycle driving signal to a plurality of controlled devices of a back end, characterized by, The driving circuit includes a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component connected in sequence; and 1) The state division component is configured to: modulate the request information for the controlled device to start, so as to meet the synchronous or asynchronous triggering requirements of the timing; the state division component includes a mode judgment logic module ModeJudge_Logic and a trigger delay module TriggerDelay, and is adapted to at least one digital input signal and one digital output signal for functional decoding according to the functional mode of the controlled device, and generating a timing-matched trigger signal according to the functional mode of the controlled device; wherein the at least one digital input signal is data configuration information Config_Data1, which includes the working mode information of the driving circuit and configuration parameters under different functional modes, wherein the working mode information of the driving circuit includes the request information TriggerBegin for the controlled device to start, and the configuration parameters under different functional modes include at least one of the durations of reset state, exposure state, readout state, and programming state; the at least one digital output signal is a timing-matched trigger signal MatchTriggerBegin transmitted to the synchronous multi-cycle configuration component; and, The ModeJudge_Logic module is configured to perform combinational logic judgment and configure a delayed storage unit based on the data configuration information Config_Data1. The TriggerDelay module is configured to modulate the delay time of the external trigger signal and the periodic enable drive signal under different functional modes based on the configuration information of the delay storage unit and the request information TriggerBegin, and output the trigger signal MatchTriggerBegin that meets the timing requirements to the synchronous multi-cycle configuration component. 2) The synchronous multi-cycle configuration component is configured to generate multi-cycle or non-cycle drive enable signals based on configuration information and trigger signals at different operating clock frequencies of controlled devices. The synchronous multi-cycle configuration component is configured to adapt to at least two digital input signals and at least two digital output signals to generate various types of periodic or non-periodic enable signals based on off-chip configuration information, and to simultaneously implement multi-cycle timing drive on-chip; wherein the at least two digital input signals are the trigger signal MatchTriggerBegin from the state division component and the data configuration information Config_Data2 from off-chip, and the at least two digital output signals are a set of drive enable signals PeriodValid and end signal ModeEnd that can characterize various cycle types of the chip; The synchronous multi-cycle configuration component includes a decoding module, k clock reset generation submodules, and k configuration submodules. The decoding module decodes the data configuration information Config_Data2 and outputs the decoded data to the k clock reset generation submodules and the k configuration submodules to configure and select at least one of them. Each submodule generates a periodic or aperiodic drive enable signal PeriodValid based on off-chip configuration information to achieve... Multi-cycle enable modulation under the same clock frequency group, where k is the number of drive enable signals generated, and k is a positive integer; the synchronous multi-cycle configuration component, based on the data configuration information Config_Data2, performs combinational logic judgment and configures the corresponding enable signal cycle storage unit, single-cycle high-level duration storage unit, and single-cycle repetition count storage unit, and implements the timing configuration of periodic and / or non-periodic drive signals through counters PeriodCounter and RepeatCounter, outputting a multi-cycle drive enable signal PeriodValid and an end signal ModeEnd for a single-cycle modulation component, and 3) The single-cycle modulation component is configured to: modulate and output a composite drive signal required by the controlled device chip according to configuration information and a drive enable signal; the single-cycle modulation component adapts to at least four digital input signals and at least one digital output signal; the single-cycle modulation component generates a periodic composite on-chip timing drive signal according to the off-chip signal type encoding and configuration information, as well as the multi-cycle drive enable signal PeriodValid and end signal ModeEnd, thereby driving the digital and analog readout units in the controlled device chip; the four digital input signals are the signal type encoding Config_Type, the corresponding signal timing data configuration information Config_Data3, the drive enable signal PeriodValid, and the end signal ModeEnd; the one digital output signal is the complex on-chip timing drive signal DriverSignal required by the digital and analog readout units in the controlled device chip; and, The single-cycle modulation component includes n driving submodules responsible for generating multiple complex on-chip timing driving signals, where n is the number of driving signals generated and is a positive integer; and Each of the n driver submodules includes a state machine submodule and a selector. It encodes the input signal type as Config_Type, determines the type and number of high / low level transitions of the drive signal through combinational logic, and generates an on-chip timing drive signal DriverSignal based on the input drive enable signal PeriodValid via the state machine submodule. Based on the device code DeviceType in the input timing data configuration information, it outputs either the on-chip timing drive signal DriverSignal or the drive enable signal PeriodValid through the selector.

2. The multi-cycle modulation driving circuit as described in claim 1, characterized in that, The digital input signals of the state division component also include the request information TriggerBegin for the controlled device to start and the termination signal ModeEnd; The TriggerBegin information is a request for the controlled device to start. After receiving the TriggerBegin information, the state division component modulates the data according to the Config_Data1 data configuration information to meet the synchronous or asynchronous triggering requirements of the controlled device chip's operating timing. The ModeEnd signal is the end signal of the controlled device's operating mode. It is fed back to the state division component and output to the single-cycle modulation component to clear the memory units in the state division component and the single-cycle modulation component and to turn off the output drive signal.

3. A multi-cycle modulation driving circuit as claimed in claim 1 or 2, characterized in that, The storage unit is a register.

4. A multi-cycle modulation drive system comprising, when in operation, a plurality of composite periodic processes, characterized by, The drive system includes a multi-cycle modulated drive circuit as described in claim 1 or 2, for generating multi-cycle drive signals for a plurality of controlled devices that control the drive system.

5. A multi-cycle modulation driving method, wherein the driving method is applied to the driving circuit of claim 1, characterized in that, The method employs a state partitioning component, a synchronous multi-cycle configuration component, and a single-cycle modulation component connected in sequence. The state partitioning component includes a mode determination logic module and a trigger delay module. The driving method includes the following steps: S1, Perform functional state division: After receiving the data configuration information Config_Data1 containing the working mode code of the controlled device, the corresponding functional mode timing, and data configuration, the state division component is configured to configure the delay storage unit based on the data configuration information Config_Data1. The delay value in the delay storage unit is represented as MatchNum. The trigger delay module is configured to start working under the trigger signal of the TriggerBegin request information requiring the controlled device to start, which is received from the external configuration information Config_Data1. When the built-in counter counts to MatchNum, it outputs the timing-matched trigger signal MatchTriggerBegin. The duration of the high level of MatchTriggerBegin is greater than a predetermined value to ensure that the synchronous triggering process can proceed normally. S2, configure the multi-cycle enable signal. After receiving the data configuration information Config_Data2 from the controlled device, the synchronous multi-cycle configuration component performs combinational logic judgment and configures the enable signal period storage unit, the high-level duration storage unit within a single cycle, and the single-cycle repetition count storage unit. The value configured in the enable signal period storage unit is represented as PeriodNum, the value configured in the high-level duration storage unit within a single cycle is represented as EnableNum, and the value configured in the single-cycle repetition count storage unit is represented as RepeatNum. Example of the synchronous multi-cycle configuration component... The k clock reset generation submodules and k configuration submodules begin operation upon receiving the timing-matched trigger signal MatchTriggerBegin. The PeriodCounter counter starts counting and outputs an enable signal PeriodValid with a single-cycle duration of PeriodNum and a high-level duration of EnableNum within that single cycle. The RepeatCounter counter counts the number of single-cycle repetitions of the enable signal until EnableNum is reached, then outputs an end signal ModeEnd. This allows for simultaneous on-chip multi-cycle drive enable of the single-cycle modulation drive submodule. S3, generate the modulation signal within a single cycle; after receiving the configuration information Config_Type and Config_Data3 from outside the chip, the single-cycle modulation component determines the type and timing information of the drive signal through combinational logic and configures the corresponding storage unit; the n drive sub-modules instantiated by the single-cycle modulation component work under the same drive enable signal PeriodValid, and work when the drive enable signal PeriodValid is high. The built-in counter and sub-state machine modulate PeriodValid into n periodic composite on-chip timing drive signals DriverSignal to realize the timing drive of the digital and analog readout units of the controlled device chip.

6. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the driving method as described in claim 5.

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