Display panel, display device and driving method

Abstract

The invention discloses a display panel, a display device and a driving method. The display panel comprises a light emitting device (L); the driving transistor (M0) is configured to generate a driving current for driving the light emitting device (L) to emit light according to the data voltage signal; the grid electrode of the threshold compensation transistor (M10) is coupled with the first control signal line (CS1), the first pole is coupled with the grid electrode of the driving transistor (M0), and the second pole is coupled with the second pole of the driving transistor (M0); the grid electrode of the voltage stabilizing transistor (M20) is coupled with the first control signal line (CS1), the first pole of the voltage stabilizing transistor (M20) is coupled with the first node (N1), and the second pole of the voltage stabilizing transistor (M20) is coupled with the first power supply signal line (VDD); an active layer of the voltage stabilizing transistor (M20) and an active layer of the threshold compensation transistor (M10) are located on the same layer and are mutually independent; the active layer of the voltage stabilizing transistor (M20) and the active layer of the driving transistor (M0) are positioned on different layers; a data write circuit (210) that supplies a data voltage signal on a data signal line (DA) to the second node (N2); a light emission control circuit (250) supplies a signal on a first power supply signal line (VDD) to a first pole of a driving transistor (M0), and turns on a second pole of the driving transistor (M0) and a light emitting device (L).

Description

Display panel, display device, and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a driving method. Background Art

[0002] Light-emitting devices such as organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) offer advantages such as self-luminescence and low energy consumption, making them a hot topic in current display panel application research. Display panels typically use pixel circuits to drive the light-emitting devices.

[0003] Summary of the Invention

[0004] The display panel provided by the embodiment of the present disclosure includes: a base substrate including a plurality of sub-pixels; each of the sub-pixels includes a pixel circuit;

[0005] The pixel circuit comprises:

[0006] Light-emitting devices;

[0007] a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0008] a threshold compensation transistor, wherein a gate of the threshold compensation transistor is coupled to the first control signal line, a first electrode of the threshold compensation transistor is coupled to the gate of the driving transistor, and a second electrode of the threshold compensation transistor is coupled to the second electrode of the driving transistor;

[0009] a voltage stabilizing transistor, wherein a gate of the voltage stabilizing transistor is coupled to the first control signal line, a first electrode of the voltage stabilizing transistor is coupled to the first node, and a second electrode of the voltage stabilizing transistor is coupled to the first power signal line;

[0010] The active layer of the voltage stabilizing transistor and the active layer of the threshold compensation transistor are located in the same layer and are independent of each other; the active layer of the voltage stabilizing transistor and the active layer of the driving transistor are located in different layers;

[0011] a data writing circuit coupled to the second node and configured to provide the data voltage signal on the data signal line to the second node in response to a signal on the scan signal line;

[0012] a voltage stabilizing circuit coupled to the first node and the driving transistor, and configured to stabilize a voltage between the first node and the gate of the driving transistor;

[0013] a noise reduction circuit coupled to the first node and the second node, configured to provide a signal on the reference voltage signal line to the second node in response to a signal on the second control signal line and / or the first light emission control signal line, and to stabilize a voltage between the first node and the second node;

[0014] a bias circuit coupled to the driving transistor and configured to provide a signal on a bias voltage signal line to a first electrode of the driving transistor in response to a signal on the second control signal line;

[0015] A light-emitting control circuit is coupled to the driving transistor and the light-emitting device, and is configured to provide a signal on the first power signal line to the first electrode of the driving transistor in response to a signal on the second light-emitting control signal line, and to connect the second electrode of the driving transistor to the light-emitting device in response to the signal on the first light-emitting control signal line.

[0016] Optionally, in some embodiments of the present disclosure, the further comprising: a first semiconductor layer located on the substrate, and a second semiconductor layer located on a side of the first semiconductor layer away from the substrate;

[0017] The first semiconductor layer includes an active layer of the driving transistor;

[0018] The second semiconductor layer includes an active layer of the threshold compensation transistor and an active layer of the voltage stabilizing transistor.

[0019] Optionally, in some embodiments of the present disclosure, the data writing circuit includes: a first transistor;

[0020] A gate of the first transistor is coupled to the scan signal line, a first electrode of the first transistor is coupled to the data signal line, and a second electrode of the first transistor is coupled to the second node.

[0021] Optionally, in some embodiments of the present disclosure, the voltage stabilizing circuit includes: a first capacitor;

[0022] A first electrode of the first capacitor is coupled to the gate of the driving transistor, and a second electrode of the first capacitor is coupled to the first node.

[0023] Optionally, in some embodiments of the present disclosure, the noise reduction circuit includes: a second transistor, a third transistor, and a second capacitor;

[0024] The gate of the second transistor is coupled to the first light emitting control signal line, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the reference voltage signal line;

[0025] The gate of the third transistor is coupled to the second control signal line, the first electrode of the third transistor is coupled to the reference voltage signal line, and the second electrode of the third transistor is coupled to the second node;

[0026] A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second node.

[0027] Optionally, in some embodiments of the present disclosure, the bias circuit includes: a fourth transistor;

[0028] A gate of the fourth transistor is coupled to the second control signal line, a first electrode of the fourth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the fourth transistor is coupled to the bias voltage signal line.

[0029] Optionally, in some embodiments of the present disclosure, the light emitting control circuit includes: a fifth transistor and a sixth transistor;

[0030] The gate of the fifth transistor is coupled to the second light emitting control signal line, the first electrode of the fifth transistor is coupled to the first power signal line, and the second electrode of the fifth transistor is coupled to the first electrode of the driving transistor;

[0031] A gate of the sixth transistor is coupled to the first light emitting control signal line, a first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the sixth transistor is coupled to the light emitting device.

[0032] Optionally, the system further includes: a reset circuit coupled to the driving transistor, configured to provide a signal on the first initialization signal line to the second electrode of the driving transistor in response to a signal on the reset signal line.

[0033] The reset circuit includes: a seventh transistor;

[0034] A gate of the seventh transistor is coupled to the reset signal line, a first electrode of the seventh transistor is coupled to the second electrode of the driving transistor, and a second electrode of the seventh transistor is coupled to the first initialization signal line.

[0035] Optionally, in some embodiments of the present disclosure, the device further includes an initialization circuit coupled to the light-emitting device and configured to provide a signal on the second initialization signal line to the light-emitting device in response to a signal on the second control signal line.

[0036] The initialization circuit includes: an eighth transistor;

[0037] A gate of the eighth transistor is coupled to the second control signal line, a first electrode of the eighth transistor is coupled to the light emitting device, and a second electrode of the eighth transistor is coupled to the second initialization signal line.

[0038] Optionally, in some embodiments of the present disclosure, the substrate further comprises: a plurality of pixel units; the pixel unit comprises at least three sub-pixels;

[0039] The first sub-pixel and the second sub-pixel in the pixel unit have the reference voltage signal line between their orthographic projections on the substrate; the orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit on the substrate are symmetrical about the orthographic projection of the reference voltage signal line on the substrate; the first sub-pixel and the second sub-pixel in the pixel unit share the reference voltage signal line;

[0040] The second sub-pixel and the third sub-pixel in the pixel unit have the data signal line and the reference voltage signal line between the orthographic projections of the base substrate.

[0041] Optionally, in some embodiments of the present disclosure, there is at least one signal line between two adjacent pixel units along the first direction, and the signal line includes at least one of a first initialization signal line, a second initialization signal line, a bias voltage signal line and a second power signal line.

[0042] Optionally, in some embodiments of the present disclosure, there is a signal line between two adjacent pixel units along the first direction, and the first initialization signal line, the second initialization signal line, the bias voltage signal line and the second power supply signal line are alternately arranged in sequence along the first direction.

[0043] Optionally, in some embodiments of the present disclosure, it also includes: a first conductive layer located between the base substrate and the first semiconductor layer; a second conductive layer and a third conductive layer located between the first semiconductor layer and the second semiconductor layer; the third conductive layer located on the side of the second conductive layer facing away from the base substrate; a fourth conductive layer located on the side of the second semiconductor layer facing away from the base substrate; a fifth conductive layer located on the side of the fourth conductive layer facing away from the base substrate; and a sixth conductive layer located on the side of the fifth conductive layer facing away from the base substrate.

[0044] An orthographic projection of the first conductive layer on the base substrate overlaps with an orthographic projection of the driving transistor on the base substrate.

[0045] Optionally, in some embodiments of the present disclosure, the signal line in the second conductive layer extends along the first direction; the second conductive layer includes the two first light-emitting control signal lines, the second light-emitting control signal line, the second control signal line and a reset signal line.

[0046] The signal line in the third conductive layer extends along a first direction; the third conductive layer includes the first control signal line.

[0047] Optionally, in some embodiments of the present disclosure, the signal line in the fourth conductive layer extends along the first direction; the fourth conductive layer includes the first control signal line, the bias voltage signal line, a first initialization signal line, and a second initialization signal line.

[0048] Optionally, in some embodiments of the present disclosure, the signal line in the fifth conductive layer extends along the first direction; the fifth conductive layer includes the scan signal line, the reference voltage signal line, the second control signal line, the first power signal line and the second power signal line.

[0049] Optionally, in some embodiments of the present disclosure, the signal line in the sixth conductive layer extends along the second direction; the sixth conductive layer includes: the first power signal line, the data signal line, the reference voltage signal line, the bias voltage signal line, the first initialization signal line, the second initialization signal line and the second power signal line.

[0050] Optionally, in some embodiments of the present disclosure, the first power signal line, the second power signal line, the reference voltage signal line, the bias voltage signal line, the first initialization signal line and the second initialization signal line are arranged in a grid shape on the orthographic projection of the substrate.

[0051] The present disclosure provides a method for driving the display panel, including:

[0052] In a reset phase, the threshold compensation transistor connects the gate of the driving transistor to the second electrode of the driving transistor in response to the signal on the first control signal line; the voltage stabilizing transistor provides the signal on the first power signal line to the first node in response to the signal on the first control signal line;

[0053] In a first biasing stage, the noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the second control signal line; and the bias circuit provides the signal on the bias voltage signal line to the first electrode of the driving transistor in response to the signal on the second control signal line.

[0054] In the data writing phase, the data writing circuit responds to the signal on the scanning signal line to provide the data voltage signal on the data signal line to the second node; the threshold compensation transistor responds to the signal on the first control signal line to connect the gate of the driving transistor to the second electrode of the driving transistor; and the voltage stabilizing transistor responds to the signal on the first control signal line to provide the signal on the first power signal line to the first node;

[0055] In the threshold compensation stage, the light emitting control circuit provides the signal on the first power signal line to the first electrode of the driving transistor in response to the signal on the second light emitting control signal line; the threshold compensation transistor connects the gate of the driving transistor to the second electrode of the driving transistor in response to the signal on the first control signal line; and the voltage stabilizing transistor provides the signal on the first power signal line to the first node in response to the signal on the first control signal line.

[0056] In a second biasing stage, the noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the second control signal line; and the bias circuit provides the signal on the bias voltage signal line to the first electrode of the driving transistor in response to the signal on the second control signal line.

[0057] In the light-emitting stage, the light-emitting control circuit provides the signal on the first power signal line to the first electrode of the driving transistor in response to the signal on the second light-emitting control signal line, and connects the second electrode of the driving transistor to the light-emitting device in response to the signal on the first light-emitting control signal line; the noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the first light-emitting control signal line;

[0058] The reset stage further includes: the reset circuit providing the signal on the first initialization signal line to the second electrode of the driving transistor in response to the signal on the reset signal line;

[0059] The first bias stage further includes: the initialization circuit providing a signal on the second initialization signal line to the light emitting device in response to a signal on the second control signal line;

[0060] The second bias stage further includes: the initialization circuit providing a signal on the second initialization signal line to the light emitting device in response to a signal on the second control signal line.

[0061] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0063] FIG2 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0064] FIG3 is another schematic diagram of the structure of the pixel circuit provided by the embodiment of the present disclosure;

[0065] FIG4 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0066] FIG5 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0067] FIG6 is a schematic diagram of some other structures of a display panel provided by an embodiment of the present disclosure;

[0068] FIG7 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0069] FIG8 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0070] FIG9 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0071] FIG10 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0072] FIG11 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0073] FIG12 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0074] FIG13 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0075] FIG14 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0076] FIG15 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0077] FIG16 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0078] FIG17 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0079] FIG18 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0080] FIG19 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0081] FIG20 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0082] FIG21 is a flowchart of some driving methods provided by embodiments of the present disclosure;

[0083] FIG22 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0084] FIG23 is another signal timing diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0086] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0087] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0088] The display device provided by the embodiment of the present disclosure includes: a display panel, and the display area of ​​the display panel includes a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0089] In the disclosed embodiments, each sub-pixel includes a pixel circuit, which includes a driving transistor and a light-emitting device to drive the light-emitting device to emit light, thereby enabling the display panel to display images. Due to factors such as process technology and device aging, the threshold voltage Vth of the driving transistor may be non-uniform. This causes the current flowing through different light-emitting devices to vary, resulting in uneven display brightness, thereby affecting the overall image display effect.

[0090] Furthermore, due to the current market's high demand for display quality, high frame rate display has become a trend in the future display industry. However, high frame rate display consumes a lot of power, resulting in a decrease in the battery life of the display device. The introduction of high and low frame rate switching technology (Variable Refresh Rate, VRR) can improve power consumption and increase the battery life of the display device. However, under low frame rate display, the hysteresis effect of the driving transistor will cause the display to have an afterimage problem, affecting the display effect; and flickering will occur when switching between each frame, further affecting the display effect.

[0091] In some embodiments of the present disclosure, as shown in FIG1 and FIG2 , a substrate 100 includes a plurality of sub-pixels (e.g., spx1, spx2, spx3 in FIG1 ); each sub-pixel (e.g., spx1, spx2, spx3 in FIG1 ) includes a pixel circuit 200;

[0092] The pixel circuit 200 includes:

[0093] Light emitting device L;

[0094] a driving transistor M0 coupled to the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;

[0095] a threshold compensation transistor M10, wherein a gate of the threshold compensation transistor M10 is coupled to the first control signal line CS1, a first electrode of the threshold compensation transistor M10 is coupled to the gate of the driving transistor M0, and a second electrode of the threshold compensation transistor M10 is coupled to the second electrode of the driving transistor M0;

[0096] a voltage-stabilizing transistor M20 , wherein a gate of the voltage-stabilizing transistor M20 is coupled to the first control signal line CS1 , a first electrode of the voltage-stabilizing transistor M20 is coupled to the first node N1 , and a second electrode of the voltage-stabilizing transistor M20 is coupled to the first power signal line VDD;

[0097] The active layer of the voltage stabilizing transistor M20 and the active layer of the threshold compensation transistor M10 are located in the same layer and are independent of each other; the active layer of the voltage stabilizing transistor M20 and the active layer of the driving transistor M0 are located in different layers;

[0098] The data writing circuit 210 is coupled to the second node N2 and is configured to provide a data voltage signal on the data signal line DA to the second node N2 in response to a signal on the scan signal line SS;

[0099] The voltage stabilizing circuit 220 is coupled to the first node N1 and the driving transistor M0 and is configured to stabilize the voltage between the first node N1 and the gate of the driving transistor M0;

[0100] The noise reduction circuit 230 is coupled to the first node N1 and the second node N2, and is configured to provide a signal on the reference voltage signal line Vref1 to the second node N2 in response to a signal on the second control signal line CS2 and / or the first light emitting control signal line EM1, and stabilize a voltage between the first node N1 and the second node N2;

[0101] The bias circuit 240 is coupled to the driving transistor M0 and is configured to provide a signal on the bias voltage signal line Vref2 to the first electrode of the driving transistor M0 in response to a signal on the second control signal line CS2;

[0102] The light-emitting control circuit 250 is coupled to the driving transistor M0 and the light-emitting device L, and is configured to provide the signal on the first power signal line VDD to the first electrode of the driving transistor M0 in response to the signal on the second light-emitting control signal line EM2, and to turn on the second electrode of the driving transistor M0 and the light-emitting device L in response to the signal on the first light-emitting control signal line EM1.

[0103] The disclosed embodiments achieve separation of threshold voltage compensation of the driving transistor and data voltage signal writing through the cooperation of the driving transistor, the threshold compensation transistor, the voltage stabilizing transistor, the data writing circuit, the voltage stabilizing circuit, the noise reduction circuit, and the light emitting control circuit. Thus, the threshold voltage compensation duration of the driving transistor is not limited by the data voltage signal writing, and the threshold voltage compensation process can be performed for a longer period of time, which is beneficial to the stability of the threshold voltage of the driving transistor. This allows for high frame rate display, avoids the impact of threshold voltage drift of the driving transistor on the light emission of the light emitting device, and improves the image quality of high frame rate display.

[0104] Furthermore, by cooperating with each other, the driving transistor, the threshold compensation transistor, the voltage stabilizing transistor, the data writing circuit, the voltage stabilizing circuit, the noise reduction circuit, and the light emitting control circuit, a strong bias is applied to the driving transistor, thereby improving the hysteresis effect of the driving transistor, thereby avoiding the afterimage problem and the flicker problem, and improving the display effect.

[0105] And by arranging the active layer of the voltage stabilizing transistor and the active layer of the threshold compensation transistor to be located in the same layer and independent of each other; the active layer of the voltage stabilizing transistor and the active layer of the driving transistor are located in different layers; the leakage of the display panel can be improved and the display quality can be improved.

[0106] 2 , the driving transistor M0 can be configured as a P-type transistor, wherein the first electrode of the driving transistor M0 can be its source, and the second electrode of the driving transistor M0 can be its drain. Of course, the driving transistor M0 can also be configured as an N-type transistor, which is not limited here.

[0107] For example, as shown in FIG2 , the second electrode of the driving transistor M0 is coupled to the anode of the light-emitting device L, and the cathode of the light-emitting device L is coupled to the second power signal line VSS. For example, the light-emitting device L may include at least one of: a micro light-emitting diode (Micro Light Emitting Diode, Micro LED), an organic light-emitting diode (Organic Light Emitting Diode, OLED) and a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED). For example, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In actual applications, the specific structure of the light-emitting device can be designed and determined according to the actual application environment, and is not limited here.

[0108] Exemplarily, the threshold compensation transistor M10 can be turned on under the control of the active level of the first control signal transmitted by the first control signal line CS1, and can be turned off under the control of the inactive level of the first control signal. Exemplarily, if the threshold compensation transistor M10 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the threshold compensation transistor M10 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0109] For example, the voltage-stabilizing transistor M20 can be turned on under the control of the active level of the first control signal transmitted by the first control signal line CS1, and can be turned off under the control of the inactive level of the first control signal. For example, if the voltage-stabilizing transistor M20 is configured as a P-type transistor, the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level. Alternatively, if the voltage-stabilizing transistor M20 is configured as an N-type transistor, the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level.

[0110] In some embodiments of the present disclosure, the material of the active layer of the driving transistor M0 is different from that of the active layer of the voltage stabilizing transistor M20 ; the material of the active layer of the voltage stabilizing transistor M20 is the same as that of the active layer of the threshold compensation transistor M10 .

[0111] In some embodiments of the present disclosure, as shown in Figure 3, the data writing circuit 210 includes: a first transistor M1; wherein the gate of the first transistor M1 is coupled to the scan signal line SS, the first electrode of the first transistor M1 is coupled to the data signal line DA, and the second electrode of the first transistor M1 is coupled to the second node N2.

[0112] Exemplarily, the first transistor M1 can be turned on under the control of the active level of the scan signal transmitted by the scan signal line SS, and can be turned off under the control of the inactive level of the scan signal. Exemplarily, if the first transistor M1 is configured as a P-type transistor, the active level of the scan signal is a low level, and the inactive level of the scan signal is a high level. Alternatively, if the first transistor M1 is configured as an N-type transistor, the active level of the scan signal is a high level, and the inactive level of the scan signal is a low level.

[0113] In some embodiments of the present disclosure, as shown in FIG3 , the voltage stabilizing circuit 220 includes: a first capacitor C1 ; wherein a first electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0 , and a second electrode of the first capacitor C1 is coupled to the first node N1 .

[0114] In some embodiments of the present disclosure, as shown in Figure 3, the noise reduction circuit 230 includes: a second transistor M2, a third transistor M3 and a second capacitor C2; wherein, the gate of the second transistor M2 is coupled to the first light-emitting control signal line EM1, the first electrode of the second transistor M2 is coupled to the second node N2, and the second electrode of the second transistor M2 is coupled to the reference voltage signal line Vref1; the gate of the third transistor M3 is coupled to the second control signal line CS2, the first electrode of the third transistor M3 is coupled to the reference voltage signal line Vref1, and the second electrode of the third transistor M3 is coupled to the second node N2; the first electrode of the second capacitor C2 is coupled to the first node N1, and the second electrode of the second capacitor C2 is coupled to the second node N2.

[0115] Exemplarily, the second transistor M2 can be turned on under the control of the active level of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1, and can be turned off under the control of the inactive level of the first light-emitting control signal. Exemplarily, if the second transistor M2 is configured as a P-type transistor, the active level of the first light-emitting control signal is a low level, and the inactive level of the first light-emitting control signal is a high level. Alternatively, if the second transistor M2 is configured as an N-type transistor, the active level of the first light-emitting control signal is a high level, and the inactive level of the first light-emitting control signal is a low level.

[0116] Exemplarily, the third transistor M3 can be turned on under the control of the active level of the second control signal transmitted by the second control signal line CS2, and can be turned off under the control of the inactive level of the second control signal. Exemplarily, the third transistor M3 is configured as a P-type transistor, then the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, the third transistor M3 is configured as an N-type transistor, then the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0117] In some embodiments of the present disclosure, as shown in Figure 3, the bias circuit 240 includes: a fourth transistor M4; wherein the gate of the fourth transistor M4 is coupled to the second control signal line CS2, the first electrode of the fourth transistor M4 is coupled to the first electrode of the driving transistor M0, and the second electrode of the fourth transistor M4 is coupled to the bias voltage signal line Vref2.

[0118] Exemplarily, the fourth transistor M4 can be turned on under the control of the active level of the second control signal transmitted by the second control signal line CS2, and can be turned off under the control of the inactive level of the second control signal. Exemplarily, the fourth transistor M4 is configured as a P-type transistor, then the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, the fourth transistor M4 is configured as an N-type transistor, then the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0119] In some embodiments of the present disclosure, as shown in Figure 3, the light-emitting control circuit 250 includes: a fifth transistor M5 and a sixth transistor M6; wherein, the gate of the fifth transistor M5 is coupled to the second light-emitting control signal line EM2, the first electrode of the fifth transistor M5 is coupled to the first power signal line VDD, and the second electrode of the fifth transistor M5 is coupled to the first electrode of the driving transistor M0; the gate of the sixth transistor M6 is coupled to the first light-emitting control signal line EM1, the first electrode of the sixth transistor M6 is coupled to the second electrode of the driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the light-emitting device L.

[0120] Exemplarily, the fifth transistor M5 can be turned on under the control of the active level of the second light-emitting control signal transmitted by the second light-emitting control signal line EM2, and can be turned off under the control of the inactive level of the second light-emitting control signal. Exemplarily, if the fifth transistor M5 is configured as a P-type transistor, the active level of the second light-emitting control signal is a low level, and the inactive level of the second light-emitting control signal is a high level. Alternatively, if the fifth transistor M5 is configured as an N-type transistor, the active level of the second light-emitting control signal is a high level, and the inactive level of the second light-emitting control signal is a low level.

[0121] Exemplarily, the sixth transistor M6 can be turned on under the control of the active level of the first light-emitting control signal transmitted by the first light-emitting control signal line EM1, and can be turned off under the control of the inactive level of the first light-emitting control signal. Exemplarily, if the sixth transistor M6 is configured as a P-type transistor, the active level of the first light-emitting control signal is a low level, and the inactive level of the first light-emitting control signal is a high level. Alternatively, if the sixth transistor M6 is configured as an N-type transistor, the active level of the first light-emitting control signal is a high level, and the inactive level of the first light-emitting control signal is a low level.

[0122] In some embodiments of the present disclosure, as shown in FIG4 , further comprising: a reset circuit 260 coupled to the driving transistor M0 , configured to provide the signal on the first initialization signal line Vini1 to the second electrode of the driving transistor M0 in response to the signal on the reset signal line RE.

[0123] In some embodiments of the present disclosure, as shown in Figure 5, the reset circuit 260 includes: a seventh transistor M7; wherein the gate of the seventh transistor M7 is coupled to the reset signal line RE, the first electrode of the seventh transistor M7 is coupled to the second electrode of the driving transistor M0, and the second electrode of the seventh transistor M7 is coupled to the first initialization signal line Vini1.

[0124] Exemplarily, the seventh transistor M7 can be turned on under the control of the active level of the reset signal transmitted by the reset signal line RE, and can be turned off under the control of the inactive level of the reset signal. Exemplarily, the seventh transistor M7 is configured as a P-type transistor, then the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level. Alternatively, the seventh transistor M7 is configured as an N-type transistor, then the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level.

[0125] In some embodiments of the present disclosure, as shown in FIG4 , the initialization circuit 270 is further included, coupled to the light-emitting device L and configured to provide the signal on the second initialization signal line Vini2 to the light-emitting device L in response to the signal on the second control signal line CS2 .

[0126] In some embodiments of the present disclosure, as shown in Figure 5, the initialization circuit 270 includes: an eighth transistor M8; wherein the gate of the eighth transistor M8 is coupled to the second control signal line CS2, the first electrode of the eighth transistor M8 is coupled to the light-emitting device L, and the second electrode of the eighth transistor M8 is coupled to the second initialization signal line Vini2.

[0127] Exemplarily, the eighth transistor M8 can be turned on under the control of the active level of the second control signal transmitted by the second control signal line CS2, and can be turned off under the control of the inactive level of the second control signal. Exemplarily, if the eighth transistor M8 is configured as a P-type transistor, the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level. Alternatively, if the eighth transistor M8 is configured as an N-type transistor, the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level.

[0128] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0129] For example, the first power signal line VDD can be configured to carry a constant first power voltage Vdd, which is generally a positive value. Furthermore, the second power signal line VSS can be configured to carry a constant second power voltage Vss, which is generally a ground voltage or a negative value. In actual applications, the specific values ​​of the first power voltage Vdd and the second power voltage Vss can be designed and determined based on the actual application environment and are not limited here.

[0130] In some embodiments of the present disclosure, as shown in FIG6 and FIG7 , the further comprising: a first semiconductor layer 110 located on the base substrate 100 , and a second semiconductor layer 120 located on a side of the first semiconductor layer 110 away from the base substrate 100 ;

[0131] The first semiconductor layer 110 includes an active layer of the driving transistor M0;

[0132] The second semiconductor layer 120 includes an active layer of the threshold compensation transistor M10 and an active layer of the voltage stabilizing transistor M20 .

[0133] 7 , the active layer of the threshold compensation transistor M10 and the active layer of the voltage stabilizing transistor M20 both extend along the second direction Y, and the active layer of the threshold compensation transistor M10 and the active layer of the voltage stabilizing transistor M20 are arranged at intervals along the first direction X.

[0134] It should be noted that the first and second semiconductor layers form the active layers of each transistor in the pixel circuit. The active layers include a channel region, and source and drain regions located on either side of the channel region. By configuring the first and second semiconductor layers to be made of different materials, the present disclosure reduces leakage current in the pixel circuit and improves the display effect and quality of the display panel.

[0135] Exemplarily, as shown in FIG6 , the first semiconductor layer 110 further includes: an active layer of a first transistor M1, an active layer of a second transistor M2, an active layer of a third transistor M3, an active layer of a fourth transistor M4, an active layer of a fifth transistor M5, an active layer of a sixth transistor M6, an active layer of a seventh transistor M7, and an active layer of an eighth transistor M8.

[0136] Exemplarily, as shown in FIG6 , the active layer of the first transistor M1 is connected to the active layer of the second transistor M2, and the active layer of the first transistor M1 and the active layer of the second transistor M2 extend along the first direction X; the active layer of the third transistor M3 is L-shaped; the active layer of the fourth transistor M4 and the active layer of the fifth transistor M5 are both connected to the active layer of the driving transistor M0, and the active layer of the fourth transistor M4 and the active layer of the fifth transistor M5 extend along the second direction Y; the active layer of the sixth transistor M6 is connected to the active layer of the seventh transistor M7 and the active layer of the eighth transistor M8, the active layer of the sixth transistor M6 is L-shaped, the active layer of the seventh transistor M7 is L-shaped, and the active layer of the eighth transistor M8 extends along the first direction X, and the active layer of the sixth transistor M6, the active layer of the seventh transistor M7, and the active layer of the eighth transistor M8 together constitute an L-shape.

[0137] Exemplarily, as shown in FIG6 , the active layer of the first transistor M1, the active layer of the second transistor M2, the active layer of the third transistor M3, and the active layer of the fourth transistor M4 are located on one side of the active layer of the driving transistor M0; the active layer of the fifth transistor M5, the active layer of the sixth transistor M6, the active layer of the seventh transistor M7, and the active layer of the eighth transistor M8 are located on the other side of the active layer of the driving transistor M0.

[0138] In some embodiments of the present disclosure, as shown in Figures 6 and 7, the material of the active layer in the first semiconductor layer 110 is a low-temperature polycrystalline silicon material, and the material of the active layer in the second semiconductor layer 120 is an oxide material. This setting can reduce the leakage current of the pixel circuit, thereby improving the display effect and display quality of the display panel.

[0139] For example, transistors using low-temperature polysilicon (LTPS) as active layers generally have high mobility and can be made thinner and smaller, with lower power consumption. In specific implementations, the active layer of the transistor can also be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, enabling the pixel circuit to achieve high mobility, be thinner and smaller, and have lower power consumption.

[0140] For example, transistors using metal oxide semiconductor materials as active layers generally have low leakage current. Therefore, in order to reduce leakage current, in some embodiments of the present disclosure, the material of the active layer of the transistor can include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials can also be used, and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor to reduce leakage current in the pixel circuit.

[0141] For example, some of the transistors in the pixel circuit of the present disclosure can be set as oxide-type transistors, and other transistors can be set as LTPS-type transistors. For example, the threshold compensation transistor M10 and the voltage-stabilizing transistor M20 are set as oxide-type transistors, and the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are set as LTPS-type transistors; thereby reducing the leakage current of the pixel circuit and improving the display quality. The embodiment of the present disclosure utilizes the low leakage characteristics of the oxide-type transistor to ensure that the gate voltage value of the driving transistor M0 is maintained under low frame rate display, thereby avoiding flickering of the display panel.

[0142] In some embodiments of the present disclosure, as shown in FIG8 and FIG9 , the substrate 100 further includes: a plurality of pixel units SPX; the pixel unit SPX includes at least three sub-pixels (eg, spx1, spx2, spx3 in the figure);

[0143] A reference voltage signal line Vref1 is provided between the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit SPX and the orthographic projections on the substrate 100; the orthographic projections of the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit SPX on the substrate 100 are substantially symmetrical with respect to the orthographic projection of the reference voltage signal line Vref1 on the substrate 100; the first sub-pixel spx1 and the second sub-pixel spx2 in the pixel unit SPX share the reference voltage signal line Vref1;

[0144] The second sub-pixel spx2 and the third sub-pixel spx3 in the pixel unit SPX have a data signal line DA and a reference voltage signal line Vref1 between the orthographic projections of the base substrate 100 ;

[0145] In some embodiments of the present disclosure, as shown in Figures 8 and 9, there is at least one signal line between two adjacent pixel units SPX along the first direction X, and the signal line includes at least one of a first initialization signal line Vini1, a second initialization signal line Vini2, a bias voltage signal line Vref2 and a second power signal line VSS.

[0146] In some embodiments of the present disclosure, as shown in Figures 8 and 9, there is a signal line between two adjacent pixel units along the first direction X, and the first initialization signal line Vini1, the second initialization signal line Vini2, the bias voltage signal line Vref2 and the second power signal line VSS are alternately arranged in sequence along the first direction X.

[0147] In some embodiments of the present disclosure, as shown in Figures 10 to 19, it also includes: a first conductive layer 130 located between the base substrate 100 and the first semiconductor layer 110; a second conductive layer 140 and a third conductive layer 150 located between the first semiconductor layer 110 and the second semiconductor layer 120; the third conductive layer 150 is located on the side of the second conductive layer 140 away from the base substrate 100; a fourth conductive layer 160 is located on the side of the second semiconductor layer 120 away from the base substrate 100; a fifth conductive layer 170 is located on the side of the fourth conductive layer 160 away from the base substrate 100; and a sixth conductive layer 180 is located on the side of the fifth conductive layer 170 away from the base substrate 100.

[0148] For example, the materials of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be conductive materials. For example, the conductive material can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of the present disclosure do not specifically limit the materials of the conductive layers, and can be set as required.

[0149] By way of example, the various structures in the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be formed using a patterning process. It should be noted that the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes such as printing and inkjet printing for forming a predetermined pattern. A photolithography process refers to a process that uses a photoresist, a mask, an exposure machine, and the like to form a pattern, including film formation, exposure, and development processes. In specific implementations, a corresponding patterning process may be selected based on the structure formed in the present disclosure.

[0150] In some embodiments of the present disclosure, as shown in FIG. 10 , the orthographic projection of the first conductive layer 130 on the base substrate 100 overlaps with the orthographic projection of the driving transistor M0 on the base substrate 100 .

[0151] The present disclosure enables the orthographic projection of the first conductive layer on the base substrate to overlap with the orthographic projection of the driving transistor on the base substrate, thereby improving the stability of the driving transistor, reducing the leakage current of the driving transistor, and improving the display effect.

[0152] In some embodiments of the present disclosure, as shown in FIG11 , the signal lines in the second conductive layer 140 extend along the first direction X; the second conductive layer 140 includes two first light emitting control signal lines EM1 , a second light emitting control signal line EM2 , a second control signal line CS2 and a reset signal line RE.

[0153] For example, as shown in FIG11 , the second conductive layer 140 further includes: a gate of the driving transistor M0, a gate of the first transistor M1, a gate of the second transistor M2, a gate of the third transistor M3, a gate of the fourth transistor M4, a gate of the fifth transistor M5, a gate of the sixth transistor M6, a gate of the seventh transistor M7, a gate of the eighth transistor M8, a first electrode of the first capacitor C1, and a second electrode of the second capacitor C2. The orthographic projection of the first electrode of the first capacitor C1 on the substrate and the orthographic projection of the second electrode of the second capacitor C2 on the substrate are spaced apart from each other.

[0154] For example, as shown in FIG11 , a first light-emission control signal line EM1 is located between the gate of the first transistor M1 and the gate of the third transistor M3. The first light-emission control signal line EM1 and the second light-emission control signal line EM2 are located on either side of the first capacitor C1 and the second capacitor C2, respectively. Another first light-emission control signal line EM1 is located between the second control signal line CS2 and the reset signal line RE. The reset signal line RE, the first light-emission control signal line EM1, and the second control signal line CS2 are located on a side of the second light-emission control signal line EM2 away from the first capacitor C1 and the second capacitor C2. The reset signal line RE, the first light-emission control signal line EM1, and the second control signal line CS2 are arranged in sequence on the second light-emission control signal line EM2 away from the first capacitor C1 and the second capacitor C2.

[0155] Among them, the first electrode of the first capacitor C1 can be reused as the gate of the driving transistor M0; the first light-emitting control signal line EM1 can be reused as the gate of the second transistor M2 and the gate of the sixth transistor M6; the second light-emitting control signal line EM2 can be reused as the gate of the fourth transistor M4; the second control signal line CS2 can be reused as the gate of the eighth transistor M8; and the reset signal line RE can be reused as the gate of the seventh transistor M7. This can simplify the circuit arrangement, save space, and improve the utilization of the display panel.

[0156] It should be noted that FIG12 is a schematic structural diagram of the first semiconductor layer 110 and the second conductive layer 140 stacked together.

[0157] In some embodiments of the present disclosure, as shown in FIG. 13 , the signal lines in the third conductive layer 150 extend along the first direction X; the third conductive layer 150 includes a first control signal line CS1 .

[0158] Exemplarily, the third conductive layer 150 also includes: a gate of the threshold compensation transistor M10, a gate of the voltage regulator transistor M20, a second electrode of the first capacitor C1, and a first electrode of the second capacitor C2; the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2 are the same entity and together constitute the first node N1.

[0159] The first control signal line CS1 can be multiplexed as the gate of the threshold compensation transistor M10 and the gate of the voltage stabilizing transistor M20; this can simplify the circuit arrangement, save space, and improve the utilization of the display panel.

[0160] In some embodiments of the present disclosure, as shown in FIG. 14 , the signal lines in the fourth conductive layer 160 extend along the first direction X; the fourth conductive layer 160 includes a bias voltage signal line Vref2 , a first control signal line CS1 , a first initialization signal line Vini1 , and a second initialization signal line Vini2 .

[0161] For example, as shown in FIG14 , the bias voltage signal line Vref2 , the first control signal line CS1 , the first initialization signal line Vini1 , and the second initialization signal line Vini2 are sequentially arranged along the second direction Y at intervals.

[0162] Exemplarily, the fourth conductive layer 160 also includes the gate of the threshold compensation transistor M10 and the gate of the voltage-stabilizing transistor M20. The first control signal line CS1 can be reused as the gate of the threshold compensation transistor M10 and the gate of the voltage-stabilizing transistor M20. This simplifies circuit layout, saves space, and improves display panel utilization.

[0163] It should be noted that FIG15 is a schematic structural diagram of the second semiconductor layer 120 and the fourth conductive layer 160 stacked together.

[0164] In some embodiments of the present disclosure, as shown in FIG. 16 , the signal lines in the fifth conductive layer 170 extend along the first direction X; the fifth conductive layer 170 includes a scan signal line SS, a reference voltage signal line Vref1 , a second control signal line CS2 , a first power signal line VDD, and a second power signal line VSS.

[0165] For example, as shown in FIG16 , the fifth conductive layer 170 further includes: a first connecting portion Z1, a second connecting portion Z2, a third connecting portion Z3, a fourth connecting portion Z4, a fifth connecting portion Z5, a sixth connecting portion Z6, a seventh connecting portion Z7, an eighth connecting portion Z8, a ninth connecting portion Z9, a tenth connecting portion Z10, an eleventh connecting portion Z11, and a twelfth connecting portion Z12; wherein the first connecting portion Z1 is used to electrically connect the first transistor M1 to the data signal line DA; the second connecting portion Z2 is used to electrically connect the first transistor M1, the second transistor M2, and the third transistor M3. The third connection portion Z3 is used to electrically connect the fourth transistor M4 to the bias voltage signal line Vref2; the fourth connection portion Z4 is used to electrically connect the first transistor M1, the second transistor M2 and the third transistor M3 to the second electrode of the second capacitor C2 in the second conductive layer 140 (the fourth connection portion Z4 can be equivalent to the second node N2); the fifth connection portion Z5 is used to isolate the four transistors M4 from the second capacitor C2 to prevent crosstalk to the signal of the first node N1 at the second capacitor C2; the sixth connection portion Z6 is used to connect the first power signal line in the sixth conductive layer 180 to the first power signal line VDD and the first power signal line VDD in the fifth conductive layer 170, the sixth connection part Z6 is also used to electrically connect the first power signal line VDD in the fifth conductive layer 170 with the fifth transistor M5 and the voltage-stabilizing transistor M20; the seventh connection part Z7 is used to electrically connect the voltage-stabilizing transistor M20 with the second electrode of the first capacitor C1 and the first electrode of the second capacitor C2 in the third conductive layer 150 (the seventh connection part Z7 can be equivalent to the first node N1); the eighth connection part Z8 is used to electrically connect the gate of the driving transistor M0 and the threshold compensation transistor M10 (the eighth connection part Z8 The ninth connection portion Z9 is used to electrically connect the driving transistor M0, the threshold compensation transistor M10, the sixth transistor M6, and the seventh transistor M7 (the ninth connection portion Z9 can be equivalent to the fourth node N4); the tenth connection portion Z10 is used to connect the seventh transistor M7 to the first initialization signal line Vini1; the eleventh connection portion Z11 is used to electrically connect the eighth transistor M8 to the second initialization signal line Vini2; the twelfth connection portion Z12 is used to electrically connect the sixth transistor M6, the eighth transistor M8 and the anode of the light-emitting device.

[0166] The fifth connecting portion Z5, the sixth connecting portion Z6, and the first power signal line VDD in the fifth conductive layer 170 are integrated into a structure; the fifth connecting portion Z5 and the sixth connecting portion Z6 are respectively located on different sides of the first power signal line VDD in the fifth conductive layer 170; and the fifth connecting portion Z5 and the sixth connecting portion Z6 both extend along the second direction;

[0167] The orthographic projection of the first power signal line VDD in the sixth conductive layer 180 on the substrate covers the orthographic projections of the second connection part Z2, the fourth connection part Z4, the seventh connection part Z7, and the eighth connection part Z8 on the substrate, thereby stabilizing the second node N2 corresponding to the fourth connection part Z4, the first node N1 corresponding to the seventh connection part Z7, and the third node N3 corresponding to the eighth connection part Z8, so that the voltages of the signals on the first node N1, the second node N2, and the third node N3 remain stable.

[0168] It should be noted that FIG17 is a schematic structural diagram of the second conductive layer 140 , the third conductive layer 150 , the fourth conductive layer 160 , and the fifth conductive layer 170 stacked together.

[0169] For example, as shown in Figure 17, the scanning signal line SS is electrically connected to the gate of the first transistor M1, the second control signal line CS2 is electrically connected to the gate of the third transistor M3 and the gate of the fourth transistor M4, the gate of the first transistor M1 is separately set from the scanning signal line SS, the gates of the third transistor M3 and the fourth transistor M4 are separately set from the second control signal line CS2, and the scanning signal line SS and the second control signal line CS2 are set in the fifth conductive layer 170. The conductivity of the fifth conductive layer 170 is higher than that of the second conductive layer 140, the third conductive layer 150 and the fourth conductive layer 160. Therefore, the conduction rate of the first transistor M1, the third transistor M3 and the fourth transistor M4 is faster, and the signal writing speed is faster, which is beneficial to improving the refresh rate of the display panel.

[0170] The present disclosure can improve the display effect by reducing the parasitic capacitance between the data signal line DA and the gate of the driving transistor M0, the first node N1, and the second node N2; the signal line extending along the first direction Y and the data signal line DA extending along the second direction X are spaced apart from each other, thereby avoiding lateral crosstalk caused by the parasitic capacitance between the data signal line DA extending along the first direction Y and the signal line extending along the first direction.

[0171] In some embodiments of the present disclosure, as shown in Figure 18, the signal line in the sixth conductive layer 180 extends along the second direction Y; the sixth conductive layer 180 includes: a first power signal line VDD, a data signal line DA, a reference voltage signal line Vref1, a bias voltage signal line Vref2, a first initialization signal line Vini1 and a second initialization signal line Vini2 and a second power signal line VSS.

[0172] It should be noted that FIG19 is a schematic structural diagram of the fifth conductive layer 170 and the sixth conductive layer 180 superimposed together.

[0173] In some embodiments of the present disclosure, as shown in FIG20 , the first power signal line VDD, the second power signal line VSS, the reference voltage signal line Vref1, the bias voltage signal line Vref2, the first initialization signal line Vini1, and the second initialization signal line Vini2 are arranged in a grid-like shape when projected onto the base substrate 100. For example, the first power signal line VDD extending in the first direction is electrically connected to the first power signal line VDD extending in the second direction, and the first power signal line VDD extending in the first direction and the first power signal line VDD extending in the second direction are arranged in a grid-like shape when projected onto the base substrate 100.

[0174] The second power signal line VSS extending along the first direction is electrically connected to the second power signal line VSS extending along the second direction. The orthographic projections of the second power signal line VSS extending along the first direction and the second power signal line VSS extending along the second direction on the base substrate 100 are arranged in a grid shape.

[0175] The reference voltage signal line Vref1 extending along the first direction is electrically connected to the reference voltage signal line Vref1 extending along the second direction. The reference voltage signal line Vref1 extending along the first direction and the reference voltage signal line Vref1 extending along the second direction are arranged in a grid shape in their orthographic projections on the base substrate 100.

[0176] The bias voltage signal line Vref2 extending along the first direction is electrically connected to the bias voltage signal line Vref2 extending along the second direction. The bias voltage signal line Vref2 extending along the first direction and the bias voltage signal line Vref2 extending along the second direction are arranged in a grid shape in their orthographic projections on the base substrate 100.

[0177] The first initialization signal lines Vini1 extending along the first direction are electrically connected to the first initialization signal lines Vini1 extending along the second direction. The orthographic projections of the first initialization signal lines Vini1 extending along the first direction and the first initialization signal lines Vini1 extending along the second direction on the base substrate 100 are arranged in a grid shape.

[0178] The second initialization signal lines Vini2 extending along the first direction are electrically connected to the second initialization signal lines Vini2 extending along the second direction. The orthographic projections of the second initialization signal lines Vini2 extending along the first direction and the second initialization signal lines Vini2 extending along the second direction on the base substrate 100 are arranged in a grid shape.

[0179] The orthographic projection of the first power signal line VDD on the base substrate 100 is arranged in a grid shape. The signal lines in the third conductive layer 150 and the fifth conductive layer 170 extend along the first direction X and are electrically connected to the signal lines in the sixth conductive layer 180 extending along the second direction Y, which can further reduce the voltage drop and improve the display effect.

[0180] Illustratively, the present disclosure arranges the first power signal line VDD, the second power signal line VSS, the reference voltage signal line Vref1, the bias voltage signal line Vref2, the first initialization signal line Vini1 and the second initialization signal line Vini2 in a grid shape, which can further reduce the power consumption of the pixel circuit and improve the stability of the current and voltage of the pixel circuit, thereby improving the display effect of the display panel.

[0181] The driving method of the display panel provided by the embodiment of the present disclosure, as shown in FIG21 , includes:

[0182] S100, reset stage, the threshold compensation transistor responds to the signal on the first control signal line to connect the gate of the driving transistor to the second electrode of the driving transistor; the voltage stabilizing transistor responds to the signal on the first control signal line to provide the signal on the first power signal line to the first node;

[0183] S200, a first bias stage: the noise reduction circuit provides a signal on the reference voltage signal line to the second node in response to a signal on the second control signal line; the bias circuit provides a signal on the bias voltage signal line to the first electrode of the driving transistor in response to a signal on the second control signal line;

[0184] S300, data writing stage, the data writing circuit responds to the signal on the scanning signal line and provides the data voltage signal on the data signal line to the second node; the threshold compensation transistor responds to the signal on the first control signal line and connects the gate of the driving transistor to the second electrode of the driving transistor; the voltage stabilizing transistor responds to the signal on the first control signal line and provides the signal on the first power signal line to the first node;

[0185] S400, threshold compensation stage: the light emitting control circuit provides the signal on the first power signal line to the first electrode of the driving transistor in response to the signal on the second light emitting control signal line; the threshold compensation transistor connects the gate of the driving transistor to the second electrode of the driving transistor in response to the signal on the first control signal line; the voltage stabilizing transistor provides the signal on the first power signal line to the first node in response to the signal on the first control signal line;

[0186] S500, second bias stage, the noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the second control signal line; the bias circuit provides the signal on the bias voltage signal line to the first electrode of the driving transistor in response to the signal on the second control signal line;

[0187] S600, in the light-emitting stage, the light-emitting control circuit responds to the signal on the second light-emitting control signal line, provides the signal on the first power signal line to the first electrode of the driving transistor, and responds to the signal on the first light-emitting control signal line to connect the second electrode of the driving transistor to the light-emitting device; the noise reduction circuit responds to the signal on the first light-emitting control signal line, provides the signal on the reference voltage signal line to the second node.

[0188] In some embodiments of the present disclosure, the reset stage also includes: the reset circuit responds to the signal on the reset signal line to provide the signal on the first initialization signal line to the second electrode of the driving transistor; the first bias stage also includes: the initialization circuit responds to the signal on the second control signal line to provide the signal on the second initialization signal line to the light-emitting device; the second bias stage also includes: the initialization circuit responds to the signal on the second control signal line to provide the signal on the second initialization signal line to the light-emitting device.

[0189] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG5 as an example and combining it with the signal timing diagram shown in FIG22 .

[0190] In some embodiments of the present disclosure, as shown in Figure 22, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, re represents the reset signal on the reset signal line RE, em1 represents the first light-emitting control signal on the first light-emitting control signal line EM1, and em2 represents the second light-emitting control signal on the second light-emitting control signal line EM2.

[0191] Furthermore, a reset phase F1 , a first bias phase F2 , a data writing phase F3 , a threshold voltage compensation phase F4 , a second bias phase F5 and a light emitting phase F6 in a display frame 1H are selected.

[0192] During the reset phase F1, the threshold compensation transistor M10 is turned on by the high level of the first control signal cs1. The voltage regulator transistor M20 is turned on by the high level of the first control signal cs1. The first transistor M1 is turned off by the high level of the scan signal ss. The second transistor M2 is turned off by the high level of the first emission control signal em1. The third transistor M3 is turned off by the high level of the second control signal cs2. The fourth transistor M4 is turned off by the high level of the second control signal cs2. The fifth transistor M5 is turned off by the high level of the second emission control signal em2. The sixth transistor M6 is turned off by the high level of the first emission control signal em1. The seventh transistor M7 is turned on by the low level of the reset signal re. The eighth transistor M8 is turned off by the high level of the second control signal cs2. The turned-on seventh transistor M7 provides the signal on the first initialization signal line Vini1 to the second electrode of the driving transistor M0; the turned-on threshold compensation transistor M10 conducts the gate of the driving transistor M0 with the second electrode of the driving transistor M0, thereby providing the signal on the first initialization signal line Vini1 to the gate of the driving transistor M0, resetting the gate of the driving transistor M0, and V g =V ini1 , where V g Represents the gate voltage of the driving transistor M0, V init1 Represents the voltage on the first initialization signal line Vini1; the turned-on voltage stabilizing transistor M20 provides the signal on the first power supply signal line VDD to the first node N1, then V N1 =Vdd, where V N1 represents the voltage on the first node N1, and Vdd represents the voltage on the first power signal line VDD.

[0193] In the first bias stage F2, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage regulating transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scanning signal ss. The second transistor M2 is turned off under the control of the high level of the first light-emitting control signal em1. The third transistor M3 is turned on under the control of the low level of the second control signal cs2. The fourth transistor M4 is turned on under the control of the low level of the second control signal cs2. The fifth transistor M5 is turned off under the control of the high level of the second light-emitting control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned on under the control of the low level of the second control signal cs2. The turned-on third transistor M3 provides the signal on the reference voltage signal line Vref1 to the second node N2, then V N2=V ref1 , where V N2 represents the voltage on the second node N2, V ref1 Represents the voltage on the reference voltage signal line Vref1; the turned-on fourth transistor M4 provides the signal on the bias voltage signal line Vref2 to the first electrode of the driving transistor M0, then, there is a large voltage difference between the gate and the source of the driving transistor M0, thereby achieving a strong bias and resetting the driving transistor M0; the turned-on eighth transistor M8 provides the signal on the second initialization signal line Vini2 to the anode of the light-emitting device L, resetting the anode of the light-emitting device L, then, V L =V ini2 , where V L Represents the voltage of the anode of the light emitting device L, V ini2 Represents the voltage on the second initialization signal line Vint2.

[0194] In the data writing phase F3, the threshold compensation transistor M10 is turned on under the control of the high level of the first control signal cs1. The voltage-stabilizing transistor M20 is turned on under the control of the high level of the first control signal cs1. The first transistor M1 is turned on under the control of the low level of the scanning signal ss. The second transistor M2 is turned off under the control of the high level of the first light-emitting control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned off under the control of the high level of the second light-emitting control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on threshold compensation transistor M10 turns on the gate of the driving transistor M0 and the second electrode of the driving transistor M0; the turned-on voltage-stabilizing transistor M20 provides the signal on the first power supply signal line VDD to the first node N1, then V N1 = Vdd; the first transistor M1 is turned on to provide the data voltage signal on the data signal line DA to the second node N2, then V N2 =V dt , where V dt Represents the voltage of the data voltage signal on the data signal line DA.

[0195] In the threshold compensation stage F4, the threshold compensation transistor M10 is turned on under the control of the high level of the first control signal cs1. The voltage regulating transistor M20 is turned on under the control of the high level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scanning signal ss. The second transistor M2 is turned off under the control of the high level of the first light-emitting control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned on under the control of the low level of the second light-emitting control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on fifth transistor M5 provides the signal on the first power supply signal line VDD to the first electrode of the driving transistor M0; the turned-on threshold compensation transistor M10 turns on the gate of the driving transistor M0 and the second electrode of the driving transistor M0, then, V g =Vdd+Vth, where Vth represents the threshold voltage of the driving transistor; the turned-on voltage stabilizing transistor M20 provides the signal on the first power signal line VDD to the first node N1, then V N1 =Vdd.

[0196] In the second bias stage F5, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage regulating transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scanning signal ss. The second transistor M2 is turned off under the control of the high level of the first light-emitting control signal em1. The third transistor M3 is turned on under the control of the low level of the second control signal cs2. The fourth transistor M4 is turned on under the control of the low level of the second control signal cs2. The fifth transistor M5 is turned off under the control of the high level of the second light-emitting control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned on under the control of the low level of the second control signal cs2. The turned-on third transistor M3 provides the signal on the reference voltage signal line Vref1 to the second node N2, then V N2 =V ref1 , through the transmission of the first capacitor C1 and the second capacitor C2 in series, then, V g =V ref1, -V dt+Vdd+Vth; the fourth transistor M4 is turned on and provides the signal on the bias voltage signal line Vref2 to the first electrode of the driving transistor M0. Then, there is a large voltage difference between the gate and the source of the driving transistor M0, thereby achieving a strong bias and resetting the driving transistor M0. The eighth transistor M8 is turned on and provides the signal on the second initialization signal line Vini2 to the anode of the light-emitting device L, resetting the anode of the light-emitting device L. Then, V L =V ini2 .

[0197] In the light-emitting stage F6, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage-stabilizing transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scanning signal ss. The second transistor M2 is turned on under the control of the low level of the first light-emitting control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned on under the control of the low level of the second light-emitting control signal em2. The sixth transistor M6 is turned on under the control of the low level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on second transistor M2 provides the signal on the reference voltage signal line Vref1 to the second node N2, then V N2 =V ref1 The conductive fifth transistor M5 provides the signal on the first power signal line VDD to the first electrode of the driving transistor M0; the conductive sixth transistor M6 connects the second electrode of the driving transistor M0 to the anode of the light-emitting device L, and provides the driving current generated by the driving transistor M0 to the anode of the light-emitting device L. The driving current charges the anode of the light-emitting device L until the light-emitting device L emits light stably. The driving transistor M0 is in a saturated working state, and V g =V ref1 -V da +Vdd+Vth, V gs =V ref1 -V da +Vth, where V gs Represents the voltage difference between the gate and source of the driving transistor M0. The driving current I oled =β*(Vgs-Vth) 2 =β*(V ref1 -V da ) 2 , Where, l represents the length of the channel of the driving transistor M0, w represents the width of the channel of the driving transistor M0, C ox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor M0 , and μ represents the mobility of the driving transistor M0 .

[0198] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG5 as an example in combination with the signal timing diagram shown in FIG23 .

[0199] In some embodiments of the present disclosure, as shown in Figure 23, ss represents the scan signal on the scan signal line SS, cs1 represents the first control signal on the first control signal line CS1, cs2 represents the second control signal on the second control signal line CS2, re represents the reset signal on the reset signal line RE, em1 represents the first light-emitting control signal on the first light-emitting control signal line EM1, and em2 represents the second light-emitting control signal on the second light-emitting control signal line EM2.

[0200] Furthermore, the reset phase F1 , the threshold voltage compensation phase F4 , the second bias phase F5 and the light emitting phase F6 in a display frame 1H are selected.

[0201] In the first phase F51 of the second bias phase F5, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage regulator transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scan signal ss. The second transistor M2 is turned off under the control of the high level of the first emission control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned off under the control of the high level of the second emission control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first emission control signal em1. The seventh transistor M7 is turned on under the control of the low level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on seventh transistor M7 provides the signal on the first initialization signal line Vini1 to the second electrode of the drive transistor M0.

[0202] In the second phase F52 of the second bias phase F5, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage regulator transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scan signal ss. The second transistor M2 is turned off under the control of the high level of the first emission control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned on under the control of the low level of the second emission control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first emission control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on fifth transistor M5 provides the signal on the first power supply signal line VDD to the first electrode of the driving transistor M0.

[0203] In the third stage F53 of the second bias stage F5, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage regulating transistor M20 is turned off under the control of the low level of the first control signal cs1. The second transistor M2 is turned off under the control of the high level of the first light-emitting control signal em1. The third transistor M3 is turned on under the control of the low level of the second control signal cs2. The fourth transistor M4 is turned on under the control of the low level of the second control signal cs2. The fifth transistor M5 is turned off under the control of the high level of the second light-emitting control signal em2. The sixth transistor M6 is turned off under the control of the high level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned on under the control of the low level of the second control signal cs2. The turned-on third transistor M3 provides the signal on the reference voltage signal line Vref1 to the second node N2, then V N2 =V ref1 The fourth transistor M4 is turned on and provides the signal on the bias voltage signal line Vref2 to the first electrode of the driving transistor M0. Then, there is a large voltage difference between the gate and the source of the driving transistor M0, thereby achieving a strong bias and resetting the driving transistor M0. The eighth transistor M8 is turned on and provides the signal on the second initialization signal line Vini2 to the anode of the light-emitting device L, resetting the anode of the light-emitting device L. Then, V L =V ini2 .

[0204] In the light-emitting stage F6, the threshold compensation transistor M10 is turned off under the control of the low level of the first control signal cs1. The voltage-stabilizing transistor M20 is turned off under the control of the low level of the first control signal cs1. The first transistor M1 is turned off under the control of the high level of the scanning signal ss. The second transistor M2 is turned on under the control of the low level of the first light-emitting control signal em1. The third transistor M3 is turned off under the control of the high level of the second control signal cs2. The fourth transistor M4 is turned off under the control of the high level of the second control signal cs2. The fifth transistor M5 is turned on under the control of the low level of the second light-emitting control signal em2. The sixth transistor M6 is turned on under the control of the low level of the first light-emitting control signal em1. The seventh transistor M7 is turned off under the control of the high level of the reset signal re. The eighth transistor M8 is turned off under the control of the high level of the second control signal cs2. The turned-on second transistor M2 provides the signal on the reference voltage signal line Vref1 to the second node N2, then V N2 =V ref1 The conductive fifth transistor M5 provides the signal on the first power signal line VDD to the first electrode of the driving transistor M0; the conductive sixth transistor M6 connects the second electrode of the driving transistor M0 to the anode of the light-emitting device L, and provides the driving current generated by the driving transistor M0 to the anode of the light-emitting device L. The driving current charges the anode of the light-emitting device L until the light-emitting device L emits light stably. The driving transistor M0 is in a saturated working state, and V g =V ref1 -V da +Vdd+Vth, V gs =V ref1 -V da +Vth, where V gs Represents the voltage difference between the gate and source of the driving transistor M0. The driving current I oled =β*(Vgs-Vth) 2 =β*(V ref1 -V da ) 2 ,

[0205] The present disclosure also provides a display device including the display panel provided in the present disclosure. The display device solves the problem in a similar manner to the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts are not repeated here.

[0206] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, an electronic watch, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0207] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0208] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein, Comprising: A substrate substrate, including a plurality of sub-pixels; Each of the sub-pixels includes a pixel circuit; The pixel circuit includes: A light-emitting device; A driving transistor, coupled to the light-emitting device, configured to generate a driving current for driving the light-emitting device to emit light according to a data voltage signal; A threshold compensation transistor, the gate of the threshold compensation transistor is coupled to a first control signal line, the first pole of the threshold compensation transistor is coupled to the gate of the driving transistor, and the second pole of the threshold compensation transistor is coupled to the second pole of the driving transistor; A voltage stabilizing transistor, the gate of the voltage stabilizing transistor is coupled to the first control signal line, the first pole of the voltage stabilizing transistor is coupled to a first node, and the second pole of the voltage stabilizing transistor is coupled to a first power supply signal line; The active layer of the voltage stabilizing transistor and the active layer of the threshold compensation transistor are located on the same layer and are independent of each other; the active layer of the voltage stabilizing transistor and the active layer of the driving transistor are located on different layers; A data writing circuit, coupled to a second node, configured to provide the data voltage signal on the data signal line to the second node in response to a signal on the scan signal line; A voltage stabilizing circuit, coupled to the first node and the driving transistor, configured to stabilize the voltage between the first node and the gate of the driving transistor; A noise reduction circuit, coupled to the first node and the second node, configured to provide the signal on the reference voltage signal line to the second node in response to a signal on a second control signal line and / or a first light-emitting control signal line, and to stabilize the voltage between the first node and the second node; A bias circuit, coupled to the driving transistor, configured to provide the signal on the bias voltage signal line to the first pole of the driving transistor in response to a signal on the second control signal line; A light-emitting control circuit, coupled to the driving transistor and the light-emitting device, configured to provide the signal on the first power supply signal line to the First pole of the driving transistor, and in response to a signal on the first light-emitting control signal line, conduct the second pole of the driving transistor and the light-emitting device.

2. The display panel according to claim 1, wherein, Further comprising: a first semiconductor layer located on the substrate substrate, and a second semiconductor layer located on a side of the first semiconductor layer away from the substrate substrate; The first semiconductor layer includes the active layer of the driving transistor; The second semiconductor layer includes the active layer of the threshold compensation transistor and the active layer of the voltage stabilizing transistor.

3. The display panel according to claim 1 or 2, wherein The data writing circuit includes: a first transistor; The gate of the first transistor is coupled to the scan signal line, the first pole of the first transistor is coupled to the data signal line, and the second pole of the first transistor is coupled to the second node.

4. The display panel according to any one of claims 1 to 3, wherein, The voltage stabilizing circuit includes: a first capacitor; The first electrode of the first capacitor is coupled to the gate of the driving transistor, and the second electrode of the first capacitor is coupled to the first node.

5. The display panel according to any one of claims 1-4, wherein, The noise reduction circuit includes: a second transistor, a third transistor, and a second capacitor; The gate of the second transistor is coupled to the first light emission control signal line, a first pole of the second transistor is coupled to the second node, and a second pole of the second transistor is coupled to the reference voltage signal line; The gate of the third transistor is coupled to the second control signal line, a first pole of the third transistor is coupled to the reference voltage signal line, and a second pole of the third transistor is coupled to the second node; A first electrode of the second capacitor is coupled to the first node, and a second electrode of the second capacitor is coupled to the second node.

6. The display panel according to any one of claims 1-5, wherein, The bias circuit includes: a fourth transistor; The gate of the fourth transistor is coupled to the second control signal line, a first pole of the fourth transistor is coupled to a first pole of the driving transistor, and a second pole of the fourth transistor is coupled to the bias voltage signal line.

7. The display panel according to any one of claims 1-6, wherein, The light emission control circuit includes: a fifth transistor and a sixth transistor; The gate of the fifth transistor is coupled to the second light emission control signal line, a first pole of the fifth transistor is coupled to the first power supply signal line, and a second pole of the fifth transistor is coupled to a first pole of the driving transistor; The gate of the sixth transistor is coupled to the first light emission control signal line, a first pole of the sixth transistor is coupled to a second pole of the driving transistor, and a second pole of the sixth transistor is coupled to the light emitting device.

8. The display panel according to any one of claims 1-7, wherein, Further included is: A reset circuit, coupled to the driving transistor, configured to provide a signal on the first initialization signal line to a second pole of the driving transistor in response to a signal on the reset signal line; The reset circuit includes: a seventh transistor; The gate of the seventh transistor is coupled to the reset signal line, a first pole of the seventh transistor is coupled to a second pole of the driving transistor, and a second pole of the seventh transistor is coupled to the first initialization signal line.

9. The display panel according to any one of claims 1-8, wherein, Further included is: An initialization circuit, coupled to the light emitting device, configured to provide a signal on the second initialization signal line to the light emitting device in response to a signal on the second control signal line; The initialization circuit includes: an eighth transistor; The gate of the eighth transistor is coupled to the second control signal line, a first pole of the eighth transistor is coupled to the light emitting device, and a second pole of the eighth transistor is coupled to the second initialization signal line.

10. The display panel according to any one of claims 1-9, wherein, The substrate further includes: a plurality of pixel units; each pixel unit includes at least three sub-pixels; There is the reference voltage signal line between the orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit on the substrate; the orthographic projections of the first sub-pixel and the second sub-pixel in the pixel unit on the substrate are symmetric about the orthographic projection of the reference voltage signal line on the substrate; the first sub-pixel and the second sub-pixel in the pixel unit share the reference voltage signal line; There are the data signal line and the reference voltage signal line between the orthographic projections of the second sub-pixel and the third sub-pixel in the pixel unit on the substrate.

11. The display panel according to claim 10, wherein, There is at least one signal line between two adjacent pixel units along the first direction, and the signal line includes at least one of a first initialization signal line, a second initialization signal line, a bias voltage signal line, and a second power supply signal line.

12. The display panel according to claim 11, wherein, There is one signal line between two adjacent pixel units along the first direction, and the first initialization signal line, the second initialization signal line, the bias voltage signal line, and the second power supply signal line are alternately arranged in sequence along the first direction.

13. The display panel according to any one of claims 2-12, wherein, It further includes: a first conductive layer located between the substrate and the first semiconductor layer; a second conductive layer and a third conductive layer located between the first semiconductor layer and the second semiconductor layer; the third conductive layer is located on the side of the second conductive layer away from the substrate; a fourth conductive layer located on the side of the second semiconductor layer away from the substrate; a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; a sixth conductive layer located on the side of the fifth conductive layer away from the substrate; The orthographic projection of the first conductive layer on the substrate overlaps with the orthographic projection of the driving transistor on the substrate.

14. The display panel according to claim 13, wherein, The signal lines in the second conductive layer extend along the first direction; the second conductive layer includes the two first light emission control signal lines, the second light emission control signal line, the second control signal line, and the reset signal line; The signal lines in the third conductive layer extend along the first direction; the third conductive layer includes the First control signal line.

15. The display panel according to claim 14, wherein, The signal lines in the fourth conductive layer extend along the first direction; the fourth conductive layer includes the first control signal line, the bias voltage signal line, the first initialization signal line, and the second initialization signal line.

16. The display panel according to claim 14, wherein, The signal lines in the fifth conductive layer extend along the first direction; the fifth conductive layer includes the scan signal line, the reference voltage signal line, the second control signal line, the first power supply signal line, and the second power supply signal line.

17. The display panel according to claim 14, wherein, The signal lines in the sixth conductive layer extend along the second direction; the sixth conductive layer includes: the first power supply signal line, the data signal line, the reference voltage signal line, the bias voltage signal line, the first initialization signal line, the second initialization signal line, and the second power supply signal line.

18. The display panel according to claim 14, wherein, The orthographic projections of the first power supply signal line, the second power supply signal line, the reference voltage signal line, the bias voltage signal line, the first initialization signal line, and the second initialization signal line on the substrate are arranged in a grid pattern.

19. A driving method for a display panel according to any one of claims 1-18, wherein, It includes: In the reset stage, the threshold compensation transistor responds to the signal on the first control signal line and conducts the gate of the driving transistor with the second pole of the driving transistor; The voltage stabilizing transistor responds to the signal on the first control signal line and provides the signal on the first power supply signal line to the first node; In the first bias stage, the noise reduction circuit responds to the signal on the second control signal line and provides the signal on the reference voltage signal line to the second node; The bias circuit provides the signal on the bias voltage signal line to the first pole of the driving transistor in response to the signal on the second control signal line; In the data writing stage, the data writing circuit provides the data voltage signal on the data signal line to the second node in response to the signal on the scan signal line; the threshold compensation transistor conducts the gate of the driving transistor and the second pole of the driving transistor in response to the signal on the first control signal line; the voltage stabilizing transistor provides the signal on the first power supply signal line to the first node in response to the signal on the first control signal line; In the threshold compensation stage, the light emission control circuit provides the signal on the first power supply signal line to the first pole of the driving transistor in response to the signal on the second light emission control signal line; the threshold compensation transistor conducts the gate of the driving transistor and the second pole of the driving transistor in response to the signal on the first control signal line; the voltage stabilizing transistor provides the signal on the first power supply signal line to the first node in response to the signal on the first control signal line; In the second bias stage, the noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the second control signal line; The bias circuit provides the signal on the bias voltage signal line to the first pole of the driving transistor in response to the signal on the second control signal line; In the light emission stage, the light emission control circuit provides the signal on the first power supply signal line to the first pole of the driving transistor in response to the signal on the second light emission control signal line, and conducts the second pole of the driving transistor and the light emitting device in response to the signal on the first light emission control signal line; The noise reduction circuit provides the signal on the reference voltage signal line to the second node in response to the signal on the first light emission control signal line; The reset stage further includes: the reset circuit provides the signal on the first initialization signal line to the second pole of the driving transistor in response to the signal on the reset signal line; The first bias stage further includes: the initialization circuit provides the signal on the second initialization signal line to the light emitting device in response to the signal on the second control signal line; The second bias stage further includes: the initialization circuit provides the signal on the second initialization signal line to the light emitting device in response to the signal on the second control signal line.

20. A display device, wherein, A display panel comprising any one of claims 1-18.

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