MEMS acceleration unit, MEMS acceleration chip and electronic equipment

Abstract

According to the MEMS acceleration unit, the MEMS acceleration chip and the electronic equipment provided by the invention, the anti-interference capability of the MEMS acceleration unit is improved under the conditions of relatively high sensitivity and signal-to-noise ratio. The MEMS acceleration unit comprises a substrate and at least one group of piezoelectric units which are sequentially stacked in the Z direction. One group of piezoelectric units comprises a plurality of first capacitors and a plurality of second capacitors, the plurality of first capacitors are connected in parallel to form a first capacitor bank, the plurality of second capacitors are connected in parallel to form a second capacitor bank, and the first capacitor bank and the second capacitor bank are connected in series. In the X direction, any one first capacitor is symmetrical with respect to the first surface, and any one second capacitor is symmetrical with respect to the first surface; the first face is a plane defined by the Z direction and the Y direction. The X direction, the Y direction and the Z direction are perpendicular to one another. Along the Y direction, any first capacitor has one first capacitor which is symmetrical with respect to the second surface, and any second capacitor has one second capacitor which is symmetrical with respect to the second surface. The second face is a plane defined by the Z direction and the X direction.

Description

Technical Field

[0001] The present application relates to the field of sensor technology, and in particular to a MEMS acceleration unit, a MEMS acceleration chip, and an electronic device. Background Art

[0002] As the functions and types of electronic devices become more and more diverse, the application of micro-electromechanical (MEMS) accelerometers (ACC) in electronic devices is becoming more and more extensive.

[0003] Because surface silicon (Si) processing technology is relatively mature and can be achieved at a relatively low cost, the most common MEMS ACC is the capacitive MEMS ACC. In recent years, with the continuous maturity of MEMS piezoelectric processing, piezoelectric MEMS ACC has also begun to gain popularity. This is due to the fact that piezoelectric sensors can directly convert acceleration energy into electrical energy through the "cantilever beam or membrane + mass block" architecture in MEMS, which has great advantages in low-power applications.

[0004] For a MEMS ACC (such as a Z-axis piezoelectric MEMS ACC), sensitivity (SENS) and signal-to-noise ratio are two more important technical indicators. This also leads designers to focus on high sensitivity and low noise designs during the design phase, while ignoring the MEMS ACC's anti-interference ability, which affects the performance of the MEMS ACC. Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a MEMS acceleration unit, a MEMS acceleration chip, and an electronic device, which can improve the anti-interference ability of the MEMS acceleration unit while maintaining high sensitivity and signal-to-noise ratio.

[0006] In a first aspect, the present application provides a MEMS acceleration unit, which includes a substrate and at least one group of piezoelectric units stacked in sequence along the Z direction. A group of piezoelectric units includes a plurality of first capacitors and a plurality of second capacitors; a plurality of first capacitors are connected in parallel to form a first capacitor group, a plurality of second capacitors are connected in parallel to form a second capacitor group, and the first capacitor group and the second capacitor group are connected in series. Along the X direction, any first capacitor has a first capacitor symmetrical about the first face, and any second capacitor has a second capacitor symmetrical about the first face; the first face is a plane surrounded by the Z direction and the Y direction; wherein the X direction, the Y direction, and the Z direction are perpendicular to each other. Along the Y direction, any first capacitor has a first capacitor symmetrical about the second face, and any second capacitor has a second capacitor symmetrical about the second face; the second face is a plane surrounded by the Z direction and the X direction.

[0007] Assume that the first capacitor includes a first capacitor A1, a first capacitor A2, a first capacitor A3, and a first capacitor A4, and the second capacitor includes a second capacitor B1, a second capacitor B2, a second capacitor B3, and a second capacitor B4, and that the first capacitor A1 and the first capacitor A2 are symmetrical with respect to the first plane, the first capacitor A3 and the first capacitor A4 are symmetrical with respect to the first plane, the second capacitor B1 and the second capacitor B2 are symmetrical with respect to the first plane, and the second capacitor B3 and the second capacitor B4 are symmetrical with respect to the first plane; the first capacitor A1 and the first capacitor A3 are symmetrical with respect to the second plane, the first capacitor A2 and the first capacitor A4 are symmetrical with respect to the second plane, the second capacitor B1 and the second capacitor B3 are symmetrical with respect to the second plane, and the second capacitor B2 and the second capacitor B4 are symmetrical with respect to the second plane.

[0008] If you want to eliminate the influence of acceleration in the X direction: take the first capacitor A1 as an example, assume that the physical tensor of the first capacitor A1 is Pi1, i1 = (1, 2, 3), where the value 1 is the physical tensor of the first capacitor A1 in the X direction, the value 2 is the physical tensor of the first capacitor A1 in the Y direction, the value 3 is the physical tensor of the first capacitor A1 in the Z direction, and so on, which will not be repeated below. Set the physical tensor of the first capacitor A2 that is symmetrical with the first capacitor A1 about the first plane to be Pi2, i2 = (-1, 2, 3). Then, the physical tensors of the first capacitor A1 and the first capacitor A2 in the X direction can cancel each other, thereby eliminating the influence of the physical tensor in the X direction on the acceleration measurement result in the Z direction.

[0009] Of course, the physical tensors of Pi1 and Pi2 in the X direction can also be set to be different in value. However, those skilled in the art should know that even if the physical tensors of Pi1 and Pi2 in the X direction are different, as long as the two are symmetrical about the first plane, the influence of the acceleration in the X direction on the acceleration measurement result in the Z direction can be improved.

[0010] To eliminate the influence of acceleration in the Y direction: Still using first capacitor A1 as an example, assuming that the physical tensor of first capacitor A1 is Pi1, i1 = (1, 2, 3), and setting the physical tensor of first capacitor A3, which is symmetrical with first capacitor A1 about the second plane, to Pi3, i3 = (1, -2, 3), the physical tensors of first capacitor A1 and first capacitor A2 in the Y direction can cancel each other out, thereby eliminating the influence of the physical tensor in the Y direction on the acceleration measurement result in the Z direction.

[0011] Of course, the physical tensors of Pi1 and Pi3 in the Y direction can also be set to be different in value, but those skilled in the art should know that even if the physical tensors of Pi1 and Pi3 in the Y direction are different, as long as the two are symmetrical about the second plane, the acceleration in the Y direction can be improved, and the impact on the acceleration measurement results in the Z direction can be improved.

[0012] On this basis, the present application can also connect multiple first capacitors in parallel to form a first capacitor group, connect multiple second capacitors in parallel to form a second capacitor group, and connect the first capacitor group and the second capacitor group in series to obtain a group of piezoelectric units. Furthermore, because the intrinsic capacitance value of the piezoelectric unit is related to the sensitivity and loss noise of the MEMS acceleration unit, and the signal-to-noise ratio of the MEMS acceleration unit is related to its own noise and the noise of the detection circuit, the intrinsic capacitance value of the piezoelectric unit is adjusted by adjusting the intrinsic capacitance value of at least one first capacitor and / or the intrinsic capacitance value of at least one second capacitor, thereby adjusting the sensitivity, noise, and signal-to-noise ratio of the MEMS acceleration unit. Among them, the detection circuit is used to detect the voltage or charge output by the MEMS acceleration unit.

[0013] In some possible implementations, the intrinsic capacitance value of the piezoelectric unit is greater than the sum of the first parasitic capacitance value, the second parasitic capacitance value, and the third parasitic capacitance value; the first parasitic capacitance value is the parasitic capacitance value in the piezoelectric unit, the second parasitic capacitance value is the parasitic capacitance value on the connection between the piezoelectric unit and the detection circuit, and the third parasitic capacitance value is the parasitic capacitance value in the detection circuit.

[0014] According to the formula It can be seen that the larger the parasitic capacitance Cp is, the greater the sensitivity S of the MEMS acceleration unit is. E In order to reduce the impact of parasitic capacitance on the sensitivity of the MEMS accelerometer, the intrinsic capacitance value C of the piezoelectric unit should be greater than the parasitic capacitance value Cp. The intrinsic capacitance value C of the piezoelectric unit can even be greater. For example, the intrinsic capacitance value C of the piezoelectric unit is greater than 3 times the parasitic capacitance value Cp.

[0015] Moreover, the higher the signal-to-noise ratio of the MEMS accelerometer, the better the performance of the MEMS accelerometer. As mentioned above, the noise (loss noise V nt ) is related to the intrinsic capacitance of the piezoelectric unit. Therefore, the present application can adjust the intrinsic capacitance of the piezoelectric unit in the MEMS acceleration unit by changing the series and parallel relationship of the multiple first capacitors and the multiple second capacitors in the MEMS acceleration unit, thereby reducing the loss noise V nt Greater than the noise V of the detection circuit nE , in order to improve the signal-to-noise ratio (SNR) of the MEMS acceleration unit.

[0016] That is, the intrinsic capacitance of the piezoelectric unit is still less than Where K is the Boltzmann constant, T is the absolute temperature, η is the dielectric loss, f2 is the upper limit of the noise bandwidth, f1 is the lower limit of the noise bandwidth, and V nE Indicates the noise of the detection circuit.

[0017] In some possible implementations, to adjust the sensitivity, noise, and signal-to-noise ratio of the MEMS accelerometer, the intrinsic capacitance values ​​of the multiple first capacitors are the same, and the intrinsic capacitance values ​​of the multiple second capacitors are the same. Furthermore, the intrinsic capacitance values ​​of the first capacitors and the intrinsic capacitance values ​​of the second capacitors are the same; or, the intrinsic capacitance values ​​of the first capacitors and the intrinsic capacitance values ​​of the second capacitors are different.

[0018] For example, if the intrinsic capacitance values ​​of the plurality of first capacitors and the plurality of second capacitors are the same, and the intrinsic capacitance value of the piezoelectric unit is not small enough, the intrinsic capacitance value of the piezoelectric unit can be further reduced by changing the intrinsic capacitance values ​​of the plurality of first capacitors and the intrinsic capacitance values ​​of the plurality of second capacitors. For example, the intrinsic capacitance value of the piezoelectric unit can be reduced by increasing the capacitance value between the plurality of first capacitors and the plurality of second capacitors.

[0019] In some possible implementations, the wiring layer may include a first wiring layer and a second wiring layer, and along the direction of the substrate pointing to the piezoelectric unit, the multiple first capacitors and the multiple second capacitors each include a first electrode, a piezoelectric layer, and a second electrode stacked in sequence. The first wiring layer is arranged on the same layer as the first electrode, and the second wiring layer is arranged on the same layer as the second electrode, and the first wiring layer and the second wiring layer are electrically isolated by the piezoelectric layer. In addition, the second electrodes of the multiple first capacitors are electrically connected to the detection circuit through the second wiring layer, and the first electrodes of the multiple second capacitors are electrically connected to the detection circuit through the first wiring layer, so that the voltage or charge is input to the detection circuit through the second wiring layer.

[0020] In the MEMS acceleration unit, the relative positions of the plurality of first capacitors and the plurality of second capacitors are different, and the wiring arrangements of the wiring in the first wiring layer and the second wiring layer are different.

[0021] Optionally, along the Y direction, the two second capacitors are located between two adjacent first capacitors. For example, along the Y direction, the second capacitor B1 and the second capacitor B3 are located between the first capacitor A1 and the first capacitor A3, and the second capacitor B2 and the second capacitor B4 are located between the first capacitor A2 and the first capacitor A4.

[0022] Alternatively, along the Y direction, the first capacitor, the second capacitor, the first capacitor, and the second capacitor are arranged in sequence. For example, along the Y direction, the first capacitor A1, the second capacitor B1, the first capacitor A3, and the second capacitor B3 are arranged in sequence, and the first capacitor A2, the second capacitor B2, the first capacitor A4, and the second capacitor B4 are arranged in sequence.

[0023] In some possible implementations, the substrate is divided into a plurality of spaced first regions and a plurality of spaced second regions, with the first capacitor located within the first region and the second capacitor located within the second region. Compared to solutions without substrate segmentation, solutions with substrate segmentation can reduce energy loss and simplify the manufacturing process.

[0024] In some possible implementations, a group of piezoelectric units may include more capacitors in addition to the multiple first capacitors and the multiple second capacitors. For example, a group of piezoelectric units may also include multiple third capacitors, which are connected in parallel to form a third capacitor group, and the multiple third capacitors are connected in series or in parallel with the first capacitor group and the second capacitor group, respectively. In this way, the equivalent capacitance of the piezoelectric unit can be adjusted by changing the series or parallel connection relationship of the multiple first capacitors, the multiple second capacitors, and the multiple third capacitors, thereby adjusting the sensitivity, noise, and signal-to-noise ratio of the MEMS accelerometer.

[0025] In a second aspect, the present application provides a MEMS accelerometer chip, which includes a housing, an application integrated circuit, a circuit board, and the MEMS acceleration unit described in the first aspect.

[0026] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0027] In a third aspect, the present application provides an electronic device, which includes a detection circuit and the MEMS accelerometer chip described in the second aspect, wherein the detection circuit is used to detect the voltage or charge output by the MEMS acceleration unit in the MEMS accelerometer chip.

[0028] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a diagram of the interaction between the MEMS accelerometer chip and the processor provided in an embodiment of the present application;

[0030] Figure 2a A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0031] Figure 2b A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0032] Figure 3 for Figure 2a or Figure 2b Cross-sectional view along C1-C2 direction;

[0033] Figure 4a A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0034] Figure 4b is a connection relationship diagram of a plurality of first capacitors and a plurality of second capacitors;

[0035] Figure 4c for Figure 4a The equivalent circuit diagram of the provided MEMS accelerometer;

[0036] Figure 5 A comparison chart of the signal-to-noise ratio of MEMS acceleration unit A and MEMS acceleration unit B provided in the related art;

[0037] Figure 6a A schematic diagram of capacitance values ​​of a plurality of first capacitors and a plurality of second capacitors provided in an embodiment of the present application;

[0038] Figure 6b for Figure 6a The signal-to-noise ratio of the corresponding MEMS accelerometer;

[0039] Figure 7a A schematic diagram of capacitance values ​​of a plurality of first capacitors and a plurality of second capacitors provided in an embodiment of the present application;

[0040] Figure 7b for Figure 7a The signal-to-noise ratio of the corresponding MEMS accelerometer;

[0041] Figure 8 A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0042] Figure 9a A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0043] Figure 9b A top view of a MEMS acceleration unit provided in an embodiment of the present application;

[0044] Figure 9c for Figure 9b The equivalent circuit diagram of the provided MEMS accelerometer;

[0045] Figure 10a This is an equivalent circuit diagram of the MEMS acceleration unit provided in an embodiment of the present application;

[0046] Figure 10b This is an equivalent circuit diagram of the MEMS acceleration unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0049] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0050] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0052] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a memory.

[0053] For example, the electronic device may be a true wireless stereo (TWS) headset, a hearing aid, a microphone, a mobile phone, a tablet computer, a laptop computer, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (e.g., a smart watch, a smart bracelet, etc.), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, a car airbag system (supplemental inflatable restraint system, SRS), etc.

[0054] For the sake of convenience, the following text takes TWS headphones as an example of an electronic device.

[0055] The TWS earphones include a MEMS accelerometer chip and a processor. The MEMS accelerometer chip includes a housing, a MEMS acceleration unit, and a circuit board arranged in the housing. The circuit board 300 may be a printed circuit board (PCB).

[0056] When a user wears the TWS headset to make a call, the vibrations of the head and throat caused by the user's voice are transmitted to the MEMS accelerometer chip through the shell and circuit board of the TWS headset. The MEMS accelerometer chip (or MEMS acceleration unit) can convert the energy generated by acceleration into a corresponding charge or voltage. Optionally, the TWS headset may also include a detection circuit for detecting the charge or voltage output by the MEMS acceleration unit.

[0057] The MEMS accelerometer chip may further include an application specific integrated circuit (ASIC), which may include, for example, a low noise amplifier (LNA). The LNA may be electrically connected to the output of the MEMS accelerometer to amplify the voltage or charge output by the MEMS accelerometer. Of course, the ASIC may also include other circuits, such as a filter with a filtering function, etc., which is not limited in the present embodiment.

[0058] like Figure 1As shown, the processor in the TWS headset can receive the charge or voltage input by the MEMS accelerometer chip or the application integrated circuit to obtain the acceleration generated by the vibration of the user's head or throat, and then convert the vibration of the user's head or throat into a corresponding voice signal based on the acceleration, thereby realizing the bone conduction technology of picking up sound.

[0059] As mentioned in the background technology, for a MEMS ACC, sensitivity and signal-to-noise ratio are two more important technical indicators. This also leads designers to focus on high sensitivity and low noise designs during the design phase, while ignoring the anti-interference ability of the MEMS ACC.

[0060] For example, the Z-axis piezoelectric MEMS ACC is mainly used to measure the acceleration of TWS headphones in the Z-axis direction. However, if the acceleration of the X-axis and Y-axis are not designed well, the measurement results of the device in the Z-axis direction will be affected by the Z-axis piezoelectric MEMS ACC, thereby affecting the performance of the Z-axis piezoelectric MEMS ACC.

[0061] The impact of the acceleration on the X-axis and Y-axis is usually measured using the crosstalk indicator.

[0062] Good design often requires high isolation. Related technologies usually resist isolation by using more chip redundant area, which leads to the chip performance area ratio (such as SNR / mm 2 ) decline.

[0063] Therefore, improving the anti-interference capability of MEMS ACC while maintaining high sensitivity and signal-to-noise ratio is the key to MEMS ACC.

[0064] Based on this, the embodiment of the present application provides a MEMS acceleration unit, such as Figure 2a and Figure 2b 、 Figure 3 As shown, the MEMS acceleration unit includes a substrate 10 and at least one group of piezoelectric units 20 stacked in sequence along the Z direction, and the substrate 10 and at least one group of piezoelectric units 20 can form a cantilever. Figure 3 As shown, the MEMS acceleration unit may further include a mass block 30 and a frame 40 . The mass block 30 and the frame 40 may be disposed on a side of the substrate facing away from the piezoelectric unit 20 .

[0065] like Figure 2aAs shown, a group of piezoelectric units 20 includes multiple first capacitors (A1, A2, A3, A4) and multiple second capacitors (B1, B2, B3, B4). In the present application, the Z direction can be the direction from the substrate 10 to the piezoelectric unit 20, or the direction from the piezoelectric unit 20 to the substrate 10. The X direction can be the direction from the first capacitor A1 to the first capacitor A2, or the direction from the first capacitor A2 to the first capacitor A1. The Y direction can be the direction from the first capacitor A1 to the first capacitor A3, or the direction from the first capacitor A3 to the first capacitor A1. Moreover, the X direction, Y direction, and Z direction are perpendicular to each other.

[0066] like Figure 2a As shown, along the X direction, any first capacitor has a first capacitor symmetrical about the first plane, and any second capacitor has a second capacitor symmetrical about the first plane. The first plane is a plane defined by the Z and Y directions. For example, first capacitor A1 and first capacitor A2 are symmetrical about the first plane, first capacitor A3 and first capacitor A4 are symmetrical about the first plane, second capacitor B1 and second capacitor B2 are symmetrical about the first plane, and second capacitor B3 and second capacitor B4 are symmetrical about the first plane. Therefore, it can be concluded that the number of first capacitors is at least four.

[0067] Taking the symmetry of first capacitor A1 and first capacitor A2 with respect to the first plane as an example, in the embodiment of the present application, if the overlapping area of ​​the orthographic projection of first capacitor A1 on the first plane and the orthographic projection of first capacitor A2 on the first plane is greater than or equal to 80%, first capacitor A1 and first capacitor A2 are considered symmetric with respect to the first plane. The symmetry of other first capacitors with respect to the first plane and other second capacitors with respect to the first plane are also based on this standard and will not be further described here.

[0068] like Figure 2a As shown, along the Y direction, any first capacitor has a first capacitor symmetrical about the second plane, and any second capacitor has a second capacitor symmetrical about the second plane. The second plane is the plane enclosed by the Z direction and the X direction. For example, the first capacitor A1 and the first capacitor A3 are symmetrical about the second plane, the first capacitor A2 and the first capacitor A4 are symmetrical about the second plane, the second capacitor B1 and the second capacitor B3 are symmetrical about the second plane, and the second capacitor B2 and the second capacitor B4 are symmetrical about the second plane. Therefore, it can be concluded that the number of second capacitors is at least 4.

[0069] Taking the symmetry of first capacitor A1 and first capacitor A3 with respect to the second plane as an example, in the embodiment of the present application, if the overlapping area of ​​the orthographic projection of first capacitor A1 on the second plane and the orthographic projection of first capacitor A3 on the second plane is greater than or equal to 80%, first capacitor A1 and first capacitor A3 are considered symmetric with respect to the second plane. The same standard is also used for the symmetry of other first capacitors and other second capacitors with respect to the second plane, and will not be further described here.

[0070] If you want to eliminate the influence of acceleration in the X direction: take the first capacitor A1 as an example, assume that the physical tensor of the first capacitor A1 is Pi1, i1 = (1, 2, 3), where the value 1 is the physical tensor of the first capacitor A1 in the X direction, the value 2 is the physical tensor of the first capacitor A1 in the Y direction, the value 3 is the physical tensor of the first capacitor A1 in the Z direction, and so on, which will not be repeated below. Set the physical tensor of the first capacitor A2 that is symmetrical with the first capacitor A1 about the first plane to be Pi2, i2 = (-1, 2, 3). Then, the physical tensors of the first capacitor A1 and the first capacitor A2 in the X direction can cancel each other, thereby eliminating the influence of the physical tensor in the X direction on the acceleration measurement result in the Z direction.

[0071] Of course, the physical tensors of Pi1 and Pi2 in the X direction can also be set to be different in value. However, those skilled in the art should know that even if the physical tensors of Pi1 and Pi2 in the X direction are different, as long as the two are symmetrical about the first plane, the influence of the acceleration in the X direction on the acceleration measurement result in the Z direction can be improved.

[0072] To eliminate the influence of acceleration in the Y direction: Still taking the first capacitor A1 as an example, assuming that the physical tensor of the first capacitor A1 is Pi1, i1 = (1, 2, 3), and the physical tensor of the first capacitor A3, which is symmetrical with the first capacitor A1 about the second plane, is Pi3, i3 = (1, -2, 3), then the physical tensors of the first capacitor A1 and the first capacitor A2 in the Y direction can cancel each other out, thereby eliminating the influence of the physical tensor in the Y direction on the acceleration measurement result in the Z direction.

[0073] Of course, the physical tensors of Pi1 and Pi3 in the Y direction can also be set to be different in value, but those skilled in the art should know that even if the physical tensors of Pi1 and Pi3 in the Y direction are different, as long as the two are symmetrical about the second plane, the acceleration in the Y direction can be improved, and the impact on the acceleration measurement results in the Z direction can be improved.

[0074] The above example uses the first capacitor A1 as an example to briefly explain how to eliminate the impact of acceleration in the X and Y directions on the acceleration measurement results in the Z direction. Because any first capacitor has at least one first capacitor symmetrically located in the X and Y directions, and any second capacitor has at least one second capacitor symmetrically located in the X and Y directions, the other first and second capacitors can also eliminate the impact of acceleration in the X and Y directions on the acceleration measurement results in the Z direction, similar to the above example.

[0075] like Figure 4a-4c As shown, in addition to being symmetrical, multiple first capacitors can also be connected in parallel to form a first capacitor group, and multiple second capacitors can also be connected in parallel to form a second capacitor group, and the first capacitor group and the second capacitor group are connected in series.

[0076] Those skilled in the art will appreciate that, while maintaining the same area of ​​the effective electrodes of multiple capacitors, the capacitance of the multiple capacitors can be adjusted by connecting them in series or in parallel. The capacitance of the capacitors is related to the sensitivity, noise, and signal-to-noise ratio of the MEMS accelerometer. Therefore, the present application can adjust the sensitivity, noise, and signal-to-noise ratio of the MEMS accelerometer by changing the series or parallel connection relationship between different capacitors.

[0077] Specifically, taking MEMS acceleration unit A and MEMS acceleration unit B as an example, assuming that the area of ​​the effective electrodes of multiple capacitors remains unchanged, and after the acceleration of the TWS headset is loaded onto the mass block 30, the energy E transmitted to the electrodes of each capacitor of MEMS acceleration unit A and MEMS acceleration unit B is the same, then the sensitivity S E for:

[0078]

[0079] Where Q represents the charge, and C represents the total capacitance of the multiple first capacitors and multiple second capacitors connected in series and in parallel in the MEMS accelerometer A or MEMS accelerometer B, or in other words, the intrinsic capacitance of at least one group of piezoelectric units. It can be seen that before the parasitic capacitance takes effect, at the same energy E, the smaller the intrinsic capacitance C, the higher the sensitivity of the MEMS accelerometer A and MEMS accelerometer B. Therefore, the sensitivity S of the MEMS accelerometer A or MEMS accelerometer B can be adjusted by adjusting the intrinsic capacitance of the piezoelectric units in the MEMS accelerometer A and MEMS accelerometer B. E .

[0080] The noise of MEMS accelerometers A and B is mainly composed of loss noise and mechanical damping noise (negligible). The loss noise Vnt is:

[0081]

[0082] Here, k represents the Boltzmann constant, T represents the absolute temperature, η represents the dielectric loss, f2 represents the upper limit of the noise bandwidth, f1 represents the lower limit of the noise bandwidth, and k(f1, f2) represents the bandwidth integral function. It can be seen that the loss noise Vnt is inversely proportional to the intrinsic capacitance of the piezoelectric element in MEMS accelerometer A and MEMS accelerometer B. Therefore, the loss noise Vnt of MEMS accelerometer A or MEMS accelerometer B can be adjusted by adjusting the intrinsic capacitance of the piezoelectric element in MEMS accelerometer A or MEMS accelerometer B.

[0083] Furthermore, the signal-to-noise ratio (SNR) of MEMS accelerometer A and MEMS accelerometer B can be obtained:

[0084]

[0085] Assuming that the intrinsic capacitance of the piezoelectric unit in MEMS accelerometer A is greater than the intrinsic capacitance of the piezoelectric unit in MEMS accelerometer B, the sensitivity S of MEMS accelerometer A is E Less than the sensitivity S of the MEMS accelerometer B E , the loss noise Vnt of MEMS acceleration unit A is smaller than the loss noise Vnt of MEMS acceleration unit B.

[0086] Furthermore, DB(S EA )-DB(V ntA )=DB(S EB )-DB(V ntB ), where DB stands for decibel, S EA Indicates the sensitivity of the MEMS accelerometer A, V ntA represents the loss noise of MEMS accelerometer A, S EB Indicates the sensitivity of MEMS accelerometer B, V ntB represents the loss noise of MEMS accelerometer B. In other words, the signal-to-noise ratio (SNR) of MEMS accelerometer A and MEMS accelerometer B should be the same according to Formula 3.

[0087] However, if Figure 5 As shown, the noise in the detection circuit V nE Greater than V ntA , and less than S EA and V ntB In the case of SNR(A)=DB(S EA )-DB(V nE ), SNR(B)=DB(S EA)-DB(V ntA ), that is, the signal-to-noise ratio SNR(A) of MEMS acceleration unit A is less than the signal-to-noise ratio SNR(B) of MEMS acceleration unit B.

[0088] Those skilled in the art should know that the higher the signal-to-noise ratio of the MEMS accelerometer, the better the performance of the MEMS accelerometer. nt The size of is related to the intrinsic capacitance value of the piezoelectric unit in the MEMS acceleration unit. Therefore, the present application can adjust the intrinsic capacitance value of the piezoelectric unit in the MEMS acceleration unit by changing the series and parallel relationship of multiple first capacitors and multiple second capacitors in the MEMS acceleration unit, thereby reducing the loss noise V nt Greater than the noise V of the detection circuit nE , in order to improve the signal-to-noise ratio (SNR) of the MEMS acceleration unit.

[0089] That is, the first standard of the intrinsic capacitance value of the piezoelectric unit in the MEMS acceleration unit can be V nt >V nE (Formula 4). For the detection circuit, small noise V nE It is difficult to achieve and the cost is very high. Therefore, the present application increases the loss noise Vnt of the MEMS acceleration unit by changing the series and parallel relationship of multiple first capacitors and multiple second capacitors in the MEMS acceleration unit, thereby achieving V nt >V nE .

[0090] On this basis, when the MEMS accelerometer is detected using a detection circuit, parasitic capacitance exists. For example, the parasitic capacitance in the piezoelectric unit 20 is a first parasitic capacitance value, the parasitic capacitance on the line connecting the piezoelectric unit 20 and the detection circuit is a second parasitic capacitance value, and the parasitic capacitance in the detection circuit is a third parasitic capacitance value.

[0091] According to the formula It can be seen that the larger the parasitic capacitance Cp, the lower the sensitivity of the MEMS accelerometer. To reduce the impact of parasitic capacitance on the sensitivity of the MEMS accelerometer, the intrinsic capacitance C of the piezoelectric unit should be greater than the parasitic capacitance Cp. The intrinsic capacitance C of the piezoelectric unit can even be greater. For example, the intrinsic capacitance C of the piezoelectric unit can be greater than three times the parasitic capacitance Cp. The parasitic capacitance Cp can be the sum of the first parasitic capacitance, the second parasitic capacitance, and the third parasitic capacitance.

[0092] That is, the second standard for adjusting the intrinsic capacitance value C of the piezoelectric unit by changing the series and parallel relationship between the plurality of first capacitors and the plurality of second capacitors in the MEMS acceleration unit may be 3Cp<C (Formula 5).

[0093] Substituting Formula 4 and Formula 5 into Formula 2 yields:

[0094]

[0095] The intrinsic capacitance values ​​of the plurality of first capacitors and the plurality of second capacitors are combined to calculate the intrinsic capacitance value of the piezoelectric unit after the plurality of first capacitors and the plurality of second capacitors are connected in series and in parallel:

[0096] The first case, such as Figure 6a As shown, it is assumed that the intrinsic capacitance values ​​of the four first capacitors and the four second capacitors are the same, all of which are 0.5pF (0.5pF is an example, and the embodiments of the present application are not limited to this, the same below). The result of connecting the four first capacitors in parallel is 0.5pF*4=2pF, the result of connecting the four second capacitors in parallel is 0.5pF*4=2pF, and the series connection result of the first capacitor group composed of the four first capacitors and the second capacitor group composed of the four second capacitors is 2pF*2pF / (2pF+2pF)=1pF. That is, after connecting the four first capacitors and the four second capacitors in series and in parallel, the intrinsic capacitance C of a group of piezoelectric units is 1pF.

[0097] Compared to Figure 5 ,like Figure 6a The intrinsic capacitance C of the piezoelectric unit shown is not small enough, which still causes V nt <V nE , that is, the first criterion is not met, which results in the signal-to-noise ratio (SNR) of the MEMS acceleration unit being still small ( Figure 6b ).

[0098] Based on this, the embodiment of the present application can further reduce the intrinsic capacitance value C of the piezoelectric unit by changing the intrinsic capacitance values ​​of the four first capacitors and the intrinsic capacitance values ​​of the four second capacitors. For details, see the second case.

[0099] The second case, such as Figure 7aAs shown, it is assumed that the intrinsic capacitance values ​​of the four first capacitors are all the same, all 0.1pF; the intrinsic capacitance values ​​of the four second capacitors are all the same, all 0.9pF. The result of connecting the four first capacitors in parallel is 0.1pF*4=0.4pF, the result of connecting the four second capacitors in parallel is 0.9pF*4=3.6pF, and the result of connecting the first capacitor group consisting of the four first capacitors and the second capacitor group consisting of the four second capacitors in series is 0.4pF*3.6pF / (0.4pF+3.6pF)=0.36pF. That is, after connecting the four first capacitors and the four second capacitors in series and in parallel, the intrinsic capacitance C of a group of piezoelectric units is 0.36pF.

[0100] Compared to Figure 6a and 6b ,like Figure 7a The intrinsic capacitance C of the piezoelectric unit shown is further reduced, so that V nt >V nE , meeting the first criterion and further improving the signal-to-noise ratio (SNR) of the MEMS acceleration unit. Figure 7b ).

[0101] Of course, if Figure 7a The intrinsic capacitance value C of the piezoelectric unit shown is still not small enough, and the intrinsic capacitance values ​​of the four first capacitors and the four second capacitors can be changed to further reduce the intrinsic capacitance value C of the piezoelectric unit. This embodiment of the present application is not limited to this.

[0102] In addition, the above example is based on 4 first capacitors and 4 second capacitors, and the intrinsic capacitance values ​​of the 4 first capacitors are the same, and the intrinsic capacitance values ​​of the 4 second capacitors are the same. In other possible implementations, the number of first capacitors and second capacitors can be greater, the intrinsic capacitance values ​​of multiple first capacitors can be the same or different, and the intrinsic capacitance values ​​of multiple second capacitors can be the same or different. In some embodiments, the MEMS acceleration unit can also include a wiring layer, and the multiple first capacitors in the first capacitor group can be connected in parallel through the wiring of the wiring layer, and the multiple first capacitors in the second capacitor group can be connected in parallel through the wiring of the wiring layer, and the first capacitor group and the second capacitor group can be connected in series through the wiring of the wiring layer.

[0103] In some possible implementations, the wiring layer may include a first wiring layer and a second wiring layer, and along the direction of the substrate 10 pointing to the piezoelectric unit 20, the multiple first capacitors and the multiple second capacitors each include a first electrode 21, a piezoelectric layer 23, and a second electrode 22 stacked in sequence. The first wiring layer is provided on the same layer as the first electrode 21, and the second wiring layer is provided on the same layer as the second electrode 22. The first wiring layer and the second wiring layer are electrically isolated from each other by the piezoelectric layer 23. Furthermore, the second electrodes of the multiple first capacitors are electrically connected to the detection circuit through the second wiring layer, and the first electrodes of the multiple second capacitors are electrically connected to the detection circuit through the first wiring layer, so that voltage or charge is input to the detection circuit through the second wiring layer.

[0104] In the MEMS acceleration unit, the relative positions of the plurality of first capacitors and the plurality of second capacitors are different, and the wiring arrangements of the wiring in the first wiring layer and the second wiring layer are different.

[0105] Optional, such as Figure 4a and Figure 9a As shown, along the Y direction, the two second capacitors are located between two adjacent first capacitors. For example, along the Y direction, the second capacitor B1 and the second capacitor B3 are located between the first capacitor A1 and the first capacitor A3, and the second capacitor B2 and the second capacitor B4 are located between the first capacitor A2 and the first capacitor A4.

[0106] Or, as Figure 8 As shown, along the Y direction, the first capacitor, the second capacitor, the first capacitor, and the second capacitor are arranged in sequence. For example, along the Y direction, the first capacitor A1, the second capacitor B1, the first capacitor A3, and the second capacitor B3 are arranged in sequence, and the first capacitor A2, the second capacitor B2, the first capacitor A4, and the second capacitor B4 are arranged in sequence.

[0107] In the first case, Figure 4a Taking the arrangement shown in the figure as an example, the routing of the traces in the first and second trace layers is introduced in detail:

[0108] like Figure 4b As shown in FIG. 1 , the first routing layer includes the first routing, the second routing, the third routing, the fourth routing, the fifth routing, and the sixth routing, and the second routing layer includes the seventh routing, the eighth routing, the ninth routing, the tenth routing, the eleventh routing, the twelfth routing, the thirteenth routing, the fourteenth routing, and the fifteenth routing. For ease of distinction, all routings in the figure are labeled with Arabic numerals. All routings in the first routing layer are thinner, and all routings in the second routing layer are thicker. Furthermore, those skilled in the art should know that Figure 4b This is a top view, so the second electrode can be seen, and the first electrode electrically connected to the first wiring layer is not shown below the second electrode.

[0109] The first electrode of first capacitor A1 is electrically connected to the first electrode of first capacitor A2 via the first routing line, and the second electrode of first capacitor A1 is electrically connected to the second electrode of first capacitor A2 via the seventh routing line. The first electrode of first capacitor A3 is electrically connected to the first electrode of first capacitor A1 via the second routing line, the tenth routing line, and the first routing line. The first electrode of first capacitor A4 is electrically connected to the first electrode of first capacitor A2 via the third routing line, the eleventh routing line, and the first routing line. The second electrode of first capacitor A3 is electrically connected to the second electrode of first capacitor A4 via the eighth routing line, and the seventh routing line is electrically connected to the eighth routing line via the ninth routing line. In this way, first capacitor A1, first capacitor A2, first capacitor A3, and first capacitor A4 are connected in parallel.

[0110] The first electrode of the second capacitor B1 is electrically connected to the first electrode of the second capacitor B3 via the fourth routing line, the tenth routing line is electrically connected to the second electrode of the second capacitor B1 via the twelfth routing line, and is electrically connected to the second electrode of the second capacitor B3 via the thirteenth routing line. The first electrode of the second capacitor B2 is electrically connected to the first electrode of the second capacitor B4 via the fifth routing line, the eleventh routing line is electrically connected to the second electrode of the second capacitor B2 via the fourteenth routing line, and is electrically connected to the second electrode of the second capacitor B4 via the fifteenth routing line. The first electrode of the second capacitor B3 is electrically connected to the first electrode of the second capacitor B4 via the sixth routing line, and the tenth routing line is connected to the eleventh routing line via the first routing line. In this way, the second capacitor B1, the second capacitor B2, the second capacitor B3, and the second capacitor B4 can be connected in parallel.

[0111] Moreover, since the tenth routing is electrically connected to the first capacitor A1 and the first capacitor A2 through the first routing, electrically connected to the first capacitor A3 through the second routing, electrically connected to the first capacitor A4 through the eleventh routing and the third routing, and is also electrically connected to the second capacitor B1 through the twelfth routing, electrically connected to the second capacitor B3 through the thirteenth routing, electrically connected to the second capacitor B2 through the eleventh routing and the fourteenth routing, and electrically connected to the second capacitor B4 through the eleventh routing and the fifteenth routing, the series connection of the first capacitor group and the second capacitor group is also realized.

[0112] In addition, in the case where the wiring of the first wiring layer is electrically connected to the wiring of the second wiring, the wiring of the first wiring layer can be electrically connected to the wiring of the second wiring through the via hole in the piezoelectric layer 23, that is, Figure 4b The black dots in the

[0113] In the second case, when the intrinsic capacitance values ​​of the plurality of first capacitors are the same and the intrinsic capacitance values ​​of the plurality of second capacitors are the same, Figure 9a and Figure 9b Taking the arrangement shown in the figure as an example, the routing of the traces in the first and second trace layers is introduced in detail:

[0114] like Figure 9a As shown in FIG. 1 , the first routing layer includes the first routing, the second routing, the third routing, and the fourth routing, and the second routing layer includes the fifth routing, the sixth routing, the seventh routing, the eighth routing, the ninth routing, the tenth routing, the eleventh routing, and the twelfth routing. For ease of distinction, all routings in the figure are labeled with Arabic numerals. All routings in the first routing layer are thinner, and all routings in the second routing layer are thicker. Furthermore, those skilled in the art should know that Figure 9a This is a top view, so the second electrode can be seen, and the first electrode electrically connected to the first wiring layer is not shown below the second electrode.

[0115] like Figure 9a As shown, the first electrode of the first capacitor A1 is electrically connected to the first electrode of the second capacitor B1 via a first wiring, thereby connecting the first capacitor A1 and the second capacitor B1 in series. The first electrode of the first capacitor A2 is electrically connected to the first electrode of the second capacitor B2 via a second wiring, thereby connecting the first capacitor A2 and the second capacitor B2 in series. The first electrode of the first capacitor A3 is electrically connected to the first electrode of the second capacitor B3 via a third wiring, thereby connecting the first capacitor A3 and the second capacitor B3 in series. The first electrode of the first capacitor A4 is electrically connected to the first electrode of the second capacitor B4 via a fourth wiring, thereby connecting the first capacitor A4 and the second capacitor B4 in series.

[0116] The ninth line is electrically connected to the second electrode of the first capacitor A1 through the fifth line, the ninth line is electrically connected to the second electrode of the first capacitor A2 through the sixth line, the ninth line is electrically connected to the second electrode of the first capacitor A3 through the seventh line, and the ninth line is electrically connected to the second electrode of the first capacitor A4 through the eighth line. The second capacitor B1 is electrically connected to the second capacitor B3 through the tenth line, the second capacitor B2 is electrically connected to the second capacitor B4 through the eleventh line, and the tenth line is also electrically connected to the eleventh line through the twelfth line. In this way, Figure 9c As shown, a first series branch of the first capacitor A1 and the second capacitor B1, a second series branch of the first capacitor A2 and the second capacitor B2, a third series branch of the first capacitor A3 and the second capacitor B3, and a fourth series branch of the first capacitor A4 and the second capacitor B4 are connected in parallel.

[0117] The reason why the first series branch, the second series branch, the third series branch, and the fourth series branch are formed first and then connected in parallel is because the intrinsic capacitance values ​​of the multiple first capacitors are the same, and the intrinsic capacitance values ​​of the multiple second capacitors are the same. Therefore, the connection node a1 between the first capacitor A1 and the second capacitor B1, the connection node a2 between the first capacitor A2 and the second capacitor B2, the connection node a3 between the first capacitor A3 and the second capacitor B3, and the connection node a4 between the first capacitor A4 and the second capacitor B4 are at the same potential.

[0118] Compared to Figure 4b The structure diagram shown uses Figure 9a , there is no need to form vias in the piezoelectric layer 23 so that part of the first wiring layer is electrically connected to part of the wiring of the second wiring layer.

[0119] Among some possible implementations, Figure 9a As shown, the voltage or charge of the first capacitor can be drawn out through the ninth trace. The voltage or charge of the second capacitor can be drawn out through the twelfth trace; or, as shown Figure 9b As shown, the second routing layer also includes a thirteenth routing line, and the size of the first capacitor A4 in the X direction is reduced (the first capacitor A2 and the first capacitor A4 still meet the symmetry condition), leaving an area on the side of the first capacitor A4 away from the first capacitor A3. The thirteenth routing line is located in this vacant area. The voltage or charge of the second capacitor is extracted through the thirteenth routing line.

[0120] In some embodiments, as Figure 2b As shown, in a group of cantilevers, the substrate 10 located on the same side of the first surface can be a whole layer that is not divided into multiple pieces. Alternatively, as shown in FIG. Figure 2a As shown, the substrate 10 may be divided into a plurality of first regions and a plurality of second regions separated by intervals. The first capacitor is located within the first region, and the second capacitor is located within the second region.

[0121] Compared with a solution in which the substrate 10 is not divided, the solution in which the substrate 10 is divided can reduce energy loss; compared with a solution in which the substrate 10 is divided, the solution in which the substrate 10 is not divided can simplify the preparation process.

[0122] In all the embodiments described above, a group of piezoelectric units 20 including multiple first capacitors and multiple second capacitors is used as an example for description. In other embodiments, a group of piezoelectric units 20 may also include more capacitors in addition to multiple first capacitors and multiple second capacitors. For example, a group of piezoelectric units also includes multiple third capacitors (C1, C2, C3, C4), and multiple third capacitors are connected in parallel to form a third capacitor group. Figure 10a and Figure 10b As shown, multiple third capacitors are connected in series or in parallel with the first capacitor group and the second capacitor group, respectively. In this way, the equivalent capacitance of the piezoelectric unit 20 can be adjusted by changing the series or parallel relationship of the multiple first capacitors, the multiple second capacitors, and the multiple third capacitors, thereby adjusting the sensitivity, noise, and signal-to-noise ratio of the MEMS accelerometer.

[0123] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A MEMS acceleration unit, characterized in that: It includes a substrate and at least one group of piezoelectric units stacked in sequence along the Z direction; A group of the piezoelectric units includes a plurality of first capacitors and a plurality of second capacitors; the plurality of first capacitors are connected in parallel to form a first capacitor group, the plurality of second capacitors are connected in parallel to form a second capacitor group, and the first capacitor group and the second capacitor group are connected in series; Along the X direction, any first capacitor has one first capacitor symmetrically about a first plane, and any second capacitor has one second capacitor symmetrically about the first plane; the first plane is a plane defined by the Z direction and the Y direction; wherein the X direction, the Y direction, and the Z direction are perpendicular to each other; Along the Y direction, any first capacitor has a first capacitor symmetrical about the second plane, and any second capacitor has a second capacitor symmetrical about the second plane; the second plane is a plane enclosed by the Z direction and the X direction.

2. The MEMS acceleration unit according to claim 1, wherein: The intrinsic capacitance value of the piezoelectric unit is greater than the sum of the first parasitic capacitance value, the second parasitic capacitance value, and the third parasitic capacitance value; the first parasitic capacitance value is the parasitic capacitance value in the piezoelectric unit, the second parasitic capacitance value is the parasitic capacitance value on the connection between the piezoelectric unit and the detection circuit, and the third parasitic capacitance value is the parasitic capacitance value in the detection circuit; The intrinsic capacitance of the piezoelectric unit is also less than Where K is the Boltzmann constant, T is the absolute temperature, η is the dielectric loss, f2 is the upper limit of the noise bandwidth, f1 is the lower limit of the noise bandwidth, and V nE represents the noise of the detection circuit; The detection circuit is used to detect the voltage or charge output by the MEMS acceleration unit.

3. The MEMS acceleration unit according to claim 2, characterized in that: An intrinsic capacitance value of the piezoelectric unit is greater than three times the sum of the first parasitic capacitance value, the second parasitic capacitance value, and the third parasitic capacitance value.

4. The MEMS acceleration unit according to any one of claims 1 to 3, characterized in that: The intrinsic capacitance values ​​of the plurality of first capacitors are all the same, and the intrinsic capacitance values ​​of the plurality of second capacitors are all the same.

5. The MEMS acceleration unit according to claim 4, characterized in that: The intrinsic capacitance value of the first capacitor and the intrinsic capacitance value of the second capacitor are the same; or, An intrinsic capacitance value of the first capacitor is different from an intrinsic capacitance value of the second capacitor.

6. The MEMS acceleration unit according to any one of claims 1 to 5, characterized in that: Along the Y direction, two of the second capacitors are located between two adjacent first capacitors; or, Along the Y direction, the first capacitor, the second capacitor, the first capacitor, and the second capacitor are arranged in sequence.

7. The MEMS acceleration unit according to any one of claims 1 to 6, characterized in that: The MEMS acceleration unit further includes a first wiring layer and a second wiring layer; Along the direction from the substrate to the piezoelectric unit, the plurality of first capacitors and the plurality of second capacitors each include a first electrode, a piezoelectric layer, and a second electrode stacked in sequence; The first wiring layer is provided on the same layer as the first electrode, the second wiring layer is provided on the same layer as the second electrode, and the first wiring layer and the second wiring layer are electrically isolated from each other by the piezoelectric layer; The second electrodes of the plurality of first capacitors are electrically connected to the detection circuit through the second routing layer, and the first electrodes of the plurality of second capacitors are electrically connected to the detection circuit through the first routing layer.

8. The MEMS acceleration unit according to any one of claims 1 to 7, characterized in that: The substrate is divided into a plurality of spaced first regions and a plurality of spaced second regions. The first capacitors are located within the first regions, and the second capacitors are located within the second regions.

9. The MEMS acceleration unit according to any one of claims 1 to 5, characterized in that: A group of the piezoelectric units further includes a plurality of third capacitors, which are connected in parallel to form a third capacitor group, and the plurality of third capacitors are respectively connected in series or in series with the first capacitor group and the second capacitor group.

10. A MEMS accelerometer chip, characterized in that: The device comprises a housing, an application integrated circuit, a circuit board, and the MEMS acceleration unit according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The device comprises a detection circuit and the MEMS accelerometer chip according to claim 10, wherein the detection circuit is used to detect the voltage or charge output by the MEMS acceleration unit in the MEMS accelerometer chip.

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