Power supply network via

Abstract

The invention relates to a power supply network via. A power supply network includes a first array of vias arranged on a particular plane of the power supply network to form a particular shape on the particular plane. The power supply network further includes a second array of vias, wherein at least one via in the second array of vias is arranged at a location within the particular shape on the particular plane.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to electronic systems, and more particularly, to power delivery network (PDN) vias. Background Art

[0002] Electronic devices, such as application specific integrated circuits (ASICs) and / or memory devices, rely on power management for reliable operation. The delivery of power within these electronic devices is an important factor affecting the overall performance of the electronic devices. Summary of the Invention

[0003] In one aspect, the present disclosure provides a power supply network for reduced loop inductance, comprising: a first through-hole array arranged on a specific plane of the power supply network to form a specific shape on the specific plane; and a second through-hole array, wherein at least one through-hole in the second through-hole array is arranged at a position within the specific shape on the specific plane.

[0004] In another aspect, the present disclosure provides a power supply network for reduced loop inductance, comprising: a first power via array arranged on a specific plane of the power supply network to form a first shape on the specific plane; and a first ground via array arranged on the specific plane of the power supply network, wherein a first ground via in the ground via array is arranged at a position within the first shape on the specific plane, and wherein the remaining ground vias in the ground via array are arranged at corresponding positions outside the first shape on the specific plane.

[0005] In another aspect, the present disclosure provides a system for reducing loop inductance, comprising: an array of power vias arranged on a power plane to form a specific shape on the power plane; and a plurality of ground via arrays, wherein at least one of the plurality of ground via arrays is arranged adjacent to the power via array on the power plane, wherein at least one ground via in at least one of the plurality of ground via arrays is arranged at a position within the specific shape on the power plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example electronic system including a power supply network is shown according to some embodiments of the present disclosure.

[0008] Figure 2A is a three-dimensional view of a portion of a power delivery network including power vias and ground vias arranged on a power plane and a ground plane according to some embodiments of the present disclosure.

[0009] Figure 2B is a top view of a portion of an example power delivery network including power and ground vias arranged on a power plane and a ground plane, according to some embodiments of the present disclosure.

[0010] Figure 3 is a top view of a portion of another example power delivery network including power vias and ground vias arranged on a power plane and a ground plane according to some embodiments of the present disclosure.

[0011] Figure 4 is a top view of a portion of another example power delivery network including power vias and ground vias arranged on a power plane and a ground plane according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Various aspects of the present disclosure relate to power delivery network (PDN) vias. As used herein, the term "PDN" refers to a system of components that deliver power from a power source to a load. A PDN can be a critical component in an electronic system designed to efficiently supply power to various components on a printed circuit board (PCB). A PDN comprises a network of power and ground planes, conductive traces, decoupling capacitors, and other elements strategically arranged to distribute power across the various components of a PCB.

[0013] The PDN can be a multi-layer PDN, which can include inner and outer layers. The outer layers can include top and bottom layers, on which components and signal traces can be located. For example, the main components can be located on the top layer, while additional components can be located on the bottom layer. The inner layers are located between the two outer (e.g., top and bottom) layers and can include power planes and ground planes. The inner layers can be composed of one inner layer (e.g., a "core layer") and additional inner layers (for multi-layer PCBs). The power plane distributes voltage to the components, while the ground plane provides a return path for current, helping to maintain a stable ground reference.

[0014] A plurality of vias (e.g., power vias, ground vias, etc.) may be located within one or more inner layers (e.g., between a power plane and a ground plane) to allow electrical signals to pass through different layers of a PDN (e.g., associated with power delivery). As used herein, the term "power via" refers to a via that serves as a path for delivering power from a power source (e.g., a power plane in a PCB) to components that require power. Additionally, as used herein, the term "ground via" refers to a via that serves as a conductive path for connecting different layers of a PCB to establish a stable ground reference. The height of the vias (e.g., power vias, ground vias, etc.) may affect and / or be a major portion of the thickness of the inner layer, which may be as thick as the required thickness of the PCB in the controller package.

[0015] It may be desirable to design the PDN structure in a way that reduces loop inductance. Loop inductance is a characteristic of the PDN that contributes to the overall impedance of the structure. Reduced inductance and resistance of the power supply path can help maintain signal integrity by preventing voltage drops and reducing noise, which improves the performance and power efficiency of the system. However, some approaches often adopt increased core thickness (e.g., the thickness of the inner layer, which may be generally proportional to the height of the through-holes of the PDN as mentioned above) in pursuit of improved manufacturability, which inevitably introduces higher loop inductance and increased susceptibility to noise interference. In addition, when the route for delivering power to the printed circuit board (PCB) becomes longer due to the increased core thickness, it can affect the stability of the transmitted voltage and reduce the speed of voltage transfer.

[0016] Aspects of the present disclosure address the above and other drawbacks by providing reduced loop inductance without further reducing core thickness. For example, compared to existing approaches, embodiments of the present disclosure provide closer proximity (e.g., reduced spacing distance) between ground vias and power vias. By placing the ground vias close to the power vias, the return current path can be kept short and close to the path of the output current. This reduces the loop area, which is critical for reducing electromagnetic interference (EMI) and maintaining a low impedance profile, which helps maintain stable voltage levels and reduces the effects of noise and other interference.

[0017] Figure 1 An example electronic system 100 including a power supply network 110 according to some embodiments of the present disclosure is shown. For clarity, the electronic system 100 has been simplified to focus on features that are particularly relevant to the present disclosure.

[0018] The electronic system 100 may be, for example, a desktop computer, a laptop computer, a television, a home theater system, a game console, a digital camera, a network router and / or switch, a printer, a scanner, a medical device, a GPS navigation device, a home device (e.g., a thermostat, a doorbell camera, a security camera, a smart lock, etc.), a wearable device, an industrial control system (e.g., an automated industrial and / or control device), a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., included in a vehicle, industrial equipment, or a networked commercial device), a system on a chip (SoC), a chipset (e.g., a collection of integrated circuits), a tile, a field programmable gate array (FPGA) structure (e.g., a segmented FPGA structure), or other such devices, or may be part of any of the above.

[0019] The electronic system 100 may include a power delivery network (PDN) 110. As used herein, the term "power delivery network" may refer to a network of components and structures designed to deliver power from a power source (e.g., voltage regulator, power supply, etc.) to various electronic components (e.g., electronic component 115). Although not specifically described herein, the power delivery network may include a plurality of power supply components, such as a power supply, a power supply, and a power supply. Figure 1 Although not specifically shown in FIG, PDN 110 may be distributed over multiple layers of a printed circuit board (PCB).

[0020] although Figure 1 , a single electronic component 115 is shown in FIG. 1 , but the PDN 110 of the system 100 may be coupled to a plurality of electronic components 115, which may include various electronic circuits, devices, and the like, such as integrated circuits (ICs), transistors, diodes, resistors, capacitors, inductors, connectors, switches, sensors, memory devices, voltage regulators, power management ICs, light-emitting diodes, crystal oscillators, radio frequency (RF) modules, and the like; although the embodiments are not limited thereto. The electronic component 115 may also be a memory device, which may include: a volatile memory device, such as (but not limited to) a random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM); or a non-volatile memory, such as NAND flash memory, read-only memory (ROM), phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM). In various embodiments, the electronic component 115 may be located (e.g., mounted) on the same PCB on which the PDN 110 is distributed.

[0021] Although the embodiments are not limited in this regard, in some embodiments, the electronic system 100 may be a controller package, such as an application-specific integrated circuit (ASIC) package (e.g., an 8-layer package) having a PDN (e.g., PDN 110) to supply power to various components of the controller package, such as logic gates, memory cells, timing components, input / output circuits, signal circuits, a power management unit, control circuits (e.g., an ASIC), sensors, etc.

[0022] Although not in Figure 1Although not specifically depicted in FIG, PDN 110 may be a multi-layer PDN that may include an outer layer (e.g., including a top and a bottom layer) and an inner layer located between the two outer layers. Although embodiments are not limited thereto, memory component 115 may be located on an outer layer (e.g., a top and / or bottom layer) of PDN 110.

[0023] Internal layers may be composed of multiple planes, such as power planes (e.g., power planes 230 and 330 shown in Figures 2 and 3 , respectively), ground planes (e.g., ground planes 240 and 340 shown in Figures 2 and 3 , respectively), and the like. These multiple planes of the internal layers may typically be coupled by vias, such as ground vias 122-1, ..., 122-N (collectively, "ground vias 122"), power vias 124-1, ..., 124-M (collectively, "power vias 124"), and the like. These two different types of vias (power vias 124 and ground vias 122) may form a circulating current path (a path for current traveling from a source and returning to its origin), thereby further forming a loop area (e.g., an enclosed area corresponding to the circulating current path). In various embodiments, ground vias 122 and power vias 124 may be arranged on the ground plane or the power plane in a manner that reduces the loop area and further reduces the loop inductance. Further details of the arrangement are shown and described in conjunction with Figures 2 to 4.

[0024] Figure 2A is a three-dimensional view of a portion of a power delivery network including power and ground vias arranged (eg, at various locations) on a power plane and a ground plane according to some embodiments of the present disclosure. Figure 2A The PDN 210 shown in FIG. 2 may be similar to Figure 1 PDN 110.

[0025] The PDN 210 may include a plurality of through-holes that may have different types of through-holes. Figure 2A As shown in FIG. 2 , the PDN 210 includes ground vias 222 - 2 - 1 , 222 - 2 - 2 , 222 - 2 - 3 and 222 - 2 - 4 (collectively referred to as ground vias 222 - 2 ). Figure 2B and power vias 224-1, 224-2, and 224-3 (collectively referred to as power vias 224) and ground vias 222-1-1, 222-1-2, 222-1-3, and 222-1-4 (collectively referred to as ground vias 222-1), for example, Figure 2B As used herein, the term "region" refers to a specific functional or operational area (e.g., on a specific plane, such as power plane 230 or ground plane 240) on which a corresponding via array (e.g., the array of ground vias 222-1 and 222-2 or the array of power vias 224) is arranged. Figure 2A The PDN 210 is not shown in its entirety. For example, the PDN 210 may further include Figure 2A Ball grid array (BGA) pads, solder bumps (alternatively referred to as "BGA balls"), etc., not shown in FIG. Figure 2A 210).

[0026] like Figure 2A As shown in FIG, the PDN 210 includes at least two different planes, such as a power plane 230 and a ground plane 240. Figure 2A , the power via 224 is arranged on (e.g., coupled to) the power plane 230 at one end and on the ground plane 240 at the other end, while the ground via 222 is arranged on (e.g., coupled to) the ground plane 240 at one end and on the power plane 230 at the other end. More specifically, the arrays of ground vias 222-1 and 222-2 are respectively arranged on openings on the power plane 230. For example, Figure 2A , the array of ground vias 222-1 is arranged within an opening 230-1 formed on the power plane 230, while the array of ground vias 222-2 is arranged within an opening 230-2 formed on the power plane 230. Similarly, each power via in the array of power vias 224-1, 224-2, and 224-3 is arranged over a corresponding opening 240-1, 240-2, and 240-3 formed on the ground plane 240.

[0027] like Figure 2A As shown in FIG. 1 , the array of power vias 224 is positioned adjacent to the array of ground vias 222 (eg, at least Figure 2B 2), and the array of ground vias 222-1 (e.g., in Figure 2B 225 ). Positioning power vias (e.g., power vias 224) adjacent to ground vias (e.g., ground vias 222) can provide benefits such as reduced loop inductance without increasing core thickness. For example, the close proximity between the ground vias and the power vias allows the return current path (current flowing back to ground) to be close to the path of the output current, thereby reducing the loop area. This reduced loop area reduces loop inductance, which helps maintain stable voltage levels and reduces the effects of noise and other interference. Furthermore, the reduced loop inductance due to the reduced loop area eliminates the need to increase the number of power vias (to enhance power delivery), thereby avoiding the potential risk of increased noise interference due to an increased number of power vias.

[0028] At the same time, increasing the number of ground vias on a PDN (e.g., PDN 210) can help reduce the overall resistance of the PDN. For example, the ground vias each provide a parallel path for return current flow. This parallelization of the paths can help reduce the overall resistance of the PDN, which is desirable for efficient power delivery, particularly in high-speed and high-frequency electronic designs.

[0029] Figure 2B is a top view of a portion of an example power delivery network 210 including power and ground vias arranged (eg, at various locations) on a power plane and a ground plane, according to some embodiments of the present disclosure. Figure 2B The power supply network 210 shown in FIG. Figure 2A For example, Figure 2B The power vias 224-1, 224-2, and 224-3 shown in FIG. Figure 2A The power through holes 224-1, 224-2 and 224-3 shown in FIG; Figure 2B The ground vias 222-2-1, 222-2-2, 222-2-3, and 222-2-4 shown in FIG. Figure 2A The ground vias 222-2-1, 222-2-2, 222-2-3 and 222-2-4 shown in FIG; and Figure 2B The ground vias 222-1-1, 222-1-2, 222-1-3, and 222-1-4 shown in FIG. Figure 2A . Furthermore, the ground vias 222 and / or power vias 224 on each region may be formed on the same BGA ball, but the embodiment is not limited thereto. For example, the ground via 222-1 may be formed on one BGA ball, while the ground via 222-2 and power via 224 may be formed on another BGA ball.

[0030] The array of power vias 224 (e.g., power vias 224-1, 224-2, and 224-3) on region 212-2 is arranged at various locations on power plane 230 to form a closed shape (alternatively referred to as a "perimeter"), such as Figure 2BAs used herein, the term "closed shape" refers to a shape in which the constituent endpoints form a continuous and uninterrupted boundary, thereby allowing the closed shape to have a region. The triangular shape 225 has power vias 224-1, 224-2, and 224-3 as respective vertices. The array of ground vias 222 on region 212-2 is further arranged on the power plane 230 to form an open shape. As used herein, the term "open shape" refers to a shape with distinct endpoints that are not connected to form a complete boundary (and thus do not form a closed loop). Although Figure 2B Three power vias 224 are shown on region 212 - 2 , but embodiments are not limited to a specific number of power vias that may be positioned adjacent to ground vias. Additionally, embodiments are not limited to a specific number of ground vias, and power vias may be adjacent to the ground vias within the region.

[0031] like Figure 2B , at least one of the ground vias 222 (e.g., ground via 222-2-2) is located within (e.g., arranged at) a position within the triangular shape 225 formed by the array of power vias 224. In other words, the via 222-2-2 is located within a perimeter corresponding to the triangular shape 225. In some embodiments, the ground via 222-2-2 may be located approximately at the center of the triangular shape 225.

[0032] like Figure 2B , the array of power vias 224 is positioned adjacent to the array of ground vias 222-2 at least at region 212-2. As an example, the spacing between ground via 222-2-2 and power via 224-1 (alternatively referred to as "core via spacing") may be 175 micrometers (μm), while the spacing between ground via 222-2-4 and power via 224-2 may be 182 μm. However, embodiments are not limited in this regard, as the spacing between power vias 224 and ground vias 222 may be dictated by substrate space / trace requirements. For example, thicker core material and / or thicker copper may require greater spacing than thinner core material and thinner copper.

[0033] The array of power vias 224 positioned adjacent to the array of ground vias 222-2 allows the two shapes formed by the array of power vias 224 and the array of ground vias 222, respectively, to overlap with each other, with at least one line segment of one shape intersecting with a line segment of the other shape. For example, a (e.g., drawn) line segment between the ground via 222-2-2 and any one of the ground vias 222-2-1, 222-2-3, and 222-2-4 intersects (e.g., crosses or passes through) the shape formed by the array of power vias 224. In other words, a line segment between two endpoints (e.g., power vias 224-1 and 224-2) (e.g., corresponding to one of the sides of the triangular shape 225) intersects a line segment 223-2 between two endpoints (e.g., ground vias 222-2-2 and 222-2-3), a line segment between two endpoints (e.g., power vias 224-2 and 224-3) (e.g., corresponding to one of the sides of the triangular shape 225) intersects a line segment 223-3 between two endpoints (e.g., ground vias 222-2-2 and 222-2-4), and a line segment between two points (e.g., power vias 224-1 and 224-3) (e.g., corresponding to one of the sides of the triangular shape 225) intersects a line segment 223-1 between two endpoints (e.g., ground vias 222-2-1 and 222-2-2).

[0034] The placement of the power via 224 relative to the ground via 222-2 can reduce loop inductance compared to previous approaches that do not employ close proximity between the power via and the ground via. As an example, compared to previous approaches, Figure 2B The close proximity of the power and ground vias shown in FIG can reduce the loop inductance by 16% (when the core thickness is 200 μm) to 33% (when the core thickness is 800 μm). For example, when the core thickness is increased by the same amount, the loop inductance of the previous method is reduced by 16%. Figure 2B The arrangement of the PDN depicted in FIG may exhibit approximately one-third the loop inductance.

[0035] Figure 3 FIG. 3 is a top view of a portion of another example power supply network 310 including power vias and ground vias arranged on a power plane and a ground plane according to some embodiments of the present disclosure. Figure 3 A specific number of power and ground vias are depicted in each zone (e.g., zones 312-1-1, 312-1-2, 312-2-1, and 312-2-2), but embodiments are not limited to a specific number of power and ground vias in each zone. Although embodiments are not limited in this regard, Figure 3 The inner layer (eg, core layer) of the example power supply network 310 shown in FIG. 3 may be 400 um.

[0036] The power supply network 310 is generally similar to Figure 2B The power supply network 210 shown in FIG. 2 includes a power supply network similar to Figure 2B For example, similar to the areas 212-1 and 212-2 shown in FIG. Figure 2B The regions 212-1, 312-1-1 and 312-1-2 may include only ground vias, while the two regions 312-2-1 and 312-2-2 may each be similar to Figure 2A and 2B The area 212-2 shown in FIG. Figure 3 As shown in FIG. 1 , the array of power vias 324 - 1 , 324 - 2 , and 324 - 3 (eg, on region 312 - 2 - 1 ) is arranged in a manner similar to that shown in FIG. Figure 2B 2, 222-3, and 222-4 are arranged adjacent to the corresponding arrays of ground vias 322-1, 322-2, 322-3, and 322-4 in a similar manner as shown in FIG.

[0037] Figure 4 FIG. 4 is a top view of a portion of another example power supply network 410 including power vias and ground vias arranged on a power plane and a ground plane according to some embodiments of the present disclosure. Figure 4 A specific number of power and ground vias are depicted in each zone (eg, zones 412-1-1, 412-1-2, 412-1-3, 412-1-4, 412-2-1, 412-2-2, 412-2-3, and 412-2-4), but embodiments are not limited to a specific number of power and ground vias in each zone.

[0038] The power supply network 410 is generally similar to Figure 2B The power supply network 210 shown in FIG. 2 includes a power supply network similar to Figure 2B For example, similar to the areas 212-1 and 212-2 shown in FIG. Figure 2B 2, the four regions 412-1-1, 412-1-2, 412-1-3, and 412-1-4 may include only ground vias, while the four regions 412-2-1, 412-2-2, 412-2-3, and 412-2-4 may each be similar to Figure 2B The area 212-2 shown in FIG. Figure 4 As shown in FIG. 1 , the array of power vias 424-1, 424-2, and 424-3 (eg, on region 412-2-1) is arranged in a manner similar to that shown in FIG. Figure 2B4. The power vias 224-1, 224-2, and 224-3 are arranged adjacent to the corresponding arrays of ground vias 422-1, 422-2, 422-3, and 422-4 in a similar manner as shown in FIG.

[0039] The arrangement of the power vias 224, 324, and / or 424 relative to the ground vias 222 (e.g., 222-1), 322, and / or 422 can reduce loop inductance compared to previous approaches that do not employ close proximity between the power vias and the ground vias. As an example, assuming a core thickness of 400 μm, compared to previous approaches, Figure 2B 、 3 The close proximity of the power vias and ground vias illustrated in Figures 4 and 5 can reduce loop inductance by 23%, 11%, and 5%, respectively. The arrangement of power vias 224, 324, and / or 424 relative to ground vias 222 (e.g., 222-1), 322, and / or 422 can be substantially beneficial in areas with limited pins, such as phase-locked loops (PLLs), and vias arranged according to various embodiments of the present disclosure can significantly reduce loop inductance (e.g., especially when placed near a memory die).

[0040] Some portions of the previously described description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means for those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0041] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0042] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0043] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. Structures for a variety of these systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0044] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, or the like.

[0045] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A power supply network (110; 210; 310; 410) for reduced loop inductance, comprising: First through hole array (124-1, ..., 124-M; 224-1, 224-2, 224-3; 324-1, 324-2, 324-3; 424 - 1 , 424 - 2 , 424 - 3 ), which are arranged at a specific plane ( 230 , 240 ; 330 , 340 ;) of the power supply network. 430, 440) to form a specific shape (225) on the specific plane; and a second through-hole array (122-1, ..., 122-N; 222-1-1, 222-1-2, 222-1-3, 222-1-4, 222-2-1, 222-2-2, 222-2-3, 222-2-4; 322-1, 322-2, 322-3, 322-4), wherein at least one through-hole in the second through-hole array is arranged at a position within the specific shape on the specific plane. 2 . The power supply network according to claim 1 , wherein the specific shape corresponds to a triangular shape having positions on the specific plane on which the first through-hole array is arranged as respective vertices of the specific shape. 3 . The power supply network according to claim 2 , wherein the at least one through-hole in the second through-hole array is arranged at a position corresponding to a center of the specific shape on the specific plane.

4. The power supply network according to any one of claims 1 to 3, wherein other through-holes (222-2-1, 222-2-3, 222-2-4; 322-2) in the second through-hole array are arranged at corresponding positions outside the specific shape on the specific plane.

5. The power supply network according to claim 4, wherein: A line segment (223-1, 223-2, 223-3) with a specific position on the specific plane as two corresponding endpoints intersects at least one side of the specific shape on the specific plane, wherein the specific position corresponds to a corresponding position on the specific plane where at least one through hole in the second through hole array and one of the other through holes in the second through hole array are arranged.

6. The power supply network according to any one of claims 1 to 3, further comprising additional second through-hole arrays (222-1-1, 222-1-2, 222-1-3, 222-1-4) arranged at corresponding positions outside the specific shape on the specific plane.

7. A power supply network (110; 210; 310; 410) for reduced loop inductance, comprising: First power via array (124-1, ..., 124-M; 224-1, 224-2, 224-3; 324-1, 324-2, 324-3; 424 - 1 , 424 - 2 , 424 - 3 ), which are arranged at a specific plane ( 230 , 240 ; 330 , 340 ;) of the power supply network. 430, 440) to form a first shape (225) on the specific plane; and A first ground via array (122-1, ..., 122-N; 222-1-1, 222-1-2, 222-1-3, 222-1-4, 222-2-1, 222-2-2, 222-2-3, 222-2-4; 322-1, 322-2, 322-3, 322-4) is arranged on the specific plane of the power supply network, wherein a first ground via (222-2-1) in the ground via array is arranged at a position within the first shape on the specific plane, and wherein the remaining ground vias (222-2-1, 222-2-3, 222-2-4; 322-2) in the ground via array are arranged at corresponding positions outside the first shape on the specific plane.

8. The power supply network according to claim 7, wherein: The first ground via array is arranged on the specific plane to form a second shape on the specific plane, wherein the second shape corresponds to an open shape having positions on the specific plane on which the ground vias in the first ground via array are arranged as respective endpoints. 9 . The power supply network according to claim 7 , wherein the remaining ground vias are arranged on the specific plane to form a specific closed shape having respective positions as end points of the specific closed shape.

10. The power supply network according to any one of claims 7 to 8, further comprising: Second power via array (124-1, ..., 124-M; 224-1, 224-2, 224-3; 324-1, 324-2, 324-3; 424-1, 424-2, 424-3), which are arranged on the specific plane to form a second shape (225) on the specific plane; and a second ground via array (122-1, ..., 122-N; 222-1-1, 222-1-2, 222-1-3, 222-1-4, 222-2-1, 222-2-2, 222-2-3, 222-2-4; 322-1, 322-2, 322-3, 322-4) arranged on the specific plane, wherein at least one ground via (222-2-1) in the second ground via array is arranged at a position within the second shape on the specific plane.

11. The power supply network according to claim 10, wherein: The second shape is located outside the first shape on the specific plane; and Line segments ( 223 - 1 , 223 - 2 , 223 - 3 ) having positions where two ground vias in the second ground via array are arranged as respective endpoints do not intersect the first shape. 12 . The power supply network according to claim 10 , wherein the ground vias in the second ground via array are arranged at corresponding positions outside the first shape on the specific plane.

13. The power supply network according to any one of claims 7 to 8, wherein the first shape corresponds to a closed shape.

14. A system for reduced loop inductance, comprising: Power via arrays (122-1, ..., 122-N; 222-1-1, 222-1-2, 222-1-3, 222-1-4, 222-2-1, 222-2-2, 222-2-3, 222-2-4; 322-1, 322-2, 322-3, 322-4) arranged on a power plane (230; 330; 430) to form a specific shape on the power plane; and a plurality of ground via arrays (124-1, ..., 124-M; 224-1, 224-2, 224-3; 324-1, 324-2, 324-3; 424-1, 424-2, 424-3), wherein at least one of the plurality of ground via arrays is arranged adjacent to the power via array on the power plane, wherein at least one ground via (222-2-1) in the at least one of the plurality of ground via arrays is arranged at a position within the specific shape on the power plane.

15. The system of claim 14, wherein: At least one of the multiple ground via arrays is arranged adjacent to the power via array, so that a first line segment with two positions on the power plane on which two power vias in the power via array are arranged as corresponding endpoints intersects with a second line segment (223-1, 223-2, 223-3) with two positions on the power plane on which two ground vias in the at least one of the multiple ground via arrays are arranged as corresponding endpoints.

16. The system of claim 15, wherein: The at least one of the plurality of ground via arrays is disposed within an opening formed in the power plane; and The second line segment intersects the opening formed on the power plane at least at two points.

17. The system of claim 14, wherein the at least one array of the plurality of ground via arrays is arranged on the power plane to form an open shape having positions where the ground vias (222-2-1, 222-2-3, 222-2-4; 322-1, 322-3, 322-4) in the at least one array are arranged as corresponding endpoints.

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