Pre-decoding processing method and device, storage medium, electronic device and computer program product

Abstract

The embodiment of the invention provides a pre-decoding processing method and device, a storage medium, an electronic device and a computer program product, and the method comprises the steps: carrying out the mode recognition decoding of a fetched non-alignment instruction in a pre-decoding process of a current period, and obtaining a mode recognition decoding result; static branch prediction is carried out on the non-aligned instruction according to the mode recognition decoding result, a branch prediction result is obtained, the branch prediction result is used for indicating instruction fetching of the non-aligned instruction of the next period, the problem that in the related technology, due to high decoding complexity, timing limitation is caused, and the operation frequency of a processor is limited can be solved, and the processing efficiency of the non-aligned instruction is improved. According to the method, the processing efficiency of the pre-decoding stage is improved, especially when non-aligned instructions are processed, the instruction fetching positions of the instructions can be predicted more accurately, the waiting time of a processor is shortened, and therefore the overall performance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of base station energy saving, and specifically, to a pre-decoding processing method, device, storage medium, electronic device and computer program product. Background Art

[0002] In the field of processor pipeline design, to improve the processor's instruction execution efficiency and pipeline throughput, existing technologies typically perform pre-decoding during the instruction fetch stage. This pre-decoding technology allows the processor to perform preliminary parsing of instructions immediately after fetching them from memory, thereby reducing the workload of the instruction decoding stage, reducing the complexity of the decoder, and reducing decoding latency. Furthermore, pre-decoding allows subsequent stages in the pipeline (such as the execution stage) to obtain instruction information more quickly, reducing pipeline stalls caused by decoding. Pre-decoding can also be combined with branch prediction mechanisms to parse branch instructions in advance, thereby improving the accuracy of branch predictions and reducing the performance loss caused by branch mispredictions. Pre-decoding can also provide the necessary information for out-of-order execution, allowing the processor to make scheduling decisions earlier and improve the efficiency of out-of-order execution.

[0003] Current pre-decoding techniques may not be able to effectively handle certain instruction types or operations, or may not provide enough information to support certain advanced processor features. High decoding complexity leads to timing limitations that restrict processor operating frequency.

[0004] Regarding the problem in related technologies where high decoding complexity leads to timing limitations that restrict the operating frequency of the processor, no solution has yet been proposed. Summary of the Invention

[0005] The embodiments of the present application provide a pre-decoding processing method, apparatus, storage medium, electronic device, and computer program product to at least solve the problem in the related art that high decoding complexity leads to timing limitations that limit the processor operating frequency.

[0006] According to one embodiment of the present application, a pre-decoding processing method is provided, the method comprising:

[0007] In the pre-decoding process of the current cycle, pattern recognition decoding is performed on the non-aligned instruction fetched to obtain a pattern recognition decoding result;

[0008] Static branch prediction is performed on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the instruction fetch of the non-aligned instruction in the next cycle.

[0009] According to another embodiment of the present application, a pre-decoding processing device is provided, including:

[0010] A pre-decoding module is used to perform pattern recognition decoding on the non-aligned instruction fetched during the pre-decoding process of the current cycle to obtain a pattern recognition decoding result;

[0011] A static branch prediction module is used to perform static branch prediction on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the fetch of the non-aligned instruction in the next cycle.

[0012] According to another embodiment of the present application, a computer program product is provided, including computer program instructions, wherein the computer program instructions enable a computer to implement the steps in any of the above method embodiments.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0015] In an embodiment of the present application, during the pre-decoding process of the current cycle, pattern recognition decoding is performed on the non-aligned instruction for instruction fetch to obtain a pattern recognition decoding result; static branch prediction is performed on the non-aligned instruction based on the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the instruction fetch of the non-aligned instruction in the next cycle, which can solve the problem in the related art that the high decoding complexity leads to timing limitations and thus limits the operating frequency of the processor, and improves the processing efficiency of the pre-decoding stage. In particular, when processing non-aligned instructions, it can more accurately predict the instruction fetch position, reduce the waiting time of the processor, and thus improve the overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a hardware structure block diagram of a computer device for the pre-decoding processing method according to an embodiment of the present application;

[0017] Figure 2 is a flowchart of a pre-decoding processing method according to an embodiment of the present application;

[0018] Figure 3 This is the process of the pre-decoding processing method according to the optional embodiment of the present application Figure 1 ;

[0019] Figure 4This is the process of the pre-decoding processing method according to the optional embodiment of the present application Figure 2 ;

[0020] Figure 5 is a schematic diagram of a decoding pipeline according to an embodiment of the present application;

[0021] Figure 6 is a schematic diagram of pre-decoding according to an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of the structure of pre-decoding according to an embodiment of the present application;

[0023] Figure 8 is a schematic diagram of the structure of the combined instruction in the pre-decoding according to an embodiment of the present application;

[0024] Figure 9 is a schematic diagram of a programming model according to an embodiment of the present application;

[0025] Figure 10 is a schematic diagram of instruction type identification according to an embodiment of the present application;

[0026] Figure 11 is a schematic diagram of pre-decoding result selection according to an embodiment of the present application;

[0027] Figure 12 is a schematic diagram of pre-decoding result information according to an embodiment of the present application;

[0028] Figure 13 is a schematic diagram of static prediction information according to an embodiment of the present application;

[0029] Figure 14 is a flowchart of a pre-decoding process according to an embodiment of the present application;

[0030] Figure 15 4 is a block diagram of a pre-decoding processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0033] The method embodiments provided in the embodiments of the present application can be executed in a computer device or similar computing device. Taking running on a computer device as an example, Figure 1 This is a hardware structure block diagram of a computer device for the pre-decoding processing method according to an embodiment of the present application. Figure 1As shown, the computer device may include one or more ( Figure 1 Only one is shown) a processor 102 (the processor 102 may include but is not limited to a microprocessor MCU or a processing device such as a programmable logic device) and a memory 104 for storing data. The computer device may also include a transmission device 106 and an input / output device 108 for communication functions. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer device. For example, the computer device may also include Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0034] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the pre-decoding processing method in the embodiment of the present application. The processor 102 executes various functional applications and single-board matching by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0035] The transmission device 106 is used to receive or send data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer device. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0036] In this embodiment, a pre-decoding processing method running on the above-mentioned computer device is provided. Figure 2 is a flowchart of a pre-decoding processing method according to an embodiment of the present application. Figure 2 As shown, the process includes the following steps:

[0037] Step S202, in the pre-decoding process of the current cycle, pattern recognition decoding is performed on the non-aligned instruction fetched to obtain a pattern recognition decoding result;

[0038] Step S204 , performing static branch prediction on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the fetch of the non-aligned instruction in the next cycle.

[0039] Through the above steps S202 to S204, the problem in the related art that the high decoding complexity leads to timing limitations that limit the processor operating frequency can be solved, and the processing efficiency of the pre-decoding stage is improved. In particular, when processing non-aligned instructions, the instruction fetch location can be more accurately predicted, reducing the processor's waiting time, thereby improving overall performance.

[0040] The pre-decoding technology for pattern recognition of combined instructions pre-decodes the combined instructions, which can obtain the pattern recognition decoding results from the instructions themselves in advance for branch instruction target address calculation. This allows for early target address recognition and enables branch switching at the early stage of the pipeline. For example, the pre-decoding of the "auipc+jalr" combined instruction can be implemented. Application scenarios of the embodiments of this application include high-performance computing, data center servers, graphics processing units, and other scenarios that require efficient instruction processing.

[0041] Figure 3 This is the process of the pre-decoding processing method according to the optional embodiment of the present application Figure 1 ,like Figure 3 As shown, the method further includes:

[0042] In step S302, during the pre-decoding process of the current cycle, vector recognition decoding is performed on the unaligned instruction to obtain a vector recognition decoding result. This vector recognition decoding result is directly used to decode the unaligned instruction. The vector recognition decoding result does not need to be stored in the cache, enabling accurate pre-decoding without consuming many resources, thereby effectively improving processor performance. Through vector recognition pre-decoding, the processor can more efficiently process instructions during the decoding phase, improving performance in applications requiring extensive vector operations, such as scientific computing and image processing.

[0043] Step S302 is performed in parallel with step S202. Pre-decoding technology for vector instructions addresses the dynamic variations in element widths across different vector instructions. By obtaining vector instruction configuration information earlier in the predecode phase, the configuration information is obtained early in the pipeline to guide decoding. This avoids processor performance degradation caused by decoding after obtaining the configuration information in later pipeline stages. This is particularly relevant for pre-decoding CSR information as specified by RISC V.

[0044] A separate pre-decoding design utilizes pattern recognition decoding results and vector recognition decoding results for the next decoding stage and static branch prediction, respectively. This structure effectively adapts to fast execution when there are no branch instructions. When there are branch instructions, branch prediction can be performed on the instructions, canceling instructions already in the decoder, enabling early branch switching.

[0045] Figure 4 This is the process of the pre-decoding processing method according to the optional embodiment of the present application Figure 2 ,like Figure 4 As shown, the method further includes:

[0046] Step S402: During the pre-decoding process of the current cycle, 16-bit decoding, 32-bit decoding, and instruction type identification are performed concurrently on the unaligned instruction, resulting in 16-bit decoding results, 32-bit decoding results, and instruction type decoding results. This parallel processing mechanism significantly improves the processing speed of the pre-decoding stage and reduces instruction processing latency, making it suitable for scenarios requiring fast response and high concurrency, such as real-time data analysis and cloud computing.

[0047] The above step S402 is performed in parallel with the above steps S202 and S302.

[0048] Based on the aforementioned parallel pre-decoding process, step S204 may specifically include performing static branch prediction based on the instruction type decoding result, the 16-bit instruction data, and the pattern recognition decoding result. This prediction mechanism can more accurately determine the execution path of instructions, reduce unnecessary branch prediction errors, and improve the processor's instruction execution efficiency, especially in complex program logic processing.

[0049] Furthermore, the 16-bit instruction data is concatenated with the instruction type decoding result to obtain a first concatenation result. Static branch prediction is then performed based on this first concatenation result and the pattern recognition decoding result. Through concatenation and pattern recognition, the processor can more carefully analyze the characteristics of the instruction and make more accurate branch predictions, making it suitable for scenarios requiring high-precision predictions, such as financial trading systems and autonomous driving systems.

[0050] In one embodiment, the method further includes performing decoding based on the 16-bit instruction data, the 16-bit decoding result, the 32-bit decoding result, and the vector identification decoding result. This comprehensive decoding method can fully exploit the potential parallelism of instructions and improve the instruction processing capability of the processor. It is suitable for scenarios that require processing large amounts of data and complex instruction sets, such as big data analysis and artificial intelligence computing.

[0051] Furthermore, under the guidance of the instruction type decoding result, the 16-bit instruction data is concatenated with the 16-bit decoding result to obtain a second concatenated result, which is then decoded based on the second concatenated result and the vector identification decoding result. Alternatively, under the guidance of the instruction type decoding result, the 16-bit instruction data is concatenated with the 32-bit decoding result to obtain a third concatenated result, which is then decoded based on the third concatenated result and the vector identification decoding result. This flexible concatenation and decoding processing method can adapt to different types of instructions, improve the versatility and adaptability of the processor, and is suitable for processor designs in multiple fields and applications.

[0052] In the embodiment of the present application, the above step S402 may specifically include:

[0053] S4021, convert the non-aligned instruction of the current cycle into n 16-bit instruction data, and obtain the two 16-bit instruction data converted from the last non-aligned instruction of the previous cycle;

[0054] S4022, perform 16-bit decoding on n 16-bit instruction data to obtain a 16-bit decoding result;

[0055] S4023, concatenate n 16-bit instruction data with 2 16-bit instruction data and perform 32-bit decoding to obtain a 32-bit decoding result;

[0056] S4024, performing instruction type decoding on the two 16-bit instruction data and the n 16-bit instruction data to obtain an instruction type decoding result;

[0057] Correspondingly, step S202 may specifically include: performing pattern recognition decoding on the two 16-bit instruction data and the unaligned instruction to obtain a pattern recognition decoding result; and step S302 may specifically include: performing vector recognition decoding on the two 16-bit instruction data and n 16-bit instruction data to obtain a vector recognition decoding result. This method significantly improves instruction processing throughput and reduces processor latency through parallel processing and data concatenation, making it suitable for scenarios requiring efficient instruction stream processing, such as video codecs and game engines.

[0058] Furthermore, S4022 may specifically include: if the instruction is not specified by the instruction set, determining the decoding result to be 2'b11; if the instruction is specified by the instruction set, for instructions that need to be split into one minimum opcode uop in the processor for processing, determining the decoding result to be 2'b00; for instructions that need to be split into two uops in the processor for processing, determining the decoding result to be 2'b01; for instructions that need to be split into at least three uops in the processor for processing, determining the decoding result to be 2'b10. This marking method of the decoding result can clearly indicate the complexity and processing method of the instruction, which helps to optimize subsequent instruction scheduling and execution, and improve the execution efficiency of the processor.

[0059] Furthermore, S4023 may specifically include: concatenating the upper 16-bit instruction data of the two 16-bit instruction data with the first 16-bit instruction data of the n 16-bit instruction data, and concatenating the second 16-bit instruction data to the nth 16-bit instruction data of the n 16-bit instruction data in sequence, to obtain n uncompressed instruction data; if it is not an instruction specified by the instruction set, determining the decoding result to be 2'b11; if it is an instruction specified by the instruction set, for instructions that need to be split into one uop for processing in the processor, determining the decoding result to be 2'b00; for instructions that need to be split into two uops for processing in the processor, determining the decoding result to be 2'b01; for instructions that need to be split into at least three uops for processing in the processor, determining the decoding result to be 2'b10. This concatenation and decoding method can effectively process uncompressed instructions, improve the flexibility and efficiency of instruction processing, and is suitable for scenarios that require processing complex instructions and large amounts of data, such as high-performance computing and deep learning.

[0060] Furthermore, S4024 may specifically include: determining the upper 16-bit instruction data and the lower 2 bits of n 16-bit instruction data in two 16-bit instruction data; determining whether the upper 16-bit instruction data and the lower 2 bits of n 16-bit instruction data are 2'b11; determining whether the n 16-bit instruction data are compressed instructions or uncompressed instructions based on the judgment results, obtaining the instruction type decoding result for each 16-bit instruction data in the n 16-bit instruction data, and marking the instruction type decoding result. This instruction type identification and marking mechanism can help the processor more effectively manage and schedule instructions, reduce the uncertainty of instruction processing, and improve the stability and performance of the processor. It is suitable for scenarios that require processing large instruction streams and optimizing instruction scheduling, such as network communications and real-time operating systems. Specifically, for the current odd-numbered 16-bit instruction data among the n 16-bit instruction data, if the lower 2 bits of the previous 16-bit instruction data are 2'b11, it is determined that the previous 16-bit instruction data and the current odd-numbered 16-bit instruction data are non-compressed instructions; if the lower 2 bits of the previous 16-bit instruction data are not 2'b11 and the lower 2 bits of the current odd-numbered 16-bit instruction data are not 2'b11, it is determined that the previous 16-bit instruction data and the current odd-numbered 16-bit instruction data are compressed instructions; if the lower 2 bits of the previous 16-bit instruction data are not 2'b11 and the lower 2 bits of the current odd-numbered 16-bit instruction data are 2'b11, it is determined that the previous 16-bit instruction data is compressed. Compressed instruction, the current odd number of 16-bit instruction data is a non-compressed instruction; among them, if the low 2 bits of the high 16-bit instruction data are 2'b11, the first 16-bit instruction data among the n 16-bit instruction data is a non-compressed instruction; if the low 2 bits of the high 16-bit instruction data are not 2'b11, and the low 2 bits of the first 16-bit instruction data are 2'b11, the first 16-bit instruction data is a non-compressed instruction; when the low 2 bits of the first 16-bit instruction data are not 2'b11, the first 16-bit instruction data is a compressed instruction; for compressed instructions, the high bit I of the 16-bit instruction data is marked as 0; for non-compressed instructions, the high bits I of the corresponding two 16-bit instruction data are both marked as 1. This sophisticated instruction type marking can help the processor identify and process instructions more accurately, reduce instruction processing errors, and improve the reliability and efficiency of the processor. It is suitable for scenarios that need to process complex instruction sets and optimize instruction execution, such as embedded systems, mobile devices, etc.

[0061] Furthermore, in the above step S202, pattern recognition decoding is performed on the two 16-bit instruction data and the non-aligned instruction to obtain the pattern recognition decoding result, which may specifically include: pattern decoding is performed on the two 16-bit instruction data and m non-aligned instructions respectively to obtain the pattern recognition decoding result, and pattern marking is performed, wherein n=2m. This pattern recognition and marking mechanism can help the processor more accurately predict the execution mode of the instruction, reduce the uncertainty of instruction processing, and improve the prediction accuracy and performance of the processor. It is suitable for scenarios that need to process a large number of instructions and optimize prediction accuracy, such as real-time data analysis, high-performance computing, etc. The pattern recognition pre-decoding technology can effectively redirect branches in the early stage of the processor pipeline, so that the processor can perform branch switching earlier. There is no need to wait until the back-end of the processor pipeline for processing, which greatly improves the processor performance.

[0062] Furthermore, in step S302, vector identification decoding is performed on the two 16-bit instruction data and the n 16-bit instruction data to obtain the vector identification decoding result. Specifically, the following steps may be performed: vector identification decoding is performed on the upper 16-bit instruction data and the n 16-bit instruction data in the two 16-bit instruction data; and each 16-bit instruction data in the n 16-bit instruction data is marked with the vector identification decoding result of the previous 16-bit instruction data, wherein the first 16-bit instruction data uses the vector identification decoding result of the upper 16-bit instruction data. This vector identification decoding and marking mechanism can help the processor process vector instructions more efficiently and improve the vector operation performance of the processor. It is suitable for scenarios requiring a large number of vector operations, such as image processing and artificial intelligence calculations. Vector pre-decoding technology can obtain vector instruction configuration information in the early stage of the processor pipeline, without waiting for the configuration instruction to be completed before performing processor work. This accelerates the processor processing speed and greatly improves processor performance.

[0063] The pre-decoding processing of the embodiment of the present application significantly improves the processing efficiency of the pre-decoding stage by parallel processing of 16-bit decoding, 32-bit decoding, instruction type recognition, pattern recognition decoding and vector recognition decoding of non-aligned instructions, reduces the waiting time of the processor, and thus improves the overall performance of the processor. In particular, when processing non-aligned instructions, by performing pattern recognition and static branch prediction on the instructions, the fetch position of subsequent instructions can be more accurately predicted, further optimizing the execution efficiency of the instruction pipeline. In addition, by performing vector recognition decoding on the instructions, the processing of vector instructions can be better supported, the processor's support capability for complex instruction sets is improved, and the computing performance and flexibility of the processor are enhanced. This pre-decoding processing method is not only applicable to general-purpose processors, but also to special-purpose processors such as GPUs, FPGAs, etc. It can be widely used in various computing-intensive and data-intensive application scenarios, such as scientific computing, graphics rendering, data mining, etc., greatly improving processing efficiency and performance.

[0064] The embodiment of the present application uses an unaligned instruction set for pre-decoding design, which can solve the problem in related technologies that supporting compressed and uncompressed instructions increases the difficulty of processor design. At the same time, it also solves the problem that mainstream pre-decoding is prone to errors, and the solution in this embodiment does not increase the cache capacity of L1 Icache, which to a certain extent reduces the CPU area overhead. In addition, it combines static branch prediction technology and proposes some new pre-decoding technologies for specific patterns to guide the static predictor to perform branch prediction in advance, switching branches earlier to improve processor performance. It also proposes vector instruction pre-decoding technology to obtain configuration register values ​​earlier and guide the decoder or decoding module to perform instruction decoding in advance, without having to wait until the register is updated before decoding to improve processor performance. At the same time, it can accurately provide instruction information for static branch prediction, avoiding static branch prediction errors caused by instruction misalignment.

[0065] The embodiment of the present application is aimed at a processor that supports both compression and non-compression, and implements a pre-decoding structure that supports mixed compression and non-compression instruction sets. Through this structure, compressed and non-compressed instruction pre-decoding can be dynamically supported, and abnormal scenarios such as illegal instructions in compressed and non-compressed instructions can be dynamically detected.

[0066] The embodiment of the present application provides an application of a pre-decoding structure in a processor that supports both compressed and uncompressed instructions. The entire pre-decoding structure is located in the instruction fetch stage of the pipeline. The number of pipeline stages in different processors may vary. Figure 5 is a schematic diagram of a decoding pipeline according to an embodiment of the present application, such as Figure 5 As shown in Figure 2. The L1 instruction cache L1 I cache is located in the fetch stage of the pipeline. Figure 6This is a schematic diagram of pre-decoding according to an embodiment of the present application. The relationship between predecode and L1 Icache is as follows: Figure 6 shown. Figure 7 is a schematic diagram of the pre-decoding structure according to an embodiment of the present application, such as Figure 7 As shown in the figure, the predecode structure is divided into 16-bit decoding module, 32-bit decoding module, instruction type decoding module, pattern recognition decoding module, vector recognition decoding module, etc. Figure 7 The 16bit; 32bit; Itype; pattern; and vtp modules, wherein the 0, 1, ..., n, and n+1 marked in each module respectively refer to the number of instantiations of the module.

[0067] Figure 8 : is a schematic diagram of the structure of the combined instruction in the pre-decoding according to the embodiment of the present application, such as Figure 8 As shown, the pattern recognition in the predecode structure is for some flow processing modules that complete branch switching by combining instructions. Predecode decodes a specific pattern in advance. By pre-processing the work that needs to be completed in the execution unit, the instruction execution result is obtained and the branch is switched in advance. For example Figure 8 The combination pattern of auipc+jalr in Figure 8 I0, I1, etc. in it represent the instruction number. Predecode can be used to pre-identify whether two consecutive instructions are auipc and jalr. The auipc instruction must be before the jalr instruction. Then, the immediate value in the auipc instruction is extracted, and the execution result of the instruction is calculated based on the immediate value. The result is used as the target address of the jalr branch instruction. This pattern can be used to switch branches earlier, without having to wait until auipc reaches the execution unit. Since this type of pattern appears very frequently during program execution, it is very effective in improving performance. The result of this pattern needs to be sent to the static prediction module for static branch prediction, so that branch switching can be performed earlier.

[0068] The VTP module in the predecoder uses pre-decoding to early identify configuration information for executing a specific vector instruction, such as element width, register grouping, mask processing strategy, and tail processing strategy. This configuration information is often implemented within a single instruction. Pre-decoding this information is pre-decoded and passed to the decoder or other units for processing, avoiding the performance loss caused by writing the configuration information to registers before executing it. Because this configuration information is dynamically configured during programming, rather than statically set in stone, the VTP structure significantly improves processor performance. Figure 9 is a schematic diagram of a programming model according to an embodiment of the present application, such as Figure 9 As shown in the figure, the vsetv1 instruction is the vector configuration instruction. Subsequent vector instructions must be guided by the vsetv1 configuration information. The vtp information needs to be sent to the decoder for decoding guidance.

[0069] The I type module in predecode is a module that identifies instruction types based on the characteristics of compressed instructions and non-compressed instructions specified in the instruction set. Figure 10 Schematic diagram of instruction type identification according to an embodiment of the present application, such as Figure 10 As shown in the figure, each instruction sent in is identified at a 16-bit granularity, because compressed instructions are all 16 bits, while non-compressed instructions are all 32 bits. Therefore, 16 bits are uniformly used for processing. Figure 10 The "b" in the command indicates a bit. The resulting output, Itype, is a single-bit signal. A value of 1 indicates an uncompressed instruction, and a value of 0 indicates a compressed instruction.

[0070] The 16-bit and 32-bit predecode modules operate in parallel without interfering with each other. Because the predecode is a critical link in the processor pipeline, a serial design would inevitably increase the number of predecode logic levels. However, parallel processing significantly reduces the number of logic levels, enabling higher processor frequencies. 16-bit and 32-bit instructions are decoded according to their respective instruction formats.

[0071] Figure 11 is a schematic diagram of the selection of pre-decoding results according to an embodiment of the present application, such as Figure 11 As shown, the final decoding result of predecode is selected. Because predecoding adopts a separate decoding structure, after decoding, it is necessary to select the decoding results of 16bit and 32bit according to Itype. For the final decoded result information, Figure 12 is a schematic diagram of the pre-decoding result information according to an embodiment of the present application, such as Figure 12 The pd0 and pd1 shown in the figure refer to the 16-bit decoding results of each 16-bit instruction being spliced ​​into the high bit of the 16-bit instruction. The spliced ​​information is sent to the decoder for further decoding. The instruction information sent to the static prediction is spliced ​​into the high bit of the 16-bit original instruction code by splicing the I type information. Figure 13 is a schematic diagram of static prediction information according to an embodiment of the present application, such as Figure 13 Since static prediction does not require the execution of decoding details, the final result sent by predecode to the static predictor is different from the structure sent to decode.

[0072] For ease of description, the embodiments of the present application are described in detail below using the RISC V instruction set as an example.

[0073] The bandwidth in this embodiment is set to 32 bits x 4. Figure 14 is a flowchart of the pre-decoding process according to an embodiment of the present application. Figure 14 As shown in the figure, pattern is the pattern recognition module, vtp is the instruction pre-decoding module of the special configuration class, the L1Icache output data pre-decoding method is used to improve the pre-decoding and backfill cache defects; the last32b reg method is used to cooperate with 16bit and 32bit to support 16bit and 32bit variable-length instruction set pre-decoding.

[0074] Step 1: When the L1I cache fetches an instruction, it sends it to the predecode module for pre-decoding. This step sends 4 x 32-bit instruction data to the predecode module each cycle. Due to unaligned instructions, the predecode module breaks all 32-bit instruction data into 16-bit data. A special configuration is made to retain the last 32-bit instruction data packet from the previous cycle for use in unaligned decoding and pattern recognition. As shown in the figure, each 32-bit instruction packet in the first step is converted into two 16-bit packets, and the process proceeds to step 2.

[0075] Step 2: In the first step, 8 16-bit instruction data are given, plus the reserved 32-bit instruction data, a total of 10 16-bit instruction data.

[0076] For compressed instruction decoding in the current bandwidth mode, the eight 16-bit data bits from the L1 I cache are sequentially sent to the 16bit0 to 16bit7 modules for compressed instruction decoding. Because 16-bit instructions are not coupled with instructions from the previous cycle, they are independent regardless of the selected instruction. Decoding of these instructions is based on their characteristics. For example, if the current 16-bit instruction information is not specified by the instruction set, it is decoded as an undefined instruction, and the decoded result pd information is marked as 2'b11. For instructions specified in the instruction set, such as instructions that need to be split into one minimum operation code uop for processing in the processor, the pd information is decoded as 2'b00 according to the opcode code of this type of instruction; for instructions that need to be split into two uops for processing in the processor, the pd information is decoded as 2'b01 according to the opcode code of this type of instruction; for instructions that need to be split into three or more uops for processing in the processor, the pd information is decoded as a binary code 2'b10 with a bit width of 2 according to the opcode code of this type of instruction; the decoding information is used to represent the instruction type. If there is other indication information, it can still be decoded according to this method, but the bit width of the pd is expanded to represent more indication information.

[0077] For uncompressed instructions, since unaligned instructions may represent half of a 32-bit instruction, meaning that the 16-bit instruction data is in the previous cycle, the high 16-bit instruction data retained from the previous cycle is concatenated with the eight newly entered 16-bit data. 16bit1 of the last 32B reg and the newly entered 16bit0 are concatenated to form the first packet of uncompressed instruction data. 16bit0 and 16bit1 are concatenated to form the second packet of uncompressed instruction data. 16bit1 and 16bit2 are concatenated to form the third packet of uncompressed instruction data, and so on, until the last 16bit6 and 16bit7 are concatenated to form the eighth packet of uncompressed instruction data. These eight packets of instruction data are sequentially fed into the uncompressed instruction pre-decoding module. The decoding of such instructions is based on their own characteristics. For example, if the current 32-bit instruction information does not conform to the instruction set, it is decoded as an undef instruction, and the pd information is marked as 2'b11. For instructions specified in the instruction set, such as instructions that need to be split into one uop for processing in the processor, the pd information is decoded as 2'b00 according to the opcode code of this type of instruction; for instructions that need to be split into two uops for processing in the processor, the pd information is decoded as 2'b01 according to the opcode code of this type of instruction; for instructions that need to be split into at least three uops for processing in the processor, the pd information is decoded as 2'b10 according to the opcode code of this type of instruction; if there is other indication information, it can still be decoded according to this method, but the bit width of the pd is expanded to represent more indication information.

[0078] The I-type decoding module handles instructions similarly to uncompressed instructions, taking into account the 16-bit instruction information retained from the previous cycle. The fifth-generation RISCV instruction set specifies that the lower two bits of compressed instructions are not 2'b11. For uncompressed instructions with the lower two bits being 2'b11, if the retained 16-bit 1 from the previous cycle is an uncompressed instruction, the first 16b0 in this cycle is considered uncompressed without checking its lower two bits. Decoding then begins at 16b1, using the lower two bits of 16b1 to determine if the instruction is uncompressed. If 16b1 is a compressed instruction, the lower two bits of 16b2 are used to determine if it is also uncompressed. This process continues until the final 16b position is reached. If the retained 16-bit 1 from the previous cycle is a compressed instruction, the same determination is followed. For compressed instructions, the I position in the upper 16b position is marked as 0. For non-compressed instructions, the high bits I of the two 16b are both marked as 1, because the non-compressed instruction consists of two 16b.

[0079] The pattern decoding module considers the entire 32-bit data retained from the previous cycle and the four currently input instructions for pattern recognition. For example, for the auipc and jalr combination instructions specified by ri scv, the 32-bit data is retained because the combined pattern may be a combination of 32-bit instructions. It may also be a combination of 32-bit and 16-bit instructions, or a combination of 16-bit instructions. Therefore, the entire 32-bit instruction data must be retained. The auipc + jalr combination pattern is used as an example. If the 1a st 32b reg retained from the previous cycle is auipc, and the first instruction packet in this cycle is jalr, this is considered a standard pattern. The instruction packet corresponding to jalr is then marked with a pattern bit using an additional signal, also using a 16-bit granularity. Although jalr is a 32-bit instruction, it is still marked with a 16-bit granularity due to misalignment. All instructions in this cycle are pattern decoded and marked in sequence. A 0 indicates that the pattern is not present; a 1 indicates that the pattern is present.

[0080] The VTP decoder module needs to consider the 16-bit instruction information retained from the previous cycle to decode VTP instructions. For the vsetvli instruction specified by RI SCV, decoding this type of instruction provides early access to configuration information, and the decoding result is the configuration information. Considering the impact of unaligned instructions, the 16-bit instruction information retained from the previous cycle is used. Because this type of instruction configures all subsequent instructions, the decoded VTP information needs to guide the decoding of all subsequent instructions. This is done by marking a VTP bit with an additional signal, also using a 16-bit marker. This marker remains unchanged until the next vsetvli instruction arrives. That is, all instructions between two vsetvli instructions use only the decoding result of the previous vsetvli instruction. The second vsetvli instruction and subsequent instructions use the decoding result of the second vsetvli instruction, and so on. Proceed to step three.

[0081] Step 3: The decoded results from the second step are grouped together. As shown in the figure, the information sent to the static prediction module is 16b0+I+16b1+I, pattern0+pattern1, and three other groups. The static prediction module performs static predictions based on the instruction type and pattern information, providing specific branch target addresses and other information to facilitate early branch switching. The decode module receives the decoded results (16b0+pd+16b1+pd), the decoded configuration information (vtp0+vtp1), and three other groups. The decode module then completes the processor's decoding based on the pd and vtp information. The pd information is selected and concatenated based on the instruction type. As shown in Figure g, an Itype of 0 selects the decoded result for compressed instructions, while an Itype of 1 selects the decoded result for non-compressed zero data.

[0082] Step 4: decode and static predictor continue to complete the next step of decoding and static prediction.

[0083] The present application also provides a pre-decoding processing device. Figure 15 is a block diagram of a pre-decoding processing device according to an embodiment of the present application. Figure 15 Shown, including:

[0084] The pre-decoding module 152 is used to perform pattern recognition decoding on the non-aligned instruction fetched during the pre-decoding process of the current cycle to obtain a pattern recognition decoding result;

[0085] The static branch prediction module 154 is configured to perform static branch prediction on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the fetch of the non-aligned instruction in the next cycle.

[0086] An embodiment of the present application further provides a computer program product, including computer program instructions, wherein the computer program instructions enable a computer to implement the steps in any of the above method embodiments.

[0087] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above method embodiments when run.

[0088] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0089] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0090] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0091] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0092] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0093] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A pre-decoding processing method, characterized in that: At least: In the pre-decoding process of the current cycle, pattern recognition decoding is performed on the non-aligned instruction fetched to obtain a pattern recognition decoding result; Static branch prediction is performed on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the instruction fetch of the non-aligned instruction in the next cycle.

2. The method according to claim 1, characterized in that The method further comprises: During the pre-decoding process of the current cycle, vector identification decoding is performed on the non-aligned instruction to obtain a vector identification decoding result, wherein the vector identification decoding result is used to perform decoding processing on the non-aligned instruction.

3. The method according to claim 2, characterized in that The method further comprises: During the pre-decoding process of the current cycle, 16-bit decoding, 32-bit decoding and instruction type identification are performed on the non-aligned instruction in parallel to obtain a 16-bit decoding result, a 32-bit decoding result and an instruction type decoding result.

4. The method according to claim 3, characterized in that Performing static branch prediction on the non-aligned instruction according to the pattern recognition decoding result, obtaining a branch prediction result includes: Static branch prediction is performed according to the instruction type decoding result, the 16-bit instruction data and the pattern recognition decoding result.

5. The method according to claim 4, characterized in that Performing static branch prediction according to the instruction type decoding result, the 16-bit instruction data, and the pattern recognition decoding result includes: Splicing the 16-bit instruction data with the instruction type decoding result to obtain a first splicing result; Static branch prediction is performed according to the first splicing result and the pattern recognition decoding result.

6. The method according to claim 3, characterized in that The method further comprises: Decoding is performed according to the 16-bit instruction data, the 16-bit decoding result, the 32-bit decoding result, and the vector identification decoding result.

7. The method according to claim 6, characterized in that Decoding according to the 16-bit instruction data, the 16-bit decoding result, the 32-bit decoding result, and the vector identification decoding result includes: Under the instruction type decoding result, the 16-bit instruction data is spliced ​​with the 16-bit decoding result to obtain a second splicing result, and decoding processing is performed according to the second splicing result and the vector identification decoding result; or Under the instruction type decoding result, the 16-bit instruction data and the 32-bit decoding result are spliced ​​to obtain a third splicing result, and decoding processing is performed according to the third splicing result and the vector identification decoding result.

8. The method according to claim 3, characterized in that The parallel 16-bit decoding, 32-bit decoding, and instruction type decoding of the non-aligned instruction include: Convert the non-aligned instruction of the current cycle into n 16-bit instruction data, and obtain the two 16-bit instruction data obtained by converting the last non-aligned instruction of the previous cycle; Performing 16-bit decoding on the n 16-bit instruction data to obtain a 16-bit decoding result; splicing the n 16-bit instruction data with the two 16-bit instruction data and then performing 32-bit decoding to obtain a 32-bit decoding result; Performing instruction type decoding on the two 16-bit instruction data and the n 16-bit instruction data to obtain an instruction type decoding result; Performing pattern recognition decoding on the non-aligned instruction fetched to obtain the pattern recognition decoding includes: performing pattern recognition decoding on the two 16-bit instruction data and the non-aligned instruction to obtain the pattern recognition decoding result; Performing vector identification decoding on the non-aligned instruction to obtain a vector identification decoding result includes: performing vector identification decoding on the two 16-bit instruction data and the n 16-bit instruction data to obtain the vector identification decoding result.

9. The method according to claim 8, characterized in that The n 16-bit instruction data are subjected to 16-bit decoding to obtain a 16-bit decoding result including: If it is not an instruction specified by the instruction set, the decoding result is determined to be 2'b11; If it is an instruction specified by the instruction set, for an instruction that needs to be split into one minimum opcode uop for processing in the processor, the decoding result is determined to be 2'b00; for an instruction that needs to be split into two uops for processing in the processor, the decoding result is determined to be 2'b01; for an instruction that needs to be split into at least three uops for processing in the processor, the decoding result is determined to be 2'b10.

10. The method according to claim 8, characterized in that The n 16-bit instruction data are concatenated with the two 16-bit instruction data and then uncompressed instruction decoding is performed to obtain n 32-bit decoding results including: splicing the upper 16-bit instruction data of the two 16-bit instruction data with the first 16-bit instruction data of the n 16-bit instruction data, and splicing the second 16-bit instruction data to the n-th 16-bit instruction data of the n 16-bit instruction data in sequence, to obtain n uncompressed instruction data; If it is not an instruction specified by the instruction set, the decoding result is determined to be 2'b11; If it is an instruction specified by the instruction set, for instructions that need to be split into one uop for processing in the processor, the decoding result is determined to be 2'b00; for instructions that need to be split into two uops for processing in the processor, the decoding result is determined to be 2'b01; for instructions that need to be split into at least three uops for processing in the processor, the decoding result is determined to be 2'b10.

11. The method according to claim 8, characterized in that The two 16-bit instruction data and the n 16-bit instruction data are subjected to instruction type decoding, and the instruction type decoding result obtained includes: Determine respectively the upper 16-bit instruction data of the two 16-bit instruction data and the lower 2 bits of the n 16-bit instruction data: Determine whether the upper 16-bit instruction data and the lower 2 bits of the n 16-bit instruction data are 2'b11; Determine whether the n 16-bit instruction data are compressed instructions or non-compressed instructions based on the judgment results, obtain an instruction type decoding result of each 16-bit instruction data in the n 16-bit instruction data, and mark the instruction type decoding result.

12. The method according to claim 11, characterized in that Determining whether the n 16-bit instruction data are compressed instructions or uncompressed instructions based on the judgment results, obtaining an instruction type decoding result for each 16-bit instruction data in the n 16-bit instruction data, and marking the instruction type decoding result includes: For the current odd-numbered 16-bit instruction data among the n 16-bit instruction data, if the lower 2 bits of the previous 16-bit instruction data are 2'b11, it is determined that the previous 16-bit instruction data and the current odd-numbered 16-bit instruction data are non-compressed instructions; if the lower 2 bits of the previous 16-bit instruction data are not 2'b11 and the lower 2 bits of the current odd-numbered 16-bit instruction data are not 2'b11, it is determined that the previous 16-bit instruction data and the current odd-numbered 16-bit instruction data are compressed instructions; if the lower 2 bits of the previous 16-bit instruction data are not 2'b11 and the lower 2 bits of the current odd-numbered 16-bit instruction data are 2'b11, it is determined that the previous 16-bit instruction data is a compressed instruction and the current odd-numbered 16-bit instruction data is a non-compressed instruction; Among them, if the lower 2 bits of the upper 16-bit instruction data are 2'b11, the first 16-bit instruction data among the n 16-bit instruction data is a non-compressed instruction; if the lower 2 bits of the upper 16-bit instruction data are not 2'b11, and the lower 2 bits of the first 16-bit instruction data are 2'b11, the first 16-bit instruction data is a non-compressed instruction; if the lower 2 bits of the first 16-bit instruction data are not 2'b11, the first 16-bit instruction data is a compressed instruction; For the compressed instruction, the high bit I of the 16-bit instruction data is marked as 0; For non-compressed instructions, the high bits I of the corresponding two 16-bit instruction data are both marked as 1.

13. The method according to claim 8, characterized in that Performing pattern recognition decoding on the two 16-bit instruction data and the non-aligned instruction, obtaining a pattern recognition decoding result including: Pattern decoding is performed on the two 16-bit instruction data and the m non-aligned instructions respectively to obtain the pattern recognition decoding result, and pattern marking is performed, wherein n=2m.

14. The method according to claim 8, characterized in that Performing vector identification decoding on the two 16-bit instruction data and the n 16-bit instruction data to obtain a vector identification decoding result includes: Performing vector recognition decoding on the upper 16-bit instruction data of the two 16-bit instruction data and the n 16-bit instruction data respectively; Each 16-bit instruction data in the n 16-bit instruction data is marked using the vector identification decoding result of the previous 16-bit instruction data, wherein the first 16-bit instruction data uses the vector identification decoding result of the high 16-bit instruction data.

15. A pre-decoding processing device, characterized in that: include: A pre-decoding module is used to perform pattern recognition decoding on the non-aligned instruction fetched during the pre-decoding process of the current cycle to obtain a pattern recognition decoding result; A static branch prediction module is used to perform static branch prediction on the non-aligned instruction according to the pattern recognition decoding result to obtain a branch prediction result, wherein the branch prediction result is used to indicate the fetch of the non-aligned instruction in the next cycle.

16. A computer-readable storage medium, characterized in that The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 14 when executed.

17. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 14.

18. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 14 are implemented.

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