A processor topology mapping management method, device, program, and storage medium

Abstract

The application discloses a processor topology mapping management method and device, a program and a storage medium, and applies to the technical field of computers, and comprises the following steps: acquiring a bitmap reflecting the fuse state of each processor core; if there is no fused processor core, then based on the bitmap, a mapping relationship between the processor core and a logical core identifier is established according to a default mapping mode; if there is a fused processor core and a binding mode is not enabled, then the mapping relationship is established according to the default mapping mode based on the bitmap; if a complete binding mode and / or the first processor core is fused, then the mapping relationship is established based on the bitmap and a logical core identifier allocation strategy; and if a fast binding mode is enabled and the first processor core is not fused, then the mapping relationship is established according to the default mapping mode. According to the scheme of the application, processor topology mapping management can be performed under the condition of meeting the requirements of users, and the operation and maintenance cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a processor topology mapping management method, device, program and storage medium. BACKGROUND

[0002] In the production process of a CPU (Central Processing Unit), core failure is a common phenomenon, which is directly related to the complexity of semiconductor manufacturing. For example, a CPU nominally has 32 cores, but actually 36 cores are manufactured. If it is found that a core is fused due to production defects, the core can be disabled and replaced with a backup core, so that the CPU performance still meets the standard and does not affect actual use. For example, in the example of Figure 1 Core 0 has a problem, so a backup core is used for replacement. However, in some cases, if it is found that the topology of the CPU is not in the preset order, an exception is determined, and the production line of the whole machine needs to replace such a CPU, which increases the operation and maintenance cost after the replacement of the high-value CPU material. However, the CPU does not affect the normal use of the business.

[0003] To sum up, how to effectively reduce the operation and maintenance cost is a technical problem that needs to be solved by the technical personnel in the field at present. SUMMARY

[0004] The present application provides a processor topology mapping management method, device, program and storage medium to reduce the operation and maintenance cost.

[0005] The present application provides a processor topology mapping management method, comprising:

[0006] Obtaining a bitmap reflecting the fused state of each processor core;

[0007] Based on the bitmap, it is judged whether there is a fused processor core;

[0008] If not, the mapping relationship between the processor core and the logical core identifier is established according to the default mapping mode based on the bitmap;

[0009] If yes, it is judged whether the binding mode is enabled; wherein the binding mode includes a complete binding mode and a quick binding mode;

[0010] If the binding mode is not enabled, the mapping relationship between the processor core and the logical core identifier is established according to the default mapping mode based on the bitmap;

[0011] If the complete binding mode is enabled and / or the first processor core is fused, a logical core identifier allocation strategy is acquired, and a mapping relationship between processor cores and logical core identifiers is established based on the bitmap and the logical core identifier allocation strategy;

[0012] If the fast binding mode is enabled and the first processor core is not fused, a mapping relationship between processor cores and logical core identifiers is established in a default mapping manner based on the bitmap.

[0013] The application provides an electronic device, comprising:

[0014] a memory for storing a computer program;

[0015] a processor for implementing the steps of the processor topology mapping management method when executing the computer program.

[0016] The application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the processor topology mapping management method.

[0017] The application provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of the processor topology mapping management method.

[0018] The application considers that, for a user with a hard requirement of a binding core operation, if each CPU establishes a mapping relationship in an original default mapping manner, it will indeed cause a logical thread pair belonging to the same processor core to be incorrectly allocated to different processor cores in some cases, so that the user task is not bound to the same processor core logical thread pair. However, the applicant considers that this situation does not meet the hard requirement of the user's binding core operation and only occurs when Core0 (the first processor) is fused.

[0019] To this end, in the scheme of the present application, a bitmap reflecting the fuse state of each processor core can be obtained, and then based on the bitmap, it is determined whether there is a processor core that is fused. It can be understood that if there is no processor core that is fused, it means that each processor core is not fused, at this time, whether the user has a hard requirement for core binding operation or not, the mapping relationship between the processor core and the logical core identifier can be established directly according to the default mapping mode, and there will be no error, in addition, when the mapping relationship is established directly according to the default mapping mode, the execution efficiency is also very high. If there is a processor core that is fused, it is necessary to determine whether the user has a hard requirement for core binding operation, that is, whether the binding mode needs to be enabled. If the binding mode is not enabled, it means that the user does not have a hard requirement for core binding operation, therefore, the mapping relationship between the processor core and the logical core identifier can also be established according to the default mapping mode based on the bitmap, to guarantee the execution efficiency.

[0020] If the binding mode is enabled, it means that the user has a hard requirement for core binding operation, at this time, if the first processor core is not fused and there is no special requirement (that is, the fast binding mode), the mapping relationship between the processor core and the logical core identifier can still be established according to the default mapping mode based on the bitmap, to guarantee the execution efficiency. In the scene with high reliability requirement, the complete binding mode will be enabled, at this time, the mapping relationship between the processor core and the logical core identifier will be established according to the pre-set reasonable logical core identifier allocation strategy combined with the bitmap, to guarantee the high reliability of the established mapping relationship, and such mapping relationship will not cause the abnormal situation that the logical threads belonging to the same processor core are incorrectly allocated to different processor cores. In addition, if the user has a hard requirement for core binding operation and the first processor core is fused, it is also necessary to regard it as enabling the complete binding mode, so as to establish the mapping relationship between the processor core and the logical core identifier according to the pre-set reasonable logical core identifier allocation strategy combined with the bitmap, to guarantee the high reliability of the established mapping relationship and avoid abnormal situations.

[0021] As can be seen from the above, the scheme of the present application can efficiently obtain a mapping relationship that can meet the user's requirements according to the user's requirement situation, and when the user has a hard requirement for core binding operation, the obtained mapping relationship has high reliability and thus avoids the occurrence of abnormal situations. In addition, it can be seen that for the above different situations, the scheme of the present application can effectively cope with them and obtain a mapping relationship that can meet the user's requirements, and there is no need to replace the CPU on the whole machine production line, which is conducive to reducing the operation and maintenance cost. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0023] Figure 1 Schematic diagram of the principle of replacing the faulty core 0 with the standby core;

[0024] Figure 2 The flow chart of the management method of processor topology mapping provided by the specific embodiment of the present application;

[0025] Figure 3 The structural schematic diagram of the electronic device provided by the specific embodiment of the present application;

[0026] Figure 4 The structural schematic diagram of the computer readable storage medium of the present application. EMBODIMENTS

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0028] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0029] Currently, in some occasions, users have a hard requirement for their applications to have a binding operation, specifically, a task must be bound to a pair of threads on the same processor core, therefore, for such a case, the CPU topology needs to be detected when the server is delivered, for example, for a 32-core CPU, the arrangement order of the CPU cores must be core 0 to core 31, for a 48-core CPU, the arrangement order of the CPU cores must be core 0 to core 47, if it is found that the topology of the CPU is not this preset order, an exception is determined, and the production line of the whole machine needs to replace such a CPU, which leads to an increase in operation and maintenance cost after replacing the high-value CPU material, but in fact, the CPU does not affect the normal use of the business.

[0030] In order to enable those skilled in the art to better understand the present application scheme, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0031] Referring to Figure 2 The processor topology mapping management method can include:

[0032] Step S201: Obtain a bitmap reflecting the meltdown state of each processor core.

[0033] Specifically, each processor core, that is, each physical core of the CPU, is also called a core, when it is determined through detection that a certain processor core has a core failure that cannot be recovered or is at high risk, the processor core will be melted down (Core Meltdown) to isolate the processor core, therefore, when the processor core is in a meltdown state, it will not be used. Of course, in actual applications, the specific rules for identifying a processor core as melted down can be set and adjusted according to actual needs, and do not affect the implementation of the present application.

[0034] The meltdown state of each processor core can be determined through detection, and then represented by a bitmap, that is, the meltdown state of each processor core can be reflected by the bitmap, the specific representation form of the bitmap can be set and adjusted according to actual needs, as long as it can effectively reflect the meltdown state of each processor core, for example, a data structure using binary bits (bits) to represent the meltdown state of each processor core can be commonly used as the bitmap of the present application, that is, each binary bit (0 or 1) corresponds to the meltdown state of a processor core (for example, Bit0 in the bitmap corresponds to Core0, Bit1 corresponds to Core1, and so on), and the states can be efficiently operated and queried through bit operations (such as AND, OR, and shift).

[0035] In actual application, the detection can be implemented in the POST stage of BIOS startup after the server is powered on, and then the bitmap is generated. For example, in one specific embodiment, in the POST stage of BIOS, the APIC ID (EBX[15:0]) of each processor core and the number (ECX[7:0]) of the core in the package are obtained as the physical position information of each processor core through the CPUID instruction (Leaf 0x1F). In addition, the fuse state of each processor core can also be obtained by reading the value of the related register.

[0036] In one specific embodiment of the present application, step S201 can specifically include:

[0037] determining whether the bitmap reflecting the fuse state of each processor core is stored in the first storage space;

[0038] if yes, reading the bitmap from the first storage space;

[0039] if no, obtaining the bitmap reflecting the fuse state of each processor core through detection, and storing the bitmap in the first storage space.

[0040] This embodiment considers that after the bitmap is obtained through detection, it can be stored, so that it is not necessary to repeat the detection after restart, and the efficiency is improved. The first storage space can be, for example, the EEPROM of the motherboard, or can be the NVRAM, as long as the bitmap can be read from the first storage space during BIOS startup.

[0041] In one specific embodiment of the present application, obtaining the bitmap reflecting the fuse state of each processor core through detection, and storing the bitmap in the first storage space can include:

[0042] reading the specified register of each processor core in parallel to obtain the fuse state of each processor core;

[0043] generating the bitmap reflecting the fuse state of each processor core based on the obtained fuse state of each processor core, and storing the bitmap in the first storage space.

[0044] The implementation considers that the specified register of each processor core is read in a parallel reading manner, so that the fuse state of each processor core can be detected synchronously, and the acquisition efficiency of the bitmap is improved. Moreover, the direct register access is adopted, so that the ACPI intermediate layer can be bypassed, and the delay is reduced. For example, in a specific case, the physical position information of each processor core is acquired through a CPUID instruction in a POST stage of a BIOS. Moreover, the fuse state of each processor core is obtained by reading the MSR register of each processor core. For example, in a specific example, the Bit5 of the MSR register of the first processor core (Core0) is read, so that whether the Core0 is fused or not can be determined.

[0045] After the fuse state of each processor core is obtained, the bitmap can be generated and stored in the first storage space according to the fuse state, for example, the code for generating the bitmap can be represented as: Bitmap = Σ (1 << i) x isCoreValid (i) (i ∈ [0, N-1]), wherein the isCoreValid (i) represents whether the processor core i is available (not fused), and the 1 << i is a bit operation logic, representing that the i-th bit of a binary number is set to 1 (and the remaining bits are 0), for example, when i = 3, the 1 << 3 is 1000 (10, 8) in binary. The Bitmap herein is the generated bitmap.

[0046] In a specific implementation, a new field can be added in the SMBIOS Type4 (Processor Information) so that the BIOS can acquire the bitmap therefrom, for example, the following field is added in the SMBIOS Type4 to report the fuse state:

[0047] The field name is CoreFusingState, the offset is 0x2A, and the description is “bitmap representing the fuse state”. The field name is Core0SpecialFlag, the offset is 0x2B, and the description is “0x01 representing that the Core0 is fused”. In the example, in addition to generating the bitmap, the Core0SpecialFlag field is specially set for the first processor core (Core0) to indicate whether the Core0 is fused, so that the BIOS can quickly determine the fuse state of the Core0 based on the field.

[0048] In a specific implementation of the present application, the following can also be included:

[0049] Based on the bitmap and the disablement of each processor core, a state flag is added for each processor core;

[0050] wherein, for any processor core, when the processor core is not fused and not disabled, the state flag added for the processor core is the state flag used to indicate that the processor core is available; and when the processor core is fused and / or disabled, the state flag added for the processor core is the state flag used to indicate that the processor core is unavailable.

[0051] In this embodiment, a state flag is further added for each processor core, and the state flag reflects whether the processor core is available. It can be understood that when a processor core is fused, the processor core is unavailable, and thus a state flag used to indicate that the processor core is unavailable is added for the processor core. When a processor core is not fused but is disabled due to other factors, for example, the processor core is actively disabled by a user, the processor core is also unavailable, and a state flag used to indicate that the processor core is unavailable is added for the processor core. Accordingly, only when a processor core is not fused and not disabled, a state flag used to indicate that the processor core is available is added for the processor core.

[0052] In this embodiment, whether a processor core is available can be more explicitly reflected by the state flag, which facilitates the calling of a related program and assists other work of the related program. That is, whether a processor core is available can be simply and quickly determined by the state flag, which can effectively assist the performance of other work.

[0053] Step S202: Based on the bitmap, it is determined whether there is a fused processor core. If not, step S203 is performed, and if yes, step S204 is performed.

[0054] Since the bitmap can reflect the fusion state of each processor core, based on the bitmap, it can be determined whether there is a fused processor core.

[0055] Step S203: Based on the bitmap, a mapping relationship between the processor cores and the logical core identifiers is established in a default mapping mode.

[0056] If there is no fused processor core, it indicates that each processor core is normal, and thus whether the user has a hard requirement for the binding core operation, the logical core identifier allocation strategy set by the present application scheme is not needed to be used to implement the allocation of the logical core identifier. The mapping relationship between the processor cores and the logical core identifiers can be directly established based on the bitmap in the default mapping mode, and no error occurs.

[0057] The default mapping mode refers to that the BIOS can establish the mapping relationship between the processor cores and the logical core identifiers according to the standard ACPI mapping rule, and the execution efficiency is high. For example, the mapping relationship between the processor cores and the logical core identifiers can be established according to the standard ACPI mapping rule in the following table. Figure 1For example, for a 32-core CPU, the mapping relationship between the processor cores and the logical core identifiers can be represented as: {0:Core0, 1:Core1, 2:Core2, 3:Core3, 4:Core4...30:Core30, 31:Core31}, that is, the logical core identifier allocated for the processor core Core0 is 0, the logical core identifier allocated for the processor core Core1 is 1, and so on, the logical core identifier allocated for the processor core Core2 is 2...the logical core identifier allocated for the processor core Core31 is 31.

[0058] The logical core identifier, that is, the logical ID, is usually numbered in the form of 0, 1, 2, 3...N for each logical core identifier, and no matter which way the mapping relationship is established, the logical core identifier needs to be continuous. For example, in the mapping relationship established in the above example, the logical core identifier is allocated from 0 to 31.

[0059] Step S204: Determine whether the binding mode is enabled. If the binding mode is not enabled, step S205 is performed, if the full binding mode and / or the first processor core is fused, step S206 is performed, and if the fast binding mode is enabled and the first processor core is not fused, step S207 is performed. The binding mode includes the full binding mode and the fast binding mode.

[0060] Whether the binding mode is enabled depends on the user's needs, and can usually be set in the BMC, so that during the BIOS running process, the current need to enable the binding mode is determined by reading the settings of the BMC or receiving the instructions of the BMC.

[0061] Step S205: If the binding mode is not enabled, the mapping relationship between the processor cores and the logical core identifiers is established based on the bitmap according to the default mapping mode.

[0062] If there is a fused processor core, it is necessary to determine whether the user has a hard requirement for binding core operation, at this time the scheme of the application will judge whether to enable the binding mode, if the binding mode is not enabled, it means that the user has no hard requirement for binding core operation, so the mapping relationship between the processor core and the logical core identifier can also be established based on the bitmap according to the default mapping mode, to ensure the execution efficiency. For example, in one occasion, the CPU is 32 cores, and for example, processor core 3 and core 0 are fused, and the mapping relationship between the processor core and the logical core identifier established according to the default mapping mode can be represented as: {0:Core32, 1:Core1, 2:Core2, 3:Core33, 4:Core4...30:Core30, 31:Core31}, that is, the processor core Core0 is fused and therefore uses the processor core Core32 to replace the core Core0, the logical core identifier allocated for the processor core Core32 is 0, the logical core identifier allocated for the processor core Core1 is 1, the logical core identifier allocated for the processor core Core2 is 2, since Core3 is fused and Core33 is used as a backup, the logical core identifier allocated for the processor core Core33 is 3, the logical core identifier allocated for the processor core Core4 is 4, and so on, the logical core identifier allocated for the processor core Core5 is 5... the logical core identifier allocated for the processor core Core31 is 31.

[0063] In addition, it needs to be explained that for the mapping relationship {0:Core32, 1:Core1, 2:Core2, 3:Core33, 4:Core4...30:Core30, 31:Core31} established in this example, it may cause the logical thread pair that should belong to the same processor core to be allocated to different processor cores, but in fact this CPU does not affect the normal use of the business, and since the user has no hard requirement for binding core operation, even if the task is not bound to the logical thread pair of the same processor core, it does not affect the use of the user.

[0064] Step S206: If the full binding mode is enabled and / or the first processor core is fused, the logical core identifier allocation strategy is obtained, and the mapping relationship between the processor core and the logical core identifier is established based on the bitmap and the logical core identifier allocation strategy.

[0065] In the scheme of the application, in the binding mode, it specifically includes the full binding mode and the fast binding mode, when the full binding mode is enabled, it means that the user has special requirements, so it is necessary to implement reasonable construction of the mapping relationship according to a reasonable logical core identifier allocation strategy.

[0066] And, in the case of enabling the binding mode, no matter whether the full binding mode or the fast binding mode is enabled, the user is hard required to have the binding core operation, therefore, no matter whether the full binding mode or the fast binding mode is enabled, as long as the first processor core (Core0) is fused, the mapping relationship construction is implemented based on the logical core identifier distribution strategy according to the requirement of the full binding mode, so as to guarantee that the hard requirement of the user's binding core operation can be met, and the case that the logical thread pair of the task is not bound to the same processor core does not occur, in other words, in the case of enabling the binding mode, if the first processor core (Core0) is fused, no matter whether the full binding mode or the fast binding mode is enabled, it can be regarded as enabling the full binding mode.

[0067] The first processor core refers to the first processor core in the arrangement order of the CPU core, and is normally the first activated core after the CPU is powered on and initialized. The arrangement order of the CPU core is usually related to the physical layout inside the chip or the identification in the manufacturing test stage.

[0068] The specific content of the logical core identifier distribution strategy can be set and adjusted according to actual needs, but it can be understood that no matter how the logical core identifier distribution strategy is set, the rationality of the established mapping relationship needs to be guaranteed, that is, after the mapping relationship is established based on the logical core identifier distribution strategy, the hard requirement of the user's binding core operation can be met, and the case that the logical thread pair of the task is not bound to the same processor core does not occur. Of course, in addition to meeting the hard requirement of the user's binding core operation, the specific strategy content of the logical core identifier distribution strategy is different, which can meet the corresponding special needs of the user, for example, the memory affinity strategy in the following facilitates the system to preferentially allocate the task to the core of the local NUMA node (quickly locate through the logical ID), which can reduce the memory access delay across the NUMA node and improve the performance.

[0069] In a specific embodiment of the present application, the obtained logical core identifier distribution strategy includes a physical order strategy;

[0070] Based on the bitmap and the logical core identifier distribution strategy, the mapping relationship between the processor core and the logical core identifier is established, including:

[0071] Based on the bitmap, the processor cores that are not fused are determined;

[0072] For the determined processor cores that are not fused, the logical core identifiers are distributed to the processor cores that are not fused in turn according to the physical order of the processor cores;

[0073] When the allocation of the logical core identifier N is completed, the allocation is ended, and the mapping relationship between the established processor core and the logical core identifier is obtained;

[0074] Wherein, N is a preset processor core nominal value; when the allocation of the logical core identifier is performed, the allocation of the logical core identifier is performed in the order from the logical core identifier 0 to the logical core identifier N-1.

[0075] In this embodiment, the mapping relationship is constructed based on the physical order strategy. In order to facilitate understanding, the bitmap is taken as an example of 0xF7 (0xF7 is a hexadecimal number, which is 11110111 in binary), which indicates that only the processor core Core3 is fused in the 8 processor cores Core0 to Core7, and the rest are not fused.

[0076] Under the physical order strategy, the logical ID is allocated to Core0, Core1, Core2... in turn according to the physical order of the processor core, that is, according to the physical number of the processor core, and when the logical ID is allocated, the allocation is performed in the order from the logical ID 0 to the logical ID N-1, so as to ensure that the logical ID is continuous.

[0077] In the example of the bitmap being 0xF7, for example, the processor core nominal value N is set to 6. First, the logical ID 0 is allocated to Core0, then the logical ID 1 is allocated to Core1, then the logical ID 2 is allocated to Core2. Core3 is fused, and no logical ID is allocated. Then the logical ID 3 is allocated to Core4, then the logical ID 4 is allocated to Core5, and then the logical ID 5 is allocated to Core6. Since the allocation of the logical ID 5 is completed (in this example, the processor core nominal value N is set to 6, 6-1=5), the allocation can be ended, and the mapping relationship between the established processor core and the logical core identifier is obtained: {0:Core0, 1:Core1, 2:Core2, 3:Core4, 4:Core5, 5:Core6}.

[0078] The processor core nominal value N reflects the number of cores provided when the CPU performance meets the standard, for example Figure 1For example, in the case of a 32-core CPU, the value of N is 32. In the above example, N = 6, indicating that the number of cores provided when the CPU performance meets the standard is 6, that is, a 6-core CPU, and the bitmap is 0xF7, which is 11110111 in binary, indicating that 2 cores have a redundant backup effect.

[0079] It can be seen that in this embodiment, under the physical order strategy, the logical ID of each Core can be allocated in sequence, ensuring the continuity of the logical ID. And for each processor core that has not been fused, the logical ID is allocated according to the physical order of the processor core, so that even if a processor core is fused, the processor core with a high physical order can be allocated a logical ID first, obtaining a high-reliability mapping relationship, which can effectively meet the hard requirement of the user's core binding operation. Moreover, when the physical order strategy is adopted, the implementation is relatively simple and convenient, ensuring the efficiency and reliability of the strategy execution.

[0080] In one specific embodiment of the present application, the obtained logical core identifier allocation strategy includes a memory affinity strategy;

[0081] Based on the bitmap and the logical core identifier allocation strategy, a mapping relationship between the processor cores and the logical core identifiers is established, including:

[0082] Based on the bitmap, each processor core that has not been fused is determined;

[0083] According to the numbering order of the non-uniform memory access nodes, the logical core identifiers are allocated to each non-uniform memory access node in sequence, and for any non-uniform memory access node, the logical core identifiers are allocated to each processor core that has not been fused and belongs to the non-uniform memory access node in sequence;

[0084] When the allocation of the logical core identifier N is completed, the allocation is ended, and the established mapping relationship between the processor cores and the logical core identifiers is obtained;

[0085] Wherein, N is a preset nominal value of the processor core, and when the logical core identifier is allocated, the logical core identifier is allocated in the order from logical core identifier 0 to logical core identifier N-1.

[0086] In this embodiment, the mapping relationship is constructed based on the memory affinity strategy, that is, the NUMA affinity strategy. For ease of understanding, still taking the bitmap of 0xF7 (binary is 11110111) as an example for illustration.

[0087] In the memory affinity strategy, the NUMA (Non-Uniform Memory Access) node distribution information needs to be determined first, that is, for each NUMA node, the processor cores belonging to the NUMA node are determined. For example, in an example, the NUMA node distribution information is represented as (Node0: Core0-3, Node1: Core4-7), that is, in this example, there are 2 NUMA nodes, and processor cores 0 to 3 belong to NUMA node 0, and processor cores 4 to 7 belong to NUMA node 1.

[0088] In this embodiment, the logical core identifier is allocated to each NUMA node in turn, for example, the allocation of each NUMA node is usually completed in the order of the number of the NUMA node, that is, in this example, the logical core identifier is first allocated to NUMA node 0, and then the logical core identifier is allocated to NUMA node 1.

[0089] For NUMA node 0, the logical core identifier is allocated, which specifically refers to the allocation of the logical core identifier to each unblown processor core in NUMA node 0. In addition, it needs to be pointed out that for any NUMA node, the logical ID is allocated to each unblown processor core belonging to the NUMA node in turn, which is usually allocated in the physical order of the processor core. Of course, in other embodiments, the order of allocating the logical ID to each unblown processor core in the same NUMA node can be set as needed.

[0090] And it can be understood that in the memory affinity strategy, the logical core identifier is allocated in the order from logical core identifier 0 to logical core identifier N-1 in the entire allocation process, so as to ensure that the logical ID is continuous.

[0091] In the example where the bitmap is 0xF7, for example, the processor core nominal value N is set to 6. First, the logical core identifier is allocated to NUMA node 0, specifically, the logical ID is allocated to Core0-3 in NUMA node 0. First, logical ID 0 can be allocated to Core0, then logical ID 1 is allocated to Core1, and then logical ID 2 is allocated to Core2. Core3 is blown and does not perform logical ID allocation.

[0092] Then the logical ID assignment is performed for Core 4-7 in NUMA node 1. The logical ID 3 can be assigned to Core 4, then the logical ID 4 is assigned to Core 5, then the logical ID 5 is assigned to Core 6 (the processor core nominal value N is set to 6 in this example, 6-1=5), thus the assignment can be ended, and the mapping relationship between the established processor core and logical core identifier is obtained: {0:Core0, 1:Core1, 2:Core2, 3:Core4, 4:Core5, 5:Core6}.

[0093] It can be seen that in this embodiment, the continuity of the logical ID is guaranteed under the memory affinity strategy, and the logical core identifier is assigned to each non-uniform memory access node in turn, so that the logical ID in the same NUMA node is continuous even if a processor core is fused, which has the advantage that the system can preferentially assign tasks to the cores in the local NUMA node (quickly locate through the logical ID), thereby reducing the memory access delay across the NUMA node, which is beneficial to improving the memory performance and realizing the NUMA affinity.

[0094] In a specific embodiment of the present application, the obtained logical core identifier assignment strategy includes a high-frequency core priority strategy.

[0095] Based on the bitmap and the logical core identifier assignment strategy, the mapping relationship between the processor core and the logical core identifier is established, which can include:

[0096] Based on the bitmap, each processor core that is not fused is determined.

[0097] For each preset high-frequency processor core, when the high-frequency processor core is not fused, the logical core identifier is assigned to the high-frequency processor core.

[0098] After the logical core identifier is assigned to each high-frequency processor core, the logical core identifier is assigned to each non-high-frequency processor core that is not fused.

[0099] When the assignment of the logical core identifier N is completed, the assignment is ended, and the mapping relationship between the established processor core and the logical core identifier is obtained.

[0100] Wherein, N is a preset processor core nominal value, and the logical core identifier is assigned in the order from logical core identifier 0 to logical core identifier N-1 when the logical core identifier is assigned.

[0101] In this embodiment, the mapping relationship is constructed based on the high-frequency core priority strategy. For ease of understanding, the bitmap is still taken as an example of 0xF7 (binary is 11110111).

[0102] In the high-frequency core priority strategy, it is necessary to determine which processor cores are predefined high-frequency processor cores. For example, in one example, a high-frequency core list can be obtained, specifically (Core3 is a high-frequency core), and in this example, there is one high-frequency processor core, specifically processor core Core3.

[0103] In this implementation, the logical ID allocation is prioritized for each high-frequency processor core. If there are multiple high-frequency processor cores, the order of logical ID allocation between these high-frequency processor cores can also be set according to actual needs, such as a random order, or also in the physical order of the processor cores.

[0104] After each high-frequency processor core that has not been fused is allocated a logical core identifier, each non-high-frequency processor core (i.e., a normal processor core other than a high-frequency processor core) that has not been fused can be allocated a logical ID. Similarly, the order of logical ID allocation between these non-high-frequency processor cores can also be set according to actual needs, such as a random order, or also in the physical order of the processor cores.

[0105] And it can be understood that in the high-frequency core priority strategy, the logical core identifier is allocated in the order from logical core identifier 0 to logical core identifier N-1 during the entire allocation process, thereby ensuring that the logical ID is continuous.

[0106] In the example where the bitmap is 0xF7, for example, the processor core nominal value N is set to 6. First, the logical ID allocation for processor core Core3 is required, but in this example, Core3 is fused, and there are no other high-frequency processor cores other than Core3, so it can be determined that the high-frequency processor core allocation logical ID process is complete.

[0107] Then, the logical ID needs to be allocated to each non-high-frequency processor core that has not been fused. First, Core0 is allocated a logical ID, which can be allocated to Core0, then logical ID 1 is allocated to Core1, then logical ID 2 is allocated to Core2, then logical ID 3 is allocated to Core4, then logical ID 4 is allocated to Core5, and then logical ID 5 is allocated to Core6 (in this example, the processor core nominal value N is set to 6, 6-1=5), so the allocation can be completed, and the mapping relationship between the established processor cores and logical core identifiers is obtained: {0:Core0, 1:Core1, 2:Core2, 3:Core4, 4:Core5, 5:Core6}.

[0108] As can be seen, this implementation ensures the continuity of logical IDs under the high-frequency core priority strategy, and prioritizes the allocation of logical IDs to high-frequency processor cores. This has the advantage of allowing high-performance, mission-critical tasks to utilize the more powerful high-frequency processor cores. Of course, even if a high-frequency processor core is unavailable (such as the Core 3 meltdown in the example above), logical IDs can still be allocated to non-high-frequency processor cores. The high-frequency core priority strategy can be applied to scenarios such as servers and high-performance computing where task priorities need to be dynamically adjusted.

[0109] Step S207: If fast bonding mode is enabled and the first processor core has not been fuselaged, then based on the bitmap, establish the mapping relationship between the processor core and the logical core identifier according to the default mapping method.

[0110] In this application's solution, the binding mode specifically includes a full binding mode and a fast binding mode. Enabling the fast binding mode indicates that the user has a hard requirement for core binding operations, but no other special needs. Furthermore, if the first processor core, Core0, is not melted at this time, there is no need to use the logical core identifier allocation strategy. Instead, the mapping relationship between the processor core and the logical core identifier can be established directly according to the default mapping method. Since Core0 is not melted, the mapping relationship established at this time can meet the user's hard requirement for core binding operations, and will not lead to the situation where tasks are not bound to logical thread pairs of the same processor core, thus ensuring execution efficiency.

[0111] In practical applications, when binding mode is enabled, it can be set to enable fast binding mode by default. Since the probability of Core 0 circuit breaking is very low, fast binding mode is sufficient for most scenarios. Of course, in scenarios with high reliability requirements or where users have specific needs, full binding mode can be selected.

[0112] In one specific embodiment of the present invention, it may further include:

[0113] When the first processor core melts, a processor core is selected from the remaining unmelted processor cores according to a preset selection rule;

[0114] The selected processor core is used as the boot processor, and the boot processor's log information is updated.

[0115] This implementation further considers that Core0 typically acts as the Bootstrap Processor (BSP). Therefore, when Core0 fuses, a processor core can be selected from the remaining unfuse cores using preset selection rules. For example, if Core1 is not fused, Core1 is selected as the BSP; if Core1 also fuses, Core2 can be selected, and so on. Of course, other implementations can set other specific selection rules, as long as they can effectively replace Core0 as the BSP. Furthermore, due to the BSP adjustment, the bootstrap processor's record information needs to be updated. The bootstrap processor's record information is typically located in the Multiple APIC Description Table (MADT) of the Advanced Programmable Interrupt Controller (ACPI), so updating the ACPI's MADT table is usually the primary task.

[0116] As can be seen, this implementation method has made adjustments to the BSP, which can effectively deal with the Core0 circuit breaker failure and ensure the reliability of the system.

[0117] In one specific embodiment of the present invention, after establishing the mapping relationship between processor cores and logical core identifiers based on bitmaps and logical core identifier allocation strategies, the method may further include:

[0118] Determine whether the established mapping relationship is incorrect;

[0119] If so, the mapping relationship between processor cores and logical core identifiers will be re-established based on the bitmap and logical core identifier allocation strategy.

[0120] This implementation takes into account that the present application's solution sets up a logical core identifier allocation strategy, which allows for the establishment of mapping relationships. However, in practical applications, due to program execution errors or other reasons, the established mapping relationships may be incorrect, causing subsequent related operations performed by the BIOS based on the mapping relationships to malfunction, thus affecting system reliability. Therefore, it is necessary to determine whether the established mapping relationship is incorrect. Of course, there are various specific ways to determine whether the established mapping relationship is incorrect. For example, in one specific embodiment of the present invention, determining whether the established mapping relationship is incorrect may include:

[0121] Determine whether the logical core identifiers are consecutive in the established mapping relationship;

[0122] If the logical core identifiers are not continuous, then the established mapping relationship is incorrect;

[0123] If the logical core identifiers are consecutive, then determine whether there are duplicate processor cores in the established mapping relationship;

[0124] If duplicate processor cores exist, the established mapping relationship is determined to be incorrect.

[0125] This implementation takes into account that, under normal circumstances, the established mapping relationship should have consecutive logical IDs and no duplicate processor cores. Therefore, if the logical IDs are not consecutive or duplicate processor cores appear, it can be determined that the established mapping relationship is incorrect. It can be seen that this implementation can very simply and quickly determine whether the mapping relationship is incorrect by checking whether the logical IDs are consecutive and whether duplicate processor cores exist.

[0126] If the established mapping relationship is incorrect, a rollback strategy can be executed, that is, the mapping relationship between the processor core and the logical core identifier can be re-established based on the bitmap and the logical core identifier allocation strategy.

[0127] In one specific embodiment of the present invention, it may further include:

[0128] When the mapping relationship between processor cores and logical core identifiers is repeatedly established and the established mapping relationship is always incorrect, the logical core identifier allocation strategy used is switched, and the mapping relationship between processor cores and logical core identifiers is re-established based on the bitmap and the switched logical core identifier allocation strategy.

[0129] This implementation takes into account that if the mapping relationship between processor cores and logical core identifiers is repeatedly established and the established mapping relationship is always incorrect, for example, if the mapping relationship is still incorrect after being established three times, the problem can be solved by switching the logical core identifier allocation strategy used. Furthermore, in practical applications, since the physical ordering strategy has the highest reliability and is less prone to errors, it is usually chosen when switching the logical core identifier allocation strategy.

[0130] In practical applications, the obtained mapping relationship can be stored in the L3 cache to achieve a cache-friendly design, and the allocation result of the logical ID can be aligned with a 64-byte cache line.

[0131] In one specific embodiment of the present invention, the method may further include: determining whether a custom mask is enabled; if so, generating a mapping relationship between processor cores and logical core identifiers based on the custom mask, and verifying whether the mapping relationship is erroneous. If the mapping relationship is erroneous, a logical core identifier allocation strategy can be obtained, and a mapping relationship between processor cores and logical core identifiers can be established based on the bitmap and the logical core identifier allocation strategy. In this embodiment, the mapping relationship can be established according to a user-defined mask, that is, which core maps to which logical ID is determined by the user-defined mask, thereby ensuring the application flexibility of this implementation method and meeting user needs in some situations. Furthermore, to avoid errors in the user-defined mask, the mapping relationship generated based on the custom mask is verified. If the mapping relationship generated based on the custom mask is erroneous, it indicates that the custom mask is invalid. In this case, the logical core identifier allocation strategy set in this application can be reverted, and the mapping relationship between processor cores and logical core identifiers can be established according to the logical core identifier allocation strategy.

[0132] In one specific embodiment of the present invention, it may further include:

[0133] The established mapping relationship is stored in the designated storage space in the baseboard management controller, and a secure access mechanism for the designated storage space is established.

[0134] In this implementation, the established mapping relationship is stored in a designated storage space of the BMC so that other programs can read it when needed. Furthermore, to ensure security and prevent arbitrary tampering, a secure access mechanism is established for the designated storage space; for example, only users with authorized permissions can read and write the mapping relationship in the designated storage space.

[0135] This application addresses the issue that, for users with strict core-binding requirements, using the default mapping method for each CPU can indeed lead to situations where logical threads belonging to the same processor core are incorrectly assigned to different cores, resulting in user tasks not being bound to logical threads on the same core. However, the applicant considers that this violation of the user's strict core-binding requirement only occurs when Core 0 (the first processor) fails.

[0136] In this application, a bitmap reflecting the fuse-breaking status of each processor core can be obtained. Based on the bitmap, it can be determined whether any processor cores are fuse-broken. If no fuse-broken processor cores exist, it means all processor cores are not fuse-broken. In this case, regardless of whether the user has a strict requirement for core binding, the mapping relationship between processor cores and logical core identifiers can be directly established using the default mapping method without errors. Furthermore, establishing the mapping relationship directly using the default mapping method also results in high execution efficiency. However, if a fuse-broken processor core exists, it is necessary to determine whether the user has a strict requirement for core binding, i.e., whether binding mode needs to be enabled. If binding mode is not enabled, it means the user does not have a strict requirement for core binding. Therefore, the mapping relationship between processor cores and logical core identifiers can still be established based on the bitmap using the default mapping method, ensuring execution efficiency.

[0137] If core binding mode is enabled, it indicates a strict requirement for core binding. In this case, if the first processor core does not fail (e.g., fast binding mode) and there are no special requirements, the mapping between processor cores and logical core identifiers can still be established based on the bitmap using the default mapping method, ensuring execution efficiency. In scenarios with high reliability requirements, full binding mode will be enabled. In this case, a pre-set reasonable logical core identifier allocation strategy, combined with the bitmap, will be used to establish the mapping between processor cores and logical core identifiers, ensuring high reliability of the established mapping. This mapping will prevent the abnormal situation where "logical threads that should belong to the same processor core are incorrectly assigned to different processor cores." Furthermore, if the user has a strict requirement for core binding and the first processor core fails (e.g., fails), it should also be considered that full binding mode is enabled. This will ensure high reliability of the established mapping by using a pre-set reasonable logical core identifier allocation strategy combined with the bitmap, preventing abnormal situations.

[0138] In summary, the proposed solution can efficiently obtain mapping relationships that meet user needs based on their requirements. When users have a strict requirement for core-binding operations, the obtained mapping relationship is highly reliable, thus avoiding abnormal situations. Furthermore, it can be seen that the proposed solution can effectively address the various situations mentioned above, obtaining mapping relationships that meet user needs without requiring the replacement of CPUs on the entire machine production line, which helps reduce maintenance costs.

[0139] Corresponding to the above methods and system embodiments, this invention also provides an electronic device, a computer-readable storage medium, and a computer program product, which can be referred to in conjunction with the above.

[0140] See Figure 3 As shown, the device may include:

[0141] Memory 301 is used to store computer programs;

[0142] Processor 302 is configured to execute a computer program to implement the steps of the processor topology mapping management method as described in any of the above embodiments.

[0143] The computer program product includes a computer program / instruction that, when executed by a processor, implements the steps of the processor topology mapping management method as described in any of the above embodiments.

[0144] See also Figure 4 The computer-readable storage medium 40 stores a computer program 41, which, when executed by a processor, implements the steps of the processor topology mapping management method as described in any of the above embodiments. The computer-readable storage medium 40 referred to herein includes RAM (Random Access Memory), main memory, ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), registers, hard disks, removable disks, or any other form of storage medium known in the art.

[0145] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0146] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for managing processor topology mapping, characterized in that, include: Obtain a bitmap that reflects the fuse-out state of each processor core; Based on the bitmap, determine whether there is a processor core that has experienced a meltdown; If it does not exist, then based on the bitmap, establish the mapping relationship between the processor core and the logical core identifier according to the default mapping method; If it exists, determine whether to enable the binding mode; wherein, the binding mode includes full binding mode and quick binding mode; If the binding mode is not enabled, the mapping relationship between the processor core and the logical core identifier is established based on the bitmap according to the default mapping method; If the full binding mode and / or the first processor core fuse is enabled, the logical core identifier allocation strategy is obtained, and a mapping relationship between the processor core and the logical core identifier is established based on the bitmap and the logical core identifier allocation strategy. If fast bonding mode is enabled and the first processor core does not fuse, then based on the bitmap, a mapping relationship between the processor core and the logical core identifier is established according to the default mapping method. The acquisition of logical core identifier allocation strategies includes physical order strategies; Based on the bitmap and the logical core identifier allocation strategy, a mapping relationship between processor cores and logical core identifiers is established, including: The individual processor cores that did not fuse were identified based on the bitmap; For each of the identified processor cores that have not been fused, logical core identifiers are assigned to each of the processor cores in the order of their physical order. When the allocation of the logical core identifier N is completed, the allocation ends, and the established mapping relationship between the processor core and the logical core identifier is obtained. Where N is the preset nominal value of the processor core. When allocating logical core identifiers, the logical core identifiers are allocated in the order from logical core identifier 0 to logical core identifier N-1.

2. The processor topology mapping management method according to claim 1, characterized in that, Also includes: When the first processor core melts, a processor core is selected from the remaining unmelted processor cores according to a preset selection rule; The selected processor core is used as the boot processor, and the boot processor's record information is updated.

3. The processor topology mapping management method according to claim 1, characterized in that, Obtain a bitmap reflecting the fuse-out state of each processor core, including: Determine whether the first storage space contains a bitmap that reflects the fuse-out state of each processor core; If so, the bitmap is read from the first storage space; If not, a bitmap reflecting the fuse-out state of each processor core is obtained by detection, and the bitmap is stored in the first storage space.

4. The processor topology mapping management method according to claim 3, characterized in that, The process involves detecting and acquiring a bitmap reflecting the fuse state of each processor core, and storing the bitmap in the first storage space, including: By reading the specified registers of each processor core in parallel, the fuse status of each processor core can be obtained. Based on the obtained fuse states of each processor core, a bitmap reflecting the fuse states of each processor core is generated, and the bitmap is stored in the first storage space.

5. The processor topology mapping management method according to claim 1, characterized in that, After establishing the mapping relationship between processor cores and logical core identifiers based on the bitmap and the logical core identifier allocation strategy, the method further includes: Determine whether the established mapping relationship is incorrect; If so, the mapping relationship between the processor core and the logical core identifier is re-established based on the bitmap and the logical core identifier allocation strategy.

6. The processor topology mapping management method according to claim 5, characterized in that, Determining whether the established mapping relationship is erroneous includes: Determine whether the logical core identifiers are continuous in the established mapping relationship; If the logical core identifiers are not continuous, then the established mapping relationship is incorrect; If the logical core identifiers are consecutive, then determine whether there are duplicate processor cores in the established mapping relationship; If duplicate processor cores exist, the established mapping relationship is determined to be incorrect.

7. The processor topology mapping management method according to claim 5, characterized in that, Also includes: When the mapping relationship between processor cores and logical core identifiers is repeatedly established and the established mapping relationship is always incorrect, the logical core identifier allocation strategy used is switched, and the mapping relationship between processor cores and logical core identifiers is re-established based on the bitmap and the switched logical core identifier allocation strategy.

8. The processor topology mapping management method according to claim 1, characterized in that, Also includes: The established mapping relationship is stored in a designated storage space in the baseboard management controller, and a secure access mechanism for the designated storage space is established.

9. The processor topology mapping management method according to claim 1, characterized in that, Also includes: Based on the bitmap and the individual disabled status of each processor core, add status flags to each processor core; Specifically, for any processor core, when the processor core is not melted and is not disabled, the status flag added to the processor core is a status flag used to indicate that the processor core is available; When the processor core is fused and / or not disabled, a status flag is added to the processor core to indicate that the processor core is unavailable.

10. The processor topology mapping management method according to any one of claims 1 to 9, characterized in that, The acquisition of logical core identifier allocation strategies includes memory affinity strategies; Based on the bitmap and the logical core identifier allocation strategy, a mapping relationship between processor cores and logical core identifiers is established, including: The individual processor cores that did not fuse were identified based on the bitmap; Logical core identifiers are assigned to each non-uniform memory access node in the order of their numbering. For any non-uniform memory access node, logical core identifiers are assigned to each non-fuse-out processor core belonging to that non-uniform memory access node in turn. When the allocation of the logical core identifier N is completed, the allocation ends, and the established mapping relationship between the processor core and the logical core identifier is obtained. Where N is the preset nominal value of the processor core. When allocating logical core identifiers, the logical core identifiers are allocated in the order from logical core identifier 0 to logical core identifier N-1.

11. The processor topology mapping management method according to any one of claims 1 to 9, characterized in that, The acquired logical core identifier allocation strategy includes a high-frequency core priority strategy; Based on the bitmap and the logical core identifier allocation strategy, a mapping relationship between processor cores and logical core identifiers is established, including: The individual processor cores that did not fuse were identified based on the bitmap; For each preset high-frequency processor core, when the high-frequency processor core is not blown, a logical core identifier is assigned to the high-frequency processor core; After allocating a logical core identifier to each high-frequency processor core, assign logical core identifiers to each non-high-frequency processor core that has not been fused. When the allocation of the logical core identifier N is completed, the allocation ends, and the established mapping relationship between the processor core and the logical core identifier is obtained. Where N is the preset nominal value of the processor core. When allocating logical core identifiers, the logical core identifiers are allocated in the order from logical core identifier 0 to logical core identifier N-1.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the processor topology mapping management method as described in any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the processor topology mapping management method as described in any one of claims 1 to 11.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the processor topology mapping management method as described in any one of claims 1 to 11.

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