System, method and device for automatically building UVM verification environment and storage medium
By automatically building a UVM verification environment system and using scripts to automatically generate components and virtual sequencers for testing, the problems of low automation and insufficient flexibility in existing technologies are solved, and an efficient and standardized verification environment is achieved.
Patent Information
- Application Number
- CN202510588483.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-09-19
AI Technical Summary
Existing technologies have low automation, low efficiency, and insufficient flexibility when building UVM verification environments. They rely on manual writing and specific tools, which easily introduces misoperations and results in insufficient functionality and scalability of the verification environment.
By automatically building a UVM verification environment system, using scripts to automatically generate components, and combining virtual sequencers and reference models for testing, automated and efficient testing is achieved. Functional error verification and coverage verification are performed by comparing components, reducing dependence on specific EDA tools.
It achieves a high degree of automation, fast verification speed, standardized and stable verification environment, reduces manual operation errors, and improves verification efficiency and flexibility.
Smart Images
Figure CN120670288A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of functional verification, and in particular to a system, method, device and storage medium for automatically building a UVM verification environment. Background Art
[0002] UVM stands for Universal Verification Methodology. It is based on the System Verilog language and combines the components required in a conventional verification environment to create a rich and scalable verification framework and environment construction mechanism.
[0003] Currently, there are two main ways to build a UVM verification environment. One is to manually write components such as uvm_env and uvm_agent. The other is to use specific commercial verification platforms such as EDA to automatically build part of the verification environment, and then combine it with manual writing to finally generate a complete verification environment.
[0004] However, the above method has at least the following three problems when building a UVM verification environment: 1) Although manual writing is highly flexible, it has a low degree of automation and low efficiency. It relies too much on the individual skills of the programmer and is prone to human error. 2) The combination of commercial platforms and manual coding results in a low degree of automation, limited flexibility, and reliance on specific EDA tools; 3) The integration between the verification environment and verification tools is insufficient, and the functionality and scalability of the environment may also be insufficient. Summary of the Invention
[0005] In response to the above three problems, the purpose of the present invention is to propose a system, method, device and storage medium for automatically building a UVM verification environment. Components for testing can be automatically generated and connected through scripts to achieve automated and efficient testing, without relying on specific EDA tools for platform and manual writing. A virtual sequencer is also used to control the unit under test and the reference model to be tested separately, and functional error verification and coverage verification are performed in the comparison component. The system has a high degree of automation, a fast verification speed, and a standardized and stable verification environment.
[0006] This is achieved through the following technical solutions: Firstly, a system for automatically building a UVM verification environment is proposed, which includes a reference model, a comparison component, a virtual sequencer, multiple transaction components II, multiple connection points and a unit under test; the comparison component includes multiple scoreboards, each of which is connected to the reference model, and each scoreboard is used to compare each expected value of the reference model with each actual result corresponding to the unit under test, to determine and record whether there is a functional error; wherein, the virtual sequencer is used to generate stimulus and transmit it to the unit under test and the reference model respectively, the multiple scoreboards include at least one scoreboard I and multiple scoreboards II, each scoreboard I is connected to the virtual sequencer, and each transaction component II is connected to each scoreboard II in a one-to-one correspondence; the virtual sequencer and each transaction component II are respectively connected to the unit under test through corresponding connection points, and are used to obtain the actual result of each corresponding actual test of the unit under test and transmit it to the corresponding scoreboard after receiving each input instruction of the user. At the same time, the virtual sequencer also controls the reference model to output each expected value based on each input instruction of the user.
[0007] Preferably, the virtual sequencer includes at least an A transaction component I and a B transaction component I, and the A transaction component I and the B transaction component I are respectively connected to the reference model and are respectively connected to at least one scoreboard I.
[0008] Preferably, the A transaction component I includes an A input end and an A output end; the A input end includes a sequence generator 1, an excitation driver 1, a monitor 1 and a virtual interface 1, and the A output end includes a monitor 2 and a virtual interface 2, both virtual interfaces 1 and 2 are connected to the unit under test through a connection point A, monitor 1 is connected to a reference model, and monitor 2 is connected to an unused scoreboard I.
[0009] Preferably, the B transaction component I includes a B input end and a B output end, the B input end includes a sequence generator 2, an excitation driver 2, a monitor 3 and a virtual interface 3, the B output end includes a read monitor, a write monitor and a virtual interface 4, the read monitor and the write monitor are each connected to an unused scoreboard I, and the virtual interface 3 and the virtual interface 4 are both connected to the unit under test through the connection point B.
[0010] Preferably, both A transaction component I and B transaction component I are active components, and each transaction component II is a passive component.
[0011] Preferably, each transaction component II includes a monitor II, an excitation driver II and a virtual interface II, each monitor II is connected to a corresponding scoreboard, each excitation driver II can be turned on or off independently, and each virtual interface II is connected to the unit under test through a corresponding connection point.
[0012] Preferably, a plurality of coverage collectors are further included, each coverage collector is connected to each corresponding scoreboard, and at the same time, based on each expected value, the test coverage of each actual result is calculated.
[0013] Secondly, a method for automatically building a UVM verification environment is also proposed, which uses a system for automatically building a UVM verification environment as described in any of the above items to run, including the following steps: S1. The virtual sequencer receives each input instruction from the user, generates each transaction operation to be executed, and sends each transaction operation to the unit under test and the reference model simultaneously; S2. The unit under test outputs each expected value based on each transaction operation in step S1 and transmits it to the comparison component; the unit under test outputs each actual result of the actual test based on each transaction operation and transmits it to the comparison component via the virtual sequence transmitter or multiple transaction components II; S3. In the comparison component, each expected value in step S2 is compared with each corresponding actual result, the test coverage is recorded, and whether there are any functional errors is determined and recorded.
[0014] Furthermore, a device is proposed, including a processor and a memory, wherein the memory is used to store a program, and the processor is configured to execute the above-mentioned method of automatically building a UVM verification environment according to the program.
[0015] In addition, a storage medium is also proposed, in which a computer program is stored. When the computer program runs in a processor, the processor is used to execute the above-mentioned method for automatically building a UVM verification environment.
[0016] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention can automatically generate and connect test components through scripts to achieve automated and efficient testing, without relying on specific EDA tools for platform and manual writing; it also controls the unit to be tested and the reference model through a virtual sequence generator to perform tests separately, and performs functional error verification and coverage verification in the comparison components, with a high degree of automation, fast verification speed, and a standardized and stable verification environment. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 This is a schematic diagram of the architecture for building a UVM verification environment. DETAILED DESCRIPTION
[0018] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.
[0019] like Figure 1The figure shows an architecture diagram for building a UVM verification environment. The architecture mainly includes a reference model, a virtual sequencer, a comparison component, multiple connection points, a unit under test, and multiple transaction components II. The reference model is an equivalent component of the function that the unit under test wants to test. By inputting the same input instructions into the reference model to obtain the expected value, and inputting the same input instructions into the unit under test to obtain the actual test result, and comparing the two, the verification result can be quickly and efficiently known. At the same time, the user only needs to input the corresponding instructions in the virtual sequencer to automatically obtain the verification test result in the comparison component.
[0020] In this embodiment, the comparison component includes multiple scoreboards, each of which is connected to the reference model and is used to receive each expected value output by the reference model. Each scoreboard also receives each actual result of the unit under test through the output end of the virtual sequence generator or multiple transaction components II, thereby comparing each expected value with the corresponding actual result to determine and record whether there is a functional error.
[0021] In this embodiment, a virtual sequencer is used to generate stimuli and transmit them to the UUT and reference model, respectively. The virtual sequencer includes at least two transaction components I, including, for example, transaction component A I and transaction component B I. Both transaction components I are active components, that is, components capable of generating stimuli. Transaction component A I includes an A input and an A output. The A input includes a sequencer 1, a stimulus driver 1, a monitor 1, and a virtual interface 1. The A output includes a monitor 2 and a virtual interface 2. Both virtual interfaces 1 and 2 are connected to the UUT via connection point A. Monitor 1 is connected to the reference model, and monitor 2 is connected to an unused scoreboard 1. Transaction component B I includes a B input and a B output. The B input includes a sequencer 2, a stimulus driver 2, a monitor 3, and a virtual interface 3. The B output includes a read monitor, a write monitor, and a virtual interface 4. The read monitor and the write monitor are each connected to an unused scoreboard 1. Both virtual interfaces 3 and 4 are connected to the UUT via connection point B.
[0022] In this embodiment, each transaction component II includes a monitor II, an excitation driver II, and a virtual interface II. Each monitor II is connected to a corresponding scoreboard II. Each excitation driver II can be freely set to an off or on state. Each virtual interface II is connected to the unit under test via a corresponding connection point. Each transaction component II is a passive component, that is, a component that cannot actively generate excitation. When the unit under test outputs a result from one or more specific functional ports, it connects to a corresponding functional port through these transaction components II to complete the transmission task. Each excitation driver II can be set to a closed state by default. If it needs to receive external instructions, it can be opened for connection and use.
[0023] It should be noted that among the multiple scoreboards, the number of scoreboards I and II can be adjusted freely, but it is necessary to at least meet the demand for scoreboard usage when the virtual sequence generator and multiple transaction components II transmit the comparison results. The monitor II in each transaction component II and each scoreboard II are connected one-to-one.
[0024] Still taking the use of transaction component A II and transaction component B II as an example, at this time, multiple scoreboards I include scoreboards 1, 2 and 3, transaction component A I is connected to the reference model and scoreboard 1 respectively, and the read monitor and write monitor in transaction component B I are connected to scoreboards 2 and 3 respectively; transaction component A I, transaction component B I and each transaction component II are respectively connected to the unit under test through corresponding connection points, and are used to obtain the actual results of each corresponding actual test of the unit under test and transmit them to the corresponding scoreboards after receiving each input instruction from the user. At the same time, the reference model is controlled to output each expected value based on each input instruction from the user.
[0025] It should be noted that each sequencer generates stimuli based on the instructions input by the user and is responsible for generating the corresponding transaction operation sequence, defining which transactions should be executed and in what order. The stimulus driver, also known as the stimulator, converts the content generated by the sequencer into specific operational instructions. These instructions are then sent to the reference model for execution via the corresponding input monitor and to the unit under test via a virtual interface. The output monitor then monitors the results of the unit under test and transmits them to the corresponding scoreboard. It also tracks the status of transaction execution in real time, collecting various data such as response time, execution sequence, and performance metrics. After comparison in the scoreboard, if anomalies are detected or the comparison results are incorrect, an alert is issued. Furthermore, if the stimuli generated by the sequencer can be directly recognized and executed by the reference model and the unit under test, they can be transmitted directly without going through the input monitor, leaving the input monitor in a disabled state.
[0026] In addition, the unit under test has multiple different functional ports. After the unit under test performs any operation, the result of the operation may be transmitted through one or more functional ports, and it may be required to transmit the results together or output the results in different forms of reading and writing. That is, it may be output through output terminal A or output terminal B, or it may be output through one or two or more of C transaction component II, D transaction component II and E transaction component II in transaction component II as the output path. The specific path selection needs to be made according to the structure and function of each transaction component to meet the output requirements of the unit under test.
[0027] In addition, each transaction component II can also use its own monitor II to further monitor the connected parts, so that omissions can be discovered in time to complete the verification work in a clear and orderly manner.
[0028] In the present embodiment, when setting up the UVM verification environment, multiple coverage collectors can also be set, each coverage collector is respectively connected to each scoreboard, and the test completeness of each actual result is determined based on each expected value, that is, the coverage consideration of the test function, and the test coverage of each user input instruction is known, so that the comparison result is more complete and comprehensive.
[0029] This architecture can be automatically constructed through existing scripts. After the user enters specific instructions in the script, the input instructions will contain configuration information such as the components he wants to use, such as which interfaces, monitors, stimulus drivers, transaction components II, and the number and names of components, as well as the specific operations he wants to test. The script will then automatically generate the corresponding components and connect these components according to the aforementioned architecture. Then, based on the specific operations he wants to test, the corresponding stimulus driver will generate the corresponding stimulus and start transmitting it for automatic testing, so that he can quickly view the corresponding test results in the comparison component.
[0030] Secondly, a method for automatically building a UVM verification environment is also proposed, which uses a system for automatically building a UVM verification environment as described above to run, including the following steps: S1. The virtual sequencer receives each input instruction from the user, generates each transaction operation to be executed, and sends each transaction operation to the unit under test and the reference model simultaneously; S2. The unit under test outputs each expected value based on each transaction operation in step S1 and transmits it to the comparison component; the unit under test outputs each actual result of the actual test based on each transaction operation and transmits it to the comparison component via the virtual sequence transmitter or multiple transaction components II; S3. In the comparison component, compare each expected value in step S2 with each corresponding actual result, record the test coverage, determine and record whether there are any functional errors, and issue a timely alarm when any errors are found.
[0031] Secondly, an electronic device is also proposed, including a processor and a memory, the memory is used to store a program, and the processor is configured to execute the above-mentioned method of automatically building a UVM verification environment according to the program.
[0032] In addition, a readable storage medium is also proposed, in which a computer program is stored. When the computer program runs in a processor, the processor is used to execute the above-mentioned method for automatically building a UVM verification environment.
[0033] In summary, the present invention can automatically generate and connect test components through scripts to achieve automated and efficient testing. Users only need to enter corresponding instructions in the virtual sequencer to automatically obtain results in the comparison component, effectively reducing the risk of errors introduced by manual operation, and no longer need to rely on specific EDA tools for platform and manual writing; the virtual sequencer is also used to control the unit to be tested and the reference model to be tested separately, and functional error verification and coverage verification are performed in the comparison component. The degree of automation is high, the verification speed is fast, the verification environment is standardized and stable, and it has significant progress.
[0034] The above embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.
Claims
1. A system for automatically building a UVM verification environment, characterized in that: The system includes a reference model, a comparison component, a virtual sequencer, multiple transaction components II, multiple connection points, and a unit under test. The comparison component includes multiple scoreboards, each of which is connected to the reference model. Each scoreboard is used to compare each expected value of the reference model with each actual result corresponding to the unit under test to determine and record whether there is a functional error. Among them, the virtual sequence generator is used to generate stimuli and transmit them to the unit under test and the reference model respectively. The multiple scoreboards include at least one scoreboard I and multiple scoreboards II. Each scoreboard I is connected to the virtual sequence generator, and each transaction component II is connected to each scoreboard II in a one-to-one correspondence. The virtual sequence generator and each transaction component II are respectively connected to the unit under test through corresponding connection points, and are used to obtain the actual results of each corresponding actual test of the unit under test and transmit them to the corresponding scoreboards after receiving each input instruction from the user. At the same time, the virtual sequence generator also controls the reference model to output each expected value based on each input instruction from the user.
2. A system for automatically building a UVM verification environment according to claim 1, characterized in that, The virtual sequencer includes at least an A transaction component I and a B transaction component I. The A transaction component I and the B transaction component I are respectively connected to a reference model and are respectively connected to at least one scoreboard I.
3. A system for automatically setting up a UVM verification environment according to claim 2, characterized in that, The A transaction component I includes an A input terminal and an A output terminal; the A input terminal includes a sequence generator 1, an excitation driver 1, a monitor 1 and a virtual interface 1, and the A output terminal includes a monitor 2 and a virtual interface 2. Both virtual interfaces 1 and 2 are connected to the unit under test through connection point A. Monitor 1 is connected to the reference model, and monitor 2 is connected to an unused scoreboard I.
4. A system for automatically building a UVM verification environment according to claim 2, characterized in that, The B transaction component I includes a B input end and a B output end. The B input end includes a sequence generator 2, an excitation driver 2, a monitor 3 and a virtual interface 3. The B output end includes a read monitor, a write monitor and a virtual interface 4. The read monitor and the write monitor are each connected to an unused scoreboard I. The virtual interface 3 and the virtual interface 4 are both connected to the unit under test through the connection point B.
5. A system for automatically setting up a UVM verification environment according to claim 2, characterized in that, A transaction component I and B transaction component I are both active components, and each transaction component II is a passive component.
6. A system for automatically building a UVM verification environment according to claim 1, characterized in that, Each transaction component II includes a monitor II, an excitation driver II and a virtual interface II. Each monitor II is connected to a corresponding scoreboard, each excitation driver II can be turned on or off independently, and each virtual interface II is connected to the unit under test through a corresponding connection point.
7. A system for automatically building a UVM verification environment according to claim 1, characterized in that, It also includes multiple coverage collectors, each coverage collector is connected to each corresponding scoreboard, and at the same time, based on each expected value, calculates the test coverage of each actual result.
8. A method for automatically setting up a UVM verification environment, comprising: operating the system for automatically setting up a UVM verification environment as claimed in any one of claims 1 to 7, wherein: The steps include: S1. The virtual sequencer receives each input instruction from the user, generates each transaction operation to be executed, and sends each transaction operation to the unit under test and the reference model simultaneously; S2. The unit under test outputs each expected value based on each transaction operation in step S1 and transmits it to the comparison component; The unit under test outputs each actual result of the actual test based on each transaction operation and transmits it to the comparison component via the virtual sequence transmitter or multiple transaction components II; S3. In the comparison component, each expected value in step S2 is compared with each corresponding actual result, the test coverage is recorded, and whether there are any functional errors is determined and recorded.
9. A device, characterized in that The method comprises a processor and a memory, wherein the memory is used to store a program, and the processor is configured to execute the method for automatically building a UVM verification environment according to claim 8 according to the program.
10. A storage medium, characterized in that: The storage medium stores a computer program. When the computer program runs in the processor, the processor is used to execute the method for automatically building a UVM verification environment as claimed in claim 8.