Chip verification method and device, equipment and storage medium

Abstract

The invention discloses a chip verification method, device and equipment and a storage medium, and relates to the field of chip verification, and the method comprises the steps: constructing corresponding sub-reference models based on the unassigned input signals and output signals of each composition module in a to-be-tested chip, so as to obtain a target reference model corresponding to the to-be-tested chip; in a chip verification process, assigning the input excitation signal value to an input signal of a corresponding composition module in the chip to be tested so as to carry out signal processing, and obtaining a simulation signal value of each composition module; assigning the input excitation signal value to an input signal of a corresponding sub-reference model in the target reference model so as to carry out signal processing, and obtaining an expected signal value of each sub-reference model; each of the simulation signal value and the expected signal value comprises an input signal value and an output signal value; and comparing the simulation signal value of each composition module with the expected signal value of each sub-reference model to verify the to-be-tested chip, and accurately positioning a specific error module when the chip verification has an error.

Description

Technical Field

[0001] This invention relates to the field of chip verification, and in particular to a chip verification method, apparatus, device, and storage medium. Background Technology

[0002] In traditional chip verification processes, the reference model functions to mimic the behavior of the design under test (DUT), i.e., the chip under test. The reference model acquires the input stimuli and configuration of the DUT, performs calculations using a pre-built algorithm model, and then transmits the expected output to the scoreboard. The scoreboard compares the expected output of the reference model with the actual output of the DUT. When the scoreboard detects a discrepancy between the expected output of the reference model and the actual output of the DUT, it marks the chip verification as a failure or error. After ruling out issues with the verification environment, the problem can be identified as a register-transfer level (RTL) issue in the chip design.

[0003] However, the reference model implements the functionality of the design under test (DUT) using a holistic algorithm, omitting most of the hardware design details within the DUT. Therefore, when the expected output of the reference model differs from the actual output of the DUT, it can only roughly determine that the chip verification has failed, but it is difficult to accurately pinpoint the specific faulty module within the chip. Clearly, accurately locating the specific faulty module when chip verification fails is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a chip verification method, apparatus, device, and storage medium. It constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test, and compares the input and output signal values ​​of each component module with the corresponding sub-reference model to determine if chip verification has failed, and accurately locates the specific faulty module when verification fails. The specific solution is as follows:

[0005] In a first aspect, the present invention provides a chip verification method, comprising:

[0006] After pre-constructing a target reference model corresponding to the chip under test, the input excitation signal value is obtained; each sub-reference model in the target reference model is a model constructed based on the input and output signals of each component module in the chip under test; the input and output signals of each component module are unassigned signals;

[0007] The input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test for signal processing, and the simulation signal value of each component module is obtained.

[0008] The input excitation signal value is assigned to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and the expected signal value of each sub-reference model is obtained; wherein, the simulation signal value and the expected signal value both include the input signal value and the output signal value;

[0009] The chip under test is verified by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

[0010] Optionally, the input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test for signal processing, and the simulation signal value of each component module is obtained, including:

[0011] The input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test for signal processing. After each component module has completed signal processing, the simulation waveform file generated by the chip under test is obtained.

[0012] The simulation waveform file is parsed to obtain the simulation signal values ​​of each component module.

[0013] Optionally, the simulation waveform file is parsed to obtain the simulation signal values ​​of each component module, including:

[0014] Based on preset control parameters, the simulation waveform file is parsed to obtain the simulation signal values ​​of each component module, and the simulation signal values ​​of each component module are transmitted to a preset file for saving according to the preset output bit width.

[0015] The preset control parameters include specified signal control parameters and / or time interval control parameters; the specified signal control parameters are used to control the simulation signal value of the specified signal parsed from the simulation waveform file; the specified signal includes input signal and output signal; the time interval control parameters are used to control the simulation signal value within the corresponding time interval parsed from the simulation waveform file.

[0016] Optionally, the chip under test can be verified by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model, including:

[0017] If the simulated signal value of any component module differs from the expected signal value of the target sub-reference model, then it is determined that the verification of any component module has failed, and the implementation code of any component module is analyzed to determine the cause of the failure.

[0018] In this context, any component module refers to any one of the component modules; the target sub-reference model is the sub-reference model corresponding to any component module.

[0019] Optionally, the implementation code of any component module may be analyzed to determine the cause of an error in that component module, including:

[0020] Based on the existence of different signal values ​​between any component module and the target sub-reference model, determine the error type of any component module that fails verification.

[0021] By utilizing error types, the corresponding error code can be determined from the implementation code of any component module;

[0022] Analyze the error codes to determine the cause of the error in any component module.

[0023] Optionally, the expected signal values ​​of each sub-reference model are stored in array form.

[0024] Optional, the process of constructing the target reference model includes:

[0025] Identify the constituent modules of the chip under test;

[0026] Obtain the input and output signals of each component module from the configuration information of each component module; where the input and output signals of each component module are unassigned signals.

[0027] A target signal table is constructed based on the input and output signals of each component module; each row of data in the target signal table includes the module name, input signal, and output signal of each component module.

[0028] Based on the input and output signals of each component module, analyze the implementation logic of each component module;

[0029] Based on the data in each row of the target signal table and the implementation logic of each component module, a sub-reference model corresponding to each component module is constructed.

[0030] By utilizing the signal connection relationships of each component module, the signal connections of each sub-reference model are made to obtain the target reference model.

[0031] In a second aspect, the present invention provides a chip verification apparatus, comprising:

[0032] The excitation signal value acquisition module is used to acquire the input excitation signal value after a target reference model corresponding to the chip under test is pre-built. Each sub-reference model in the target reference model is a model built based on the input and output signals of each component module in the chip under test. The input and output signals of each component module are unassigned signals.

[0033] The simulation signal value acquisition module is used to assign the input excitation signal value to the input signal of the corresponding component module in the chip under test for signal processing, and to acquire the simulation signal value of each component module.

[0034] The expected signal value acquisition module is used to assign the input excitation signal value to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and to acquire the expected signal value of each sub-reference model; wherein, both the simulation signal value and the expected signal value include the input signal value and the output signal value;

[0035] The chip verification module is used to verify the chip under test by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

[0036] Thirdly, the present invention provides an electronic device, comprising:

[0037] Memory, used to store computer programs;

[0038] A processor is used to execute a computer program to implement the steps of the aforementioned chip verification method.

[0039] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned chip verification method.

[0040] In this invention, after pre-constructing a target reference model corresponding to the chip under test, input excitation signal values ​​are obtained. Each sub-reference model in the target reference model is a model constructed based on the input and output signals of each component module in the chip under test. The input and output signals of each component module are unassigned signals. The input excitation signal values ​​are assigned to the input signals of the corresponding component modules in the chip under test for signal processing, and the simulated signal values ​​of each component module are obtained. The input excitation signal values ​​are assigned to the input signals of the corresponding sub-reference models in the target reference model for signal processing, and the expected signal values ​​of each sub-reference model are obtained. The simulated signal values ​​and expected signal values ​​both include input signal values ​​and output signal values. The chip under test is verified by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

[0041] Beneficial effects: This invention pre-constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test (DUT). Then, based on the sub-reference models corresponding to each component module in the DUT, a target reference model corresponding to the DUT is constructed. This allows the target reference model to focus on the internal structure of the DUT. During the DUT verification process, the expected input and output signal values ​​of each sub-reference model can be obtained through the target reference model. By comparing the expected input and output signal values ​​of each sub-reference model with the simulated input and output signal values ​​of each component module, not only can the consistency of the signal value comparison determine whether the chip verification has failed, but the specific faulty module can also be accurately located, thus improving the accuracy of chip verification. Attached Figure Description

[0042] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A flowchart of a chip verification method provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a verification platform provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of the signal connection relationship of each component module in a chip under test provided by an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram illustrating the signal connection relationship of each sub-reference model in a target reference model provided in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of a chip verification device provided in an embodiment of the present invention;

[0048] Figure 6 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0050] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0051] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] In traditional chip verification processes, the reference model implements the functionality of the design under test (DUT) using a holistic algorithm, omitting most of the hardware design details. Therefore, when the expected output of the reference model differs from the actual output of the DUT, only a rough determination of a chip verification error can be made, but it's difficult to accurately pinpoint the specific faulty module within the chip. To address this, this invention provides a chip verification method that constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test. The method then compares the input and output signal values ​​of each component module with the corresponding sub-reference model to determine if a chip verification error has occurred, and accurately locates the specific faulty module when an error occurs.

[0053] See Figure 1 As shown, an embodiment of the present invention provides a chip verification method, including:

[0054] Step S11: After pre-constructing the target reference model corresponding to the chip under test, obtain the input excitation signal value; each sub-reference model in the target reference model is a model constructed based on the input and output signals of each component module in the chip under test; the input and output signals of each component module are unassigned signals.

[0055] In this embodiment of the invention, corresponding sub-reference models are pre-constructed based on the unassigned input and output signals of each component module in the chip under test (DUT). A target reference model corresponding to the DUT is then constructed based on the sub-reference models corresponding to each component module. After constructing the target reference model corresponding to the DUT, the chip verification process begins. Specifically, a simulation tool is first invoked to execute test cases, thereby driving the stimulus generator to generate input stimulus signal values.

[0056] It should be noted that the construction process of the target reference model corresponding to the chip under test may specifically include: determining each component module of the chip under test; obtaining the input and output signals of each component module from the configuration information of each component module; wherein, the input and output signals of each component module are unassigned signals; constructing a target signal table based on the input and output signals of each component module; wherein, each row of data in the target signal table includes the module name, input signal, and output signal of each component module; analyzing the implementation logic of each component module based on the input and output signals of each component module; constructing sub-reference models corresponding to each component module based on the data in each row of the target signal table and the implementation logic of each component module; and connecting the sub-reference models using the signal connection relationships of each component module to obtain the target reference model corresponding to the chip under test.

[0057] Specifically, according to the module design of the chip under test (DUT), the DUT is divided into multiple component modules. The unassigned input and output signals of each component module are extracted from its configuration information. A target signal table is then constructed based on these unassigned input and output signals. Each row in the target signal table corresponds one-to-one with a component module in the DUT; that is, each row includes the module name, input signal, and output signal of a component module. The target signal table is shown in Table 1 below.

[0058] Table 1 Target Signal Table

[0059]

[0060] Furthermore, since the sub-reference model only implements the same logical functions as the component modules, meaning the sub-reference model functions identically to the corresponding component modules, the sub-reference model does not need to concern itself with the actual code implementation of the component modules. Therefore, by analyzing the input and output signals of each component module, the implementation logic of each component module is determined. Then, based on the data in each row of the target signal table and the implementation logic of each component module, a sub-reference model corresponding to each component module is constructed. Finally, according to the signal connection relationship of each component module in the chip under test, the sub-reference models are connected to obtain the target reference model corresponding to the chip under test.

[0061] Step S12: Assign the input excitation signal value to the input signal of the corresponding component module in the chip under test for signal processing, and obtain the simulation signal value of each component module.

[0062] In this embodiment of the invention, the input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test by the driver for signal processing, and the simulation input signal value and simulation output signal value of each component module in the chip under test are obtained.

[0063] According to one specific example, the input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test by the driver for signal processing. After the signal processing of each component module in the chip under test is completed, the simulation waveform file generated by the chip under test is obtained. The simulation waveform file is parsed to obtain the simulation signal value of each component module. The simulation signal value includes the simulation input signal value and the simulation output signal value.

[0064] For example, after each component module in the chip under test has completed signal processing, the simulation waveform file generated by the chip under test is obtained, such as the FSDB (Fast Signal DataBase, a binary waveform file format) waveform file. The simulation input signal value and simulation output signal value of each component module are extracted from the simulation waveform file using the fsdbreport (a tool for extracting signal data from FSDB waveform files).

[0065] Specifically, in the process of parsing the simulation waveform file to obtain the simulation signal values ​​of each component module, the simulation waveform file can also be parsed based on preset control parameters to obtain the simulation signal values ​​of each component module, and the simulation signal values ​​of each component module can be transmitted to a preset file for saving according to the preset output bit width.

[0066] The preset control parameters include specified signal control parameters and / or time interval control parameters; the specified signal control parameters are used to control the simulation signal value of the specified signal parsed from the simulation waveform file; the specified signal includes input signal and output signal; the time interval control parameters are used to control the simulation signal value within the corresponding time interval parsed from the simulation waveform file.

[0067] In one specific example, based on specified signal control parameters, the simulation waveform file is parsed to extract the simulation signal values ​​of the input and output signals of each component module, thereby obtaining the simulation input and output signal values ​​of each component module.

[0068] In another specific example, based on specified signal control parameters and time interval control parameters, the simulation waveform file is parsed to extract the simulation signal values ​​of the input and output signals of each component module within the corresponding time interval, thereby obtaining the simulation input signal values ​​and simulation output signal values ​​of each component module.

[0069] It should be noted that the preset output bit width can be set according to the actual transmission load and actual computing resources.

[0070] Step S13: Assign the input excitation signal value to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and obtain the expected signal value of each sub-reference model; wherein, the simulation signal value and the expected signal value both include the input signal value and the output signal value.

[0071] In this embodiment of the invention, the input of the chip under test is monitored by a monitor, and when an input excitation signal value is detected, the input excitation signal value is assigned to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and the expected input signal value and expected output signal value of each sub-reference model are obtained.

[0072] It should be noted that, in this embodiment of the invention, the expected signal values ​​of each sub-reference model are stored in array form. That is, the expected input signal values ​​and expected output signal values ​​of each sub-reference model are stored in array form, and one array is used to store the expected input signal values ​​and expected output signal values ​​of one sub-reference model.

[0073] Step S14: Verify the chip under test by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

[0074] In this embodiment of the invention, after obtaining the simulated signal values ​​of each component module and the expected signal values ​​of each sub-reference model, the simulated signal values ​​of each component module and the expected signal values ​​of the corresponding sub-reference models are compared to verify the chip under test.

[0075] Specifically, the chip under test is verified by comparing the simulated input and output signal values ​​of each component module with the expected input and output signal values ​​of the corresponding sub-reference model.

[0076] If the simulation input signal value and simulation output signal value of each component module are consistent with the expected input signal value and expected output signal value of the corresponding sub-reference model, then the chip under test is determined to have passed the verification; otherwise, the chip under test is determined to have failed the verification.

[0077] In other words, if the simulated signal value of any component module differs from the expected signal value of the target sub-reference model, it is determined that the chip under test has encountered a verification error. Further, it is determined that the error lies with any specific component module. Then, the implementation code of that component module is analyzed to determine the cause of the error. The target sub-reference model is the sub-reference model corresponding to any component module. In this way, this embodiment of the invention, through the consistency of signal value comparison, can not only determine whether the chip verification has encountered an error, but also accurately locate the specific module that malfunctions, improving the accuracy of chip verification. Furthermore, it allows for timely analysis of the implementation code of the malfunctioning module to determine the cause of the error.

[0078] Furthermore, to improve the efficiency of determining the cause of errors, embodiments of the present invention can first determine the error type of any component module's verification failure based on the existence of different signal values ​​between any component module and the target sub-reference model; using the error type, determine the corresponding erroneous code from the implementation code of any component module; and analyze the erroneous code to determine the cause of the error in any component module. In this way, embodiments of the present invention determine the erroneous code from the implementation code of the component module based on the error type of the verification failure, and parses the erroneous code to determine the cause of the error in the component module. Compared to analyzing all the implementation code, this significantly improves the efficiency of determining the cause of errors.

[0079] Specifically, if the simulation input signal value of any component module is different from the expected input signal value of the target sub-reference model, but the simulation output signal value of any component module is the same as the expected output signal value of the target sub-reference model; or, the simulation input signal value of any component module is the same as the expected input signal value of the target sub-reference model, but the simulation output signal value of any component module is different from the expected output signal value of the target sub-reference model; or, the simulation input signal value and simulation output signal value of any component module are different from both the expected input signal value and expected output signal value of the target sub-reference model, then it is determined that the verification of any component module has failed.

[0080] Since the logical functions of the component modules are consistent with those of the corresponding sub-reference models, if the simulation input signal value of the component module is the same as the expected input signal value of the corresponding sub-reference model, but the simulation output signal value of the component module is different from the expected output signal value of the corresponding sub-reference model, then the component module is basically considered to have a verification error. Alternatively, if the simulation input signal value of the component module is different from the expected input signal value of the corresponding sub-reference model, but the simulation output signal value of the component module is the same as the expected output signal value of the corresponding sub-reference model, then the component module is also basically considered to have a verification error. However, if the simulated input signal value of the component module differs from the expected input signal value of the corresponding sub-reference model, and the simulated output signal value of the component module differs from the expected output signal value of the corresponding sub-reference model, then to further verify whether the component module has truly failed verification, the simulated input signal value of the component module can be assigned to the input signal of the corresponding sub-reference model. This allows the sub-reference model to perform signal processing based on the simulated input signal value of the component module, re-obtain the corresponding expected output signal value, and then compare the simulated output signal value of the component module with the re-obtained expected output signal value of the sub-reference model to determine whether the component module has truly failed verification. Specifically, if the simulated output signal value of the component module and the re-obtained expected output signal value of the sub-reference model are the same, the component module is considered to have passed verification; if they are different, the component module is considered to have failed verification, thereby improving the accuracy of chip verification.

[0081] Beneficial effects: This invention pre-constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test (DUT). Then, based on the sub-reference models corresponding to each component module in the DUT, a target reference model corresponding to the DUT is constructed. This allows the target reference model to focus on the internal structure of the DUT. During the DUT verification process, the expected input and output signal values ​​of each sub-reference model can be obtained through the target reference model. By comparing the expected input and output signal values ​​of each sub-reference model with the simulated input and output signal values ​​of each component module, not only can the consistency of the signal value comparison determine whether the chip verification has failed, but the specific faulty module can also be accurately located, thus improving the accuracy of chip verification.

[0082] by Figure 2 Taking the verification platform shown as an example, the chip verification method provided by the embodiments of the present invention will be described in detail. The specific scheme is as follows:

[0083] First, the verification platform includes a chip under test (DUT), an input agent, an output agent, a target reference model, and a scoring board. The input agent includes an excitation generator, a driver, and a first monitor. The output agent includes a second monitor. The first monitor monitors the inputs of the DUT, and the second monitor monitors the outputs of the DUT. The target reference model is constructed by first identifying the constituent modules of the DUT and acquiring the input and output signals of each module to build a target signal table. Each row in the target signal table includes the module name, input signal, and output signal of each constituent module. Based on the input and output signals of each constituent module, the implementation logic of each module is analyzed. Then, based on the data in the target signal table and the implementation logic of each constituent module, a sub-reference model corresponding to each constituent module is constructed. Finally, using the signal connection relationships of each constituent module, the sub-reference models are connected to obtain the target reference model corresponding to the DUT. It should be noted that the signal connection relationships of the constituent modules in the DUT are consistent with the signal connection relationships of the sub-reference models in the target reference model, as detailed in [link to relevant documentation]. Figure 3 and Figure 4 .

[0084] In the chip verification process, the verification platform executes test cases by calling simulation tools. It uses the driver in the input agent to drive the excitation generator to generate input excitation signal values ​​and assigns these values ​​to the input signals of the corresponding modules in the chip under test for signal processing. After each module in the chip under test has completed signal processing, the platform obtains the simulation waveform file generated by the chip under test through the second monitor in the output agent. It then parses the simulation waveform file to obtain the simulation input signal values ​​and simulation output signal values ​​of each module in the chip under test and sends these values ​​to the scoring board.

[0085] The verification platform monitors the input of the chip under test through the first monitor in the input agent. When the input excitation signal value is detected, the input excitation signal value is assigned to the input signal of the corresponding sub-reference model in the target reference model for signal processing. Correspondingly, the scoring board obtains the expected input signal value and expected output signal value of each sub-reference model sent by the target reference model.

[0086] Finally, the scoring board verifies the chip under test by comparing the simulated input and output signal values ​​of each component module with the expected input and output signal values ​​of the corresponding sub-reference model. Specifically, if the simulated input and output signal values ​​of any component module differ from the expected input and output signal values ​​of the corresponding sub-reference model, it is determined that the verification of that component module has failed, and the implementation code of that component module is analyzed to determine the cause of the error.

[0087] Beneficial effects: This invention pre-constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test (DUT). Then, based on the sub-reference models corresponding to each component module in the DUT, a target reference model corresponding to the DUT is constructed. This allows the target reference model to focus on the internal structure of the DUT. During the DUT verification process, the expected input and output signal values ​​of each sub-reference model can be obtained through the target reference model. By comparing the expected input and output signal values ​​of each sub-reference model with the simulated input and output signal values ​​of each component module, not only can the consistency of the signal value comparison determine whether the chip verification has failed, but the specific faulty module can also be accurately located, thus improving the accuracy of chip verification.

[0088] See Figure 5 As shown, an embodiment of the present invention provides a chip verification device, comprising:

[0089] The excitation signal value acquisition module 11 is used to acquire the input excitation signal value after a target reference model corresponding to the chip under test is pre-built; each sub-reference model in the target reference model is a model built based on the input and output signals of each component module in the chip under test; the input and output signals of each component module are unassigned signals;

[0090] The simulation signal value acquisition module 12 is used to assign the input excitation signal value to the input signal of the corresponding component module in the chip under test for signal processing, and to acquire the simulation signal value of each component module.

[0091] The expected signal value acquisition module 13 is used to assign the input excitation signal value to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and to acquire the expected signal value of each sub-reference model; wherein, both the simulation signal value and the expected signal value include the input signal value and the output signal value;

[0092] The chip verification module 14 is used to verify the chip under test by comparing the simulation signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

[0093] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0094] Beneficial effects: This invention pre-constructs corresponding sub-reference models based on the unassigned input and output signals of each component module in the chip under test (DUT). Then, based on the sub-reference models corresponding to each component module in the DUT, a target reference model corresponding to the DUT is constructed. This allows the target reference model to focus on the internal structure of the DUT. During the DUT verification process, the expected input and output signal values ​​of each sub-reference model in the target reference model can be obtained through the signal value acquisition module. The chip verification module then compares the expected input and output signal values ​​of each sub-reference model with the simulated input and output signal values ​​of each component module. This not only determines whether the chip verification is flawed based on the consistency of the signal value comparison but also accurately locates the specific faulty module when the chip verification fails, thus improving the accuracy of chip verification.

[0095] Furthermore, embodiments of this application also disclose an electronic device, Figure 6 This is a structural diagram of an electronic device according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application. Specifically, the electronic device may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip verification method disclosed in any of the foregoing embodiments. Furthermore, the electronic device in this embodiment may specifically be an electronic computer.

[0096] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0097] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0098] The operating system 221 is used to manage and control the various hardware devices on the electronic device and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the chip verification method executed by the electronic device as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0099] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned disclosed chip verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0100] Furthermore, the present invention also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the aforementioned disclosed chip verification method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0102] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0104] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0105] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip verification method, characterized in that, include: After pre-constructing a target reference model corresponding to the chip under test, the input excitation signal value is obtained; Each sub-reference model in the target reference model is a model constructed based on the input and output signals of each component module in the chip under test; the input and output signals of each component module are unassigned signals; The input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test for signal processing, and the simulation signal value of each component module is obtained. The input excitation signal value is assigned to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and the expected signal value of each sub-reference model is obtained; wherein, the simulation signal value and the expected signal value both include the input signal value and the output signal value; The chip under test is verified by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

2. The chip verification method according to claim 1, characterized in that, The step of assigning the input excitation signal value to the input signal of the corresponding component module in the chip under test for signal processing and obtaining the simulation signal value of each component module includes: The input excitation signal value is assigned to the input signal of the corresponding component module in the chip under test for signal processing, and after each component module has completed signal processing, the simulation waveform file generated by the chip under test is obtained. The simulation waveform file is parsed to obtain the simulation signal values ​​of each component module.

3. The chip verification method according to claim 2, characterized in that, The step of parsing the simulation waveform file to obtain the simulation signal values ​​of each component module includes: Based on preset control parameters, the simulation waveform file is parsed to obtain the simulation signal values ​​of each component module, and the simulation signal values ​​of each component module are transmitted to a preset file for saving according to the preset output bit width. The preset control parameters include specified signal control parameters and / or time interval control parameters; the specified signal control parameters are used to control the simulation signal value of the specified signal parsed from the simulation waveform file; the specified signal includes an input signal and an output signal; the time interval control parameters are used to control the simulation signal value within the corresponding time interval parsed from the simulation waveform file.

4. The chip verification method according to claim 1, characterized in that, The verification of the chip under test by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model includes: If the simulated signal value of any component module differs from the expected signal value of the target sub-reference model, it is determined that the verification of that component module has failed, and the implementation code of that component module is analyzed to determine the cause of the error. Wherein, any component module is any one of the component modules; the target sub-reference model is the sub-reference model corresponding to any component module.

5. The chip verification method according to claim 4, characterized in that, The analysis of the implementation code of any of the component modules to determine the cause of the error in any of the component modules includes: Based on the fact that any component module and the target sub-reference model have different signal values, determine the error type of the verification failure of any component module. Using the error type, determine the corresponding error code from the implementation code of any of the component modules; The error codes are analyzed to determine the cause of the error in any of the component modules.

6. The chip verification method according to claim 1, characterized in that, The expected signal values ​​of each sub-reference model are stored in array form.

7. The chip verification method according to any one of claims 1 to 6, characterized in that, The construction process of the target reference model includes: Identify the constituent modules of the chip under test; The input and output signals of each component module are obtained from the configuration information of each component module; wherein, the input and output signals of each component module are unassigned signals. A target signal table is constructed based on the input and output signals of each component module; wherein, each row of data in the target signal table includes the module name, input signal, and output signal of each component module; Based on the input and output signals of each component module, analyze the implementation logic of each component module; Based on the data in each row of the target signal table and the implementation logic of each component module, a sub-reference model corresponding to each component module is constructed. By utilizing the signal connection relationships of each component module, the sub-reference models are connected to obtain the target reference model.

8. A chip verification device, characterized in that, include: The excitation signal value acquisition module is used to acquire the input excitation signal value after a target reference model corresponding to the chip under test has been pre-built; Each sub-reference model in the target reference model is a model constructed based on the input and output signals of each component module in the chip under test; the input and output signals of each component module are unassigned signals; The simulation signal value acquisition module is used to assign the input excitation signal value to the input signal of the corresponding component module in the chip under test for signal processing, and to acquire the simulation signal value of each component module. The expected signal value acquisition module is used to assign the input excitation signal value to the input signal of the corresponding sub-reference model in the target reference model for signal processing, and to acquire the expected signal value of each sub-reference model; wherein, both the simulation signal value and the expected signal value include the input signal value and the output signal value; The chip verification module is used to verify the chip under test by comparing the simulated signal values ​​of each component module with the expected signal values ​​of each sub-reference model.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the chip verification method as described in any one of claims 1 to 7.

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