Address management method and device for heterogeneous system and computer device

Abstract

The present disclosure provides an address management method and device for a heterogeneous system and a computer device, relates to the technical field of computers, and particularly relates to the fields of data processing, data transmission, etc.The implementation scheme is as follows: a second virtual address space of a data transmission module is divided into second sub-virtual address spaces which are the same in number as data processing modules, and the size of the second sub-virtual address space is the same as that of a first virtual address space of the data processing module; a unique identifier is allocated to the data processing module, and the unique identifier is a natural number; for the first virtual address space, the first virtual address space is offset by a preset offset amount via the unique identifier, so as to determine a second sub-virtual address space corresponding to the first virtual address space in the second sub-virtual address space, and the preset offset amount is the product of the unique identifier and the size of the first virtual address space; and a mapping relationship between the first virtual address space and the corresponding second sub-virtual address space is established.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, in particular, to the fields of data processing and data transmission, and specifically, to an address management method and device for a heterogeneous system, a computer device, a computer readable storage medium, and a computer program product. BACKGROUND

[0002] Heterogeneous devices generally refer to hardware modules with different functions and architectures in a system, such as CODEC, DMA, GPU, etc. These modules have different memory requirements and management methods due to functional differences. The MMU is responsible for virtual address and physical address conversion, the virtual address is a program logical address, the physical memory is a real storage unit, and the page table records the mapping relationship between the two.

[0003] In the prior art, the memory management of heterogeneous devices is independent of each other, resulting in low resource utilization, complex address management logic across devices, and easy conflicts, which further limits the collaborative working efficiency and stability of the heterogeneous system. SUMMARY

[0004] The present disclosure provides an address management method and device for a heterogeneous system, a computer device, a computer readable storage medium, and a computer program product.

[0005] According to an aspect of the present disclosure, there is provided an address management method for a heterogeneous system, the heterogeneous system comprising at least one data processing module and a data transfer module, each of the at least one data processing module having a first virtual address space of a same size, and the data transfer module having a second virtual address space of a size greater than or equal to a size of a sum of the first virtual address spaces of all the at least one data processing module, the method comprising: dividing the second virtual address space of the data transfer module into at least one second sub-virtual address space of a same number as the at least one data processing module, wherein each of the at least one second sub-virtual address space has a same size as the first virtual address space of each of the data processing module; assigning a unique identifier to each of the data processing module, wherein the unique identifier is a natural number; for each of the first virtual address space, offsetting the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between each of the first virtual address space and the corresponding second sub-virtual address space.

[0006] According to an aspect of the present disclosure, the address management method for the heterogeneous system further comprises: assigning a first physical address space to each of the data processing module by applying discrete physical memory page addresses in a granularity of a page, the first physical address space having a size equal to that of the first virtual address space.

[0007] According to an aspect of the present disclosure, the assigning of the first physical address space to each of the data processing module by applying discrete physical memory page addresses in a granularity of a page comprises: constructing a plurality of physical memory page address queues, wherein each of the plurality of physical memory page address queues has a threshold capacity same as the size of the first physical address space and is used to store a group of physical memory page addresses, the group of physical memory page addresses being same in address bits exceeding the first virtual address space; for each of the obtained physical memory page, determining a physical memory page address queue corresponding to the physical memory page among the plurality of physical memory page address queues based on the address bits of the physical memory page address exceeding the first virtual address space; and in response to any of the plurality of physical memory page address queues first reaching the threshold capacity, selecting the group of physical memory page addresses stored in the physical memory page address queue.

[0008] According to an aspect of the present disclosure, the address management method for a heterogeneous system further includes reserving a first sub-virtual address space in the first virtual address space of each data processing module, wherein each first sub-virtual address space has a same size; and mapping the first sub-virtual address space of all the at least one data processing module to a same first sub-physical address space in the first physical address space, the first sub-physical address space having a same size as the first sub-virtual address space.

[0009] According to an aspect of the present disclosure, the address management method for a heterogeneous system further includes, in response to a target physical address being provided by an external data storage module to any data processing module of the at least one data processing module, searching for a target virtual address corresponding to the currently provided target physical address from a preset cache list, or re-determining a target virtual address corresponding to the currently provided target physical address, the target virtual address being in the first virtual address space, wherein the cache list records a mapping relationship between at least one target physical address and a corresponding target virtual address provided by the external data storage module and a time stamp when the mapping relationship is established.

[0010] According to an aspect of the present disclosure, searching for a target virtual address corresponding to a target physical address from a preset cache list includes, in response to determining that the cache list has a target virtual address corresponding to the currently provided target physical address, obtaining the target virtual address from the cache list; and updating the corresponding time stamp in the cache list based on a time when the target virtual address is obtained.

[0011] According to an aspect of the present disclosure, re-determining a target virtual address corresponding to the currently provided target physical address includes, in response to determining that the cache list does not have a target virtual address corresponding to the currently provided target physical address, re-allocating a corresponding target virtual address for the target physical address; and updating the cache list based on a mapping relationship between the currently provided target physical address and the re-allocated target virtual address and a time stamp when the mapping relationship is established.

[0012] According to another aspect of the present disclosure, there is provided an address management apparatus for a heterogeneous system, the heterogeneous system comprising at least one data processing module and a data transfer module, each of the at least one data processing module having a first virtual address space of a same size, and the data transfer module having a second virtual address space of a size greater than or equal to a size of a sum of the first virtual address spaces of all of the at least one data processing module, the apparatus comprising: a division unit configured to divide the second virtual address space of the data transfer module into at least one second sub-virtual address space of a same number as that of the at least one data processing module, wherein each of the at least one second sub-virtual address space has a same size as that of the first virtual address space of each of the data processing modules; an identifier allocation unit configured to allocate a unique identifier to each of the data processing modules, wherein the unique identifier is a natural number; an offset unit configured to offset, for each of the first virtual address spaces, the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and the size of the first virtual address space; and a relationship establishment unit configured to establish a mapping relationship between each of the first virtual address spaces and the corresponding second sub-virtual address space.

[0013] According to another aspect of the present disclosure, there is provided a computer device, comprising: at least one processor; and a memory having a computer program stored thereon, the computer program, when executed by the at least one processor, causing the at least one processor to perform the method provided by the present disclosure.

[0014] According to another aspect of the present disclosure, there is provided a computer readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, causing the processor to perform the method provided by the present disclosure.

[0015] According to another aspect of the present disclosure, there is provided a computer program product comprising a computer program, the computer program, when executed by a processor, causing the processor to perform the method provided by the present disclosure.

[0016] According to one or at least one embodiment of the present disclosure, device memory can be shared between heterogeneous devices, so that data transfer can be completed without the need to copy data, device memory can be dynamically allocated and recycled to various hardware devices, and unified device memory management of the entire system can be realized.

[0017] These and other aspects of the present disclosure will become clear from the embodiments described hereinafter, and will be apparent to those skilled in the art from the embodiments described hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments and together with the description serve to explain exemplary implementations of the application. The illustrated embodiments are exemplary only and not limiting of the scope of the disclosure. In all

[0019] Figure 1 is a flowchart illustrating an address management method for a heterogeneous system according to an exemplary embodiment.

[0020] Figure 2 is a schematic diagram illustrating a second virtual address space partitioning method according to an exemplary embodiment.

[0021] Figure 3 is a schematic diagram illustrating an application discrete physical memory page address according to an exemplary embodiment.

[0022] Figure 4 is a schematic diagram illustrating a first sub-virtual address space and a first sub-physical address space mapping according to an exemplary embodiment.

[0023] Figure 5 is a schematic diagram illustrating a mapping relationship cache according to an exemplary embodiment.

[0024] Figure 6 is a schematic block diagram illustrating an address management apparatus for a heterogeneous system according to an exemplary embodiment.

[0025] Figure 7 is a block diagram illustrating an exemplary computer device that can be applied to an exemplary embodiment. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, in which various details are set forth to assist in an understanding of the present disclosure. It will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, it will be apparent to one of ordinary skill in the art that the present disclosure can be practiced without the specific details set forth herein. Accordingly, the following description is to be taken in a manner of explanation and not limitation.

[0027] In the present disclosure, the terms "first", "second", and the like are used to describe various elements, not to limit the position relationship, the time relationship, or the importance relationship of these elements. Such terms are only used to distinguish one element from another element. In some examples, the first element and the second element can refer to the same instance of the element, and in some cases, based on the context of the description, they can also refer to different instances.

[0028] The terminology used in the description of the various described examples herein is for the purpose of describing particular examples only and is not intended to be limiting. Unless specifically defined otherwise, any term used herein can encompass one or more embodiments. As used herein, the term "and / or" means any one or all possible combinations of one or more

[0029] In related technologies, the memory management of heterogeneous devices is independent of each other, and the memory region needs to be pre-divided, which cannot dynamically allocate free memory, resulting in low resource utilization, and the virtual address space of different devices is greatly different, lacking unified conversion logic, and the management is complex and prone to conflict. These problems restrict the performance and resource utilization of the heterogeneous system. For example, in a heterogeneous system, the encoding and decoding module and the GPU module independently manage the device memory, resulting in that the free device memory of each module cannot be used by the other module, and the data transfer between modules relies on copying, which limits the data transfer and running efficiency.

[0030] To this end, an embodiment of the present disclosure provides an address management method for a heterogeneous system, which can realize data transmission and data sharing between heterogeneous devices in a heterogeneous system composed of various heterogeneous devices through a unified device memory and address management method without data copying or transfer, thereby improving memory use efficiency.

[0031] Exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. Before describing the address management method for a heterogeneous system according to an embodiment of the present disclosure, an example system in which the method can be implemented is first described.

[0032] Figure 1 is a flowchart illustrating an address management method 100 for a heterogeneous system according to an exemplary embodiment.

[0033] As shown in Figure 1 , the method 100 includes steps S101, S102, S103, and S104.

[0034] In an example, a heterogeneous system can refer to a combination of at least one data processing module and one data transmission module. Among them, the data processing module can be an entity that undertakes the core task of data processing and executes specific algorithm logic. For example, in the media processing scenario, it can be embodied as a codec instance that undertakes video and audio codec work, and through operations such as encoding compression and decoding restoration on the input media data stream, the content format conversion and processing are realized; while the data transmission module can focus on the data transfer between hardware, and can rely on, for example, a direct memory access mechanism such as DMA to efficiently transfer data, so as to quickly move data between different hardware components, such as codec chips and memories, codec chips and display chips, and improve data flow efficiency.

[0035] In an example, the first virtual address space can be an independent continuous address space used for addressing and memory management inside the data processing module, and the size of the space is strictly consistent among multiple data processing modules of the same type, such as multiple parallel codec instances, to ensure that the address mapping logic is unified between modules and lay a foundation for cross-module data interaction; the second virtual address space can be a virtual address range of the data transmission module, which needs to cover the address requirements of the entire data interaction link, and the size of the space can be designed to be greater than or equal to the sum of the first virtual address spaces of all data processing modules, to ensure that the data transmission module can accommodate the address mapping relationship of all data processing modules, and provide non-conflicting and scalable address mapping support for operations such as DMA transmission between codec instances and other hardware.

[0036] In step S101, the second virtual address space of the data transmission module is divided into at least one second sub-virtual address space which is the same as the number of at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module.

[0037] In an example, by dividing the second virtual address space of the data transmission module into second sub-virtual address spaces which are the same as the number of data processing modules, and the size of each second sub-virtual address space is consistent with the first virtual address space, each data processing module can have an independent virtual address region, thereby avoiding address conflicts between different data processing modules in the data transmission module; at the same time, equal division of the second virtual address space according to the size of the first virtual address space can also make each sub-space and the address range of the corresponding data processing module clear and size-adapted.

[0038] In step S102, a unique identifier is assigned to each data processing module, wherein the unique identifier is a natural number.

[0039] In an example, the unique identifier can be used to uniquely distinguish each data processing module, so that the data transmission module can accurately identify the address region corresponding to each data processing module, avoiding confusion during address conversion. The allocation of the unique identifier can use a natural number, such as sequentially increasing assignment starting from 0, etc.

[0040] In step S103, for each first virtual address space, the first virtual address space is offset by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and the size of the first virtual address space.

[0041] In an example, for each first virtual address space, it can be offset by a preset offset via the unique identifier, so as to determine the corresponding second sub-virtual address space in the second virtual address space. The setting of the preset offset can simplify the virtual address conversion to a simple mathematical operation: since the preset offset is essentially the starting address of the second sub-virtual address space corresponding to the data processing module in the second virtual address space, through the mathematical calculation of "first virtual address + preset offset", the virtual address corresponding to the address in the data transmission module can be directly obtained, without the aid of other system components, nor the need for complex lookup table or mapping logic, which can greatly improve the address conversion efficiency.

[0042] Specifically, the preset offset can be set as "unique identifier x first virtual address space size", so that the first virtual address space in the data processing module can be positioned to the corresponding second sub-virtual address space in the data transmission module via offset. For example, if the unique identifier of a certain data processing module is N, by offsetting its first virtual address space by N times the size of the first virtual address space, the corresponding second sub-virtual address space in the data transmission module after offset can be obtained.

[0043] In step S104, a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space is established.

[0044] In an example, after establishing the mapping relationship, the physical memory accessed by the data processing module through the first virtual address can also be directly accessed by the data transmission module through the corresponding second sub-virtual address, that is, the first virtual address space of the data processing module and the corresponding second sub-virtual address space of the data transmission module can be allowed to point to the same block of physical memory, so that efficient data interaction can be realized without data duplication.

[0045] Thus, through the ordered partitioning of the second virtual address space, the unique identifier identifying the data processing module, the address translation and the mapping relationship establishment, efficient address coordination of the data processing module and the data transmission module in the heterogeneous system is achieved, the copy operation in data transmission is avoided, the system data interaction efficiency is improved, and the complexity of multi-module address management is simplified.

[0046] Figure 2 is a schematic diagram illustrating a second virtual address space partitioning method according to an example embodiment.

[0047] As shown in Figure 2 As described above, in the memory address management scenario of the heterogeneous system, the data processing module can be embodied as a codec instance, for example: a video codec task process. Each codec instance can independently process video stream data. For the address coordination needs of such codec instances, the mapping relationship between the second virtual address space 202 (as shown on the left side of the figure) and the first virtual address spaces 201 of the plurality of codec instances (as shown on the right side of the figure, corresponding to a plurality of 4G virtual address spaces of the plurality of codec instances) can be constructed: first, since the size of the first virtual address space 201 of a single codec instance is 4G, the second virtual address space 202 of the data transmission module can be partitioned into a plurality of 4G-sized second sub-virtual address spaces 203 according to the number of codec instances, for example, the 4G intervals with 0G, 4G, 8G, …, N x 4G as the starting addresses in the figure. Then, a unique identifier can be assigned to each codec instance, such as 0, 1, 2, …, N, for distinguishing the address spaces of different instances. After that, the first virtual address space 201 of each codec instance, i.e., video_va, can be mapped to the corresponding second sub-virtual address space 203 in the second virtual address space 202, i.e., dma_va, through the offset calculated by the unique identifier. Wherein, id<<32 is a bit operation, which means shifting the binary representation of id to the left by 32 bits. In the diagram, since a 4G address space corresponds to a 32-bit address length, “id<<32” can be equivalent to “id x 4G”, so that the first virtual address space of the Nth codec instance can be accurately mapped to the 4G sub-space allocated for it in the second virtual address space 202, i.e., the second sub-virtual address space 203, after being offset by N x 4G. Specifically, for example, the codec instance with a unique identifier of 0 can be mapped to the second sub-virtual address space 203 of 0~4G after being offset by 0 x 4G, and the codec instance with a unique identifier of 1 can be mapped to the second sub-virtual address space 203 of 4~8G after being offset by 1 x 4G (i.e., id<<32).

[0048] In some embodiments, the above Figure 1The address management method 100 for a heterogeneous system shown can also include allocating a first physical address space for each data processing module by applying for discrete physical memory page addresses at a page granularity, the size of the first physical address space being equal to the size of the first virtual address space.

[0049] In an example, the granularity can refer to a preset granularity of a memory page, which can be preset by a unified memory management unit according to a hardware architecture and performance requirements, such as 4 KB, etc., as a minimum unit of memory allocation. The discrete physical memory pages can mean that the applied physical memory pages are not distributed continuously in the actual physical address space, but are scattered in different physical address locations. Using the discrete allocation manner can avoid allocation failure due to insufficient continuous memory blocks, and can also improve the overall utilization of physical memory. The first physical address space can be an actual physical storage area allocated for the data processing module, used to carry data accessed by the module through the first virtual address space, and the size thereof can be equal to that of the first virtual address space, so as to ensure that each address in the virtual address space can correspond to a unique physical address, meeting the memory capacity requirement of the data processing module.

[0050] Therefore, by using the discrete page allocation and page granularity management, the utilization of physical memory and the allocation flexibility are improved while ensuring that the data processing module obtains sufficient physical memory, the limitations of continuous memory allocation are avoided, and the effectiveness of data access is ensured through adaptation to the virtual address mapping mechanism.

[0051] In some embodiments, allocating a first physical address space for each data processing module by applying for discrete physical memory page addresses at a page granularity includes: constructing a plurality of physical memory page address queues, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a group of physical memory page addresses, and the group of physical memory page addresses are the same in the address bits exceeding the first virtual address space; for each obtained physical memory page address, determining the physical memory page address queue corresponding to the physical memory page address in the plurality of physical memory page address queues based on the address bits of the physical memory page address exceeding the first virtual address space; and in response to any physical memory page address queue in the plurality of physical memory page address queues reaching the threshold capacity first, selecting a group of physical memory page addresses stored in the physical memory page address queue.

[0052] In an example, the physical memory page address queue can refer to a set of collections for storing physical memory page addresses, each queue having a preset threshold capacity equal to the size of the first physical address space, i.e., just enough to accommodate all the physical memory pages required by each data processing module, so that physical pages meeting certain address characteristics can be classified and managed, facilitating quick screening of available memory. The address bits exceeding the first virtual address space can refer to the bits in the address of the physical memory page that are higher than the maximum address of the first virtual address space. For example, if the maximum address of the first virtual address space is 32 bits, the address bits exceeding the first virtual address space are 33 bits and above. The physical page addresses in the same queue have the same address bits exceeding the first virtual address space, which can represent that these physical page addresses belong to the same high address segment, thereby meeting the hardware constraints of the data processing module on the physical address.

[0053] In an example, when constructing multiple physical memory page address queues, queues can be created in advance according to different high address segments that may exist, each queue storing only physical page addresses having the same address bits exceeding the first virtual address space, and the threshold capacity of the queue being set to the total number of physical pages corresponding to the first physical address space. Such grouping management can reduce the complexity of subsequent screening. Specifically, for the address of each applied physical memory page, the address bits exceeding the first virtual address space can be extracted, compared with the characteristics of the address bits of each queue, and the physical page address can be classified into the corresponding queue, thereby ensuring that the physical page addresses in the same queue always meet the condition of consistent high address segment.

[0054] In an example, when the number of physical pages in a certain queue among the multiple queues first reaches the threshold capacity, since the physical page addresses in this queue can meet both the hardware constraint of consistent high address segment and the demand of the data processing module on the memory capacity, all the physical page addresses stored in this queue can be selected to constitute the first physical address space.

[0055] Therefore, through queue management and address bit screening, the allocated physical memory page addresses can meet both the hardware constraints of the data processing module and the capacity demand, improving the accuracy and efficiency of physical memory allocation, and reducing the risk of hardware exceptions caused by address incompatibility.

[0056] Figure 3 is a schematic diagram illustrating application of discrete physical memory page addresses according to an example embodiment.

[0057] As Figure 3As shown, taking a codec instance that undertakes a data processing task such as video coding as an example, when allocating the first physical address space for the codec instance, a manner of applying for discrete physical memory page addresses in page granularity can be adopted. First, a plurality of physical memory page address queues 301 (for example, queue 0~queue 3) can be constructed, the threshold capacity of each queue can be consistent with the size of the first physical address space required by each codec instance, and each physical memory page address queue 301 can store a group of physical memory page addresses 302 (for example, page address 0~page address M, page address 0~page address N, page address 0~page address P and page address 0~page address Y), each physical memory page address queue 301 is the same in the address bits exceeding the first virtual address space of the codec instance, so as to adapt to the constraint requirement of the high address bits of the physical address of the codec hardware. When applying for discrete physical memory pages, the physical memory page address 302 can be classified into the corresponding physical memory page address queue 301 according to the address bits exceeding the first virtual address space, so as to ensure that the physical page addresses of the same queue meet the condition of consistent high address bits. Once a certain physical memory page address queue 301 first reaches the threshold capacity, the discrete physical memory page addresses of the queue can be selected and allocated to the codec instance, and other physical memory page addresses of other queues that do not reach the threshold capacity can be released.

[0058] In some embodiments, the address management method 100 for a heterogeneous system as shown above can further include: reserving a first sub-virtual address space in the first virtual address space of each data processing module, wherein the size of each first sub-virtual address space is the same; and mapping the first sub-virtual address space of all the at least one data processing module to a same first sub-physical address space in the first physical address space, the size of the first sub-physical address space being the same as the size of the first sub-virtual address space. Figure 1

[0059] In an example, the first sub-virtual address space can refer to a specific range pre-defined in the first virtual address space of each data processing module, and the size of the first sub-virtual address space remains the same in all data processing modules. The first sub-physical address space can refer to an independent storage area in the physical memory, and the size of the first sub-physical address space is equal to the size of the first sub-virtual address space, which serves as a physical carrier for sharing data of all data processing modules. The reservation operation can be completed in the module initialization stage, for example, a continuous address segment can be defined in the first virtual address space. In addition, the size of the first sub-virtual address space reserved by each data processing module is the same, which can ensure that the virtual address logic of accessing the shared data of each module is consistent, and simplify the address identification across modules.

[0060] ​Therefore, by reserving the mapping between the first sub-virtual address and the corresponding first sub-physical address, direct sharing between data processing modules without data duplication is achieved, which not only ensures the consistency and stability of the shared address, but also reduces the data interaction across modules, and improves the system sharing efficiency and data consistency.

[0061] Figure 4 is a schematic diagram illustrating the mapping of the first sub-virtual address space and the first sub-physical address space according to an example embodiment.

[0062] As shown in Figure 4 , still taking the data processing module as an example of a codec instance (such as an independent process for performing video codec tasks), as shown on the left side of the figure, each codec instance can have an independent first virtual address space. In the initialization phase, to achieve efficient data sharing between codec instances, a fixed size of, for example, 0-512M first sub-virtual address space 401 can be reserved in the first virtual address space of each codec instance. The address space is consistent in size among the codec instances, and is used as a virtual entry for shared data access. When the codec instances need to exchange, for example, encoding parameters and intermediate frame data, access can be initiated through the first sub-virtual address space 401 in their respective first virtual address space. At the same time, as shown on the right side of the figure, the first sub-virtual address space 401 of all codec instances can be mapped to the same first sub-physical address space 402, which also has a space size of 512M. In this way, without duplicating data between codec instances, the real-time collaboration requirements can be achieved by mapping the virtual address to the shared physical space.

[0063] In some embodiments, the address management method 100 for a heterogeneous system as shown in Figure 1 may further include: in response to the external data storage module providing a target physical address to any of the at least one data processing module, finding a target virtual address corresponding to the currently provided target physical address from a preset cache list, or re-determining a target virtual address corresponding to the currently provided target physical address, the target virtual address being in the first virtual address space, wherein the cache list records the mapping relationship between at least one target physical address and the corresponding target virtual address provided by the external data storage module and the time stamp when the mapping relationship is established.

[0064] In an example, the external data storage module can refer to a separate storage unit of the data processing module providing data to be processed, which can pass data through a physical address; the target physical address can refer to the storage location identifier of the external data in the physical memory; the target virtual address can refer to the address in the first virtual address space accessible to the data processing module, for establishing a mapping between the target virtual address and the target physical address; and the cache list can refer to a collection of preset dynamic mapping records, in which the mapping relationship between the target physical address and the target virtual address established and the corresponding time stamp of the mapping creation can be stored.

[0065] In an example, since the external data storage module directly accesses the memory with a relatively large delay, and the data bandwidth is limited, and the allocation and release of the external device are managed by the external data storage module. Therefore, for the data processing module, the life cycle of the external data storage module is invisible (such as a camera, a network, a file system, etc., only responsible for the application, filling, and release of the physical memory), and it is impossible to achieve the synchronous application and release of the virtual memory of the data processing module and the physical memory of the external data storage module. Only the corresponding virtual memory can be allocated before use and released after use, and this scheme leads to the fact that the codec page table can only be updated by frequently accessing the device memory of the CPU. Based on the above reasons, the cache list mechanism can be used to reduce the consumption caused by page table updating.

[0066] In an example, further, since the cache list has a limited capacity, when a new mapping is inserted to cause the cache list to exceed the preset capacity, the cache list can be traversed to filter out the mapping entry with the earliest timestamp, i.e., the longest time not accessed, release the target virtual address occupied by the mapping entry, re-mark the target virtual address as idle for subsequent reuse, and remove the old entry from the cache list to make room for the new mapping.

[0067] Therefore, by recording or reusing the mapping relationship through the cache list, the redundant operations of repeatedly allocating virtual addresses and updating the page table are avoided, and the performance overhead caused by address mapping is reduced; the cache eviction mechanism of the timestamp ensures that the mapping relationship of high-frequency access data is preferentially retained, maximizes the address reuse efficiency in the limited cache capacity, and improves the efficiency of data interaction between the data processing module and the external storage in a heterogeneous system.

[0068] In some embodiments, finding the target virtual address corresponding to the target physical address from the preset cache list includes: in response to determining that the cache list has the target virtual address corresponding to the currently provided target physical address, obtaining the target virtual address from the cache list; and updating the corresponding timestamp in the cache list based on the time of obtaining the target virtual address.

[0069] In an example, when the external data storage module delivers the target physical address to the data processing module, the cache list can be preferentially retrieved to take advantage of the feature that the external data has repeated access, and to reduce repeated address mapping. Specifically, the current input target physical address can be matched with the physical addresses recorded in the cache list one by one, if there is an exactly identical entry, the corresponding target virtual address can be directly extracted, and at the same time, the timestamp of the entry is marked as the latest access time, ensuring that the mapping relationship of high-frequency access in the cache list is retained for a longer time.

[0070] Therefore, by reusing the existing mapping relationship and the updating mechanism of the timestamp, not only can the number of repeated accesses be reduced and the cache management be optimized, but also the efficiency of the data processing module accessing the external data can be improved, and the mapping relationship of high-frequency use in the cache list can be ensured to be retained.

[0071] In some embodiments, the target virtual address corresponding to the currently provided target physical address is re-determined, including: in response to determining that the cache list does not exist the target virtual address corresponding to the currently provided target physical address, re-allocating the corresponding target virtual address for the target physical address; and updating the cache list based on the mapping relationship between the currently provided target physical address and the re-allocated target virtual address, and the timestamp when the mapping relationship is established.

[0072] In an example, when it is determined that there is no target virtual address corresponding to the current target physical address after retrieving the cache list, a corresponding target virtual address can be re-allocated for the target physical address. Specifically, an unoccupied virtual address can be selected in the first virtual address space of the first data processing module, and the unoccupied virtual address is determined as the corresponding target virtual address. Then, the cache list can be updated based on the mapping relationship between the target virtual address and the target physical address, and the corresponding timestamp, so as to ensure that the data processing module can access the external data through the target virtual address.

[0073] Therefore, by dynamically creating a new address mapping and updating the cache list, the effective access of the data processing module to the new target physical address is ensured, and the reuse basis for subsequent repeated access is laid. At the same time, the cache resources are managed in combination with the timestamp, further improving the flexibility and overall efficiency of the system address mapping.

[0074] Figure 5 is a schematic diagram illustrating mapping relationship caching according to an example embodiment.

[0075] As Figure 5As shown, the data processing module may be a codec instance that processes video stream codec tasks independently, and the external data storage module may be a storage unit that stores original video frames and codec configuration parameters. The cache list 504 records the target physical address 501 provided by the external data storage module to the codec instance, the corresponding target virtual address 502 in the first virtual address space of the codec instance, and the timestamp 503 of the mapping establishment. When the external data storage module provides the target physical address 501, i.e., the physical memory location corresponding to the codec data to be processed, to the codec instance, the address mapping can be determined based on the preset cache list 504. Specifically, the codec instance can first retrieve the cache list 504. If the target physical address 501 has a corresponding record, the target virtual address 502 in the first virtual address space can be directly obtained for data access, and the timestamp 503 of the record is updated to mark the latest access time. If there is no corresponding mapping relationship record in the cache list 504, a new target virtual address 502 can be applied in the first virtual address space of the codec instance, and the mapping between the target virtual address 502 and the target physical address 501 is established by updating the page table. At the same time, the mapping in the cache list 504 that has not been accessed by the codec instance for the longest time is removed, the corresponding target virtual address 502 is released, and the new mapping relationship (including the target physical address 501, the target virtual address 502, and the current timestamp 503) is inserted into the cache list 504. In this way, by means of cache reuse and dynamic update, the address requirements of the codec instance for data access can be adapted, the efficiency of data interaction in the codec process can be improved, and the smooth execution of the codec task can be ensured.

[0076] Embodiments of the present disclosure further provide an address management apparatus for a heterogeneous system.

[0077] Figure 6 FIG. 6 is a schematic block diagram illustrating an address management apparatus 600 for a heterogeneous system according to an example embodiment.

[0078] The partition unit 601 is configured to partition the second virtual address space of the data transmission module into at least one second sub-virtual address space which is the same as the number of the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module.

[0079] The identifier allocation unit 602 is configured to allocate a unique identifier to each data processing module, wherein the unique identifier is a natural number.

[0080] The offset unit 603 is configured to offset, for each first virtual address space, the first virtual address space by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space among the at least one second sub-virtual address space, wherein the preset offset is a product of the unique identifier and a size of the first virtual address space.

[0081] The relationship establishing unit 604 is configured to establish a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

[0082] The operations of the above-mentioned division unit 601, identifier allocation unit 602, offset unit 603, and relationship establishing unit 604 can be the same as those of the division unit 101, identifier allocation unit 102, offset unit 103, and relationship establishing unit 104 in combination with the description of the device 100. Figure 1 The steps S101, S102, S103, and S104 are the same as the operations of the steps S101, S102, S103, and S104, and thus the details of each aspect are not described here. In addition, the device 600 and the above-mentioned units can further include further sub-modules.

[0083] In some embodiments, the device 600 can further include an address space allocation unit 605 configured to allocate a first physical address space for each data processing module by applying for discrete physical memory page addresses in a page granularity, and the size of the first physical address space is equal to the size of the first virtual address space.

[0084] In some embodiments, the address space allocation unit 605 can include a queue construction unit 6051 configured to construct a plurality of physical memory page address queues, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a group of physical memory page addresses, and the group of physical memory page addresses are the same in the address bits exceeding the first virtual address space; a queue determination unit 6052 configured to determine, for each applied physical memory page address, a physical memory page address queue corresponding to the physical memory page in the plurality of physical memory page address queues based on the address bits of the physical memory page address exceeding the first virtual address space; and a storage unit 6053 configured to select a group of physical memory page addresses stored in the physical memory page address queue in response to any physical memory page address queue in the plurality of physical memory page address queues reaching the threshold capacity first.

[0085] In some embodiments, the device 600 can further include a reservation unit 606 configured to reserve a first sub-virtual address space in the first virtual address space of each data processing module, wherein the size of each first sub-virtual address space is the same; and a mapping unit 607 configured to map the first sub-virtual address spaces of all the at least one data processing module to the same first sub-physical address space in the first physical address space, and the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

[0086] In some embodiments, the apparatus 600 can further include an address determining unit 608 configured to, in response to the external data storage module providing a target physical address to any of the at least one data processing module, find a target virtual address corresponding to the currently provided target physical address from a preset cache list, or re-determine a target virtual address corresponding to the currently provided target physical address, the target virtual address being in the first virtual address space, wherein the cache list records a mapping relationship between at least one target physical address and a corresponding target virtual address that has been provided by the external data storage module and a time stamp of when the mapping relationship is established.

[0087] In some embodiments, the address determining unit 608 can include an obtaining unit 6081, a time stamp updating unit 6082, a re-allocating unit 6083, and a list updating unit 6084. The obtaining unit 6081 is configured to, in response to determining that there is a target virtual address corresponding to the currently provided target physical address in the cache list, obtain the target virtual address from the cache list. The time stamp updating unit 6082 is configured to update the corresponding time stamp in the cache list based on a time of obtaining the target virtual address. The re-allocating unit 6083 is configured to, in response to determining that there is no target virtual address corresponding to the currently provided target physical address in the cache list, re-allocate a corresponding target virtual address for the target physical address. The list updating unit 6084 is configured to update the cache list based on a mapping relationship between the currently provided target physical address and the re-allocated target virtual address, and a time stamp of when the mapping relationship is established.

[0088] While specific functionality is discussed above with reference to particular modules, it should be noted that the functionality of the various modules discussed herein can be split into multiple modules, and / or at least some functionality of multiple modules can be combined into a single module. A particular module discussed herein performing an action includes that particular module itself performing the action, or alternatively, that particular module invoking or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the particular module). Thus, a particular module performing an action can include the particular module itself performing the action, and / or another module invoked or otherwise accessed by the particular module performing the action.

[0089] It should also be understood that the above discussion about Figure 6The various modules described can be implemented in hardware or in hardware combined with software and / or firmware. For example, the modules can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, the modules can be implemented as hardware logic / circuitry. For example, the modules can be implemented together in a System on Chip (SoC). The SoC can include an integrated circuit chip (which includes one or more of a processor (e.g., a Central Processing Unit (CPU), a microcontroller, a microprocessor, a Digital Signal Processor (DSP), etc.), memory, one or more communication interfaces, and / or other circuitry), and can optionally execute received program code and / or include embedded firmware to perform functions.

[0090] According to an aspect of the disclosure, there is provided a computer device comprising a memory, a processor, and a computer program stored on the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0091] According to an aspect of the disclosure, there is provided a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0092] According to an aspect of the disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0093] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which Figure 7 Illustrative examples of the computer device, the non-transitory computer-readable storage medium, and the computer program product are described in the following

[0094] Figure 7 An example configuration of a computer device 700 that can be used to implement the methods described herein is shown.

[0095] The computer device 700 can be various different types of devices. Examples of the computer device 700 include, but are not limited to: a desktop computer, a server computer, a notebook or netbook computer, a mobile device (e.g., a tablet computer, a cellular or other wireless phone (e.g., a smart phone), a notepad computer, a mobile station), a wearable device (e.g., glasses, a watch), an entertainment device (e.g., an entertainment appliance, a set-top box, a game console), a television or other display device, an automobile computer, and so forth.

[0096] The computer device 700 can include at least one processor 702, memory 704, communication interface(s) 706, display device 708, other input / output (I / O) devices 710, and one or more mass storage devices 712, which can communicate with one another via a system bus 714 or other appropriate connection.

[0097] The processor 702 can be a single processing unit or a plurality of processing units, all of which can include single or multiple computing units or multiple cores. The processor 702 can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and / or any devices that manipulate signals based on operational instructions. Among other capabilities, the processor 702 can be configured to fetch and execute computer-readable instructions stored in the memory 704, the mass storage device 712, or any other computer-readable medium; the program codes of an operating system 716, the program codes of application programs 718, the program codes of other programs 720, and the like.

[0098] The memory 704 and the mass storage device 712 are examples of computer-readable storage media for storing instructions which are executed by the processor 702 to implement the various functionalities described above. For example, the memory 704 can generally include both volatile memory and nonvolatile memory (e.g., RAM, ROM, etc.). In addition, the mass storage device 712 can generally include hard disk drives, solid state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CD, DVD), storage arrays, network attached storage, storage area networks, and the like. The memory 704 and the mass storage device 712 can be collectively referred to herein as the memory or the computer-readable storage medium, and can be non-transitory media that can store the computer-readable, processor-executable program instructions as computer program codes, which can be executed by the processor 702 as a particular machine configured to implement the operations and functionalities described in the examples herein.

[0099] A plurality of programs can be stored on the mass storage device 712. These programs include an operating system 716, one or more application programs 718, other programs 720, and program data 722, and they can be loaded into the memory 704 for execution. Examples of such application programs or program modules can include, for example Figure 1 Computer program logic (e.g., computer program code or instructions) of the method 100 shown and / or additional embodiments described herein.

[0100] Although the method 100 is shown and described as being performed by a single computer device 700, the method 100 can be performed by a plurality of computer devices, such as a client-server system, a peer-to-peer system, a cloud computing system, and the like. Figure 7The operating system 716, the application programs 718, the other programs 720 and the program data 722, or portions thereof, can also be downloaded via computer

[0101] Computer readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by a computer. In contrast, communication media can embody computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism. As defined herein, computer readable storage media does not include communication media.

[0102] One or more communication interfaces 706 are used to exchange data with other devices, such as over a network, direct connection, or the like. Such communication interfaces can be one or more of: any type of network interface (e.g., network interface card (NIC)), wired or wireless (such as IEEE 802.11 wireless LAN (WLAN) wireless interface, Global TM Interface, near field communication (NFC) interface, or the like. The communication interfaces 706 can facilitate communications within a variety of networks and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, and the like. The communication interfaces 706 can also provide communication with external storage devices (not shown), such as storage arrays, network attached storage, storage area networks, and the like.

[0103] In some examples, a display device 708, such as a monitor, can be included for displaying information and images to a user. Other I / O devices 710 can be devices that receive various inputs from a user and provide various outputs to the user, and can include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and the like.

[0104] The techniques described herein can be supported by these various configurations of the computer device 700 and are not limited to the specific examples of the techniques described herein. For example, the functionality can also be implemented all or in part through use of a distributed system, e.g., cloud computing, over a network. Cloud computing can include and / or be represented as a platform of the cloud. The platform abstracts underlying functionality of hardware (e.g., servers) and software resources of the cloud. Resources can include applications and / or data that is stored, accessed, and / or computed upon in the cloud, e.g., on servers that are remote from the computer device 700. Resources can also include services provided over the Internet and / or over a subscriber network, such as a cellular or Wi-Fi network. The platform can abstract resources and functionality to connect the computer device 700 with other computer devices. Thus, the functionality described herein can be implemented all or in part through use of a platform that abstracts the functionality of the cloud. For example, functionality can be implemented partially on the computer device 700 and partially by the platform that abstracts the functionality of the cloud.

Claims

1. An address management method for heterogeneous systems, characterized in that, The heterogeneous system includes at least one data processing module and a data transmission module. Each data processing module has a first virtual address space of the same size, and the data transmission module has a second virtual address space of a size greater than or equal to the sum of the first virtual address spaces of all the at least one data processing module. The method includes: The second virtual address space of the data transmission module is divided into at least one second sub-virtual address space, which is the same number as the number of the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module. Each data processing module is assigned a unique identifier, wherein the unique identifier is a natural number; For each first virtual address space, the first virtual address space is offset by a preset offset via the unique identifier to determine a second sub-virtual address space corresponding to the first virtual address space within the at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space; and Establish a mapping relationship between each first virtual address space and its corresponding second sub-virtual address space.

2. The method according to claim 1, characterized in that, The method further includes: By requesting discrete physical memory page addresses at the page granularity, a first physical address space is allocated to each data processing module, and the size of the first physical address space is equal to the size of the first virtual address space.

3. The method according to claim 2, characterized in that, The process of allocating a first physical address space for each data processing module by requesting discrete physical memory page addresses at the page granularity includes: Multiple physical memory page address queues are constructed, wherein the threshold capacity of each physical memory page address queue is the same as the size of the first physical address space and is used to store a set of physical memory page addresses, wherein the set of physical memory page addresses are identical in the address bits that exceed the maximum address of the first virtual address space; For each physical memory page address obtained from a request, based on the address bits by which the physical memory page address exceeds the maximum address of the first virtual address space, a physical memory page address queue corresponding to the physical memory page address is determined from the plurality of physical memory page address queues; and In response to any physical memory page address queue in the plurality of physical memory page address queues reaching the threshold capacity first, the set of physical memory page addresses stored in the physical memory page address queue is selected.

4. The method according to claim 2 or 3, characterized in that, The method further includes: A first sub-virtual address space is reserved in the first virtual address space of each data processing module, wherein each first sub-virtual address space is of the same size; and The first sub-virtual address space of all at least one data processing module is mapped to the same first sub-physical address space within the first physical address space, and the size of the first sub-physical address space is the same as the size of the first sub-virtual address space.

5. The method according to any one of claims 1-3, characterized in that, The method further includes: In response to an external data storage module providing a target physical address to any of the at least one data processing modules, the system searches for a target virtual address corresponding to the currently provided target physical address from a preset cache list, or re-determines a target virtual address corresponding to the currently provided target physical address. The target virtual address is in the first virtual address space. The cache list records the mapping relationship between at least one target physical address and its corresponding target virtual address that has been provided by the external data storage module, as well as the timestamp when the mapping relationship was established.

6. The method according to claim 5, characterized in that, The step of searching for the target virtual address corresponding to the target physical address from a preset cache list includes: In response to determining that a target virtual address corresponding to the currently provided target physical address exists in the cache list, the target virtual address is retrieved from the cache list; and The timestamp in the cache list is updated based on the time when the target virtual address is obtained.

7. The method according to claim 5, characterized in that, The process of re-determining the target virtual address corresponding to the currently provided target physical address includes: In response to determining that the target virtual address corresponding to the currently provided target physical address does not exist in the cache list, a corresponding target virtual address is reallocated for the target physical address; and The cache list is updated based on the mapping relationship between the currently provided target physical address and the reallocated target virtual address, and the timestamp when the mapping relationship was established.

8. An address management device for heterogeneous systems, characterized in that, The heterogeneous system includes at least one data processing module and a data transmission module. Each data processing module has a first virtual address space of the same size, and the data transmission module has a second virtual address space of a size greater than or equal to the sum of the first virtual address spaces of all the at least one data processing module. The device includes: The partitioning unit is configured to divide the second virtual address space of the data transmission module into at least one second sub-virtual address space, the same number as the at least one data processing module, wherein the size of each second sub-virtual address space is the same as the size of the first virtual address space of each data processing module. An identifier allocation unit is configured to assign a unique identifier to each data processing module, wherein the unique identifier is a natural number; An offset unit is configured to offset the first virtual address space by a preset offset via the unique identifier for each first virtual address space, in order to determine a second sub-virtual address space corresponding to the first virtual address space within the at least one second sub-virtual address space, wherein the preset offset is the product of the unique identifier and the size of the first virtual address space; and The relationship establishment unit is configured to establish a mapping relationship between each first virtual address space and the corresponding second sub-virtual address space.

9. A computer device, characterized in that, The computer device includes: At least one processor; and A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-7.

11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-7.

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