Computing Die and multi-core heterogeneous GPU chip structure for realizing data consistency retention characteristic based on VRB protocol

Abstract

The embodiment of the invention provides a Die structure, a chip structure, a method, equipment and a medium. The Die structure comprises at least one core; the protocol processing engine is connected with the at least one core and used for transmitting data related to the calculation task executed by the at least one core, the data related to the calculation task executed by the at least one core can be transmitted through the protocol processing engine, and the independent design of the protocol processing engine can flexibly adapt to different transmission protocols; the compatibility and expansibility of data interaction are enhanced in a heterogeneous computing or distributed system; according to the method, the core focuses on execution of the calculation task, and the protocol processing engine focuses on data scheduling and protocol analysis, so that the waiting time of the core due to data carrying is shortened, and the data transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a die structure, a chip structure, a method, a device and a storage medium. Background Art

[0002] With the development of science and technology, the demand for computing power for AI model training and reasoning is growing exponentially. Multi-core heterogeneous GPU chips have become key hardware supporting AI applications due to their powerful parallel computing capabilities. In existing technologies, the multiple Die structures in GPU chips cannot adapt to data of different protocols when transmitting data, and the compatibility of data transmission is low. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a Die structure, chip structure, method, device and storage medium that overcome the above problems or at least partially solve the above problems.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a Die structure, which includes:

[0005] At least one core;

[0006] A protocol processing engine is connected to the at least one core and is used to transmit data involved in the computing task performed by the at least one core.

[0007] Optionally, the protocol processing engine is configured to transmit data between cores in the same Die structure based on the first protocol, and / or transmit data between cores in different Die structures based on the VRB protocol.

[0008] Optionally, the protocol processing engine is used to receive data sent by the first core in the current Die structure based on the first protocol, and send the data to the second core of the same Die structure; or, send the data to the protocol processing engine of other Die structures based on the VRB protocol, so that the protocol processing engine of the other Die structure sends the data to the third core of the other structure based on the first protocol; or, receive data sent by the protocol processing engine of other structures based on the VRB protocol, and send the data to the fourth core of the current Die structure based on the first protocol.

[0009] Optionally, the protocol processing engine is configured to, upon receiving data transmitted by the fifth core, determine a data type of the data and transmit the data to a sixth core corresponding to the data type.

[0010] Optionally, the protocol processing engine is used to determine the transmission priorities of the multiple data respectively when receiving multiple data transmitted by at least one core; and transmit the multiple data according to the transmission priorities of the multiple data.

[0011] Optionally, the core includes at least one of a GPU core, a CPU core, and an AI acceleration core.

[0012] The present invention also discloses a chip structure, which includes:

[0013] Multiple Die structures, the Die structure includes: at least one core and a protocol processing engine, the protocol processing engine is connected to the at least one core, and the protocol processing engine is used to transmit data involved in the at least one core performing a computing task.

[0014] Optionally, the chip structure further includes:

[0015] A global shared memory is connected to the multiple Die structures respectively, and the Die structures are used to send updated data to the global shared memory based on the VRB protocol, so as to synchronously update the data in the global shared memory.

[0016] Optionally, the chip is used to determine a target data source from the multiple Die structures and the global shared memory when data needs to be read, and read the data from the target data source.

[0017] Optionally, the chip structure further includes:

[0018] A lock management module, wherein the lock management modules are respectively connected to the multiple Die structures, and the lock management module is used to allocate lock resources to the multiple Die structures according to the lock resource requests sent by the multiple Die structures, so that the multiple Die structures can perform read and write operations on the global shared memory according to the allocated lock resources.

[0019] Optionally, the lock management module is further configured to stop allocating lock resources to other Die structures when the lock resource request sent by the target Die structure among the multiple Die structures is an exclusive request.

[0020] Optionally, the chip further includes: a management module; the management modules are respectively connected to the multiple Die structures;

[0021] The management module is used to monitor the network parameters of the Die structure and adjust the frequency of updating the data in the global shared memory according to the network parameters.

[0022] The present invention also discloses a data transmission method based on the Die structure, which is applied to the Die structure as described above, and includes:

[0023] Data involved in executing a computing task by the at least one core is transmitted through the protocol processing engine.

[0024] The present invention also discloses an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the data transmission method or steps based on the Die structure as described above are implemented.

[0025] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data transmission method based on the Die structure are implemented.

[0026] The embodiments of the present invention include the following advantages:

[0027] The present invention discloses a Die structure, chip structure, method, device and storage medium. The present invention can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a structural block diagram of a Die structure provided by an embodiment of the present invention;

[0029] Figure 2 This is a structural block diagram of a chip structure provided by an embodiment of the present invention;

[0030] Figure 3 A structural block diagram of another chip structure provided by an embodiment of the present invention;

[0031] Figure 4 This is a flowchart of a data transmission method based on a Die structure provided by an embodiment of the present invention;

[0032] Figure 5 This is a flowchart of the steps of a data transmission method based on a chip structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] One of the core concepts of the embodiments of the present invention is that the present invention can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0035] Reference Figure 1 , shows a structural block diagram of a Die structure 10 provided in an embodiment of the present invention, the Die structure 10 includes:

[0036] at least one core 101;

[0037] The protocol processing engine 102 is connected to at least one core 101 and is used to transmit data involved in the computing task performed by at least one core.

[0038] In an embodiment of the present invention, Die refers to an integrated circuit chip unit in a chip, which contains various circuit elements and structures that implement specific functions. Each computing Die integrates multiple types of computing cores 101, and each computing core 101 has different functions. The core 101 is the main computing unit in the Die structure, responsible for performing various computing tasks. It can be a central processing unit (CPU) core, a graphics processing unit (GPU) core or other dedicated processor core. Its performance and function determine the ability of the entire Die structure to process computing tasks.

[0039] The protocol processing engine 102 is a functional module connected to the core 101. It is mainly responsible for processing the data transmission protocol involved when the core performs computing tasks. It can package and transmit the data generated by the core 101 according to a specific protocol, and unpack the received data according to the protocol and provide it to the core for use, ensuring that data is transmitted accurately and efficiently between different modules.

[0040] The present invention also discloses a Die structure, which can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0041] In one embodiment of the present invention, the protocol processing engine is used to transmit data between cores in the same Die structure based on the first protocol, and / or transmit data between cores in different Die structures based on the VRB protocol.

[0042] In the embodiments of the present invention, the VRB protocol refers to V2V RDMA BAND, where V2V refers to the Video to Video (V2V) protocol, a network protocol for video communication; RDMA stands for Remote Direct Memory Access, which allows a computer to directly access the memory of another computer without the intervention of the operating system; and BAND stands for bandwidth, which generally refers to the on-chip remote direct memory access bandwidth technology based on the Video to Video (V2V) protocol.

[0043] The first protocol refers to the protocol followed for data transmission between cores in the same Die structure to ensure efficient and accurate interaction of data between cores in the same Die structure. The specific first protocol may vary depending on the design requirements and application scenarios of the Die structure, such as the PCIE protocol and on-chip protocol.

[0044] When a core has data to transmit to other cores in the same Die structure, the data to be transmitted will first be encapsulated and formatted according to the provisions of the first protocol. The first protocol will define specific rules such as data encoding method, frame structure, transmission rate, etc. For example, a specific binary encoding method is used to represent data, the data is divided into frames of fixed size, and check bits and other information for error detection and correction are added to the frame.

[0045] The data transmission channel is determined based on the hardware architecture and communication mechanism within the Die structure. In the same Die structure, there is usually a dedicated internal bus or interconnection network to connect each core. The protocol processing engine will select an available channel to transmit data based on the current channel usage. For example, if there are multiple buses, it will select a bus with a lighter load for data transmission to ensure transmission efficiency and stability. Through the selected channel, the formatted data is sent to the target core bit by bit or frame by frame according to the transmission rate and timing specified by the first protocol.

[0046] When a core in a Die structure has data to send to a core in another Die structure, the sender first encapsulates the data to be transmitted. The encapsulated data will be formatted according to the VRB protocol. The VRB protocol defines a specific data frame structure, including a frame header, a data segment, and a frame trailer. The frame header will contain some fields for identifying the protocol version, frame type, checksum information, etc. The data segment is used to store the actual data to be transmitted; the frame trailer may contain some information for frame end identification and additional checksum. The data will be divided into data blocks of the size specified by the VRB protocol and assembled according to the frame structure. At the same time, the data may be encoded to improve the reliability and efficiency of data transmission.

[0047] Different Die structures are usually connected through specific network interfaces. The VRB protocol processing engine will adapt the formatted data to the corresponding network interface. After network interface adaptation, the data will be transmitted on the communication link between different Dies. The VRB protocol will specify the timing, synchronization method, error detection and recovery mechanism of data transmission. During the transmission process, the sender will send the data frame bit by bit according to the rate and format specified by the protocol, and the receiver will accurately receive the data frame based on the synchronization signal. If an error occurs during the transmission process, the error detection mechanism of the VRB protocol will detect the error and ensure the integrity of the data through corresponding recovery mechanisms, such as requesting retransmission and using error correction codes for error correction.

[0048] After receiving the data, the protocol processing engine in the target Die structure will first deformat the data according to the VRB protocol, remove the frame header, frame trailer and other protocol-related information, and extract the original data block. Then, based on the target Die identifier, target core identifier and other information contained in the data, the data will be accurately routed to the target core. Finally, the target core will decapsulate the data and deliver the truly required data to the corresponding processing module inside the target core for further processing. The VRB protocol draws on the advantages of RDMA technology and adopts a hardware-based direct memory access method, allowing computing Dies to bypass the CPU and directly access each other's memory, greatly reducing transmission latency.

[0049] In one embodiment of the present invention, a protocol processing engine is used to receive data sent by the first core in the current Die structure based on the first protocol, and send the data to the second core of the same Die structure; or, send data to the protocol processing engine of other Die structures based on the VRB protocol, so that the protocol processing engine of other Die structures sends data to the third core of other structures based on the first protocol; or, receive data sent by the protocol processing engine of other structures based on the VRB protocol, and send the data to the fourth core of the current Die structure based on the first protocol.

[0050] In an embodiment of the present invention, the protocol processing engine 102 can monitor the communication channel within the current Die structure and receive data sent by the first core based on the first protocol. During the receiving process, it will perform operations such as data verification and decoding according to the provisions of the first protocol to ensure the integrity and accuracy of the data. After confirming that the data is correct, the protocol processing engine sends the data to the communication channel connected to the second core in the same Die structure based on the identification information of the second core contained in the data, thereby realizing the transmission of data between different cores in the same Die structure. In this process, the relevant rules of the first protocol are still followed, such as the transmission format and timing of the data.

[0051] When data needs to be sent to other Die structures, the protocol processing engine first encapsulates the data from the first core of the current Die structure according to the VRB protocol. During the encapsulation process, relevant information such as the source Die identifier and the target Die identifier will be added. Then, the encapsulated data will be sent to the protocol processing engine of the other Die structure through the communication link connecting different Die structures. During the sending process, the data transmission rate is controlled according to the VRB protocol, and possible errors are handled.

[0052] After receiving data based on the VRB protocol, the protocol processing engine of other Die structures first decapsulates the data and extracts the original data. Then, according to the identifier of the third core in the data, the data is sent to the target core based on the first protocol to complete the data transmission within different Die structures.

[0053] The protocol processing engine receives data sent by protocol processing engines of other Die structures based on the VRB protocol by connecting communication links of different Die structures. When receiving, it will perform VRB protocol-related operations, such as synchronous data reception and data error detection. After confirming that the data is correct, it will decapsulate the received data and extract the original data. Then, based on the identification information of the fourth core in the data, the data will be sent to the fourth core in the current Die structure based on the first protocol, thereby realizing the final transmission of the data within the current Die structure.

[0054] Based on the first protocol and the VRB protocol respectively, the present invention can select a suitable transmission mode according to the scope of data transmission (within the same Die structure or between different Die structures), optimize the data transmission path, improve data transmission efficiency, and reduce transmission delay.

[0055] In one embodiment of the present invention, the protocol processing engine is configured to, upon receiving data transmitted by the fifth core, determine the data type of the data and transmit the data to a sixth core corresponding to the data type.

[0056] In an embodiment of the present invention, the fifth core can be a core in the same Die structure or a core in a different Die structure, the sixth core can be a core in the same Die structure or a core in a different Die structure, the data can include a data feature identification field, the data feature identification field can include a data type identification (Data Type ID), the data type identification can be identified by an unsigned integer (for example, 8 bits), for example, 01 represents image data in the training data, 02 represents text data, 03 represents real-time video stream data in the reasoning process, etc. The protocol processing engine can adopt different processing strategies based on this identification.

[0057] The protocol processing engine 102 analyzes the received data and determines its data type based on pre-set rules or data type identification information carried by the data itself. After determining the data type, the protocol processing engine will query the internal mapping relationship or configuration information to find the sixth core corresponding to the data type. Then, the protocol processing engine transmits the data to the sixth core through an appropriate communication path. The present invention can accurately transmit data to the corresponding core according to the data type, avoiding the situation of incorrect data transmission or misprocessing, improving the accuracy and pertinence of data processing in the system, and allowing each core to focus on processing the data type it is good at, thereby improving the operating efficiency of the overall system.

[0058] In one embodiment of the present invention, the protocol processing engine is configured to determine transmission priorities of the multiple data respectively when receiving multiple data transmitted by at least one core; and transmit the multiple data according to the transmission priorities of the multiple data.

[0059] In an embodiment of the present invention, the protocol processing engine 102 continuously monitors and receives multiple data transmitted from at least one core through corresponding communication interfaces and links. During the receiving process, the data will be preliminarily processed, such as signal conversion, format verification, etc., to ensure that the received data is complete and meets the transmission requirements.

[0060] The data feature identification field in the data can also include a data priority identification, which can be represented by an unsigned integer. For example, 0001 represents key parameter update data in AI model training (highest priority), 0010 represents ordinary training data, 0100 represents inference data, etc. The data sender and receiver determine the transmission and processing order of the data based on the priority.

[0061] For each data received, the protocol processing engine 102 will determine its transmission priority according to the priority identifier obtained by parsing and the pre-set priority determination rules. After determining the transmission priority of all data, the protocol processing engine will sort the multiple data in order from high to low priority, and then, based on the sorting results, send the data in sequence through the appropriate communication path and transmission method to ensure that high-priority data can reach the target core first and accurately, while avoiding excessive delay or blocking of low-priority data transmission.

[0062] In one embodiment of the present invention, the data feature identification field may also include a cache policy identifier (Cache Policy ID), which may be an unsigned integer identifier (e.g., 4 bits), such as 0001 indicating that the data needs to be cached, 0010 indicating that the data does not need to be cached, etc. The receiving end may reasonably manage cache resources based on this identifier.

[0063] The data may also include a reliability control field, which may include a cyclic redundancy check code (CRCCode), which may be represented by an unsigned integer (e.g., 32 bits, specifically determined by the CRC algorithm). At the data sending end, the protocol processing engine 102 may calculate and generate a CRC code based on the content of the data packet (including the packet header and data payload) and add it to the packet header. The protocol processing engine 102 at the receiving end recalculates the CRC code of the received data packet and compares it with the CRC code in the packet header to determine whether the data is complete. If they are inconsistent, retransmission is requested.

[0064] The data may also include a general control field, which may include a packet ID, which may be represented by an unsigned integer (eg, 32 bits), and is used for tracking, sorting, and confirming packets, facilitating the correct reassembly of packets by the receiving end.

[0065] The general control field may include a source address (Source Address), which is represented by a hardware address (for example, 64 bits, determined according to the hardware architecture), and may instruct the sender of the data packet to calculate the Die address so that the receiver knows the source of the data.

[0066] The general control field may include a destination address, which may be represented by a hardware address (e.g., 64 bits, depending on the hardware architecture). The receiving end of the data packet may be specified to calculate the Die address to ensure that the data is accurately transmitted to the target location.

[0067] The general control field may include a packet length (Packet Length), which may be represented by an unsigned integer (eg, 16 bits) and indicates the byte length of the entire packet (including the header and data payload), to help the receiving end correctly parse the packet.

[0068] Data can also include data payload. For example, AI data (AIData) can be represented by a byte array, representing the actual AI data carried, such as image pixel data and text content in the training data set, or video frame data and model parameter update data generated during the inference process. The specific format and content of the data can be determined based on the data type identification field.

[0069] In one embodiment of the present invention, the core includes at least one of a GPU core, a CPU core, and an AI acceleration core.

[0070] In an embodiment of the present invention, each computing die integrates multiple types of computing cores, including AI acceleration cores optimized for deep learning matrix operations, CPU cores for general computing tasks, and GPU cores for assisting graphics-related AI applications (such as computer vision). These cores are interconnected through a high-speed internal bus to form a closely coordinated computing unit.

[0071] In one embodiment of the present invention, Figure 1 The Die structure 10 can also include a memory 103, which can be used to temporarily store data and instructions that are frequently accessed during the calculation process, reduce the number of accesses to the external memory, and improve the data access speed. For example, during AI reasoning, commonly used model parameters and intermediate calculation results are cached locally to speed up the reasoning speed.

[0072] In one embodiment of the present invention, the protocol processing engine is further configured to detect data transmission parameters and adjust the data transmission rate according to the transmission parameters.

[0073] In the embodiment of the present invention, transmission parameters refer to relevant parameters that can reflect the transmission status during the data transmission process. The transmission parameters may include parameters such as data packet transmission success rate, error rate, network bandwidth, and signal strength utilization.

[0074] The protocol processing engine 102 can continuously monitor the status of the communication link on which data transmission depends, including detecting the bandwidth utilization of the link. For example, by periodically measuring the ratio of the amount of data actually transmitted on the link within a certain period of time to the total bandwidth of the link, the busyness of the link can be determined. The signal strength can also be monitored. If the signal strength is too weak, it may mean that there is interference or the distance is too far during the transmission process. In addition, the error rate is also an important monitoring indicator. The transmission quality of the link is evaluated by counting the ratio of the number of received erroneous data frames to the total number of data frames.

[0075] When multiple cores transmit data simultaneously, network congestion may occur. The protocol processing engine can analyze the traffic situation in the network, such as observing the queue length and delay time of the data packet. If it is found that the data packet waits in the queue for too long or the queue length continues to increase, it means that the network may be congested.

[0076] In one example, when the protocol processing engine 102 finds that the packet error rate exceeds a certain threshold during AI model training, it can automatically reduce the data transmission rate and increase the redundancy of the CRC check code to improve the reliability of data transmission; in the AI ​​reasoning scenario, when it is detected that the network bandwidth utilization is low, the data transmission rate is appropriately increased to ensure a quick response.

[0077] The present invention can adjust the data transmission rate by detecting the transmission parameters of the data. Under different network environments and device conditions, the protocol processing engine can automatically adjust the transmission rate, making the system more adaptable and ensuring that data transmission can proceed normally under various complex situations.

[0078] The present invention discloses a Die structure, which can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0079] Reference Figure 3 , shows a structural block diagram of a chip structure 20 provided by an embodiment of the present invention. The chip structure 20 may include:

[0080] Multiple Die structures 201, the Die structure includes: at least one core and a protocol processing engine, the protocol processing engine is connected to the at least one core, and the protocol processing engine is used to transmit data involved in the at least one core executing a computing task.

[0081] The present invention discloses a chip structure that can transmit data involved in executing computing tasks of at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0082] In one embodiment of the present invention, the chip structure further includes:

[0083] The global shared memory is connected to multiple Die structures respectively. The Die structure is used to send updated data to the global shared memory based on the VRB protocol to synchronously update the data in the global shared memory.

[0084] In the embodiment of the present invention, Figure 2 The chip structure also includes: global shared memory 202, which is used to store data shared by each computing Die during AI model training and inference, such as model parameters, training samples, and inference results. Each computing Die 201 is equipped with a local consistent cache to retain copies of some shared data.

[0085] The global shared memory 202 and the computing die 201 use the VRB protocol to carry out data interaction, ensuring that data can be transmitted accurately and efficiently between the two.

[0086] In one example, Die includes 2011, 2012, and 201n. When a computing Die 2011 performs an update operation on shared data such as AI model parameters, its local consistency cache will immediately perceive the change. Subsequently, the local consistency cache will send the update message to the consistency caches of other computing Dies 2012 and 201n and the global shared memory 202 through the VRB protocol.

[0087] If write propagation is used, the update message will carry the new data value, which will prompt other copies to update synchronously to keep all copy data consistent. If write invalidation is used, the update message will notify other copies that the data has expired. When other computing Dies try to access the data next time, they will obtain it from the latest data source to ensure data consistency. The present invention can quickly send processed data to the global shared memory for updating through multiple Die structures, realize data sharing, help improve the overall data processing efficiency of the chip, and ensure data consistency.

[0088] It should be noted that data is transmitted between the global shared memory and the computing die based on the VRB protocol. The global shared memory and the computing die use the VRB protocol to carry out data interaction, which can ensure that data can be transmitted between the two accurately and efficiently.

[0089] In one embodiment of the present invention, the chip is used to determine a target data source from multiple Die structures and a global shared memory when data needs to be read, and read the data from the target data source.

[0090] In the embodiment of the present invention, when the chip receives a data read request, it first parses the information in the request, including the identifier, type, and related operation instructions of the required data.

[0091] Based on the request information, the metadata stored in the chip is queried. The metadata contains information about the data storage location, such as the data range stored in each Die structure, the distribution of data in the global shared memory, and the data update time. By querying the metadata, the system can preliminarily determine the Die structure and global shared memory area that may store the target data.

[0092] After determining the possible data sources, you can further evaluate the status of each data source. This includes checking the current workload of the Die structure and global shared memory, the availability of data, and whether there are data conflicts. For example, if a Die structure is currently busy processing other tasks, it may cause data reading delays. In this case, you can give priority to data sources with better status.

[0093] The target data source is finally determined by comprehensively considering factors such as metadata and data source status. If the required data exists in the global shared memory and is in good condition, it is preferred to read from the global shared memory because the global shared memory usually has a higher access speed and wider data sharing. If the data in the global shared memory is not the latest, or there is an access conflict, and the latest and available data is stored in a Die structure, the system will choose to read the data from the Die structure.

[0094] Once the target data source is determined, a data channel can be established between the requester and the target data source. This channel may be a high-speed bus inside the chip, a dedicated communication link, or other connection methods to ensure that data can be transmitted quickly and stably.

[0095] A read instruction is sent to the target data source through a data channel. The read instruction includes specific read parameters, such as the starting address of the data, the read length, etc. The target data source determines the data content to be read according to these instructions. The target data source reads the corresponding data from its storage unit according to the read instruction and transmits the data to the requester through the data channel. During the data transmission process, some necessary processing is performed on the data, such as data format conversion and verification, to ensure the correctness and compatibility of the data. The present invention reasonably selects the target data source according to the workload and status of each data source, so that each Die structure and global shared memory in the chip can be used in a balanced manner, avoiding performance degradation or failure of a component due to excessive use, and optimizing the allocation and use of chip resources.

[0096] In one embodiment of the present invention, the chip is used to obtain the storage timestamps of the corresponding replica data in multiple Dies and the storage timestamps of the corresponding replica data in the global shared memory; and determine the target data source based on the storage timestamps of the corresponding replica data in multiple Dies and the storage timestamps of the corresponding replica data in the global shared memory.

[0097] In an embodiment of the present invention, each Die structure and the data storage area in the global shared memory are equipped with a timestamp recording function. When data is written, the current timestamp information is automatically recorded and stored in association with the corresponding data copy. The timestamp can reflect the update time of the data. A newer timestamp means that the data is most recently updated.

[0098] When the target data source needs to be determined, the chip can use internal control logic to read the storage timestamps of the corresponding replica data from multiple Die structures and the global shared memory respectively. The chip can compare the storage timestamps of the corresponding replica data obtained from multiple Die structures and the global shared memory. If the storage timestamp of the replica data in the global shared memory is later than that in all Die structures, then the global shared memory will be determined as the target data source, because the data in the global shared memory is the latest, and reading data from here can ensure the timeliness of the data.

[0099] If the storage timestamp of the replica data in a Die structure is later than that in the global shared memory and other Die structures, then the Die structure will be determined as the target data source, which indicates that the latest data update is stored in the Die structure.

[0100] If the timestamps in multiple Die structures or global shared memory are the same, other factors need to be considered to determine the target data source, such as the current load and access speed of each data source. If the global shared memory has a faster access speed and a lower load, the global shared memory can be selected as the target data source even if the timestamps are the same.

[0101] The present invention determines the target data source by comparing the stored timestamps, which can ensure that the read data is the latest. Using the timestamp as the judgment basis can effectively avoid reading outdated data, thereby improving the accuracy and reliability of the system.

[0102] In one embodiment of the present invention, Figure 3 , shows a block diagram of another chip structure 20 provided by an embodiment of the present invention, the chip structure further includes:

[0103] The lock management module 203 is connected to multiple Die structures respectively. The lock management module is used to allocate lock resources to multiple Die structures according to lock resource requests sent by multiple Die structures, so that multiple Die structures can perform read and write operations on the global shared memory according to the allocated lock resources.

[0104] In an embodiment of the present invention, the lock resource is the permission of the Die structure to perform read and write operations on data in the global shared memory. When multiple Die structures need to perform read and write operations on the global shared memory, they will send lock resource requests to the lock management module. The request may include information such as the identifier of the Die structure, the requested lock type (read lock or write lock), and the duration of the request. For example, when a Die structure wants to perform a write operation on a data block in the global shared memory, it will send a write lock request.

[0105] After receiving requests from multiple Die structures, the lock management module will make lock resource allocation decisions based on a certain strategy: following the basic rules of read-write locks, that is, multiple read operations can be performed simultaneously, but write operations are mutually exclusive with other read and write operations. If multiple Die structures send read lock requests, the lock management module can allocate read locks to them at the same time; if a Die structure sends a write lock request, the lock management module will not allocate any locks (read locks or write locks) to other Die structures while the request is being processed until the write operation is completed and the lock is released.

[0106] The order of allocating lock resources can be determined based on factors such as the task priority of the Die structure and the order in which requests arrive. For example, the lock management module will give priority to Die structure requests corresponding to high-priority tasks.

[0107] The lock management module allocates lock resources to the corresponding Die structure based on the decision results. The allocation process is usually achieved by sending a lock grant signal to the Die structure. The signal contains information such as the lock type and validity period. The Die structure that obtains the lock resource obtains the permission to perform corresponding read and write operations on the global shared memory. When the Die structure completes the read and write operations on the global shared memory, it will send a lock release request to the lock management module. After receiving the request, the lock management module will mark the corresponding lock resource as available so that it can be allocated to other Die structures.

[0108] It should be noted that the lock resource request is transmitted between the lock management module and multiple Die structures based on the VRB protocol, which can take advantage of the low latency feature of the VRB protocol and significantly reduce the waiting time for lock acquisition and release.

[0109] The present invention ensures the mutual exclusivity and consistency of multiple Die structures when performing read and write operations on the global shared memory through the allocation and management of lock resources by the lock management module. During write operations, due to the exclusivity of the write lock, other Die structures cannot perform read and write operations at the same time, avoiding data conflicts and inconsistencies caused by multiple write operations modifying the same data at the same time. During multiple read operations, multiple Die structures can obtain read locks at the same time, improving the concurrency performance of read operations.

[0110] In an embodiment of the present invention, the lock management module is further configured to stop allocating lock resources to other Die structures when the lock resource request sent by the target Die structure among the multiple Die structures is an exclusive request.

[0111] In an embodiment of the present invention, when the target Die structure among multiple Die structures sends an exclusive lock resource request to the lock management module, the request will clearly indicate the exclusive nature of the request. This request will also include key information such as the identifier of the target Die structure, the requested lock type (exclusive lock), and the duration of the request.

[0112] After receiving the exclusive request of the target Die structure, the lock management module will immediately stop allocating lock resources to other Die structures. This means that for any lock resource requests sent by other Die structures thereafter, the lock management module will put them into the waiting queue and will not allocate them for the time being.

[0113] The lock management module will verify the exclusive request of the target Die structure and check the legitimacy of the request, such as whether it complies with the system's lock allocation rules and whether there is a resource conflict. If the verification passes, the lock management module will allocate the exclusive lock resource to the target Die structure. The allocation process is achieved by sending a lock grant signal to the target Die structure. The signal contains detailed information such as the type and validity period of the exclusive lock.

[0114] In the present invention, when the target Die structure needs to perform some operations that require extremely high data integrity, the exclusive lock can ensure that during the operation, the global shared memory will not be interfered with by the read and write operations of other Die structures. This avoids the data inconsistency problem that may occur when multiple Die structures modify or read the same data at the same time, thereby ensuring the integrity and accuracy of the data.

[0115] In one embodiment of the present invention, Figure 3 , the chip further includes: a management module 204; the management module is respectively connected to a plurality of Die structures;

[0116] The management module 204 is used to monitor the network parameters of the Die structure and adjust the frequency of updating the data in the global shared memory according to the network parameters.

[0117] In the embodiment of the present invention, network parameters may include multiple aspects, such as network bandwidth, network delay, packet loss rate, Die load, etc. These parameters can reflect the data transmission between the Die structure and the global shared memory.

[0118] The management module can pre-set threshold ranges for different network parameters. For example, it can set an acceptable upper limit for network delay and packet loss rate. When network parameters exceed these thresholds, it indicates that the network condition is poor. When they are below the threshold, it indicates that the network condition is good.

[0119] When the management module determines that the network condition is good, it means that data can be transmitted quickly and stably between the Die structure and the global shared memory. At this time, the management module can appropriately increase the frequency of updating the data in the global shared memory. For example, the update frequency can be increased from once per second to multiple times per second to ensure that the data in the global shared memory is always kept up to date.

[0120] When network conditions are poor, such as severe bandwidth shortages or high packet loss rates, frequent data updates can increase the network burden and make data transmission more unstable. In these cases, the management module significantly reduces the frequency of data updates to the global shared memory. For example, it can reduce the update frequency from once per second to once every few minutes to ensure data transmission in a relatively stable network environment.

[0121] By dynamically adjusting the data update frequency according to network parameters, the present invention allows the management module to avoid unnecessary data transmission when the network condition is poor, thereby reducing network congestion and improving the utilization efficiency of network resources. When the network bandwidth is sufficient, timely increasing the update frequency can fully utilize network resources and ensure the real-time nature of data.

[0122] The present invention discloses a chip structure that can transmit data involved in executing computing tasks of at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0123] Reference Figure 4 , shows a flowchart of a data transmission method based on a Die structure provided by an embodiment of the present invention. The method is applied to the above-mentioned Die structure, and the method includes:

[0124] Step 301: transmitting data involved in executing a computing task by at least one core through a protocol processing engine.

[0125] The present invention discloses a data transmission method based on the Die structure, which can transmit data involved in at least one core executing a computing task through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0126] In one embodiment of the present invention, data involved in at least one core executing a computing task is transmitted through a protocol processing engine, including: transmitting data between cores in the same Die structure based on a first protocol through the protocol processing engine, and / or transmitting data between cores in different Die structures based on a VRB protocol through the protocol processing engine.

[0127] In one embodiment of the present invention, data is transmitted between cores in the same Die structure based on a first protocol through a protocol processing engine, including: receiving data sent by the first core in the current Die structure based on the first protocol through a protocol processing engine, and sending the data to the second core of the same Die structure.

[0128] In one embodiment of the present invention, data between cores of different Die structures is transmitted based on the VRB protocol through a protocol processing engine, including: receiving data sent by the first core in the current Die structure through the protocol processing engine based on the first protocol, and sending the data to the protocol processing engines of other Die structures based on the VRB protocol, so that the protocol processing engines of other Die structures send the data to the third core of other structures based on the first protocol; or, receiving data sent by the processing engines of other Die structures based on the VRB protocol through the protocol processing engine, and sending the data to the fourth core of the current Die structure based on the first protocol.

[0129] In one embodiment of the present invention, data involved in executing a computing task by at least one core is transmitted through a protocol processing engine, including: when receiving data transmitted by the fifth core, determining the data type of the data, and transmitting the data to the sixth core corresponding to the data type.

[0130] In an embodiment of the present invention, the method further includes: upon receiving multiple data transmitted by at least one core, determining transmission priorities of the multiple data respectively; and transmitting the multiple data according to the transmission priorities of the multiple data.

[0131] In one embodiment of the present invention, the core includes at least one of a GPU core, a CPU core, and an AI acceleration core.

[0132] In one embodiment of the present invention, the method further includes: detecting transmission parameters of the data, and adjusting the data transmission rate of the data according to the transmission parameters.

[0133] The present invention discloses a data transmission method based on the Die structure, which can transmit data involved in at least one core executing a computing task through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0134] Reference Figure 5 , shows a flowchart of the steps of a chip structure-based data transmission method provided by an embodiment of the present invention. The method is applied to the above chip structure, and the method includes:

[0135] Step 401: transmitting data involved in executing a computing task by at least one core through a protocol processing engine.

[0136] The present invention discloses a data transmission method based on a chip structure, which can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0137] In one embodiment of the present invention, the chip structure also includes: a global shared memory, which is connected to multiple Die structures respectively, and also includes: sending updated data to the global shared memory through the Die structure based on the VRB protocol to synchronously update the data in the global shared memory.

[0138] In an embodiment of the present invention, the method further includes: when data needs to be read, the chip determines a target data source from multiple Die structures and a global shared memory, and reads data from the target data source.

[0139] In one embodiment of the present invention, when a chip needs to read data, it determines a target data source from multiple Die structures and a global shared memory, including:

[0140] Obtain the storage timestamps of the corresponding replica data in multiple Dies and the storage timestamps of the corresponding replica data in the global shared memory through the chip; determine the target data source based on the storage timestamps of the corresponding replica data in multiple Dies and the storage timestamps of the corresponding replica data in the global shared memory.

[0141] In one embodiment of the present invention, the chip structure also includes: a lock management module, which is connected to multiple Die structures respectively, and also includes: allocating lock resources to multiple Die structures according to lock resource requests sent by multiple Die structures through the lock management module, so that multiple Die structures can perform read and write operations on the global shared memory according to the allocated lock resources.

[0142] In an embodiment of the present invention, the method further includes: when the lock resource request sent by the target Die structure among the multiple Die structures is an exclusive request, stopping allocating lock resources to other Die structures by the lock management module.

[0143] In one embodiment of the present invention, the chip further includes: a management module; the management modules are respectively connected to multiple Die structures; and further includes: monitoring network parameters of the Die structure and adjusting the frequency of updating data in the global shared memory according to the network parameters.

[0144] The present invention discloses a data transmission method based on a chip structure, which can transmit data involved in the execution of computing tasks by at least one core through a protocol processing engine. The independent design of the protocol processing engine can flexibly adapt to different transmission protocols, thereby enhancing the compatibility and scalability of data interaction in heterogeneous computing or distributed systems. The present invention focuses on the execution of computing tasks through the core, while the protocol processing engine focuses on data scheduling and protocol parsing, significantly reducing the waiting time of the core due to data handling and improving data transmission efficiency.

[0145] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0146] An embodiment of the present invention further provides an electronic device, including:

[0147] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the various processes of the above-mentioned Die structure-based data transmission method or chip structure-based data transmission method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0148] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned Die structure-based data transmission method or chip structure-based data transmission method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0149] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0150] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0151] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0152] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0153] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0154] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0155] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0156] The above is a detailed introduction to the Die structure, chip structure, method, device and medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A Die structure, characterized in that: The Die structure includes: At least one core; A protocol processing engine is connected to the at least one core and is used to transmit data involved in the computing task performed by the at least one core.

2. The Die structure according to claim 1, characterized in that: The protocol processing engine is configured to transmit data between cores in the same Die structure based on the first protocol, and / or transmit data between cores in different Die structures based on the VRB protocol.

3. The Die structure according to claim 2, characterized in that: The protocol processing engine is configured to receive data sent by a first core in a current Die structure based on a first protocol, and send the data to a second core in the same Die structure; Or, sending the data to a protocol processing engine of another Die structure based on a VRB protocol, so that the protocol processing engine of the other Die structure sends the data to a third core of the other structure based on the first protocol; Or, data sent by a protocol processing engine of another structure is received based on the VRB protocol, and the data is sent to the fourth core of the current Die structure based on the first protocol.

4. The Die structure according to claim 1, characterized in that: The protocol processing engine is configured to, upon receiving data transmitted by the fifth core, determine a data type of the data and transmit the data to a sixth core corresponding to the data type.

5. The Die structure according to claim 1, characterized in that: The protocol processing engine is used to determine the transmission priorities of the multiple data respectively when receiving the multiple data transmitted by at least one core; and transmit the multiple data according to the transmission priorities of the multiple data.

6. The Die structure according to claim 1, characterized in that: The core includes at least one of a GPU core, a CPU core, and an AI acceleration core.

7. A chip structure, characterized in that: The chip structure includes: Multiple Die structures, the Die structure includes: at least one core and a protocol processing engine, the protocol processing engine is connected to the at least one core, and the protocol processing engine is used to transmit data involved in the at least one core performing a computing task.

8. The chip structure according to claim 7, characterized in that: The chip structure further includes: A global shared memory is connected to the multiple Die structures respectively, and the Die structures are used to send updated data to the global shared memory based on the VRB protocol, so as to synchronously update the data in the global shared memory.

9. The chip structure according to claim 8, characterized in that: The chip is used to determine a target data source from the multiple Die structures and the global shared memory when data needs to be read, and read the data from the target data source.

10. The chip structure according to claim 8, characterized in that: The chip structure further includes: A lock management module, wherein the lock management modules are respectively connected to the multiple Die structures, and the lock management module is used to allocate lock resources to the multiple Die structures according to the lock resource requests sent by the multiple Die structures, so that the multiple Die structures can perform read and write operations on the global shared memory according to the allocated lock resources.

11. The chip structure according to claim 10, characterized in that: The lock management module is further configured to stop allocating lock resources to other Die structures when the lock resource request sent by the target Die structure among the multiple Die structures is an exclusive request.

12. The chip structure according to claim 8, characterized in that: The chip further includes: a management module; the management modules are respectively connected to the plurality of Die structures; The management module is used to monitor the network parameters of the Die structure and adjust the frequency of updating the data in the global shared memory according to the network parameters.

13. A data transmission method based on Die structure, characterized in that: The method is applied to the Die structure according to any one of claims 1 to 7, and the method includes: Data involved in executing a computing task by the at least one core is transmitted through the protocol processing engine.

14. The method according to claim 13, characterized in that The transmitting, through the protocol processing engine, data related to the at least one core executing the computing task, includes: The protocol processing engine is used to transmit data between cores in the same Die structure based on the first protocol, and / or the protocol processing engine is used to transmit data between cores in different Die structures based on the VRB protocol.

15. The method according to claim 14, characterized in that The transmitting of data between cores in the same Die structure based on the first protocol by the protocol processing engine includes: The protocol processing engine receives data sent by a first core in a current Die structure based on a first protocol, and sends the data to a second core in the same Die structure.

16. The method according to claim 14, characterized in that The transmitting of data between cores of different Die structures based on the VRB protocol by the protocol processing engine includes: Receiving, by the protocol processing engine, data sent by the first core in the current Die structure based on the first protocol, and sending the data to the protocol processing engine of the other Die structure based on the VRB protocol, so that the protocol processing engine of the other Die structure sends the data to the third core of the other structure based on the first protocol; or The protocol processing engine receives data sent by processing engines of other Die structures based on the VRB protocol, and sends the data to the fourth core of the current Die structure based on the first protocol.

17. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the data transmission method based on the Die structure as described in any one of claims 13 to 16 are implemented.

18. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the data transmission method based on the Die structure according to any one of claims 13 to 16 are implemented.

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