Reconfigurable network-on-chip of data stream accelerator

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a reconfigurable network-on-chip of a data stream accelerator. The reconfigurable network-on-chip of the data stream accelerator adopts a dual-mode reconfigurable router architecture, each router is integrated with four HT switches, and the connection direction is controlled through a mode selection signal; meanwhile, a normal mode of standard Mesh connection and a high throughput HT mode of directional aggregation bandwidth are supported; in a high throughput HT mode, a north port IN, a south port IS, an east port IE and a west port IW are used for injecting data in parallel, in order to make full use of the bandwidth of each router, unused output ports are reconstructed to transmit data in the same direction, and a high-bandwidth link is formed; and the FC layer and the CONV layer are optimized. According to the reconfigurable network-on-chip of the data flow accelerator, unused ports, buffer areas and routing logic are redirected to the target direction by dynamically switching the router mode, and maximum utilization of bandwidth resources is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a reconfigurable network on chip of a data stream accelerator. Background Art

[0002] In recent years, deep neural networks (DNNs) have demonstrated tremendous potential, with convolutional neural networks (CNNs) and Transformers leading the way in computer vision (CV) and natural language processing (NLP). Both architectures include fully connected (FC) layers. Due to their large number of parameters, FC layers require high bandwidth, making efficient communication crucial for accelerating them.

[0003] To accelerate various DNN algorithms, many DNN accelerators have been developed. Among them, NoC-based accelerators have received widespread attention. NoCs enable efficient communication between multiple processing units, effectively reducing the bottlenecks common in traditional bus-based systems.

[0004] In addition, some accelerators have further introduced reconfigurable networks on chip (NoCs). These accelerators provide higher flexibility, support multiple data flows, and can adapt to various DNN types. However, existing reconfigurable NoCs (such as multi-planes and virtual channels) do not fully integrate channels, buffers, and routing logic resources, resulting in insufficient bandwidth utilization.

[0005] In order to maximize the utilization of bandwidth resources, the present invention proposes a reconfigurable network-on-chip for a data flow accelerator. Summary of the Invention

[0006] In order to overcome the defects of the prior art, the present invention provides a simple and efficient reconfigurable network-on-chip for data flow accelerator.

[0007] The present invention is achieved through the following technical solutions:

[0008] A reconfigurable network-on-chip (NoC) for data flow accelerators uses a dual-mode reconfigurable router architecture. Each router integrates four HT switches: N_HT, E_HT, S_HT, and W_HT. Connection direction is controlled by a mode selection signal. The router supports both the normal mode for standard mesh connections and the high-throughput HT mode for directional aggregated bandwidth.

[0009] In high-throughput HT mode, data is injected into four ports in parallel: the north port IN, the south port IS, the east port IE, and the west port IW. To fully utilize the bandwidth of each router, unused output ports are reconfigured to transmit data in the same direction, forming a high-bandwidth link.

[0010] Optimize the FC layer (fully connected layer): weight parameters are injected in parallel through multiple inputs, the number of nodes in a single row is set to a multiple of 4, and four-way concurrent transmission is supported;

[0011] Optimize the CONV layer: For large-size ifmaps, use high-throughput HT mode to accelerate diagonal multicast to reduce transmission delay;

[0012] Supports configuration packets, control packets, and payload packets. Control packets are used to define unicast / multicast / broadcast types. Configuration packets contain mode instructions, which trigger mode switching and reuse idle resources to improve throughput.

[0013] The reconfigurable network-on-chip of the data flow accelerator of the present invention includes an HT-NoC architecture and a router architecture;

[0014] The HT-NoC architecture adopts a two-dimensional grid topology design and uses an XY routing algorithm and wormhole flow control with a channel width of 32 bits. The routers in the westernmost row serve as the entry point into the NoC. Each router has four ingress connections: the north port IN, the south port IS, the east port IE, and the west port IW. The routers in the bottom row serve as the egress points.

[0015] The HT-NoC architecture supports unicast, multicast and broadcast communications, and the communication packets are divided into three types: configuration packets, control packets and payload packets;

[0016] The configuration packet specifies the operating mode of the router, and the control packet indicates the communication type (unicast, multicast, or broadcast) and the number of payload packets to be transmitted; the control packet is followed by one or more payload packets, each of which contains only data.

[0017] The structure of the communication data packet includes a header flit and a mode flit. The header flit is used to specify the data packet type and communication type, and the mode flit is used to define the mode required to configure the data packet.

[0018] When the communication type is unicast, the communication data packet also includes the X and Y coordinates of the target node of the unicast communication, represented by ADX and ADY respectively, and the number of payload data packets NP;

[0019] When the communication type is multicast or broadcast, the communication data packet also includes the source coordinates ASX of multicast or the source coordinates AS of broadcast communication, and the number NP of payload data packets.

[0020] In the router architecture, each router has five ports: north, south, west, east, and local;

[0021] Incoming data packets are first stored in the input buffer FIFO of their corresponding ingress port. Afterwards, the incoming data is processed in the routing logic block (RLB) corresponding to the ingress port, and the routing logic block (RLB) determines the destination of the data packet. Finally, the data packet is forwarded to the central crossbar switch and then sent to the output port.

[0022] To operate in a specific mode, the router first receives a configuration packet that specifies the desired mode. After processing the packet, the router sets the mode select signal on each switch, thereby controlling the HT switches to operate in the selected mode.

[0023] Normal mode is the default mode. In this mode, each router is directly connected to its four neighboring routers, and the router's available output bandwidth is evenly distributed among its five output ports. The limited bandwidth of each port is compensated by data reuse, which refers to the situation where a single piece of data is used by multiple nodes. The data is only obtained once from the source node and then propagated to all destination nodes.

[0024] High-throughput HT mode is designed for sustained high-bandwidth traffic patterns that maintain a consistent direction: input data is injected into the HT-NoC through the routers in the westernmost column and transmitted to the nodes in the east. In high-throughput HT mode, the router can simultaneously process up to four packets from the same adjacent router. Because these four packets arrive at different input ports, they are processed by four independent input buffers (FIFOs) and routing logic blocks (RLBs), maximizing the router's internal resource utilization.

[0025] To map a given FC layer onto the HT-NoC architecture, an output-stationary OS dataflow model is adopted, where each output neuron is assigned to a specific node; the ifmap and weight required to calculate a given output neuron are first sent to the corresponding node; for a given X×Y configuration of the HT-NoC architecture, the first X output neurons are mapped to the first row:

[0026] If the number of output neurons exceeds the number of nodes, only the first XY neurons will be mapped simultaneously, and neurons ranked higher than XY will wait until the initial node is released before they can be mapped onto the grid; this mechanism allows weight packets of four consecutive nodes to be injected into the HT-NoC architecture simultaneously.

[0027] The data propagation phase of the FC layer includes three stages: ifmap propagation, weight propagation and ofmap collection.

[0028] In the ifmap propagation phase, the input neurons are propagated to all nodes of the grid; due to the data reuse feature, this phase is executed in normal mode;

[0029] During the weight propagation phase, each node receives the weights required to compute the corresponding output neuron. Unlike input neurons, weights are injected from all input ports of the routers in the westernmost column: north port IN, south port IS, east port IE, and west port IW. Due to the huge traffic load, this phase is performed in high-throughput HT mode, because for each row, four packets with different destinations are injected into the HT-NoC architecture simultaneously.

[0030] During the ofmap gather phase, each node in a given column of the grid sends its output neuron to the external output port of that column; the ofmap gather phase is executed in normal mode using unicast; the number of nodes in a row of the grid is a multiple of 4, and the HT-NoC architecture is configured with 12 columns.

[0031] To map a given CONV layer, a row-stationary RS data flow model is adopted to map the virtual configuration onto the physical grid.

[0032] To map this layer onto a 12 × 12 physical grid, the virtual configuration is cut into blocks of size 12 × 3. Data propagation in the CONV layer follows the same stages as the FC layer. Since weights are reused between nodes in the same row, weight propagation is performed in normal mode;

[0033] However, since ifmaps are not reused horizontally, their propagation uses the high throughput HT mode.

[0034] The ofmap collection phase is executed in normal mode using unicast;

[0035] To improve the data propagation efficiency in the HT-NoC architecture, the number of rows in the HT-NoC architecture is a multiple of 3 and is configured as 12 columns.

[0036] The beneficial effects of the present invention are as follows: the reconfigurable on-chip network of the data flow accelerator redirects unused ports, buffers and routing logic to the target direction by dynamically switching the router mode, thereby maximizing the utilization of bandwidth resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Attachment Figure 1 Schematic diagram of the HT-NoC architecture of the present invention.

[0039] Attachment Figure 2 This is a schematic diagram of the communication data packet structure of the present invention.

[0040] Attachment Figure 3 Schematic diagram of the router architecture of the present invention.

[0041] Attachment Figure 4 This is a schematic diagram of the router connection structure of the present invention.

[0042] Attachment Figure 5 Schematic diagram of the mapping method of the FC layer and the CONV layer of the present invention.

[0043] Attachment Figure 3 and attached Figure 4 The English symbols in the table are as follows:

[0044] Table 1 Attached Figure 3 and attached Figure 4 English and Chinese annotations

[0045]

[0046] DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0048] The data flow accelerator's reconfigurable network-on-chip uses a dual-mode reconfigurable router architecture. Each router integrates four HT switches: N_HT, E_HT, S_HT, and W_HT. Connection direction is controlled by a mode selection signal. It supports both the normal mode for standard mesh connections and the high-throughput HT mode for directional aggregated bandwidth.

[0049] In high-throughput HT mode, data is injected into the four ports (i.e., fully connected FC layer weights) in parallel using the north port IN, south port IS, east port IE, and west port IW. To fully utilize the bandwidth of each router, unused output ports are reconfigured to transmit data in the same direction (redirecting the north and south ports to the east and west adjacent routers), forming high-bandwidth links.

[0050] Optimize the FC layer (fully connected layer): weight parameters are injected in parallel through multiple inputs, the number of nodes in a single row is set to a multiple of 4, and four-way concurrent transmission is supported;

[0051] Optimize the CONV layer: For large-size ifmaps, use high-throughput HT mode to accelerate diagonal multicast to reduce transmission delay;

[0052] Supports configuration packets, control packets, and payload packets. Configuration packets contain mode instructions, and control packets define unicast / multicast / broadcast types. Configuration packets trigger mode switching and reuse idle resources (such as channels and buffers) to improve throughput.

[0053] The data flow accelerator's reconfigurable on-chip network includes an HT-NoC architecture and a router architecture;

[0054] The HT-NoC architecture adopts a two-dimensional grid topology design and uses an XY routing algorithm and wormhole flow control, with a channel width of 32 bits; Figure 1 As shown, the routers in the westernmost column serve as the entry points into the NoC; each router has four entry connections, namely the north port IN, the south port IS, the east port IE, and the west port IW, and the routers in the bottom row serve as the exit points;

[0055] The HT-NoC architecture supports unicast, multicast, and broadcast communications. Each router in the HT-NoC can operate in two different modes. Communication packets are divided into three types: configuration packets, control packets, and payload packets.

[0056] The configuration packet specifies the operating mode of the router, and the control packet indicates the communication type (unicast, multicast, or broadcast) and the number of payload packets to be transmitted; the control packet is followed by one or more payload packets, each of which contains only data.

[0057] exist Figure 2 The structure of a communication packet is shown in Figure 1, which includes a header flit and a mode flit. The header flit is used to specify the packet type and communication type, and the mode flit is used to define the mode required to configure the packet.

[0058] When the communication type is unicast, the communication data packet also includes the X and Y coordinates of the target node of the unicast communication, represented by ADX and ADY respectively, and the number of payload data packets NP;

[0059] When the communication type is multicast or broadcast, the communication data packet also includes the source coordinates ASX of multicast or the source coordinates AS of broadcast communication, and the number NP of payload data packets.

[0060] like Figure 3 As shown, in the router architecture, each router has five ports: north, south, west, east and local;

[0061] Incoming data packets are first stored in the input buffer FIFO of their corresponding ingress port. Afterwards, the incoming data is processed in the routing logic block (RLB) corresponding to the ingress port, and the routing logic block (RLB) determines the destination of the data packet. Finally, the data packet is forwarded to the central crossbar switch and then sent to the output port.

[0062] To introduce dynamic flexibility, the router can operate in two modes: normal mode and high-throughput HT mode. Each router is surrounded by four HT switches: N_HT, E_HT, S_HT, and W_HT. To operate in a specific mode, the router first receives a configuration packet that specifies the desired mode. After processing the packet, the router sets the mode select signal on each switch, thereby controlling the HT switches to operate in the selected mode.

[0063] Normal mode is the default mode. In this mode, each router is directly connected to its four neighbors, and the router's available output bandwidth is evenly distributed across its five output ports. This mode is suitable for applications that require multiple output ports by default, and for traffic patterns with moderate bandwidth requirements, where limited per-port bandwidth is compensated by data reuse, which occurs when a single piece of data is used by multiple nodes. In this case, data is retrieved only once from the source node and then propagated to all destination nodes.

[0064] High-throughput HT mode is designed for sustained, high-bandwidth traffic patterns that maintain a consistent direction, such as west-to-east, east-to-west, north-to-south, or south-to-north. A typical example is the propagation of weights in the FC layer. In the remainder of this paper, the present invention's research and results will focus on data traffic moving from west to east, as input data is injected into the HT-NoC via the router in the westernmost column and transmitted to the nodes in the east. However, this technique can also be adapted to other traffic directions. To fully utilize the available bandwidth of each router, unused output ports are reconfigured to transmit data in the same direction (west to east). As a result, in high-throughput HT mode, a router can simultaneously process up to four packets from the same neighboring router. In contrast, in normal mode, a router can only process one packet at a time from a given neighboring router. Because these four packets arrive at different input ports, they are processed by four independent input buffers (FIFOs) and routing logic blocks (RLBs), maximizing the utilization of the router's internal resources. Figure 4Figure 1 shows how routers are connected. Black arrows represent connections used in normal mode, where router R is connected to all of its neighboring routers. Blue arrows represent connections in high-throughput HT mode, where R is disconnected from its northern RN and southern RS neighbors and instead reroutes its northern and southern connections to connect to RW and RE. Red arrows represent connections used in both modes.

[0065] For the entry point routers in the westernmost column, in normal mode, connections IN, IE, and IS are connected to the neighboring routers RN, RE, and RS, respectively, while only IW serves as the entry point into the NoC. However, in high-throughput HT mode, IN, IS, and IE are disconnected from the neighboring routers and instead serve as additional entry points along with IW.

[0066] To map a given FC layer onto the HT-NoC architecture, an output-stationary OS dataflow model is adopted, where each output neuron is assigned to a specific node; the ifmap and weight required to calculate a given output neuron are first sent to the corresponding node; for a given X×Y configuration of the HT-NoC architecture, the first X output neurons are mapped to the first row:

[0067] If the number of output neurons exceeds the number of nodes, only the first XY neurons will be mapped simultaneously, and neurons ranked higher than XY will wait until the initial node is released before they can be mapped onto the grid. Figure 5 The process of mapping an FC layer with M input neurons and N output neurons to an X×Y accelerator is shown. For clarity, the output neurons and their corresponding nodes are intentionally colored the same. In the first row, the weights of nodes 1, 5, and 9 are injected into the HT-NoC through the IN port of router 1, while the weights of nodes 2, 6, and 10 are injected through the IE port. The weights of nodes 3, 7, and 11 are injected through the IS port, and the weights of nodes 4, 8, and 12 are injected through the IW port. This mechanism allows the weight packets of four consecutive nodes to be injected into the HT-NoC architecture simultaneously. The same process applies to the remaining rows.

[0068] The data propagation phase of the FC layer consists of three phases, as shown in Table 2: ifmap propagation, weight propagation, and ofmap collection. In addition to these phases, a computation phase can also be included, although no communication occurs during the computation phase because this is not managed by the NoC.

[0069] Table 2 Data propagation stages of FC layer and CONV layer

[0070] stage FC layer communication type model CONV layer communication type model Ifmap propagation broadcast normal Diagonal Multicast normal Weight Propagation Unicast HT Horizontal Multicast normal calculate No communication No communication No communication No communication Ofmap collection Unicast normal Unicast normal

[0071] During the ifmap propagation phase, the input neuron is propagated to all nodes of the grid. Figure 5 All input neurons in I1 to IM are injected through the IW port. Due to the data reuse feature, this stage is executed in normal mode;

[0072] During the weight propagation phase, each node receives the weights required to compute the corresponding output neuron. Unlike input neurons, weights are injected from all input ports of the routers in the westernmost column: north port IN, south port IS, east port IE, and west port IW. Due to the huge traffic load, this phase is performed in high-throughput HT mode, because for each row, four packets with different destinations are injected into the HT-NoC architecture simultaneously.

[0073] During the ofmap gather phase, each node in a given column of the grid sends its output neuron to the external output port of that column; the ofmap gather phase is executed in normal mode using unicast. Since four packets with different destinations can be transmitted simultaneously, it is important to ensure that four packets are sent to different nodes at a time; otherwise, the available bandwidth will not be fully utilized. Therefore, the number of nodes in a row of the grid should be a multiple of four, resulting in the HT-NoC architecture being configured with 12 columns.

[0074] To map a given CONV layer, a row-stationary RS data flow model is used. In theory, executing a two-dimensional CONV layer requires an O×K grid, where K is the number of filter rows and O is the number of ofmap columns. However, this virtual configuration does not necessarily correspond to the dimensions of the physical grid. Therefore, it is necessary to map this virtual configuration onto the physical grid. For example, the first CONV layer of VGG-16 applies a 3×3 filter to a 224×224 input image, generating a 224×224 ofmap. In this case, the virtual configuration is 224×3. To map this layer onto a 12×12 physical grid, the virtual configuration is cut into blocks of size 12×3. Figure 5 As shown, the first yellow block (containing columns 1 to 12) is mapped to the yellow area. The following blocks are mapped to the columns of the same color of the physical grid. After processing the first 48 columns, the next columns are mapped to the grid and executed. This process continues until all virtual columns have been processed. The data propagation of the CONV layer follows the same stages as the FC layer, as shown in Table 1. Since weights are reused between nodes in the same row, weight propagation is performed in normal mode. However, since ifmaps are not reused in the horizontal direction, their propagation uses high throughput HT mode. The ofmap collection phase is performed in normal mode using unicast. In modern convolutional neural networks (CNNs), 3×3 filters are widely used due to their effectiveness in feature extraction.

[0075] To improve the data propagation efficiency in the HT-NoC architecture, the number of rows in the HT-NoC architecture is a multiple of 3 and is configured as 12 columns.

[0076] The HT-NoC architecture was synthesized using the Xilinx Vivado Design Suite, targeting the AMD Versal XCVC1902 device. The performance of the HT-NoC was evaluated on various FC and CONV layers, summarized in Table 3, from existing deep neural network (DNN) models. Furthermore, the latency and dynamic energy consumption of propagating input data (weights and ifmaps) were analyzed. Results were obtained after running post-simulation of the HT-NoC's RTL model. The results show that the HT-NoC increases LUT usage by 17% and flip-flop usage by 4% compared to the baseline, primarily due to the addition of HT switches and logic for decoding the configuration word for mode switching.

[0077] Table 3 Layer Benchmarks

[0078]

[0079] FC layers are dominated by weight parameters, which are three orders of magnitude larger than the input neuron parameters. In terms of latency, HT-NoC improves data propagation speed by 4x across all layers, attributed to utilizing north, south, east, and west ports for communication. From an energy perspective, HT-NoC reduces energy consumption by an average of 2.7x per FC layer.

[0080] For all CONV layers, filter propagation latency is the same in both NoCs, as the HT-NoC architecture does not accelerate filter data transmission. However, the energy consumption of filter propagation increases slightly in the HT-NoC architecture, attributed to the reconfiguration mechanism. For ifmaps, the HT-NoC architecture achieves a 2.35x speedup and an average 2x energy savings over the baseline NoC. Unlike FC layers, the performance of the HT-NoC architecture in CONV layers depends significantly on the data size of each layer. For example, latency reduction reaches 55% in CONV2, 30% in CONV5 and CONV6, and only 5% in CONV11. Energy reduction is 45% in CONV2, 18% in CONV5 and CONV6, and a slight 5% increase in CONV11. This variation is due to the different ifmap and filter sizes in each layer. In early layers, the ifmap size is much larger than the filter. For example, CONV2, which exhibited the greatest speedup and energy reduction, had an ifmap size of 1,225,824 pixels and a filter size of only 36,864 pixels. In contrast, CONV11 had a filter size of 2,359,296 pixels and an ifmap size of only 100,352 pixels. These pixel counts reflect the total number of pixels across all channels of the filter and ifmap in each layer. Therefore, HT-NoC's performance in CONV layers is affected by the size of the ifmap relative to the filter. Optimal results are achieved when the ifmap is much larger than the filter.

[0081] The embodiment described above is only one specific implementation of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A reconfigurable network-on-chip for a data flow accelerator, characterized by: Adopting a dual-mode reconfigurable router architecture, each router integrates four HT switches: N_HT, E_HT, S_HT, and W_HT. Connection direction is controlled by mode selection signals. It supports both the normal mode for standard Mesh connections and the high-throughput HT mode for directional aggregated bandwidth. In high-throughput HT mode, data is injected into four ports in parallel: the north port IN, the south port IS, the east port IE, and the west port IW. To fully utilize the bandwidth of each router, unused output ports are reconfigured to transmit data in the same direction, forming a high-bandwidth link. Optimization of the FC layer: weight parameters are injected in parallel through multiple inputs, and the number of nodes in a single row is set to a multiple of 4, supporting four-way concurrent transmission; Optimization of the CONV layer: For large-size ifmaps, high-throughput HT mode is used to accelerate diagonal multicast to reduce transmission delay; Supports configuration packages, control packages and payload packages, and defines unicast / multicast / broadcast types through control packages; The configuration package contains mode instructions, which trigger mode switching through the configuration package to reuse idle resources to improve throughput.

2. The reconfigurable network-on-chip of the data flow accelerator according to claim 1, characterized in that: Including HT-NoC architecture and router architecture; The HT-NoC architecture adopts a two-dimensional grid topology design and uses an XY routing algorithm and wormhole flow control. The channel width is 32 bits. The routers in the westernmost column serve as the entry point into the on-chip network NoC. Each router has four entry connections, namely the north port IN, the south port IS, the east port IE, and the west port IW. The routers in the bottom row serve as the exit points. In the router architecture, each router has five ports: north, south, west, east, and local; Incoming data packets are first stored in the input buffer FIFO of their corresponding ingress port. Afterwards, the incoming data is processed in the routing logic block (RLB) corresponding to the ingress port, and the routing logic block (RLB) determines the destination of the data packet. Finally, the data packet is forwarded to the central crossbar switch and then sent to the output port. To operate in a specific mode, the router first receives a configuration packet that specifies the desired mode; after processing the packet, the router sets the mode selection signal of each switch, thereby controlling the HT switch to operate in the selected mode.

3. The reconfigurable network-on-chip of the data flow accelerator according to claim 2, characterized in that: The HT-NoC architecture supports unicast, multicast and broadcast communications, and the communication packets are divided into three types: configuration packets, control packets and payload packets; Configuration packets specify the router's operating mode, and control packets indicate the type of communication and the number of payload packets to be transmitted.

4. The reconfigurable network-on-chip of the data flow accelerator according to claim 3, characterized in that: The structure of the communication data packet includes a header flit and a mode flit. The header flit is used to specify the data packet type and communication type, and the mode flit is used to define the mode required to configure the data packet. When the communication type is unicast, the communication data packet also includes the X and Y coordinates of the target node of the unicast communication, represented by ADX and ADY respectively, and the number of payload data packets NP; When the communication type is multicast or broadcast, the communication data packet also includes the source coordinates ASX of multicast or the source coordinates AS of broadcast communication, and the number NP of payload data packets.

5. The reconfigurable network-on-chip of the data flow accelerator according to claim 2, characterized in that: Normal mode is the default mode, in which each router is directly connected to its four neighboring routers, and the router's effective output bandwidth is evenly distributed among its five output ports; The limited bandwidth of each port is compensated by data reuse, which refers to the situation where a single piece of data is used by multiple nodes. The data is only obtained once from the source node and then propagated to all destination nodes. In high-throughput HT mode, continuous high-bandwidth traffic patterns maintain a consistent direction, and the router is able to simultaneously process up to four packets from the same neighboring router; these four packets arrive at different input ports and are processed by four independent input buffers (FIFOs) and routing logic blocks (RLBs), thereby maximizing the utilization of the router's internal resources.

6. The reconfigurable network-on-chip of the data flow accelerator according to claim 2, characterized in that: To map a given FC layer onto the HT-NoC architecture, an output-stationary OS dataflow model is adopted, where each output neuron is assigned to a specific node; the ifmap and weight required to calculate a given output neuron are first sent to the corresponding node; for a given X×Y configuration of the HT-NoC architecture, the first X output neurons are mapped to the first row: If the number of output neurons exceeds the number of nodes, only the first XY neurons will be mapped simultaneously, and neurons ranked higher than XY will wait until the initial node is released before they can be mapped onto the grid; This mechanism allows the weight packets of four consecutive nodes to be injected into the HT-NoC architecture simultaneously.

7. The reconfigurable network-on-chip of the data flow accelerator according to claim 6, characterized in that: The data propagation phase of the FC layer includes three stages: ifmap propagation, weight propagation, and ofmap collection; In the ifmap propagation phase, the input neuron is propagated to all nodes of the grid, executing in normal mode; In the weight propagation phase, each node receives the weights required to compute the corresponding output neuron; Unlike input neurons, weights are injected from all input ports of the router in the westernmost column, namely, north port IN, south port IS, east port IE, and west port IW. Due to the huge traffic load, this stage is performed in high-throughput HT mode, because for each row, four packets with different destinations are injected into the HT-NoC architecture simultaneously. In the ofmap gather phase, each node in a given column of the grid sends its output neuron to the external output port of that column; the ofmap gather phase is executed in normal mode using unicast; the number of nodes in a row of the grid is a multiple of 4, configuring the HT-NoC architecture into 12 columns.

8. The reconfigurable network-on-chip of the data flow accelerator according to claim 2, characterized in that: In order to map a given CONV layer, a row-stationary RS data flow model is adopted to map the virtual configuration onto the physical grid; The data propagation phase of CONV consists of three stages: ifmap propagation, weight propagation, and ofmap collection; Since ifmap is not reused in the horizontal direction, high throughput HT mode is used during the ifmap propagation phase; Since weights are reused between nodes in the same row, weight propagation proceeds in normal mode; The ofmap collection phase is executed in normal mode using unicast; To improve the data propagation efficiency in the HT-NoC architecture, the number of rows in the HT-NoC architecture is a multiple of 3 and is configured as 12 columns.

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