Reconstruction method of integrated circuit layout file, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an integrated circuit layout file reconstruction method, electronic equipment and a storage medium. The method comprises the following steps: acquiring a set of repeated image areas in a layout image of an integrated circuit layout, wherein the repeated image areas are image areas which are the same as at least one other image area after affine transformation in the layout image; dividing the set of repeated image areas into at least one image area group, wherein the repeated image areas in each image area group are the same after affine transformation; and generating a new layout file with a hierarchical unit structure of the integrated circuit layout based on the at least one image region group.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor integrated circuit technology, and more particularly, to a method, electronic device, and computer-readable storage medium for reconstructing a layout file of an integrated circuit layout. Background Art

[0002] The layout file of a semiconductor integrated circuit is the core data carrier of the physical layout. It contains data such as the geometric shape (such as transistors, connecting lines, etc.), hierarchical structure, layout size, etc. of the semiconductor integrated circuit or chip. Therefore, the layout file is a key input file for photolithography mask manufacturing.

[0003] Chip process size represents the minimum feature size of components such as transistors in semiconductor manufacturing and is typically measured in nanometers. As chip process sizes continue to shrink, the number of elements contained in the layout is growing exponentially. In this context, the efficient organization of elements in the layout file is becoming increasingly important. Inefficient element organization can severely impact the efficiency of various stages of integrated circuit and chip manufacturing. Summary of the Invention

[0004] In order to at least partially solve the above and other possible problems, an embodiment of the present disclosure provides a solution for reconstructing a layout file of an integrated circuit layout.

[0005] According to one aspect of the present disclosure, a method for reconstructing a layout file for an integrated circuit layout is provided. The method includes: obtaining a set of repeated image regions in a layout image of the integrated circuit layout, wherein the repeated image regions are image regions in the layout image that are identical to at least one other image region after an affine transformation; dividing the set of repeated image regions into at least one image region group, wherein the repeated image regions in each image region group are identical to each other after an affine transformation; and generating a new layout file for the integrated circuit layout having a hierarchical unit structure based on the at least one image region group.

[0006] In a second aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions comprising: obtaining a set of repeated image areas in a layout image of an integrated circuit layout, the repeated image areas being image areas in the layout image that are identical to at least one other image area after an affine transformation; dividing the set of repeated image areas into at least one image area group, the repeated image areas in each image area group being identical to each other after an affine transformation; and generating a new layout file having a hierarchical unit structure for the integrated circuit layout based on the at least one image area group.

[0007] In some embodiments of the present disclosure, the action also includes: obtaining information associated with an initial layout file of the integrated circuit layout, the information including graphic information and hierarchical information of the initial layout file; determining a zoom setting and a coordinate transformation setting based on a size of the integrated circuit layout and a predefined layout image resolution; and generating a layout image by rendering based on the obtained information and the determined zoom setting and coordinate transformation setting, wherein different structural layers in the hierarchical structure of the integrated circuit layout are rendered into different colors.

[0008] In some embodiments of the present disclosure, the affine transformation includes at least one of translation, rotation, and scaling.

[0009] In some embodiments of the present disclosure, obtaining a set of repeated image areas in a layout image includes the following steps: a) dividing the layout image into a plurality of image blocks according to a predetermined block size; b) classifying the plurality of image blocks based on image features and geometric features of each of the plurality of image blocks; c) generating a matrix based on positions and categories of the plurality of image blocks; and d) determining repeated image areas of the layout image based on the generated matrix, and generating a set of repeated image areas.

[0010] In some embodiments of the present disclosure, b) classifying the multiple image blocks based on the image features and geometric features of each image block in the multiple image blocks includes: for each image block in the multiple image blocks, using an image feature algorithm to obtain the image features of the corresponding image block, obtaining the geometric features of the corresponding image block by determining the physical position of the corresponding image block in the integrated circuit layout, and fusing the image features and geometric features of the corresponding image block; and classifying the multiple image blocks based on the fused features of each image block in the multiple image blocks using a clustering algorithm.

[0011] In some embodiments of the present disclosure, obtaining a set of repeated image areas in a layout image further includes: changing the predetermined block size at least once; performing steps a) to d) after each change of the predetermined block size; determining an optimal predetermined block size by evaluating the area and / or number of elements of the repeated image areas corresponding to various predetermined block sizes; and determining a set of repeated image areas based on the optimal predetermined block.

[0012] In some embodiments of the present disclosure, obtaining a set of repeated image regions in a layout image further includes: performing preprocessing including image denoising and texture enhancement on the layout image before dividing the layout image into a plurality of image blocks.

[0013] In some embodiments of the present disclosure, dividing a set of repeated image regions into at least one image region group includes: clustering the repeated image regions in the set using an image algorithm with scaling and rotation invariance; and determining at least one image region group based on the clustering result.

[0014] In some embodiments of the present disclosure, generating a new layout file having a hierarchical unit structure for an integrated circuit layout based on at least one image area group includes: determining a repeated image area in each image area group as a basic unit; generating a first hierarchical structure including at least two layers and a reference relationship between layers based on the basic unit, wherein one of the at least two layers includes the basic unit of each image area group, and the reference relationship includes affine transformation information between the basic unit in each image area group and other repeated image areas; and generating a new layout file having a hierarchical unit structure for the integrated circuit layout based on the first hierarchical structure.

[0015] In some embodiments of the present disclosure, the first hierarchical structure includes a first layer, a second layer, and a reference relationship between the first layer and the second layer, wherein the first layer includes non-repeating image areas, the second layer includes basic units of each image area group, and the affine transformation information in the reference relationship includes at least one of a translation position, a scaling factor, and a rotation angle.

[0016] In some embodiments of the present disclosure, generating a new layout file having a hierarchical cell structure for an integrated circuit layout based on a first hierarchical structure includes: selecting at least a portion of basic cells from a second layer; generating a second hierarchical structure by iteratively generating a hierarchical structure identical to the first hierarchical structure within each basic cell in at least a portion of the basic cells; and generating a new layout file based on the second hierarchical structure and the initial layout file.

[0017] In some embodiments of the present disclosure, generating a new layout file having a hierarchical unit structure for an integrated circuit layout based on at least one image area group further includes: before determining the basic unit, for each image area group in the at least one image area group: determining the physical position of each repeated image area in the corresponding image area group in the integrated circuit layout, obtaining the geometric figures at the physical position from the initial layout file, and verifying based on the obtained geometric figures whether each repeated image area in the corresponding image area group is identical to each other after at least one of translation, rotation and scaling operations and removing different image areas.

[0018] In a third aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0019] It should be understood that the contents described in the Summary of the Invention section are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present disclosure.

[0021] Figure 1 A schematic diagram illustrating an example scenario in which embodiments of the present disclosure can be implemented is shown.

[0022] Figure 2 A schematic flowchart of a method for reconstructing a layout file of an integrated circuit layout according to an embodiment of the present disclosure is shown.

[0023] Figure 3A An exemplary schematic diagram of generating a layout image by rendering an initial layout file according to an embodiment of the present disclosure is shown.

[0024] Figure 3B A schematic diagram illustrating an exemplary integrated circuit layout according to an embodiment of the present disclosure is shown.

[0025] Figure 3C A schematic diagram illustrating an exemplary integrated circuit layout image according to an embodiment of the present disclosure is shown.

[0026] Figure 4A A schematic diagram showing a partial process of image processing on a layout image according to an embodiment of the present disclosure is shown.

[0027] Figure 4B A schematic diagram showing an exemplary layout image after preprocessing according to an embodiment of the present disclosure is shown.

[0028] Figure 5 A schematic diagram showing a partial process of image processing on a layout image according to an embodiment of the present disclosure is shown.

[0029] Figure 6 A schematic diagram showing a partial process of image processing on a layout image according to an embodiment of the present disclosure is shown.

[0030] Figure 7 A schematic diagram showing a partial process of image processing on a layout image according to an embodiment of the present disclosure is shown.

[0031] Figure 8A schematic diagram illustrating dividing a set of repeated image regions into at least one image region group according to an embodiment of the present disclosure is shown.

[0032] Figure 9 A schematic diagram of generating a new layout file with a hierarchical unit structure according to an embodiment of the present disclosure is shown.

[0033] Figure 10 A schematic diagram of generating a new layout file with a hierarchical unit structure according to an embodiment of the present disclosure is shown.

[0034] Figure 11 A schematic flowchart of a process of generating a layout image by rendering a layout file of an integrated circuit according to an embodiment of the present disclosure is shown.

[0035] Figure 12 A schematic flowchart of a process of obtaining a set of repeated image regions in a layout image by performing image processing on the layout image according to an embodiment of the present disclosure is shown.

[0036] Figure 13 A schematic flowchart of a process of dividing a set of repeated image regions into at least one image region group according to an embodiment of the present disclosure is shown.

[0037] Figure 14 A schematic flowchart of a process for generating a new layout file of an integrated circuit layout based on at least one image region group according to an embodiment of the present disclosure is shown.

[0038] Figure 15 A schematic flowchart of a process of generating a new layout file based on a first hierarchical structure according to an embodiment of the present disclosure is shown.

[0039] Figure 16 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0040] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art. Those skilled in the art can derive alternative technical solutions from the following description without departing from the spirit and scope of protection of the present disclosure.

[0041] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based, at least in part, on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." Other explicit and implicit definitions may be included below.

[0042] As mentioned above, the number of elements in the layout of integrated circuits is increasing, and the organizational efficiency of the element organization structure of the layout file will have a great impact on mask manufacturing, process rule verification (such as Design Rule Check, DRC and layout and principle Figure 1 This can impact manufacturing processes such as Layout Versus Schematic (LVS) and Optical Proximity Correction (OPC). For example, DRC scans all patterns in the layout for conformance to manufacturing rules, such as minimum line width and spacing requirements. OPC simulates lithography imaging and adds correction patterns. Therefore, if the layout file's element organization is inefficient, repeated calculations of duplicate modules can occur, resulting in low operational efficiency.

[0043] Currently, there are two main storage structures for various geometric data in layout files, one is the flat structure (FlatStructure) and the other is the hierarchical cell structure (Hierarchical Cell Structure). All geometric figures in the flat structure are flattened in corresponding positions, so the data compression rate is not high. The hierarchical cell structure usually includes multiple levels, and there are several basic units in each level. These units are connected to form a tree structure by referencing each other. The references between units place the child units in different positions of the parent unit through various linear transformations (such as translation, scaling, and rotation). This nested cell reference in the hierarchical cell structure advantageously reduces the redundant storage of repeated geometric data.

[0044] In integrated circuit manufacturing, since the design principles, generation methods, and sources of layout files are uncontrollable, the data organization or element organization structure in the layout files that need to be processed is often not efficient enough, and there will be a large number of repeated modules that are not organized according to or only partially organized according to the hierarchical structure. In order to improve the efficiency of the organizational structure, some solutions will analyze the characteristics of each hierarchy and the geometric characteristics of each unit based on the current hierarchy and basic units of the layout file, so as to find units with similar characteristics to merge to improve data utilization. In addition, there are some solutions that obtain all the geometric figures in the layout, generate some initial seed areas based on the seed area generation algorithm, and then search for possible repeated areas in the entire layout file based on the geometric characteristics of the seed areas, and try to add new geometric figures around the found repeated areas, so as to find possible repeated areas in the entire layout based on the new areas, and iterate multiple rounds until convergence.

[0045] However, these solutions rely heavily on the original hierarchical structure and basic units of the layout, resulting in poor robustness. Because they require multiple rounds of data extraction and matching on all geometric data in the layout, these solutions are computationally intensive and time-consuming. Furthermore, current solutions are primarily based on geometric feature matching and utilize algorithms based on geometric features and geometric properties, making it difficult to handle scenarios where rotation and scaling exist between different repetitive regions. Furthermore, most algorithms extract geometric features from local regions, lacking a global perspective and easily falling into local optimality rather than finding a globally optimal reconstruction method.

[0046] Embodiments of the present disclosure provide an improved solution for reconstructing the layout file of an integrated circuit layout. In this improved solution, the initial layout file of the integrated circuit layout is rendered to generate a layout image. The layout image is then image processed to obtain a set of repeated image regions. After grouping the set of repeated image regions, a new layout file with a hierarchical unit structure is reconstructed. In this way, the layout file of the integrated circuit layout can be efficiently reconstructed. The reconstruction process does not rely on the original hierarchical structure of the layout file and is therefore also applicable to layouts with poor hierarchical structures. This expands the application scope and application scenarios of layout file reconstruction. Because the layout file is rendered into a layout image, features can be extracted from both global and local perspectives, which facilitates finding the globally optimal reconstruction method. Moreover, computational matching on a single layout image avoids performing a large amount of iterative matching of geometric data, thereby significantly improving computational and processing efficiency. In addition, the layout image generated by rendering can easily extract image features, which facilitates matching issues after scaling and / or rotation of geometric figures within basic units and is more conducive to detecting graphic distortion caused by OPC. In addition, image features can be advantageously combined with geometric features, thereby compensating for each other's shortcomings in feature matching during the reconstruction process, while ensuring the nanometer-level precision of geometric features and the physical perceptibility of image features.

[0047] Figure 1 A schematic diagram of an example scenario 100 in which embodiments of the present disclosure can be implemented is shown. Computing device 110 in example scenario 100 can be any device with computing capabilities. Computing device 110 can include storage 111 and processing 112. In one example, computing device 110 can be any type of stationary computing device, mobile computing device, or portable computing device. For example, computing device 110 includes, but is not limited to, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a multimedia computer, a mobile phone, and the like. In another example, all or a portion of the components of computing device 110 can be distributed in the cloud.

[0048] In the example scenario 100 , the computing device 110 may obtain an initial layout file 120 of an integrated circuit layout and reconstruct the initial layout file 120 , thereby generating or outputting a reconstructed new layout file 130 .

[0049] Figure 2 FIG2 shows a schematic flow chart of a method 200 for reconstructing a layout file of an integrated circuit layout according to an embodiment of the present disclosure. Figure 1 100 and executed by a computing device 110. For the purpose of discussion, Figure 1Method 200 will be described.

[0050] In block 201, computing device 110 obtains a set of repeated image regions in a layout image of an integrated circuit layout. Repeated image regions are image regions in the layout image that are identical to at least one other image region after undergoing an affine transformation. Each repeated image region may correspond to a geometric region in the layout. Recurring repeated image regions may be found in the layout image using methods such as image processing, and these repeated image regions may be identified to generate a set of image regions. In other words, as long as an image region appears repeatedly in the layout image, it may be included in the set of repeated image regions. In some embodiments, the affine transformation includes at least one of translation, rotation, and scaling. Translation refers to shifting the image region as a whole to change its coordinate position, rotation refers to rotating the image region as a whole to change its orientation, and scaling refers to scaling the image region as a whole to change its size or dimension. In other words, after undergoing at least one of translation, rotation, and scaling, the repeated image region may become the same as at least one other image region.

[0051] At block 202, computing device 110 divides the set of repeated image regions into at least one image region group, wherein the repeated image regions in each image region group are identical to each other after undergoing an affine transformation. Thus, the set of repeated image regions can be divided into at least one group, so that substantially different image regions are grouped into different groups and substantially identical image regions are grouped into the same group. Repeated image regions in the same group can reference or establish associations with each other through an affine transformation.

[0052] At block 203, computing device 110 generates a new layout file 130 of the integrated circuit layout with a hierarchical unit structure based on at least one image region group. The image regions within each image region group are recurring and can reference each other through affine transformations. Based on this, a new layout file can be created using at least one image region group of the layout image, following the hierarchical unit structure. Compared to the initial layout file, this new layout file reduces duplicate data, is more efficient in terms of storage and organization, and can improve processing efficiency in all stages of chip manufacturing.

[0053] Figure 3A FIG. 1 shows an exemplary schematic diagram of generating a layout image 20 by rendering an initial layout file 10 according to an embodiment of the present disclosure. Figure 3B A schematic diagram illustrating an exemplary integrated circuit layout according to an embodiment of the present disclosure is shown, and Figure 3C FIG. 1 shows a schematic diagram of an exemplary integrated circuit layout image according to an embodiment of the present disclosure. Figures 3A to 3C As shown, the layout file 10 can be Figure 1The initial layout file 120 of the integrated circuit layout shown in FIG. 1 can be converted into a layout image 20 by rendering. In some embodiments of the present disclosure, the computing device 110 can obtain information associated with the initial layout file of the integrated circuit layout, including graphic information and layer information of the initial layout file. The computing device 110 also determines a scaling setting and a coordinate transformation setting based on the size of the integrated circuit layout and a predefined layout image resolution. Thus, the computing device 110 generates the layout image 20 by rendering based on the obtained information and the determined scaling setting and coordinate transformation setting.

[0054] As an example, computing device 110 may parse layout file 10 to extract relevant information and calculate the required scaling dimensions based on the layout dimensions (typically in nanometers) and a predefined layout image resolution. This allows for coordinate conversion and scaling to convert the physical dimensions of the geometric shapes in the layout into corresponding pixel values. Computing device 110 may then construct a canvas and draw the extracted geometric shapes as a layout image on the canvas, for example, using a graphics library in a programming language. In one example, the graphics library may include Pillow in Python, Matplotlib, OpenCV in C++, or a custom-developed drawing algorithm. In one embodiment, obtaining information associated with the initial layout file of the integrated circuit layout includes obtaining graphic information and hierarchy information from the initial layout file. For example, the graphic information may include polygons, rectangles, paths, and circles. If the initial layout file has a hierarchical structure, computing device 110 may obtain the hierarchy information. For example, the hierarchy information may include basic units and reference information. Computing device 110 may recursively process references to subunits to ensure that all instances are rendered correctly. In one embodiment, different structural layers in the hierarchical structure of the integrated circuit layout can be rendered in different colors. As an example, the hierarchical structure of the layout may include structural layers such as metal layers, diffusion layers, and contact layers, and the computing device 110 may render different structural layers with different colors, thereby retaining the physical separation information of the original device. In this way, interference between different structural layers can be avoided to cause feature confusion, and it is beneficial to perform image segmentation and image feature extraction based on different colors in subsequent steps. It can be understood that the generation and acquisition of layout images can be implemented in other existing ways or new ways to be developed in the future, without being limited thereto. However, the above-mentioned layout image generation method is more preferred for reconstructing layout files using layout images, because the above-mentioned method can obtain layout images that are more conducive to subsequent repeated image area detection, and can be applied to layout files that already have a certain hierarchical structure, thereby helping to achieve efficient and accurate layout file reconstruction in a larger range of applications and scenarios.

[0055] Figure 4A A schematic diagram showing an optional process of image processing the layout image 20 according to an embodiment of the present disclosure is shown, and Figure 4B FIG. 2 shows a schematic diagram of an exemplary layout image 20 after preprocessing according to an embodiment of the present disclosure. Figure 4A and Figure 4B As shown, in some embodiments of the present disclosure, computing device 110 can perform preprocessing on layout image 20, including image denoising and texture enhancement. For example, Gaussian filtering or algorithms such as erosion and dilation operations in image morphology can be used to denoise the image, and Fourier transforms or Laplace transforms can be used to enhance texture details at the image edges. This preprocessing can produce a layout image with better image quality and better suited for subsequent processing.

[0056] Figure 5 FIG. 2 shows a schematic diagram of an optional process of image processing for a layout image 20 according to an embodiment of the present disclosure. Figure 5As shown, in some embodiments of the present disclosure, the computing device 110 divides the layout image 20 into multiple image blocks according to a predetermined block size. As an example, as shown by the dotted lines in the figure, the layout image 20 can be divided into 10×6 image blocks or any other number of image blocks in the horizontal and vertical directions according to the predetermined block size or predetermined granularity. In one example, a layout such as SRAM has obvious edge contour features, so the connected contour area in the image can be obtained based on the edge detection algorithm (such as Canny edge detection). In some embodiments of the present disclosure, the computing device 110 classifies the multiple image blocks based on the image features and geometric features of each image block in the multiple image blocks. Specifically, image features refer to features extracted from the image. For example, image features can be image texture features and color features, etc., and can form multiple different categories of features (such as SIFT features, SURF features, Gabor features, neural network features, etc.) according to the different algorithms used to extract features. Geometric features refer to features extracted from geometric figures. For example, the geometric features of an image block correspond to the geometric features of layout elements within the image block (e.g., minimum line width, perimeter, area, edge spacing, etc.). Different categories of geometric features can be formed based on defined geometric rules. Furthermore, computing device 110 can cluster all image blocks based on their geometric and image features, for example using common clustering algorithms such as Kmeans or density-based clustering (DBSCAN), to further classify all image blocks into several categories. In one example, the classification process can use Euclidean distance as a similarity metric and iteratively optimize the intra-cluster sum of squares to achieve compact clusters within clusters and separate clusters between clusters. In one example, the number of categories into which the image blocks are classified can be predefined. In one embodiment, computing device 110 can perform the following operations for each of the multiple image blocks: utilize an image feature algorithm to obtain image features of the corresponding image block; determine the physical location of the corresponding image block in the integrated circuit layout to obtain geometric features of the corresponding image block; and fuse the image and geometric features of the corresponding image block. As an example, an image feature operator (such as a Gabor filter, a gray-level co-occurrence matrix, etc.) can be used to extract image features from an image block. In addition, the area corresponding to the image block in the layout can be calculated based on the position and size of the image block and according to a scaling parameter, thereby obtaining a geometric figure within the area, wherein the geometric features of the geometric figure can be described by the topological structure features of the figure or the positional relationship between the vertex and the center point of the figure within the area. The image features and the geometric features can be normalized and feature fused separately to obtain fused features of all image blocks. Thus, the computing device 110 can classify the multiple image blocks using a clustering algorithm based on the fused features of each image block in the multiple image blocks.In this way, the image features and geometric features of each image block can be combined to form a fused feature for use in other subsequent classification processing steps. By considering both image and geometric features, it can provide many advantages over conventional solutions that only consider geometric features. Specifically, image features can provide an observation dimension that is closer to the global perspective than geometric features, while geometric features make up for the defects of image features in expressing blind spots caused by resolution loss. By combining the two, it is possible to simultaneously ensure the nanometer-level accuracy of geometric data and the physical perception of image features.

[0057] Figure 6 and Figure 7 FIG. 2 shows a schematic diagram of an optional process of image processing for a layout image 20 according to an embodiment of the present disclosure. Figure 6 and Figure 7 As shown, in some embodiments of the present disclosure, computing device 110 generates a matrix based on the positions and categories of multiple image blocks. Based on the generated matrix, computing device 110 determines repeated image regions 20A to 20H of layout image 20 and generates a set 21 of repeated image regions. Repeated image regions refer to image regions that appear repeatedly in the layout image (including regions with different rotational orientations and different scales). Repeated image regions can be composed of one or more image blocks. By generating a matrix, the process of finding repeated image regions in the layout image is converted into the process of finding repeated sub-matrices in a large matrix.

[0058] As an example, a matrix can be formed based on the multiple image blocks into which the layout image 20 is divided. For example, if the layout image 20 is divided into 10×6 image blocks, the corresponding matrix is ​​a 10×6 matrix, and the elements in the matrix are the classification results (e.g., category numbers) determined after each image block is classified. Repeated sub-matrices can be found and determined in the matrix through matrix algorithms such as brute force enumeration and hash block methods. Then, the position of the repeated sub-matrices in the layout image can be calculated from the position mapping of the repeated sub-matrices, so that the repeated image areas 20A to 20H that appear repeatedly in the layout image can be determined. The repeated image areas 20A to 20H are identified and form a set 21 of repeated image areas.

[0059] It is understandable that other methods can also be used to detect repeated image regions and generate sets. For example, repeated image regions can be determined by image comparison, or repeated image regions can be determined in the layout image using a neural network model. Figures 5 to 7 The described steps to obtain repeated image regions and generate a set are more preferred because this approach can convert the image into a matrix and use a matrix algorithm to determine the repeated image regions, thereby achieving more efficient and comprehensive repeated image region detection.

[0060] In some embodiments of the present disclosure, the computing device 110 may change the size of the predetermined block of the layout image 20 at least once, and after each change of the predetermined block size, repeatedly execute Figures 5 to 7 That is, the division of the layout image 20 can be repeated multiple times at different granularities, thereby allowing the layout image 20 to be divided multiple times according to a larger predetermined block size or a smaller predetermined block size, and the steps of image block classification, matrix generation, and determination of repeated image regions are performed for the results of each division, thereby obtaining a set of multiple different repeated image regions corresponding to a plurality of different predetermined block sizes. In some embodiments of the present disclosure, the computing device 110 can determine the optimal predetermined block size by evaluating the area and / or number of elements in the repeated image regions corresponding to various predetermined block sizes, and determine the set of repeated image regions based on the optimal predetermined block size. For example, the ratio of the area of ​​the repeated image region to the total area of ​​the layout or the ratio of the number of elements in the repeated image region to the total number of elements in the layout can be evaluated, which helps determine the profitability of reconstructing the layout file and thereby select the image division method with the best profitability. For example, the computing device 110 can select the predetermined block with the largest area of ​​the repeated image region as the optimal predetermined block, or can select other predetermined blocks as the optimal predetermined block based on cost or other factors. In this way, repeated image regions generated by various block division methods can be compared to obtain an optimal or desired set of repeated image regions.

[0061] Figure 8 FIG. 2 shows a schematic diagram of dividing a set 21 of repeated image regions into at least one image region group 22-1, 22-2 and 22-3 according to an embodiment of the present disclosure. Figure 8As shown, in some embodiments of the present disclosure, computing device 110 utilizes an image algorithm with scale and rotation invariance to cluster duplicate image regions in set 21 of duplicate image regions and, based on the clustering results, determines at least one image region group 22-1, 22-2, and 22-3. For example, computing device 110 may extract texture features from each image region 20A to 20H in the set of duplicate image regions, for example, using an image algorithm with scale and rotation invariance (such as the SIFT operator, SUFR operator, or ORB operator). Using this scale and rotation invariance, duplicate regions can be identified even after scaling or rotation. Using the extracted texture features and auxiliary information such as image region size, computing device 110 may utilize a clustering algorithm to cluster set 21 of duplicate image regions, thereby obtaining image region groups 22-1, 22-2, and 22-3. For example, set 21 including repeated image regions 20A to 20H is divided into three image region groups: image region group 22-1 includes repeated image regions 20A, 20E, 20F, and 20G; image region group 22-2 includes repeated image regions 20B and 20C; and image region group 22-3 includes repeated image regions 20D and 20H. Each image region group includes multiple repeated image regions that differ only in position, orientation, and / or scale. It will be understood that the number of repeated image regions and image region groups shown in the figures is merely exemplary and non-limiting, and that the number of repeated image regions and image region groups may be greater or lesser, or any other number.

[0062] Figure 9 FIG. 1 shows a schematic diagram of generating a new layout file having a hierarchical unit structure according to an embodiment of the present disclosure. Figure 9As shown, in some embodiments of the present disclosure, the computing device 110 determines a repeating image region in each image region group as a basic unit, and generates a first hierarchical structure 23 based on the basic unit, including at least two layers and a reference relationship between the layers. One of the at least two layers includes the basic unit of each image region group, and the reference relationship includes affine transformation information between the basic unit and other repeating image regions in each image region group. The basic unit or the repeating image region determined as the basic unit may include a set of all image elements in the corresponding area in the layout. Thus, the image region group can be used to establish a hierarchical structure that can reduce repeating modules. In some embodiments, the first hierarchical structure 23 includes a first layer 231, a second layer 232, and a reference relationship between the first layer 231 and the second layer 232. The first layer 231 includes non-repeating image regions, the second layer 232 includes the basic unit of each image region group, and the affine transformation information in the reference relationship includes at least one of a translation position, a scaling factor, and a rotation angle. For example, the repeated image regions 20A, 20C, and 20D in the image region groups 22-1, 22-2, and 22-3 can be identified as basic units and arranged in the second layer 232, respectively. Other image regions in the layout image that are not classified as repeated image regions (i.e., non-repeated image regions) are arranged in the first layer 231. The non-repeated image regions can include all geometric shapes within them. The first layer 231 is connected to the basic units in the second layer 232 via a reference relationship. This reference relationship records transformation information between the basic units and the repeated image regions outside the basic units, such as translation position, scaling factor, and rotation angle. Thus, the repeated image regions outside the basic units can be represented using the reference relationship between the basic units in the first layer 231 and the first and second layers 231, 232, without having to arrange and store the repeated image regions in the first and second layers 231, 232 of the hierarchical structure. This reduces the number of repeated modules and repeated units within the layout file. In some embodiments of the present disclosure, the computing unit 110 generates a new layout file for the integrated circuit layout with a hierarchical unit structure based on the first hierarchical structure 23. In this way, the repetitive units in the layout can be determined to the greatest extent possible, and the inefficient initial layout file can be rebuilt into a hierarchical unit structure with a more efficient organizational structure.

[0063] In some embodiments of the present disclosure, before determining the basic unit, for each of at least one image region group 22-1, 22-2, and 22-3, the computing device 110 determines the physical location of each repeated image region in the corresponding image region group in the integrated circuit layout, obtains the geometry at the physical location from the initial layout file, and, based on the obtained geometry, verifies whether the repeated image regions in the corresponding image region group are identical after at least one of translation, rotation, and scaling operations, and removes different image regions. For example, the physical location of each image region in the layout file can be calculated based on the pixel location and scaling scale of the image region in the layout image, thereby obtaining the geometry corresponding to the physical location. Then, a transformation matrix (e.g., including a translation vector, rotation angle, and scaling factor) can be calculated for the geometry of different image regions in the same image region group. Based on the transformation matrix, it is determined whether the geometry of different image regions in the same image region group is consistent after undergoing linear transformation. If all image regions within the same group are consistent, the verification is considered successful. If there are inconsistent image regions, these can be removed, or some or all of the previous steps can be re-executed to regenerate the image region group. In this way, the duplicate image regions generated by image processing and their grouping results can be verified to ensure the correctness of the reconstructed layout file.

[0064] Figure 10 FIG. 1 shows a schematic diagram of a new layout file having a hierarchical cell structure for generating an integrated circuit layout according to an embodiment of the present disclosure. Figure 10 As shown, in some embodiments of the present disclosure, the computing unit 110 selects at least a portion of basic units from the second layer 232, and generates a second hierarchical structure 24 by iteratively generating a hierarchical structure identical to the first hierarchical structure 23 within each basic unit of the selected at least a portion of basic units. As an example, the computing unit 110 may select a larger basic unit, such as the image area 20C, from the second layer 232. The computing unit 110 may iteratively perform the steps of: Figures 3A to 9That is, using a process identical or similar to that used to process the initial layout file for the layout, rendering, image processing, grouping, and first-level hierarchical structure generation are performed on the selected basic units, thereby further establishing the first-level hierarchical structure within the selected basic units and obtaining reference information for basic units of even smaller granularity. The above process can be further iterated for basic units of even smaller granularity and subsequently generated basic units. For example, image region 20C, serving as a basic unit, is further processed to generate hierarchical structure 24C and a lower-level hierarchical structure 241C. Thus, the first hierarchical structure 23 is converted into a second hierarchical structure 24 having N (greater than 2) layers. It will be understood that the number of basic units selected above and the number of hierarchical layers are merely exemplary and non-limiting. More basic units can be selected as needed to form hierarchical structures with more or fewer layers. As long as the basic units of the second layer 232 and the subsequently obtained basic units of even smaller granularity contain repeated units or regions, they can be selected for further iterative processing.

[0065] In some embodiments of the present disclosure, computing device 110 generates a new layout file 130 based on the second hierarchical structure 24 and initial layout file 120 or 10. For example, information about basic units and reference relationships (also referred to as vertices and edges in the structure) at each level of the second hierarchical structure 24 can be traversed from bottom to top. Furthermore, the coordinate positions of the basic units can be used to obtain the geometry within the basic units by querying the initial layout file of the layout. Based on the obtained information and the geometry of the basic units, new layout file 130 is generated using the second hierarchical structure according to the storage format information of the layout file.

[0066] Through the embodiments of the present disclosure, the initial file of the integrated circuit layout can be rendered into a layout image and image processing can be performed to obtain repeated image areas and their groupings for reconstructing the layout file. In this way, features can be extracted from both the global perspective and the local perspective at the pixel level, which is more conducive to determining the global optimal solution. Moreover, since the calculation matching is performed on a single image and does not depend on the initial hierarchical structure of the layout file, the processing efficiency can be significantly improved and it is suitable for the reconstruction of layouts with poor hierarchical structures. In addition, the layout image generated by rendering is easy to introduce image features, thereby obtaining more beneficial effects. The texture features in the image have the characteristics of scale and rotation invariance, so it is helpful to solve the problem that the geometric figures within the basic unit are difficult to match successfully after scaling or rotation. OPC will correct the original shape of the layout, and the corrected graphics become very complex and difficult to describe with geometric features, but can be extracted with image features. Therefore, image features are more helpful in perceiving and correcting graphic distortion caused by optical proximity effects. The combination or fusion of image features and geometric features can compensate for the blind spots in image representation caused by resolution loss (possible information loss after rendering the layout into an image, leading to misidentification). It also provides an observation dimension closer to the global perspective than geometric features, thereby simultaneously ensuring the nanometer-level accuracy of geometric data and the physical perceptibility of image features. Furthermore, some embodiments of the present disclosure, by introducing correctness verification and benefit evaluation, can reconstruct layout files with a more efficient and accurate hierarchical structure, thereby maximizing the organizational structure of layout files and improving processing efficiency at every stage of integrated circuit or chip manufacturing.

[0067] Figure 11 A schematic flowchart of a process 1100 for generating a layout image according to an embodiment of the present disclosure is shown.

[0068] In block 1101 , the computing device 110 obtains information associated with an initial layout file of an integrated circuit layout, the information including graphic information and hierarchical information of the initial layout file.

[0069] At block 1102 , the computing device 110 determines scaling settings and coordinate conversion settings based on the size of the integrated circuit layout and a predefined layout image resolution.

[0070] In block 1103 , the computing device 110 generates a layout image by rendering based on the acquired information and the determined scaling setting and coordinate conversion setting, wherein different structural layers in the hierarchical structure of the integrated circuit layout are rendered in different colors.

[0071] Figure 12 A schematic flowchart of a process 1200 of obtaining a set of repeated image regions in a layout image by performing image processing on the layout image according to an embodiment of the present disclosure is shown. Figure 12 The process 1200 shown may be Figure 2 201 is implemented.

[0072] In block 1201 , the computing device 110 divides the layout image into multiple image blocks according to a predetermined block size. In some embodiments of the present disclosure, before block 1201 , the computing device 110 performs pre-processing on the layout image including image denoising and texture enhancement.

[0073] At block 1202, computing device 110 classifies the plurality of image blocks based on image features and geometric features of each of the plurality of image blocks. In some embodiments of the present disclosure, computing device 110 utilizes an image feature algorithm to obtain image features of the corresponding image block, obtains geometric features of the corresponding image block by determining a physical location of the corresponding image block in an integrated circuit layout, and fuses the image features and geometric features of the corresponding image block. In some embodiments of the present disclosure, computing device 110 utilizes a clustering algorithm to classify the plurality of image blocks based on the fused features of each of the plurality of image blocks.

[0074] In block 1203 , the computing device 110 generates a matrix based on the positions and categories of the plurality of image patches.

[0075] At block 1204 , computing device 110 determines repeating image regions of the layout image based on the generated matrix, and generates a set of repeating image regions.

[0076] At block 1205 , computing device 110 determines whether to change the predetermined chunk size.

[0077] In block 1206 , if it is determined to change the predetermined block size, the computing device 110 changes the predetermined block size and returns to block 1201 to re-execute the operations of blocks 1201 to 1204 according to the changed predetermined block size.

[0078] In box 1207, if it is determined not to change the predetermined block size, the computing device 110 determines the optimal predetermined block size by evaluating the area and / or number of elements of the repeated image areas corresponding to various predetermined block sizes, and determines a set of repeated image areas based on the optimal predetermined block.

[0079] Figure 13 A schematic flow chart of a process 1300 of dividing a set of repeated image regions into at least one image region group according to an embodiment of the present disclosure is shown. Figure 13 The process 1300 shown may be performed at Figure 2 This is implemented at block 202 of .

[0080] In block 1301 , computing device 110 clusters repeated image regions in a collection using an image algorithm with scale and rotation invariance.

[0081] In block 1302 , the computing device 110 determines at least one image region group based on the clustering results.

[0082] Figure 14 A schematic flowchart of a process 1400 for generating a new layout file of an integrated circuit layout based on at least one image region group according to an embodiment of the present disclosure is shown. Figure 14 The process 1400 shown may be performed at Figure 2 This is implemented at block 203 of .

[0083] At block 1401, the computing device 110 determines a repeating image region in each image region group as a basic unit. In some embodiments of the present disclosure, before determining the basic unit, for each image region group in at least one image region group, the computing device 110 determines the physical location of each repeating image region in the corresponding image region group in the integrated circuit layout, obtains the geometry of the physical location from the initial layout file, and verifies based on the obtained geometry whether each repeating image region in the corresponding image region group is identical after at least one of translation, rotation, and scaling operations, and removes different image regions.

[0084] At block 1402, the computing device 110 generates a first hierarchical structure based on the basic units, the first hierarchical structure comprising at least two layers and representing reference relationships between the layers, wherein one of the at least two layers comprises the basic units of each image region group, and the reference relationships comprise affine transformation information between the basic units in each image region group and other repeated image regions. In some embodiments of the present disclosure, the first hierarchical structure comprises a first layer, a second layer, and a reference relationship between the first and second layers, wherein the first layer comprises non-repeating image regions, the second layer comprises the basic units of each image region group, and the affine transformation information in the reference relationships comprises at least one of a translation position, a scaling factor, and a rotation angle.

[0085] Those skilled in the art will appreciate that a third layer can be generated corresponding to a portion of the image in the first or second layer, and a reference relationship can be formed including the first, second, and third layers, which can also be used for implementation. Based on the teachings of the embodiments of the present invention, those skilled in the art can expand the implementation by using a relationship between at least two layers, and the present invention is not specifically limited here.

[0086] At block 1403 , the computing device 110 generates a new layout file of the integrated circuit layout having a hierarchical cell structure based on the first hierarchical structure.

[0087] Figure 15 FIG15 is a schematic flowchart of a process 1500 of generating a new layout file based on a first hierarchical structure according to an embodiment of the present disclosure. Figure 15 The process 1500 shown may be performed at Figure 14 This is implemented at box 1403 of .

[0088] In block 1501 , the computing device 110 selects at least a portion of base units from a second level of a first hierarchy.

[0089] At block 1502 , the computing device 110 generates a second hierarchical structure by iteratively generating a hierarchical structure identical to the first hierarchical structure within each of at least a portion of the base units.

[0090] In block 1503 , the computing device 110 generates a new layout file based on the second hierarchical structure and the initial layout file.

[0091] Figure 16 1. A schematic block diagram of an example device 1600 that can be used to implement embodiments of the present disclosure is shown. The device 1600 can be implemented as a computing device 110 for performing the method 200 and processes 1100-1500.

[0092] As shown, device 1600 includes a central processing unit (CPU) 1601, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 1602 or loaded from a storage unit 1608 into a random access memory (RAM) 1603. RAM 1603 may also store various programs and data required for the operation of device 1600, such as the measurement data mentioned above. CPU 1601, ROM 1602, and RAM 1603 are interconnected via a bus 1604. An input / output (I / O) interface 1605 is also connected to bus 1604.

[0093] Various components in device 1600 are connected to I / O interface 1605, including an input unit 1606, such as a keyboard and mouse; an output unit 1607, such as various types of displays and speakers; a storage unit 1608, such as a magnetic disk and optical disk; and a communication unit 1609, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1609 allows device 1600 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0094] Processing unit 1601 executes the methods or processes described above, method 200 and processes 1100 through 1500. For example, in some embodiments, method 200 and processes 1100 through 1500 may be implemented as a computer software program or computer program product tangibly embodied on a machine-readable medium, such as a non-transitory computer-readable medium, such as storage unit 1608. In some embodiments, part or all of the computer program may be loaded and / or installed onto device 1600 via ROM 1602 and / or communication unit 1609. When the computer program is loaded into RAM 1603 and executed by CPU 1601, one or more steps of method 200 and processes 1100 through 1500 described above may be performed. Alternatively, in other embodiments, CPU 1601 may be configured to execute method 200 and processes 1100 through 1500 in any other suitable manner (e.g., via firmware).

[0095] Those skilled in the art will appreciate that the various steps of the method disclosed above can be implemented by a general-purpose computing device. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they can be implemented using program code executable by a computing device, which can then be stored in a storage device and executed by the computing device. Alternatively, they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present disclosure is not limited to any particular combination of hardware and software.

[0096] It should be understood that although the detailed description above mentions several devices or sub-devices of a device, this division is merely exemplary and not mandatory. In fact, according to embodiments of the present disclosure, the features and functions of two or more devices described above may be embodied in a single device. Conversely, the features and functions of a single device described above may be further divided and embodied by multiple devices.

[0097] The foregoing description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that the present disclosure is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for reconstructing a layout file of an integrated circuit layout, comprising: Acquire a set of repeated image regions in a layout image of the integrated circuit layout, wherein the repeated image regions are image regions in the layout image that are identical to at least one other image region after affine transformation; dividing the set of repeated image regions into at least one image region group, wherein the repeated image regions in each image region group are identical to each other after affine transformation; as well as A new layout file having a hierarchical cell structure of the integrated circuit layout is generated based on the at least one image region group.

2. The method according to claim 1, further comprising: Acquiring information associated with an initial layout file of the integrated circuit layout, the information including graphic information and layer information of the initial layout file; Determining scaling settings and coordinate transformation settings based on the size of the integrated circuit layout and a predefined layout image resolution; and The layout image is generated by rendering based on the acquired information and the determined scaling setting and coordinate conversion setting, wherein different structural layers in the hierarchical structure of the integrated circuit layout are rendered in different colors. The method according to claim 1 , wherein the affine transformation comprises at least one of translation, rotation, and scaling.

4. The method according to claim 1, wherein obtaining a set of repeated image regions in the layout image comprises the following steps: a) dividing the layout image into a plurality of image blocks according to a predetermined block size; b) classifying the plurality of image blocks based on image features and geometric features of each of the plurality of image blocks; c) generating a matrix based on the positions and categories of the plurality of image blocks; as well as d) determining a repeated image region of the layout image based on the generated matrix, and generating a set of the repeated image regions.

5. The method according to claim 4, wherein b) classifying the plurality of image blocks based on image features and geometric features of each of the plurality of image blocks comprises: For each image block in the plurality of image blocks, Using image feature algorithms to obtain image features of corresponding image blocks; Obtaining geometric features of the corresponding image block by determining a physical location of the corresponding image block in the integrated circuit layout; and fusing the image features and the geometric features of the corresponding image blocks; as well as Based on the fused features of each image block in the multiple image blocks, a clustering algorithm is used to classify the multiple image blocks.

6. The method according to claim 4, wherein obtaining a set of repeated image regions in the layout image further comprises: changing the predetermined block size at least once; After each change in the predetermined block size, performing steps a) to d); Determining an optimal predetermined block size by evaluating the area and / or number of elements of the repeated image region corresponding to various predetermined block sizes; and Based on the optimal predetermined block, a set of repeated image regions is determined.

7. The method according to claim 4, wherein obtaining a set of repeated image regions in the layout image further comprises: Before dividing the layout image into a plurality of image blocks, the layout image is preprocessed including image denoising and texture enhancement.

8. The method of claim 1 , wherein dividing the set of repeating image regions into at least one image region group comprises: clustering repeated image regions in the set using an image algorithm with scaling and rotation invariance; as well as The at least one image region group is determined based on the clustering result.

9. The method according to claim 1 , wherein generating a new layout file having a hierarchical cell structure of the integrated circuit layout based on the at least one image region group comprises: determining a repeated image region in each image region group as a basic unit; generating a first hierarchical structure including at least two layers and a reference relationship between the layers based on the basic unit, wherein one of the at least two layers includes the basic unit of each image region group, and the reference relationship includes affine transformation information between the basic unit in each image region group and other repeated image regions; as well as A new layout file having a hierarchical cell structure of the integrated circuit layout is generated based on the first hierarchical structure.

10. The method according to claim 9, wherein the first hierarchical structure includes a first layer, a second layer, and a reference relationship between the first layer and the second layer, wherein the first layer includes non-repeating image areas, the second layer includes basic units of each image area group, and the affine transformation information in the reference relationship includes at least one of a translation position, a scaling factor, and a rotation angle.

11. The method according to claim 9, wherein generating a new layout file having a hierarchical cell structure of the integrated circuit layout based on the first hierarchical structure comprises: selecting at least a portion of basic units from a layer including the basic units in the first hierarchical structure; generating a second hierarchical structure by iteratively generating a hierarchical structure identical to the first hierarchical structure in each of the at least a portion of the basic units; and The new layout file is generated based on the second hierarchical structure and the initial layout file of the integrated circuit layout.

12. The method according to claim 9, wherein generating a new layout file having a hierarchical cell structure of the integrated circuit layout based on the at least one image region group further comprises: Before determining the basic unit, for each image area group in the at least one image area group: determining a physical location of each repeated image region in a corresponding image region group in the integrated circuit layout, Obtaining the geometry at the physical location from an initial layout file of the integrated circuit layout, and Based on the acquired geometric figures, it is verified whether the repeated image regions in the corresponding image region group are identical to each other after being subjected to at least one of translation, rotation and scaling operations, and different image regions are removed.

13. An electronic device comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the electronic device to perform actions when executed by the processor, the actions comprising: Acquire a set of repeated image regions in a layout image of an integrated circuit layout, wherein the repeated image regions are image regions in the layout image that are identical to at least one other image region after affine transformation; dividing the set of repeated image regions into at least one image region group, wherein the repeated image regions in each image region group are identical to each other after affine transformation; and A new layout file having a hierarchical cell structure of the integrated circuit layout is generated based on the at least one image region group.

14. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

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