Chip-based first-in first-out queue full-state verification method, electronic equipment and medium
By setting the interface module and virtual depth for the FIFO and forcibly triggering the FIFO full state logic simulation, the problem of the FIFO queue failing to reach the full state is solved, and the coverage of the chip verification is improved.
Patent Information
- Application Number
- CN202510727830.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-03
- Publication Date
- 2025-09-19
AI Technical Summary
In the prior art, the FIFO queue fails to reach the FIFO full state during the verification process, resulting in low chip verification coverage.
Set up an interface module for the FIFO to be tested and set a virtual depth in the interface module. During chip simulation, when the actual depth reaches the virtual depth, the FIFO full state logic simulation is forcibly triggered.
Ensure that the FIFO full status of each FIFO is verified, improving the chip verification coverage.
Smart Images
Figure CN120671630A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a chip first-in-first-out queue full state verification method, electronic equipment and medium. Background Art
[0002] In chip design, it is necessary to set up multiple first-in-first-out queues (FIFOs for short). Each FIFO is set with a corresponding depth. When the number of FIFO buffers reaches the corresponding depth, the FIFO queue is full (FIFOfull), which triggers the logic corresponding to the FIFO full state for verification. However, due to various factors, many FIFOs are released before reaching the FIFO full state. As a result, many FIFOs have not reached the FIFO full state during the entire verification process, resulting in many logics corresponding to the FIFO full state being unable to be verified, resulting in low chip verification coverage. Therefore, how to provide a method for verifying the FIFO full state and improving the chip verification coverage has become a technical problem that needs to be solved urgently. Summary of the Invention
[0003] The present invention aims to provide a chip first-in first-out queue full state verification method, electronic equipment and medium, which can realize the verification of FIFO full state and improve the chip verification coverage.
[0004] According to a first aspect of the present invention, a method for verifying a full state of a chip first-in-first-out queue is provided, comprising:
[0005] Step S1, setting a corresponding interface module for the FIFO to be tested, and interconnecting the FIFO to be tested with the interface module corresponding to the FIFO to be tested;
[0006] Step S2: setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested, wherein the virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested;
[0007] Step S3: During chip simulation, if the depth of information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module corresponding to the FIFO to be tested will force the full state signal corresponding to the FIFO to be tested to be high, triggering the execution of the logic simulation of the full state of the FIFO to be tested.
[0008] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.
[0009] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.
[0010] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides a chip first-in-first-out queue full status verification method, electronic device, and medium that achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:
[0011] The present invention sets a corresponding interface module for each FIFO to be tested, and sets a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested. During the chip simulation process, when the depth of the currently stored information in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, a logic simulation of the full state of the FIFO to be tested can be triggered, thereby ensuring that the FIFO full state of each FIFO to be tested is verified, thereby improving the chip verification coverage. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0013] Figure 1 This is a flow chart of a chip first-in-first-out queue full status verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.
[0015] The embodiment of the present invention provides a method for verifying the full state of a chip first-in first-out queue, such as Figure 1 Shown, including:
[0016] Step S1: setting a corresponding interface module for the FIFO to be tested, and interconnecting the FIFO to be tested and the interface module corresponding to the FIFO to be tested.
[0017] It should be noted that the FIFO to be tested is a FIFO set in the chip design. The FIFO to be tested and the interface module corresponding to the FIFO to be tested can be interconnected in a binding manner. Specifically, the interface module corresponding to the FIFO to be tested can be connected to the clock signal line, reset signal line, and full status signal line of the FIFO to be tested.
[0018] Step S2: setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested, wherein the virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested.
[0019] It should be noted that the size of the virtual depth corresponding to the FIFO to be tested is determined according to the specific situation of the FIFO to be tested.
[0020] Step S3: During chip simulation, if the depth of information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module corresponding to the FIFO to be tested will force the full state signal corresponding to the FIFO to be tested to be high, triggering the execution of the logic simulation of the full state of the FIFO to be tested.
[0021] It should be noted that by setting the virtual depth corresponding to the FIFO to be tested, and triggering the execution of the logic simulation of the full state of the FIFO to be tested when the depth of the current stored information in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the FIFO full state of the FIFO to be tested is made easier to verify, thereby improving the chip verification coverage.
[0022] There may be multiple FIFOs to be tested in the chip. The corresponding virtual depth configuration information can be set according to the requirements of each FIFO to be tested to ensure that each FIFO to be tested can be verified. As an embodiment, the method further includes:
[0023] Step S0: Set the FIFO virtual depth configuration file {F1, F2, ..., F m ,...,F M}, F m Design the virtual depth configuration information of the mth FIFO to be tested for the chip, F m ={F1 m ,F2 m ,F3 m}, F1 m F mThe corresponding virtual depth configuration mode includes fixed mode and random mode. m F m The corresponding time window, F m The corresponding time window is less than or equal to the chip simulation time. When F1 m In fixed mode, F3 m To fix the virtual depth value, when F1 m In random mode, F3 m is a virtual depth interval, and the maximum value of the virtual depth interval is less than or equal to the actual depth corresponding to the FIFO to be tested.
[0024] It should be noted that the FIFO virtual depth can be set to a fixed value through the fixed mode, the FIFO virtual depth value can be reasonably set within the virtual depth range through the random mode, and the time interval for setting the virtual depth can be controlled through the time window, thereby meeting the different FIFO virtual depth configuration requirements of different FIFOs to be tested. If a part of the FIFOs in the chip does not need to set the depth to verify the FIFO full state, the FIFO virtual depth configuration information can be set for this part of the FIFO, and the actual depth corresponding to the FIFO can be used by default. That is, the embodiment of the present invention only uses the FIFO with the virtual depth setting requirement as the FIFO to be tested.
[0025] As an embodiment, step S2 includes:
[0026] Step S21: If the depth configuration mode of the FIFO to be tested is fixed, the virtual depth of the FIFO to be tested is set to the corresponding fixed virtual depth value in the corresponding time window, and the virtual depth of the FIFO to be tested is set to the actual depth of the FIFO to be tested outside the corresponding time window.
[0027] It should be noted that based on {F1,F2,...,F m ,...,F M} can determine the corresponding {F1 m ,F2 m ,F3 m}, based on {F1 m ,F2 m ,F3 m}Implement step S21.
[0028] As an embodiment, step S2 includes:
[0029] Step S22: If the depth configuration mode corresponding to the FIFO to be tested is the random mode, a random depth value is generated as the virtual depth corresponding to the FIFO to be tested based on the corresponding virtual depth interval in the time window, and the virtual depth corresponding to the FIFO to be tested is set to the actual depth corresponding to the FIFO to be tested during the time outside the corresponding time window.
[0030] It should be noted that based on {F1,F2,...,F m ,...,F M} can determine the corresponding {F1 m ,F2 m ,F3 m}, based on {F1 m ,F2 m ,F3 m}Implement step S22.
[0031] If the embodiment of the present invention is applied to chip verification generated based on hardware description language, it can be directly implemented based on steps S1 to S3. In addition, the embodiment of the present invention can also be applied to the chip co-simulation process. Chip co-simulation refers to simulating different parts of the chip design or models of different abstract levels together to verify the interaction and overall function between them. This usually involves combining multiple simulation tools or different types of simulation models to simulate the behavior of the chip in different environments and conditions. Usually, a chip model generated by a high-level language is set for chip design, and the output of the chip model is used as a standard to verify whether the output of the chip design generated based on the hardware language is correct to achieve co-simulation.
[0032] As an embodiment, if the chip simulation process is a chip co-simulation, each FIFO to be tested includes a FIFO model to be tested generated based on a high-level programming language. The FIFO to be tested is generated based on a hardware description language. The high-level programming language can specifically be C language, C++ language, etc. The hardware description language can specifically be Verilog, VHDL, SystemVerilog, etc. The method further includes:
[0033] Step S10 : setting an interface module model for each FIFO model to be tested. The interface module model is generated based on a high-level programming language. The interface module model is provided with a preset application programming interface (API) for controlling a full status signal of the FIFO model to be tested.
[0034] Step S20: interconnecting the interface module model corresponding to the FIFO to be tested and the interface module corresponding to the FIFO via a direct programming interface (DPI). The direct programming interface is used to implement interaction between a high-level programming language and a hardware description language.
[0035] As an embodiment, if the co-simulation is controlled based on a test case generated by a hardware description language, the co-simulation master is the design to be tested, and step S2 includes:
[0036] Step E21 : Setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested.
[0037] It should be noted that step E21 is specifically implemented in the interface module corresponding to the FIFO to be tested through step S21 or step S22.
[0038] Step E22 : The interface module corresponding to the FIFO to be tested transmits the virtual depth corresponding to the FIFO to the interface module model corresponding to the FIFO to be tested through the direct programming interface.
[0039] It should be noted that the virtual depth corresponding to the FIFO in step E22 is the virtual depth corresponding to the FIFO generated based on the hardware description language. The direct programming interface converts the virtual depth corresponding to the FIFO sent by the interface module corresponding to the FIFO to be tested into the virtual depth corresponding to the FIFO corresponding to the high-level programming language and transmits it to the interface module model corresponding to the FIFO to be tested.
[0040] As an embodiment, if the co-simulation is controlled based on a test case generated by a high-level programming language, the co-simulation master is a chip model, and step S2 includes:
[0041] Step C21: setting a virtual depth corresponding to the FIFO to be tested in the interface module model corresponding to the FIFO to be tested.
[0042] It should be noted that step C21 is specifically implemented in the interface module model corresponding to the FIFO to be tested through step S21 or step S22.
[0043] Step C22: The interface module model corresponding to the FIFO to be tested transmits the virtual depth corresponding to the FIFO to the interface module corresponding to the FIFO to be tested through the direct programming interface.
[0044] It should be noted that the virtual depth corresponding to the FIFO in step C22 is the virtual depth corresponding to the FIFO generated based on the high-level programming language. The direct programming interface converts the virtual depth corresponding to the FIFO sent by the interface module corresponding to the FIFO to be tested into the virtual depth corresponding to the FIFO corresponding to the hardware description language and transmits it to the interface module corresponding to the FIFO to be tested.
[0045] As an embodiment, the method further includes:
[0046] Step S4: During the chip simulation process, if the depth of the information currently stored in the FIFO model to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module model corresponding to the FIFO to be tested calls the corresponding preset API to force the full state signal corresponding to the FIFO model to be tested to be high, thereby triggering the execution of the logic simulation of the full state of the FIFO model to be tested.
[0047] As an embodiment, the chip described in the embodiment of the present invention may be a graphics processing unit (Graphics Processing Unit, for short) chip.
[0048] An embodiment of the present invention sets a corresponding interface module for each FIFO to be tested, and sets a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested. During the chip simulation process, when the depth of the currently stored information in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, a logic simulation of the full state of the FIFO to be tested can be triggered, thereby ensuring that the FIFO full state of each FIFO to be tested is verified, thereby improving the chip verification coverage.
[0049] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.
[0050] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.
[0051] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.
[0052] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.
Claims
1. A chip first-in first-out queue full state verification method, characterized in that: include: Step S1, setting a corresponding interface module for the FIFO to be tested, and interconnecting the FIFO to be tested with the interface module corresponding to the FIFO to be tested; Step S2: setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested, wherein the virtual depth corresponding to the FIFO to be tested is less than or equal to the actual depth corresponding to the FIFO to be tested; Step S3: During chip simulation, if the depth of information currently stored in the FIFO to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module corresponding to the FIFO to be tested will force the full state signal corresponding to the FIFO to be tested to be high, triggering the execution of the logic simulation of the full state of the FIFO to be tested.
2. The method according to claim 1, characterized in that If the chip simulation process is chip co-simulation, each FIFO to be tested includes a FIFO model to be tested generated based on a high-level programming language, and the FIFO to be tested is generated based on a hardware description language. The method further includes: Step S10: setting an interface module model for each FIFO model to be tested, where the interface module model is generated based on a high-level programming language and a preset API for controlling a full state signal of the FIFO model to be tested is set in the interface module model; Step S20: interconnecting the interface module model corresponding to the FIFO to be tested and the interface module corresponding to the FIFO through a direct programming interface, wherein the direct programming interface is used to implement interaction between a high-level programming language and a hardware description language.
3. The method according to claim 2, characterized in that If the co-simulation master is the design to be tested, step S2 includes: Step E21: setting a virtual depth corresponding to the FIFO to be tested in the interface module corresponding to the FIFO to be tested; Step E22 : The interface module corresponding to the FIFO to be tested transmits the virtual depth corresponding to the FIFO to the interface module model corresponding to the FIFO to be tested through the direct programming interface.
4. The method according to claim 2, characterized in that If the co-simulation master is a chip model, step S2 includes: Step C21: setting a virtual depth corresponding to the FIFO to be tested in the interface module model corresponding to the FIFO to be tested; Step C22: The interface module model corresponding to the FIFO to be tested transmits the virtual depth corresponding to the FIFO to the interface module corresponding to the FIFO to be tested through the direct programming interface.
5. The method according to claim 3 or 4, characterized in that The method further comprises: Step S4: During the chip simulation process, if the depth of the information currently stored in the FIFO model to be tested reaches the virtual depth corresponding to the FIFO to be tested, the interface module model corresponding to the FIFO to be tested calls the corresponding preset API to force the full state signal corresponding to the FIFO model to be tested to be high, thereby triggering the execution of the logic simulation of the full state of the FIFO model to be tested.
6. The method according to claim 1, characterized in that The chip is a GPU chip.
7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.
8. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 6.