A specialized accelerator for hierarchical greedy decoding algorithm

Abstract

The application discloses a special accelerator for a hierarchical greedy decoding algorithm, and belongs to the technical field of quantum computation, and comprises a transformation unit, a decoding core and a permutation unit; the transformation unit is used for receiving original error symptoms, and multiplying the original error symptoms with a transformation matrix through sparse matrix vector multiplication to generate transformed error symptoms; the decoding core is used for executing a hierarchical greedy decoding algorithm, dividing error patterns into left errors and right errors, and performing calculation including guessing right errors and decoding left errors in parallel based on the transformed error symptoms to obtain new values of the error patterns; and the permutation unit is used for receiving the new values of the error patterns, multiplying the new values of the error patterns with a permutation matrix through sparse matrix vector multiplication to calculate final error patterns. The application can realize real-time qLDPC decoding and significantly reduce decoding delay.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum computing, and particularly relates to a special accelerator for a hierarchical greedy decoding algorithm. BACKGROUND

[0002] Quantum error correction (QEC) is one of the key technologies to realize large-scale fault-tolerant quantum computing. In the field of QEC, quantum low-density parity-check codes (qLDPC) are of great interest due to their constant coding rate and high error threshold, and are considered as a promising quantum error-correcting code that can realize large-scale fault-tolerant quantum systems. However, due to the large sparsity and irregularity of the check matrix of qLDPC codes, real-time decoding is still a serious challenge.

[0003] Traditional decoding algorithms such as belief propagation (BP) and its improved version belief propagation + ordered statistical decoding (BP+OSD) cannot meet the requirements of accurate and real-time decoding under the superconducting quantum platform. Specifically, although the BP algorithm has advantages in computational complexity and parallelism, making it potentially implementable for decoding acceleration on hardware such as FPGA and ASIC, it is limited by the problem of quantum degeneracy (i.e., multiple possible error patterns correspond to the same error syndrome), and the BP algorithm often converges to incorrect error patterns, resulting in low decoding accuracy and ineffective decoding. For example, in the decoding of the binary Bose-Chaudhuri-Hocquenghem (BB) code [[784, 24, 24]], the logical error rate of BP is 1649.5 times higher than that of BP+OSD. In order to improve the probability of BP finding the correct solution, the number of iterations of BP must be increased. However, the iterations of BP can only be executed in series, and increasing the number of iterations of BP greatly increases the decoding time. Moreover, as the size of the error-correcting code increases, the time of each iteration of BP will also gradually increase. For example, for the BB code [[90, 8, 10]], the decoding time of BP has already exceeded the real-time decoding requirement (1 μs) on the superconducting platform.

[0004] In order to improve the decoding accuracy of BP, BP+OSD introduces OSD as a post-processing technique to correct the decoding result of BP by solving a linear system. However, OSD involves sorting and matrix inversion, which are computationally intensive sequential operations, making it difficult to deploy on hardware acceleration platforms such as FPGA and ASIC, resulting in significant latency. This high latency makes it difficult for BP+OSD to meet the real-time decoding requirements of fault-tolerant quantum computing. Quantum systems usually require the decoder to complete operations within each QEC cycle (usually less than 1 μs). If the decoding speed cannot keep up with the error syndrome generation speed, error syndromes will be generated, delaying subsequent quantum operations, and this delay overhead increases exponentially with the circuit depth. Even for a small BB code [[72, 12, 6]], the decoding time of BP+OSD is as high as about μs, far exceeding the 1 μs requirement of real-time decoding. This highlights the limitations of existing software decoding algorithms in achieving high-performance hardware acceleration.

[0005] To meet the requirement of real-time decoding, the industry has invested a lot of attention in decoding dedicated hardware accelerators. However, general-purpose processors (such as CPUs or GPUs) are inefficient in handling the fine-grained, bit-level operations common in QEC. This is because these operations are incompatible with the wide vector execution units of CPUs and GPUs, resulting in low utilization and inefficient memory access. In contrast, FPGAs (Field Programmable Gate Arrays) are better suited for such tasks due to their reconfigurability and high parallelism. Furthermore, decoding accelerators implemented based on FPGAs can be tightly integrated with superconducting quantum systems, as error syndromes are typically generated and transmitted by readout modules implemented on FPGAs. This tightly coupled decoding accelerator can directly access error syndrome data, avoiding the latency associated with transferring data to an external processor, and further reducing decoding time.

[0006] Therefore, there is an urgent need for a dedicated hardware accelerator that can fully utilize the sparsity of qLDPC codes and the parallelism of decoding algorithms to overcome the bottleneck of existing decoders in terms of accuracy and latency, and to achieve real-time qLDPC decoding on superconducting quantum platforms. SUMMARY

[0007] In view of the above, the purpose of the present application is to provide a dedicated accelerator for hierarchical greedy decoding algorithm, by designing a hardware accelerator that can fully utilize the sparsity of qLDPC codes and the parallelism of hierarchical greedy decoding algorithm, to achieve real-time qLDPC decoding. And by optimizing the data flow and designing a special computing unit, the problem of traditional processors such as CPU, GPU not supporting fine-grained bit-level operations is solved, and the decoding delay is significantly reduced.

[0008] To achieve the above application purpose, the technical scheme provided by the present application is as follows:

[0009] The dedicated accelerator for hierarchical greedy decoding algorithm provided by the embodiment of the present application comprises:

[0010] The transformation unit is used to receive the original error syndrome and multiply it with the transformation matrix through sparse matrix vector multiplication to generate the transformed error syndrome;

[0011] The decoding core is used to execute the hierarchical greedy decoding algorithm, divide the error pattern into left error and right error, and perform the calculation including guessing the right error and decoding the left error in parallel based on the transformed error syndrome to obtain the new value of the error pattern;

[0012] The permutation unit is used to receive the new value of the error pattern and multiply it with the permutation matrix through sparse matrix vector multiplication to calculate the final error pattern.

[0013] Preferably, the decoding core comprises a plurality of hierarchical decoding units, a first comparison tree and an execution controller;

[0014] The plurality of hierarchical decoding units are configured to receive the transformed error syndrome to calculate the objective function value of each candidate error guess in parallel;

[0015] The first comparison tree is configured to receive the objective function values from the plurality of hierarchical decoding units, compare and identify the minimum objective function value, and compare the minimum objective function value with the current minimum objective function value to store the minimum objective function value and the corresponding error pattern;

[0016] The execution controller is configured to control the continuation or termination of the decoding process.

[0017] Preferably, each hierarchical decoding unit comprises a first error syndrome incremental update unit, a plurality of greedy decoding cores and a first log-likelihood ratio calculation unit;

[0018] The first error syndrome incremental update unit is configured to perform sparse matrix vector multiplication and XOR operation to calculate the error syndrome corresponding to the left error, and split the error syndrome corresponding to the left error into K partial error syndromes for the K greedy decoding cores;

[0019] The plurality of greedy decoding cores are configured to respectively process the K partial error syndromes, and splice the decoded partial left errors into a complete left error;

[0020] The first log-likelihood ratio calculation unit is configured to calculate the objective function value according to the complete left error.

[0021] Preferably, in the first error syndrome incremental update unit, the sparse matrix is stored in a specific compression format, including a sparse matrix table and a non-zero row index table; when calculating, the non-zero element row index is extracted from the sparse matrix table and the non-zero row index table according to the input column index, and XOR operation is only applied to these non-zero elements; after performing incremental update and sparse XOR operation to obtain the left error syndrome, the value at the selected row index in the current iteration is operated with a specific value and written back; and the left error syndrome corresponding to the error bit identified in the current iteration is stored for subsequent iteration to reuse residual error syndrome calculation data.

[0022] Preferably, each greedy decoding core comprises a second error syndrome incremental update unit, a second log-likelihood ratio calculation unit and a second comparison tree;

[0023] The second error syndrome incremental update unit is configured to receive partial left error syndrome and divide the left error to be decoded into two parts of a first candidate guess and a second candidate guess, calculate the second candidate guess based on the received partial left error syndrome and the first candidate guess, and once the second candidate guess is obtained, splice the first candidate guess and the second candidate guess to form the left error.

[0024] The second log-likelihood ratio calculation unit is configured to calculate a target function value according to non-zero elements in the first candidate guess and the second candidate guess.

[0025] The second comparison tree is configured to output the target function value output by the second log-likelihood ratio calculation unit and identify the minimum value therein, and regard the left error corresponding to the minimum value as the best of the current iteration and output.

[0026] Preferably, the target function value is the number of non-zero values in the left error, and the corresponding weights are retrieved from the weight register file using their indices, and then the adder tree is applied to calculate in parallel to evaluate the likelihood of the occurrence of the left error.

[0027] Preferably, in the second comparison tree, once it is found that the currently calculated target function value is smaller than the existing minimum target function value, the currently calculated target function value is updated as the minimum target function value, and the guessing is stopped.

[0028] Preferably, in the first comparison tree, once it is found that the currently calculated target function value is smaller than the existing minimum target function value, the currently calculated target function value is updated as the minimum target function value, and the iteration is stopped.

[0029] Preferably, before real-time decoding is performed, the transformation matrix and the permutation matrix are preloaded into the sparse matrix cache.

[0030] The accelerator hardware architecture designed by the present application fully utilizes the sparsity in the check matrix and the parallelism of the hierarchical greedy decoding algorithm, and the error syndrome incremental update unit avoids repeated calculation by storing and reusing error syndrome data, further reducing the decoding latency. Compared with the prior art, the present application has at least the following beneficial effects:

[0031] (1) Extremely low decoding delay: the accelerator designed by the present application realizes a decoding delay of less than 1 s. For example, for the largest BB code [[784, 24, 24]], the decoding delay is only 840 ns. This real-time performance is crucial for fault-tolerant quantum computing, which can effectively prevent error syndrome backlog and delay subsequent quantum operations

[0032] (2) Delay insensitive to code size: Compared with the BP decoder, the delay of the accelerator designed in the present application is not sensitive to the size of the qLDPC code, showing a logarithmic growth trend. For example, on the BB code, when the size of the check matrix increases by about 10 times, the delay only increases from 720 ns to 840 ns. This shows that the accelerator architecture designed in the present application has good scalability and can process larger scale qLDPC codes.

[0033] (3) High efficiency and low resource occupation: When the accelerator designed in the present application is implemented on the FPGA, the resource occupation rate is extremely low. For example, for the medium-sized BB code [[144, 12, 12]], the LUT and FF resource utilization rates are less than 10% and 1%, respectively. Even for the large BB code [[784, 24, 24]], only 31.26% of the LUT and 2.35% of the FF are required. This makes the accelerator designed in the present application be able to be seamlessly integrated into the FPGA control processor of the current superconducting quantum platform. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 is a whole hardware architecture schematic diagram of a special accelerator for a hierarchical greedy decoding algorithm provided by an embodiment of the present application;

[0036] Figure 2 is a pseudo code schematic diagram of a hierarchical greedy decoding algorithm provided by an embodiment of the present application;

[0037] Figure 3 is a schematic diagram of a first error syndrome incremental update unit provided by an embodiment of the present application;

[0038] Figure 4 is a hardware architecture schematic diagram of a greedy decoding core provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and do not limit the protection scope of the present application.

[0040] The inventive concept of the present application is that, in view of the low computational efficiency and high delay of the qLDPC decoder in the prior art, embodiments of the present application provide a special accelerator for a hierarchical greedy decoding algorithm. The accelerator aims to fully utilize the sparsity characteristics of the qLDPC code, combine the parallel computing advantages of the independently designed hierarchical greedy decoding algorithm, reduce the data transmission delay through careful optimization of the data flow path. At the same time, a special transformation unit, decoding core and permutation unit are designed, which are respectively responsible for the transformation processing of error symptoms, parallel decoding calculation and the final error mode permutation output, and the units work cooperatively to realize efficient real-time decoding. This design not only improves the real-time performance of qLDPC decoding, but also guarantees the accuracy and stability of the decoding, and provides strong support for high-speed communication systems.

[0041] As shown in Figure 1 , embodiments provide a special accelerator for a hierarchical greedy decoding algorithm, which aims to support the hierarchical greedy decoding algorithm ( Figure 2 ) to realize real-time decoding of qLDPC codes. The accelerator is directly designed based on the structure of the hierarchical greedy decoding algorithm, maps each operation to the special logic on the FPGA, and designs the data flow and sparse computation to minimize the decoding delay. The special accelerator mainly includes three core components: a transformation unit, a decoding core and a permutation unit, wherein the decoding core includes a hierarchical decoding unit (HDU), a first comparison tree and an execution controller, and the HDU includes a first error syndrome incremental update unit, a greedy decoding core (GDC) and a first log-likelihood ratio (LLR) calculation unit.

[0042] Based on this hardware architecture, the decoding data flow of the special accelerator includes five main steps:

[0043] (1) Error symptom transformation: the transformation unit receives the original error symptom , and multiplies it with the transformation matrix through sparse matrix vector multiplication (MVM) to generate the transformed error symptom . The transformation matrix will be pre-loaded into the sparse matrix buffer before performing real-time decoding.

[0044] (2) Target value calculation: the transformed error symptom is sent to multiple hierarchical decoding units (HDU), and each HDU is responsible for calculating the target function value of the th candidate error guess . The error pattern will be divided into left error and right error . Each HDU first triggers the first syndrome increment update unit to compute the syndrome of left errors , denoted as , denotes an arbitrary sparse matrix. Then, the syndrome of left errors will be split into K partial syndromes of left errors according to the block diagonalization of the decoupled check matrix and fed into K greedy decoding cores (GDCs). Each GDC processes its corresponding block matrix and and outputs a partial error where . The outputs of all GDCs are integrated into a complete left error . The first log-likelihood ratio (LLR) computation unit then computes the final objective function value using the complete error and the weight corresponding to each error bit .

[0045] (3) Comparison: The comparison tree receives the objective function values from the HDUs and compares them in parallel to identify the solution with the minimum weight. The output is the best solution corresponding to the minimum weight error guess.

[0046] (4) Parameter update: The best solution output by the first comparison tree is compared with the current minimum value . If the new solution reduces the minimum value, a parameter update is triggered and the new values of , and are stored. The execution controller monitors the enable signal to decide whether the decoding procedure continues or terminates.

[0047] (5) Error pattern permutation: The permutation unit receives the error pattern and computes the final error pattern by multiplying it with the permutation matrix . To speed up the decoding computation, the permutation matrix is also preloaded into the sparse matrix buffer before the real-time decoding is performed.

[0048] In the embodiment, as shown in (a) in Figure 3 , to efficiently compute the syndrome of left errors , To represent right-hand error symptoms, this invention proposes a first error symptom incremental update unit with two key features: First, sparse MVM and XOR: by utilizing right-hand error... Due to the sparsity of the matrix, this invention transforms the complex MVM process into a simple row selection. This is achieved by decoupling the arbitrary sparse matrix in the parity check matrix. The columns are also sparse. This invention only selects non-zero elements and error symptoms to perform XOR operations, thereby accelerating the decoding process; secondly, incremental update: by storing and reusing the error bits identified in the previous iteration. Corresponding symptoms of left error This avoids recalculating the entire error symptom, thus significantly reducing redundant calculations.

[0049] In the embodiments, Figure 3 (b) shows an example of computing the second iteration using the first error symptom incremental update unit. First, sparse MVM is applied to compute... That is, in the second iteration The calculation results. Sparse matrix. The storage uses the compression format proposed in this invention, which includes a sparse matrix table and a non-zero row index table. The sparse matrix table stores column addresses and the number of non-zero elements in each column, while the non-zero row index table records the row indices corresponding to these non-zero elements. In the example, the input column index... Therefore, obtain directly The first column is then processed, and the row indices of "1" in the first column (i.e., 1 and 4) are extracted from the non-zero row index table. This non-zero extraction prepares the ground for the subsequent sparse XOR. Since any value XORed with zero remains unchanged, only these non-zero elements need to be XORed. Next, an incremental update and sparse XOR are performed to obtain the left error symptoms. .from The values ​​at the selected line indices (i.e., 1 and 4) in the register file are retrieved, XORed with 1, and the result is written back. Register file. After all first error symptom incremental update units are completed, the error bits identified in the current iteration will be... corresponding Store to The register file. This allows residual error symptoms to be reused to compute data in subsequent iterations.

[0050] In the embodiments, Figure 4 The architecture and computational flow of the Greedy Decoding Core (GDC) were demonstrated to effectively support... Figure 2 The GreedyGuess process in the GDC. Each GDC consists of three main components: a second error symptom incremental update unit, a second log-likelihood ratio (LLR) calculation unit, and a second comparison tree. The left error to be decoded... partitioned into a first candidate guess and a second candidate guess two parts, each GDC receives a left error syndrome and all first candidate guesses as input. Multiple second error syndrome increment update units compute in parallel using arbitrary matrices and sparsity of the right part Once the left part of the is obtained, it is concatenated with and to form the left error To evaluate the likelihood of the candidate left error occurring, the GDC invokes a second LLR computation unit to compute the objective function value The LLR computation unit efficiently performs this task by focusing on the non-zero elements of and using their indices to retrieve the corresponding weights from the weight register file and then applying a tree of adders to compute the objective function value in parallel. Finally, all computed objective function values are sent to a comparison tree that identifies the minimum value. The left error corresponding to this minimum value is considered the best solution for the current iteration.

[0051] The above detailed description of the specific embodiments of the present application has described the technical solutions and beneficial effects of the present application. It should be understood that the above description is only the most preferred embodiment of the present application and is not intended to limit the present application. Any modifications, supplements and equivalent replacements made within the principle range of the present application shall be included in the protection scope of the present application.

Claims

1. A dedicated accelerator for hierarchical greedy decoding algorithms, characterized in that, include: Transformation unit, decoding core, and permutation unit; The transformation unit is used to receive the original error symptoms and generate the transformed error symptoms by multiplying them with the transformation matrix through sparse matrix-vector multiplication. The decoding core is used to execute a hierarchical greedy decoding algorithm, which divides the error mode into left error and right error, and performs calculations in parallel, including guessing right error and decoding left error, based on the transformed error symptoms, to obtain a new value of the error mode. The permutation unit is used to receive new values ​​of the error mode and calculate the final error mode by multiplying it with the permutation matrix using sparse matrix-vector multiplication.

2. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 1, characterized in that, The decoding core includes: multiple hierarchical decoding units, a first comparison tree, and an execution controller; Multiple hierarchical decoding units are used to receive the transformed error symptoms to compute the objective function value of each candidate error guess in parallel. The first comparison tree is used to receive the target function values ​​from multiple hierarchical decoding units, compare and identify the minimum target function value, and then compare it with the currently existing minimum target function value and store the minimum target function value and the new value of the corresponding error mode. The execution controller is used to control whether the decoding process continues or terminates.

3. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 2, characterized in that, Each hierarchical decoding unit includes: a first error symptom incremental update unit, multiple greedy decoding cores, and a first log-likelihood ratio calculation unit; The first error symptom incremental update unit is used to perform sparse matrix-vector multiplication and XOR operation to calculate the error symptom corresponding to the left error, and split the error symptom corresponding to the left error into K parts of the left error symptom and send them to K greedy decoding cores respectively; The multiple greedy decoding cores are used to process K partial left error symptoms respectively, and concatenate the decoded partial left errors into complete left errors; The first log-likelihood ratio calculation unit is used to calculate the objective function value based on the complete left error.

4. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 3, characterized in that, In the first error symptom incremental update unit, a sparse matrix is ​​stored using a specific compression format, which includes a sparse matrix table and a non-zero row index table. During calculation, based on the input column index, the row indices of non-zero elements are extracted from the sparse matrix table and the non-zero row index table, and an XOR operation is applied only to these non-zero elements. After performing incremental update and sparse XOR operation to obtain the left error symptom, the value at the selected row index in the current iteration is operated with a specific value and written back. The left error symptom corresponding to the error bit identified in the current iteration is stored so that the residual error symptom calculation data can be reused in subsequent iterations.

5. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 3, characterized in that, Each greedy decoding core includes: a second error symptom incremental update unit, a second log-likelihood ratio calculation unit, and a second comparison tree; The second error symptom incremental update unit is used to receive partial left error symptoms and divide the left error to be decoded into two parts: a first candidate guess and a second candidate guess. The second candidate guess is calculated based on the received partial left error symptoms and the first candidate guess. Once the second candidate guess is obtained, the first candidate guess and the second candidate guess are concatenated to form the left error. The second log-likelihood ratio calculation unit is used to calculate the objective function value based on the non-zero elements in the first and second candidate guesses; The second comparison tree is used to receive the objective function value output by the second log-likelihood ratio calculation unit and identify the minimum value among them. The left error corresponding to the minimum value is regarded as the best value for the current iteration and output.

6. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 5, characterized in that, The objective function is to minimize the number of non-zero values ​​in the left error, and the corresponding weights are retrieved from the weight register file using their indices. Then, the weights are calculated in parallel using an adder tree to evaluate the probability of a left error occurring.

7. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 5, characterized in that, In the second comparison tree, once it is found that the currently calculated objective function value is less than the existing minimum objective function value, the currently calculated objective function value is updated to the minimum objective function value, and guessing stops.

8. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 2, characterized in that, In the first comparison tree, once it is found that the currently calculated objective function value is less than the existing minimum objective function value, the currently calculated objective function value is updated to the minimum objective function value, and the iteration stops.

9. The dedicated accelerator for hierarchical greedy decoding algorithms according to claim 1, characterized in that, Before performing real-time decoding, the transformation matrix and permutation matrix are preloaded into the sparse matrix cache.

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