IC device aliasing multi-target detection algorithm based on attention mechanism

Abstract

The invention discloses an IC device aliasing multi-target detection algorithm based on an attention mechanism, and relates to the technical field of computer vision and industrial detection, and the algorithm comprises the following steps: S1, constructing an IC device aliasing feature database; s2, constructing a double-path attention feature enhancement network; s3, designing a target decoupling detection module; s4, model training is carried out on the mixed loss function; and S5, deploying the lightweight model to the embedded platform. According to the invention, dynamic double-path attention mechanism cooperative calibration is designed, a gating fusion strategy, a topological relation constraint module and a model compression technology are combined, real-time high-precision detection is realized on an embedded platform, and the production line detection efficiency and the yield are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of computer vision and industrial detection technology, and specifically to an attention mechanism-based IC device aliasing multi-target detection algorithm. Background Art

[0002] Current core challenges facing integrated circuit inspection include severe aliasing interference caused by device miniaturization and high-density assembly. Traditional inspection methods suffer from feature confusion and missed detections in complex stacking scenarios. Existing solutions suffer from three limitations: contour matching-based algorithms struggle to distinguish similar devices; deep learning models are sensitive to occlusion and cannot resolve assembly relationships; and 3D reconstruction methods suffer from poor real-time performance and high costs. Industrial production lines urgently need a highly robust inspection solution that can run in real time on embedded platforms while simultaneously achieving precise positioning and topological analysis.

[0003] Therefore, we proposed an attention-based multi-target detection algorithm for IC device aliasing, designed a dynamic dual-path attention mechanism for collaborative calibration, and combined it with a gated fusion strategy, a topological relationship constraint module, and model compression technology to achieve technological breakthroughs in detection accuracy, assembly relationship recognition, and computational efficiency. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides an IC device aliasing multi-target detection algorithm based on the attention mechanism, which solves the problems raised by the above background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: an IC device aliasing multi-target detection algorithm based on an attention mechanism, comprising the following steps:

[0006] Step S1: Build an IC device aliasing feature database, collect multi-angle IC component images through imaging equipment, annotate device bounding boxes and pin topology relationships, and calculate and filter aliasing samples with an occlusion rate ≥ 30%;

[0007] Step S2: Construct a dual-path attention feature enhancement network, including:

[0008] (a) Spatial attention module: Generates the spatial weight matrix W_s∈[0,1]^H×W of the pin-dense area;

[0009] (b) Channel attention module: calculates the material feature channel response weight W_c∈R^C;

[0010] (c) Dynamic feature calibration unit: It fuses W_s and W_c through a gating mechanism and outputs a calibration feature map;

[0011] Step S3: Design a target decoupling detection module, including:

[0012] (a) Adaptive non-maximum suppression algorithm based on attention weight, dynamically adjusting the intersection-over-union ratio threshold;

[0013] (b) Topological relationship constraint branch, modeling the spatial distribution of pins through graph convolutional network;

[0014] Step S4: Use a hybrid loss function that includes attention focus loss and topology consistency loss to train the model;

[0015] Step S5: Deploy the lightweight model to the embedded platform to achieve real-time multi-target detection and topological relationship output.

[0016] Furthermore, the labeled device boundary box and pin topology relationship in step S1 are:

[0017] Mark the device's minimum external rectangle and pin coordinates, and establish a topological relationship diagram G = (V, E);

[0018] The vertex set V represents the device body, and the edge set E represents the assembly connection relationship.

[0019] Furthermore, the spatial attention module implementation of step S2(a) includes:

[0020] (a) Perform dilated convolution on the feature pyramid P3-P5 layers with a dilation rate of d = 2;

[0021] (b) Generate the initial spatial weight matrix through 3×3 convolution;

[0022] (c) Apply softmax normalization: W_s' = exp(W_s / √d) / Σexp(W_s /

[0023] √d), where d = 256.

[0024] Furthermore, the calculation process of the dynamic feature calibration unit in step S2(c) is as follows:

[0025] G=σ(Conv1×1([W_s';W_c']));

[0026]

[0027] in represents channel-by-channel multiplication, ⊙ represents element-by-element multiplication, and σ is the sigmoid activation function.

[0028] Furthermore, the adaptive non-maximum suppression algorithm of step S3(a) includes:

[0029] (a) Construct the feature similarity matrix S = W_att·X^T, where X∈R^{N×d} is the detection box feature;

[0030] (b) Dynamic IoU threshold setting: τ_ij = 0.5 × (1 + cos (πS_ij / 2));

[0031] (c) Suppression operation is performed when the IoU between detection boxes is greater than τ_ij.

[0032] Furthermore, the topological relationship constraint branch of step S3(b) includes:

[0033] (a) Construct a graph structure G = (V, E), where the vertex V represents the device and the edge E represents the assembly relationship;

[0034] (b) Update vertex features through a two-layer graph convolutional network:

[0035]

[0036] in is the normalized adjacency matrix, W^{(l)} is a learnable parameter;

[0037] (c) Output topological matching matrix M∈[0,1]^{N×N}.

[0038] Furthermore, the hybrid loss function of step S4 is:

[0039] L_total=0.8L_det+0.5L_att+0.3L_top;

[0040] in:

[0041] L_det=FocalLoss(cls)+GIoULoss(reg);

[0042] L_att=||W_s'°W_c'||_F^2;

[0043] L_top = 1-IoU(M_pred, M_gt).

[0044] Furthermore, the lightweight deployment of step S5 includes:

[0045] (a) Channel pruning based on Taylor expansion: retain Channel;

[0046] (b) INT8 quantization: linear quantization is performed on the weight parameters:

[0047] W_q=round(127*(W-min(W)) / (max(W)-min(W)));

[0048] (c) Deployed on the Jetson Xavier platform and accelerated inference through TensorRT.

[0049] The present invention provides an IC device aliasing multi-target detection algorithm based on an attention mechanism.

[0050] Compared with the existing technology, it has the following beneficial effects:

[0051] 1. Strong adaptability to complex scenarios: Through the spatial-channel collaborative perception mechanism, it effectively solves the feature confusion problem caused by high-density device stacking and significantly improves the detection robustness in aliasing scenarios.

[0052] 2. Multi-dimensional information fusion: Innovatively integrate visual inspection and topological relationship analysis to achieve intelligent analysis of assembly relationships while accurately positioning, breaking through the single-dimensional limitations of traditional inspection methods.

[0053] 3. Dynamic adaptive optimization: A gated fusion strategy is used to achieve scene-adaptive adjustment of feature calibration weights, taking into account the detection requirements of different occlusion levels and device types.

[0054] 4. Industrial deployment friendly: Through lightweight network design and model compression technology, it meets the real-time requirements of embedded platforms while maintaining accuracy, significantly reducing hardware upgrade costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the process of the present invention;

[0056] Figure 2 Schematic diagram of the system architecture of the present invention. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0058] Example 1

[0059] like Figure 1 、 Figure 2 As shown in the figure, this example provides an IC device aliasing multi-target detection method based on the attention mechanism. Taking 5000 IC data taken from multiple angles as an example, the method includes the following steps:

[0060] Step S1: Build an IC device aliasing feature database, collect multi-angle IC component images through imaging equipment, annotate device bounding boxes and pin topology relationships, and calculate and filter aliasing samples with an occlusion rate ≥ 30%;

[0061] Step S2: Construct a dual-path attention feature enhancement network, including:

[0062] (a) Spatial attention module: Generates the spatial weight matrix W_s∈[0,1]^H×W of the pin-dense area;

[0063] (b) Channel attention module: calculates the material feature channel response weight W_c∈R^C;

[0064] (c) Dynamic feature calibration unit: It fuses W_s and W_c through a gating mechanism and outputs a calibration feature map;

[0065] Step S3: Design a target decoupling detection module, including:

[0066] (a) Adaptive non-maximum suppression algorithm based on attention weight, dynamically adjusting the intersection-over-union ratio threshold;

[0067] (b) Topological relationship constraint branch, modeling the spatial distribution of pins through graph convolutional network;

[0068] Step S4: Use a hybrid loss function that includes attention focus loss and topology consistency loss to train the model;

[0069] Step S5: Deploy the lightweight model to the embedded platform to achieve real-time multi-target detection and topological relationship output.

[0070] The device boundary box and pin topology relationship of step S1 are as follows:

[0071] Mark the device's minimum external rectangle and pin coordinates, and establish a topological relationship diagram G = (V, E);

[0072] The vertex set V represents the device body, and the edge set E represents the assembly connection relationship.

[0073] The spatial attention module implementation of step S2(a) includes:

[0074] (a) Perform dilated convolution on the feature pyramid P3-P5 layers with a dilation rate of d = 2;

[0075] (b) Generate the initial spatial weight matrix through 3×3 convolution;

[0076] (c) Apply softmax normalization: W_s' = exp(W_s / √d) / Σexp(W_s /

[0077] √d), where d = 256.

[0078] The calculation process of the dynamic feature calibration unit in step S2(c) is as follows:

[0079] G=σ(Conv1×1([W_s';W_c']));

[0080]

[0081] in represents channel-by-channel multiplication, ⊙ represents element-by-element multiplication, and σ is the sigmoid activation function.

[0082] The adaptive non-maximum suppression algorithm of step S3(a) includes:

[0083] (a) Construct the feature similarity matrix S = W_att·X^T, where X∈R^{N×d} is the detection box feature;

[0084] (b) Dynamic IoU threshold setting: τ_ij = 0.5 × (1 + cos (πS_ij / 2));

[0085] (c) Suppression operation is performed when the IoU between detection boxes is greater than τ_ij.

[0086] The topological relationship constraint branch of step S3(b) includes:

[0087] (a) Construct a graph structure G = (V, E), where the vertex V represents the device and the edge E represents the assembly relationship;

[0088] (b) Update vertex features through a two-layer graph convolutional network:

[0089]

[0090] in is the normalized adjacency matrix, W^{(l)} is a learnable parameter;

[0091] (c) Output topological matching matrix M∈[0,1]^{N×N}.

[0092] Among them, the hybrid loss function of step S4 is:

[0093] L_total=0.8L_det+0.5L_att+0.3L_top;

[0094] in:

[0095] L_det=FocalLoss(cls)+GIoULoss(reg);

[0096] L_att=||W_s'°W_c'||_F^2;

[0097] L_top = 1-IoU(M_pred,M_gt);

[0098] The lightweight deployment in step S5 includes:

[0099] (a),Channel pruning based on Taylor expansion: retain| Channel;

[0100] (b) INT8 quantization: linear quantization is performed on the weight parameters:

[0101] W_q=round(127*(W-min(W)) / (max(W)-min(W)))

[0102] (c) Deployed on the Jetson Xavier platform and accelerated inference through TensorRT.

[0103] The implementation effect of this embodiment is as follows:

[0104] (1) Achieves 82.3% mAP at η = 40% occlusion rate, a 41.2% improvement over the traditional YOLOv5 (58% → 82.3%), solving the problem of feature confusion. By enhancing local feature perception through dilated convolution, the discrimination of dense pins is improved by 2.3 times (see the table below for experimental data).

[0105] (2) The topology matching accuracy (TA) reaches 91.5%, the assembly error detection rate is improved to 98.7% (an increase of 65.1 percentage points compared with the traditional method), and the single-frame topology analysis takes only 8.3ms.

[0106] Table 1 Mixed scene test (1000 frames)

[0107]

[0108] The above-described embodiments merely represent several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. IC device aliasing multi-target detection algorithm based on attention mechanism, characterized by: include: Build an IC device aliasing feature database, collect multi-angle IC component images, annotate device bounding boxes and pin topology relationships, and screen aliasing samples with occlusion rates ≥ 30%; Construct a dual-path attention feature enhancement network, including a spatial attention module, a channel attention module, and a dynamic feature calibration unit; Design a target decoupling detection module, including an adaptive non-maximum suppression algorithm based on attention weights and a topological relationship constraint branch; The model is trained using a hybrid loss function that includes attention focus loss and topological consistency loss; Deploy lightweight models to embedded platforms to achieve real-time multi-target detection and topological relationship output.

2. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The device boundary box and pin topology relationship are marked by the minimum circumscribed rectangular box and pin coordinates of the device, and a topology relationship graph G = (V, E) is established, where the vertex set V represents the device body and the edge set E represents the assembly connection relationship.

3. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The spatial attention module performs dilation convolution with a dilation rate of d=2 on the feature pyramid P3-P5 layers, generates the initial spatial weight matrix through 3×3 convolution, and obtains W_s' through softmax normalization.

4. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The dynamic feature calibration unit is implemented by G = σ(Conv1×1([W_s'; W_c'])) and Calculate, where represents channel-by-channel multiplication, ⊙ represents element-by-element multiplication, and σ is the sigmoid activation function.

5. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The adaptive non-maximum suppression algorithm constructs a feature similarity matrix S = W_att·X^T, sets a dynamic IoU threshold with τ_ij = 0.5×(1+cos(πS_ij / 2)), and performs a suppression operation on the detection box with IoU>τ_ij.

6. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The topological relationship constraint branch constructs the graph structure G = (V, E), which is then passed through a two-layer graph convolutional network. Update vertex features and output the topological matching matrix M∈[0,1]^{N×N}.

7. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The hybrid loss function L_total = 0.8L_det + 0.5L_att + 0.3L_top, where L_det = FocalLoss(cls) + GIoULoss(reg), L_att = ||W_s'°W_c'||_F^2, L_top = 1-IoU(M_pred,M_gt).

8. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: Lightweight deployment includes Taylor expansion based retention Channel pruning, INT8 quantization, and accelerated inference through TensorRT on the Jetson Xavier platform.

9. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1 is characterized in that: The dual-path attention feature enhancement network fuses the spatial weight matrix W_s and the channel response weight W_c through a gating mechanism, and outputs a calibrated feature map to enhance feature expression.

10. The IC device aliasing multi-target detection algorithm based on the attention mechanism according to claim 1, characterized in that: The target decoupling detection module combines the adaptive non-maximum suppression algorithm with the topology constraint branch to achieve effective detection of aliased IC devices and topology relationship analysis.

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