Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scanning line and a plurality of pixel driving circuits, and every two adjacent rows of pixel driving circuits are arranged in a mirror image mode. The pixel driving circuit comprises a driving transistor and a first light-emitting control transistor, and a first node, electrically connected with an anode of a light-emitting element, of the first light-emitting control transistor is arranged between a first power supply signal line and a light-emitting control signal line, so that the first node is close to a middle area of the pixel driving circuit; in this way, the length difference of conduction paths between the two adjacent rows of pixel driving circuits arranged in a mirroring mode and the anodes of the light-emitting elements is reduced, and the potential difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits arranged in the mirroring mode can be reduced. Therefore, the brightness difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits arranged in a mirroring mode can be reduced, and the brightness uniformity of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light-emitting diode display technology has many advantages, such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, wide operating temperature range, and the ability to achieve flexible display and large-area full-color display. It is recognized by the industry as the display technology with the most development potential.

[0003] Currently, to improve the yield and performance of organic light-emitting diode (OLED) display panels, the pixel driving circuits for odd rows are mirrored in their layout with those for even rows. Currently, the key nodes where transistors in the pixel driving circuits electrically connect to the light-emitting elements are located on the bottom side of the pixel driving circuits. As a result, after mirroring, the key nodes in each row of the pixel driving circuits appear to be arranged in a sparse and dense pattern. Because the light-emitting elements in each row are arranged at equal intervals, the length of the conductive paths between the key nodes in the pixel driving circuits and the corresponding light-emitting elements in odd rows is dependent on the length of the conductive paths between the key nodes in the pixel driving circuits and the corresponding light-emitting elements in even rows. This results in a difference in potential between the light-emitting elements in odd rows and those in even rows, ultimately leading to a significant difference in brightness between the light-emitting elements in odd and even rows.

[0004] Therefore, it is necessary to provide a display panel and a display device to improve this defect. Summary of the Invention

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the uniformity of brightness of the display panel.

[0006] To achieve the above objectives, according to a first aspect of the present application, a display panel is provided, comprising a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in an array to form a plurality of rows of the pixel driving circuits and a plurality of columns of the pixel driving circuits, and the pixel driving circuits in two adjacent rows are mirror-imaged. The pixel driving circuits comprise:

[0007] a driving transistor connected in series with the light emitting element between the first power signal line and the second power signal line;

[0008] a first light emission control transistor connected in series between the driving transistor and the light emitting element, and electrically connected to the anode of the light emitting element at the first node, wherein a first light emission control gate of the first light emission control transistor is electrically connected to the light emission control signal line;

[0009] a first reset transistor, the first reset transistor being electrically connected to the first node and the first scan line, the orthographic projections of the first power signal line, the light-emitting control signal line, and the first scan line on a reference plane being arranged sequentially along a column direction from the driving transistor to the first reset transistor, and the reference plane being parallel to a light-emitting surface of the display panel;

[0010] The orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light emitting control signal line on the reference plane.

[0011] Optionally, the first light emission control transistor includes a first light emission control active portion, one end of the first light emission control active portion is electrically connected to the anode of the light emitting element;

[0012] The orthographic projection of the first light-emitting control active portion on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

[0013] Optionally, an extension direction of the first light emitting control active portion is parallel to an extension direction of the light emitting control signal line, and an extension direction of the first light emitting control gate is perpendicular to an extension direction of the light emitting control signal line.

[0014] Optionally, the driving transistor includes a driving active portion, and the driving active portion includes a first sub-portion and a second sub-portion extending in different directions;

[0015] Among them, along the direction perpendicular to the extension direction of the light-emitting control signal line, the first sub-portion partially overlaps with the first light-emitting control active portion; along the extension direction of the light-emitting control signal line, the second sub-portion partially overlaps with the first light-emitting control active portion.

[0016] Optionally, the light emitting control signal line and the first light emitting control gate are provided in different layers.

[0017] Optionally, the light emitting control signal line and the first power signal line are arranged on the same layer.

[0018] Optionally, the display panel includes:

[0019] a first active layer including the first light emission control active portion;

[0020] a first gate layer, disposed on the first active layer and comprising the first light-emitting control gate;

[0021] The first source-drain electrode layer is disposed on the first gate layer and includes the light emitting control signal line and a first power signal line.

[0022] Optionally, the pixel driving circuit includes a storage capacitor and a second light emitting control transistor, and the display panel includes:

[0023] a first gate layer, comprising a first plate of the storage capacitor;

[0024] a second gate layer, comprising a second plate of the storage capacitor;

[0025] The display panel further includes a first connecting portion, the second electrode is electrically connected to the second light-emitting control transistor via the first connecting portion, and the orthographic projection of the second electrode on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line on the reference plane.

[0026] Optionally, the first connecting portion is provided in the same layer as the first power signal line and the light emitting control signal line, and is made of the same material;

[0027] Wherein, along a direction perpendicular to an extending direction of the light-emitting control signal line, the first connecting portion is located on a side of the light-emitting control signal line away from the first power signal line.

[0028] According to a second aspect of the present application, a display device is provided, comprising the display panel as described above.

[0029] In the display panel of the embodiment of the present application, by placing the first node electrically connecting the first light-emitting control transistor to the anode of the light-emitting element between the first power signal line and the light-emitting control signal line, the first node can be brought close to the middle area of ​​the pixel driving circuit, thereby reducing the length difference of the conduction path between two adjacent rows of pixel driving circuits in a mirrored arrangement and the anode of the light-emitting element. In this way, the potential difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement can be reduced, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0030] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0032] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0033] Figure 1 A top view of a display panel provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a pixel driving circuit in a display panel provided in an embodiment of the present application;

[0035] Figure 3 A stack-up diagram of a pixel driving circuit in a display panel provided in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the film layer structure of a display panel provided in an embodiment of the present application;

[0037] Figure 5 A film layer diagram of the active layer provided in an embodiment of the present application;

[0038] Figure 6 A film layer diagram of the first gate layer provided in an embodiment of the present application;

[0039] Figure 7 A stacking diagram of an active layer and a first gate layer in a display panel provided in an embodiment of the present application;

[0040] Figure 8 A film layer diagram of a second gate layer in a display panel provided in an embodiment of the present application;

[0041] Figure 9 A stacking diagram of an active layer, a first gate layer, and a second gate layer in a display panel provided in an embodiment of the present application;

[0042] Figure 10 A film layer diagram of a first source / drain electrode layer in a display panel provided in an embodiment of the present application;

[0043] Figure 11 A stacking diagram of an active layer, a first gate layer, a second gate layer, and a first source and drain layer in a display panel provided in an embodiment of the present application;

[0044] Figure 12 A film layer diagram of a second source / drain electrode layer in a display panel provided in an embodiment of the present application;

[0045] Figure 13 A stacking diagram of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer in a display panel provided in an embodiment of the present application;

[0046] Figure 14 A film layer diagram of the anode layer in the display panel provided in an embodiment of the present application;

[0047] Figure 15A stacking diagram of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a second source-drain electrode layer, and an anode layer in a display panel provided in an embodiment of the present application;

[0048] Figure 16 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0050] An embodiment of the present application provides a display panel, which includes a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits. The plurality of pixel driving circuits are arranged in an array to form multiple rows of pixel driving circuits and multiple columns of pixel driving circuits. One row of two adjacent rows of pixel driving circuits is arranged in a mirror image of the other row. The pixel driving circuit includes a driving transistor, a first light-emitting control transistor, and a first reset transistor. The driving transistor is connected in series with the light-emitting element between the first power signal line and the second power signal line. The first light-emitting control transistor is connected in series between the driving transistor and the light-emitting element and is electrically connected to the anode of the light-emitting element at a first node. A first light-emitting control gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. A first reset transistor is electrically connected to the first node and the first scan line. The orthographic projections of the first power signal line, the light-emitting control signal line, and the first scan line on a reference plane are arranged sequentially along a column direction from the driving transistor to the first reset transistor. The reference plane is parallel to a light-emitting surface of the display panel. The orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

[0051] In an embodiment of the present application, by placing the first node electrically connecting the first light-emitting control transistor to the anode of the light-emitting element between the first power signal line and the light-emitting control signal line, the first node can be brought close to the middle area of ​​the pixel driving circuit, thereby reducing the length difference of the conduction path between two adjacent rows of pixel driving circuits in a mirrored arrangement and the anode of the light-emitting element. In this way, the potential difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement can be reduced, thereby reducing the brightness difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0052] See also Figure 1 and Figure 2 , Figure 1 A top view of a display panel provided in an embodiment of the present application, Figure 2 This is a schematic diagram of a pixel driver circuit in a display panel according to an embodiment of the present application. The display panel 100 includes a display area AA and a border area NA, with the border area NA being disposed outside the display area AA. The display area AA is the area for displaying images. The display panel includes a light-emitting element EL located in the display area AA, a first power signal line VDD, a second power signal line VSS, a light-emission control signal line EM, a first scan line Scan1, and a plurality of pixel driver circuits PD. The plurality of pixel driver circuits PD are arranged in an array to form multiple rows and columns of pixel driver circuits, with one row of adjacent rows of pixel driver circuits mirroring the other row.

[0053] It should be noted that the mirror setting of two adjacent rows of pixel driving circuits means that: in two adjacent rows of pixel driving circuits, the orthographic projection of the pattern of one row of pixel driving circuits on the reference plane and the orthographic projection of the pattern of the other row of pixel driving circuits on the reference plane can be symmetrical about an imaginary symmetry axis, and the pattern of the conductive structure connected between the two adjacent rows of pixel driving circuits may not be mirrored.

[0054] Combine Figure 2 As shown, the pixel driving circuit PD includes a driving transistor T1, a first emission control transistor T6, and a first reset transistor T7. The driving transistor T1 and the light-emitting element EL are connected in series between a first power signal line VDD and a second power signal line VSS. The first emission control transistor T6 is connected in series between the first power signal line VDD and the light-emitting element EL. The anodes of the first emission control transistor T6 and the light-emitting element EL are electrically connected to a first node C, and the first emission control gate of the first emission control transistor T6 is electrically connected to the emission control signal line EM. The first reset transistor T7 is electrically connected to the first node C and the first scan line Scan1. It should be noted that the first node C refers to the junction between the first emission control transistor T6 and the light-emitting element EL.

[0055] Combine Figure 2 and Figure 3 As shown, Figure 3 In the stack-up diagram of the pixel driving circuit in the display panel provided in the embodiment of the present application, the orthographic projection of the first node C on the reference plane is located between the orthographic projections of the first power signal line VDD and the light-emitting control signal line EM on the reference plane, and the reference plane is parallel to the light-emitting surface of the display panel.

[0056] In the embodiment of the present application, by placing the first node C electrically connecting the first light-emitting control transistor T6 and the anode of the light-emitting element EM between the first power signal line VDD and the light-emitting control signal line EM, the first node C can be brought close to the middle area of ​​the pixel driving circuit PD, thereby reducing the difference in the length of the conductive path between the two adjacent rows of the pixel driving circuits PD and the anodes of the light-emitting elements EL in the mirrored arrangement. In this way, the difference in the potential of the light-emitting elements corresponding to the two adjacent rows of the pixel driving circuits in the mirrored arrangement can be reduced, thereby reducing the difference in the brightness of the light-emitting elements corresponding to the two adjacent rows of the pixel driving circuits in the mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0057] In some embodiments, as Figure 2 As shown, the pixel driving circuit PD includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a second reset transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset transistor T7, a third reset transistor T8 and a storage capacitor Cst.

[0058] like Figure 2As shown, the first electrode of the driving transistor T1 is electrically connected to the second node A, the second electrode of the driving transistor T1 is electrically connected to the third node B, and the driving gate of the driving transistor T1 is electrically connected to the fourth node Q; the first electrode of the switching transistor T2 is electrically connected to the data line Data, the second electrode of the switching transistor T2 is electrically connected to the second node A, and the switching gate of the switching transistor T2 is electrically connected to the second scan line Scan2; the first electrode of the compensation transistor T3 is electrically connected to the fourth node Q, the second electrode of the compensation transistor T3 is electrically connected to the third node B, and the compensation gate of the compensation transistor T3 is electrically connected to the first scan signal line Scan2; the first electrode of the second reset transistor T4 is electrically connected to the second reset signal line VI2, the second electrode of the second reset transistor T4 is electrically connected to the fourth node Q, and the second reset gate of the second reset transistor T4 is electrically connected to the third scan line Scan3; the first electrode of the second light-emitting control transistor T5 is electrically connected to the first power signal line VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second node A, and the first electrode of the second light-emitting control transistor T5 is electrically connected to the first power signal line VDD. The second light control gate is electrically connected to the light control signal line EM; the first electrode of the first light control transistor T6 is electrically connected to the third node B, the second electrode of the first light control transistor T6 is electrically connected to the first node C, and the first light control gate of the first light control transistor T6 is electrically connected to the light control signal line EM; the first electrode of the first reset transistor T7 is electrically connected to the first reset signal line VI1, the second electrode of the first reset transistor T7 is electrically connected to the first node A, and the first reset gate of the first reset transistor T7 is electrically connected to the first scan line Scan1; the first electrode of the third reset transistor T8 is electrically connected to the third reset signal line VI3, the second electrode of the third reset transistor T8 is electrically connected to the second node A, and the third reset gate of the third reset transistor T8 is electrically connected to the first scan signal line Scan1; the first plate of the storage capacitor Cst is electrically connected to the first power signal line VDD, and the second plate of the storage capacitor Cst is electrically connected to the fourth node Q; the anode of the light emitting device EL is electrically connected to the first node C, and the cathode of the light emitting device EL is electrically connected to the second power signal line VSS.

[0059] In an embodiment of the present application, the first power signal line VDD is used to provide a constant voltage high level signal to the pixel driving circuit PD, and the second power signal line VSS is used to provide a constant voltage low level signal to the pixel driving circuit PD.

[0060] It should be noted that in the embodiment of the present application, the first electrode of the transistor is one of the source and the drain, and the second electrode is the other of the source and the drain, and the first electrode and the second electrode of each transistor can be the same or different.

[0061] The following is for Figure 2 and Figure 3 The structure shown in FIG. 1 describes the film layer structure of the pixel driving circuit of the present application.

[0062] In some embodiments, see Figure 4 , Figure 4 A schematic diagram of the film layer structure of a display panel provided in an embodiment of the present application, wherein the display panel 100 includes a substrate 11, an active layer 12 arranged on the substrate 11, a first gate insulating layer 13 arranged on the active layer 12, a first gate layer 14 arranged on the first gate insulating layer 13, a second gate insulating layer 15 arranged on the first gate layer 14, a second gate layer 16 arranged on the second gate insulating layer 15, a first interlayer dielectric layer 17 arranged on the second gate layer 16, a first source-drain layer 18 arranged on the first interlayer dielectric layer 17, a second interlayer dielectric layer 19 arranged on the first source-drain layer 18, a second source-drain layer 20 arranged on the second interlayer dielectric layer 19, and a planarizing layer 21 arranged on the second source-drain layer 20.

[0063] In some embodiments, see Figure 4 The substrate 11 may be a single-layer substrate formed of an organic material or an inorganic material, or a double-layer or multi-layer substrate formed of at least one of an organic material and an inorganic material, wherein the organic material may be but is not limited to polyimide, and the inorganic material may be but is not limited to glass.

[0064] like Figure 4 As shown, the active layer 12 is provided on the substrate 11. The material of the active layer 12 includes a metal oxide semiconductor material or a silicon semiconductor material. The metal oxide semiconductor material may be specifically indium gallium zinc oxide, and the silicon semiconductor material may be specifically amorphous silicon or low temperature polysilicon.

[0065] In an embodiment of the present application, the material of the active layer 12 includes low-temperature polysilicon.

[0066] like Figure 4 As shown, the first gate insulating layer 13, the second gate insulating layer 15, the first interlayer dielectric layer 17, and the second interlayer dielectric layer 19 are respectively disposed on corresponding metal layers or active layers to separate and insulate different metal layers or active layers. The first gate insulating layer 13, the second gate insulating layer 15, the first interlayer dielectric layer 17, and the second interlayer dielectric layer 19 can be a single-layer structure or a stacked-layer structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0067] like Figure 4As shown, the first gate layer 14, the second gate layer 16, the first source-drain electrode layer 18 and the second source-drain electrode layer 20 are respectively arranged on the corresponding insulating layer or the interlayer dielectric layer. The first gate layer 14, the second gate layer 16, the first source-drain electrode layer 18 and the second source-drain electrode layer 20 can be a single-layer structure formed by at least one of copper, molybdenum, titanium, aluminum, silver, etc., or a stacked structure of two or more layers formed by at least two of the above-mentioned metal materials.

[0068] like Figure 4 As shown, the planar layer 21 is provided on the second source-drain electrode layer 20 . The material of the planar layer 21 may be at least one inorganic insulating material selected from silicon nitride, silicon oxide, or silicon oxynitride, or an organic insulating material with leveling properties.

[0069] like Figure 4 As shown, the display panel also includes a light-emitting device layer, which is arranged on the side of the flat layer 21 away from the second source and drain layer 20. The light-emitting device layer includes an anode layer 22 arranged on the flat layer 21, a pixel definition layer 23 arranged on the anode layer 22, a spacer layer 24 arranged on the pixel definition layer 23, a light-emitting material layer and a cathode layer (not shown in the figure) arranged on the pixel definition layer 23.

[0070] like Figure 5 As shown, Figure 5 A film layer diagram of the active layer provided for an embodiment of the present application, wherein the active layer 12 includes a driving active portion T1A of the driving transistor T1, a switching active portion T2A of the switching transistor T2, a compensation active portion T3A of the compensation transistor T3, a second reset active portion T4A of the second reset transistor T4, a second light-emitting control active portion T5A of the second light-emitting control transistor T5, a first light-emitting control active portion T6A of the first light-emitting control transistor T6, a first reset active portion T7A of the first reset transistor T7, and a third reset active portion T8A of the third reset transistor T8.

[0071] like Figure 5 As shown, the driving active portion T1A, the switching active portion T2A, the compensation active portion T3A, the second reset active portion T4A, the first light-emission control active portion T5A, the second light-emission control active portion T6A, the first reset active portion T7A, and the third reset active portion T8A are connected to each other. The switching active portion T2A is long and extends along the column direction Y. The driving active portion T1A is disposed between the first light-emission control active portion T5A and the second light-emission control active portion T6A.

[0072] Combine Figure 4 and Figure 5As shown, one end of the first light emitting control active portion T6A is electrically connected to the anode of the light emitting element EL, and the orthographic projection of the first light emitting active portion T6A on the reference plane is located between the orthographic projections of the first power signal line VDD and the light emitting control signal line EM on the reference plane.

[0073] Combine Figure 4 and Figure 5 As shown, the first end of the first light-emitting control active portion T6A and the first end of the first reset active portion T7A are connected to a first node C, which is the portion indicated by the dashed box in the figure. By positioning the orthographic projection of the first light-emitting control active portion T6A on the reference plane between the orthographic projections of the first power signal line VDD and the light-emitting control signal line EM on the reference plane, the first node C can be brought closer to the center region of the pixel driver circuit PD. This can reduce the potential difference between the light-emitting elements corresponding to two adjacent rows of the pixel driver circuits in a mirrored arrangement, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of the pixel driver circuits in the mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0074] In some embodiments, an extending direction of the first light emitting control active portion T6A is parallel to an extending direction of the light emitting control signal line EM.

[0075] Combine Figure 4 and Figure 5 As shown, the first light-emitting control active portion T6A and the light-emitting control signal line EM both extend along the row direction X. By arranging the first light-emitting control active portion T6A horizontally, the first node C can be closer to the middle area of ​​the pixel driving circuit. This can further reduce the potential difference between the light-emitting elements corresponding to two adjacent rows of pixel driving circuits in a mirrored arrangement, thereby reducing the brightness difference between the light-emitting elements corresponding to two adjacent rows of pixel driving circuits in a mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0076] In some embodiments, combined Figure 4 and Figure 5 As shown, the driving active portion T1A is "L"-shaped and includes a first sub-portion T1A1 and a second sub-portion T1A2 extending in different directions. The first sub-portion T1A1 extends along the column direction Y, and the second sub-portion T1A2 extends along the row direction X.

[0077] Combine Figure 4 and Figure 5As shown, along a direction perpendicular to the extension direction of the light-emission control signal line EM (i.e., the column direction Y), the first sub-portion T1A1 partially overlaps the first light-emission control active portion T6A; and along the extension direction of the light-emission control signal line (i.e., the row direction X), the second sub-portion T1A2 partially overlaps the first light-emission control active portion T6A. By configuring the driving active portion T1A in an "L" shape formed by the first sub-portion T1A1 and the second sub-portion T1A2, the first light-emission control active portion T6A is positioned in the space enclosed by the first sub-portion T1A1 and the second sub-portion T1A2. This reduces the distance between the driving active portion T1A and the first light-emission control active portion T6A in the column direction Y, bringing the first node C closer to the center region of the pixel driving circuit. This further reduces the potential difference between the light-emitting elements corresponding to two adjacent rows of the pixel driving circuits in the mirrored arrangement, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of the pixel driving circuits in the mirrored arrangement, thereby improving the brightness uniformity of the display panel.

[0078] like Figure 6 As shown, Figure 6 A film layer diagram of the first gate layer provided in an embodiment of the present application, wherein the first gate layer 14 includes a driving gate T1G of the driving transistor T1, a switching gate T2G of the switching transistor T2, a compensation gate T3G of the compensation transistor T3, a second reset gate T4G of the second reset transistor T4, a second light-emitting control gate T5G of the second light-emitting control transistor T5, a first light-emitting control gate T6G of the first light-emitting control transistor T6, a first reset gate T7G of the first reset transistor T7, a third reset gate T8G of the third reset transistor T8, and a first plate Cst1 of the storage capacitor Cst.

[0079] Combine Figures 4 to 7 As shown, Figure 7 This diagram shows the stackup of the active layer and first gate layer in the display panel provided in an embodiment of the present application. The driving gate T1G includes a first main portion T1G1 and an extension portion T1G2. The extension portion T1G2 extends from the side of the first main portion T1G1 near the first light-emitting control gate T6G along the row direction X. The orthographic projection of the first main portion T1G1 on the reference plane overlaps with the orthographic projection of the first sub-portion T1A1 on the reference plane, and the orthographic projection of the extension portion T1G2 on the reference plane overlaps with the orthographic projection of the second sub-portion T1A2 on the reference plane. The driving gate T1G can be reused as the first plate Cst1 of the storage capacitor Cst.

[0080] Combine Figures 4 to 7As shown, the first light-emission control gate T6G extends perpendicularly to the direction of extension of the light-emission control signal line EM. The first light-emission control gate T6G is in an elongated strip shape and extends along the column direction Y. The orthographic projection of the first light-emission control gate T6G on the reference plane partially overlaps with the orthographic projection of the first light-emission control active portion T6A on the reference plane. The second light-emission control gate T5G extends along the row direction X. The orthographic projection of the second light-emission control gate T5G on the reference plane partially overlaps with the orthographic projection of the second light-emission control active portion T5A on the reference plane. The first light-emission control gate T6G and the second light-emission control gate TG5 are connected to each other to simultaneously receive the light-emission control signal transmitted by the light-emission control signal line EM.

[0081] like Figure 8 As shown, Figure 8 This is a film layer diagram of the second gate layer in the display panel provided by an embodiment of the present application. The second gate layer 16 includes a second plate Cst2 of the storage capacitor Cst and a first reset signal line VI1. The first four signal lines VI1 extend along the row direction X.

[0082] Combine Figure 8 and Figure 9 As shown, Figure 9 The stacking diagram of the active layer, the first gate layer and the second gate layer in the display panel provided in the embodiment of the present application, the orthographic projection of the second electrode plate Cst and the first electrode plate Cst1 on the reference plane partially overlap to form a storage capacitor Cst.

[0083] In some embodiments, in conjunction with FIG. Figures 4 to 9 As shown, the emission control signal line EM and the first emission control gate T6G are provided in different layers. By providing the emission control signal line EM and the first emission control gate T6G in different film layers, the metal pattern of the first gate layer 14 can be prevented from blocking the portion of the active layer 12 connected between the first emission control active portion T6A and the first reset active portion T7A, ensuring that the portion connected between the first emission control active portion T6A and the first reset active portion T7A can be conductive.

[0084] In some embodiments, the light-emission control signal line EM is provided on the same layer as the first power signal line VDD. Placing the light-emission control signal line EM in the same film layer as the first power signal line VDD ensures that the portion connecting the first light-emission control active portion T6A and the first reset active portion T7A can be conductive without adding additional film layers.

[0085] In some embodiments, the display panel includes a first connecting portion 181, and the second electrode plate C12 is electrically connected to the second emission control transistor T5 via the first connecting portion 181. The orthographic projection of the second electrode plate C12 on a reference plane partially overlaps with the orthographic projection of the emission control signal line EM on the reference plane. By adding the first connecting portion 181, the first connecting portion 181 is used to bridge the second electrode plate C12 and one end of the second emission control active portion T5A of the second emission control transistor T5. This not only transmits the first power supply signal received by the second electrode plate C12 to the second emission control transistor T5, but also prevents a short circuit between the first power supply signal line VDD and the emission control signal line EM.

[0086] In some embodiments, the first connection portion 181 is disposed in the same layer as the first power signal line VDD and the emission control signal line EM, and is made of the same material. The first connection portion 181 is located perpendicular to the direction in which the emission control signal line EM extends, on a side of the emission control signal line EM that is further away from the first power signal line VDD. By utilizing the film layer in which the first power signal line VDD resides for the first connection portion 181 and placing the first connection portion 181 on a side of the emission control signal line EM that is further away from the first power signal line VDD, sufficient space is reserved between the emission control signal line EM and the first power signal line VDD for placement of the first emission control transistor T6. This allows the first node C to be positioned close to the center of the pixel driver circuit PD while preventing a short between the first power signal line VDD and the emission control signal line EM. This reduces the difference in the length of the conductive path between the pixel driver circuits PD and the anodes of the light-emitting elements EL in two adjacent rows of mirrored arrangements. This reduces the potential difference between the light-emitting elements corresponding to the two adjacent rows of mirrored arrangements, thereby reducing the brightness difference between the light-emitting elements corresponding to the two adjacent rows of mirrored arrangements, thereby improving the brightness uniformity of the display panel.

[0087] like Figure 10 As shown, Figure 10 A film layer diagram of the first source and drain layer in the display panel provided in an embodiment of the present application, wherein the first source and drain layer 18 includes a second reset signal line VI2, a third scan line Scan3, a second scan line Scan2, a first power signal line VDD, a light-emitting control signal line EM, a first reset signal line VI1, and a first connecting portion 181. The second reset signal line VI2, the third scan line Scan3, the second scan line Scan2, the first power signal line VDD, the light-emitting control signal line EM, and the first reset signal line VI1 are arranged in sequence along the column direction Y from the driving transistor T1 to the first reset transistor T7, and extend along the row direction X.

[0088] like Figure 11 As shown, Figure 11A stacked diagram of the active layer, the first gate layer, the second gate layer and the first source and drain layer in the display panel provided in an embodiment of the present application, wherein the third scan line Scan3 of the first source and drain layer 18 and the third scan line Scan3 of the first gate layer 14 have the same extension direction, and their orthographic projections on the reference plane are partially overlapped.

[0089] Combine Figure 10 and Figure 11 As shown, the second electrode plate C12 is electrically connected to the first end of the second emission control active portion T5A of the second emission control transistor T5 via the first connection portion 181 to transmit the first power signal to the second emission control transistor T5. The orthographic projection of the second electrode plate C12 on the reference plane partially overlaps with the orthographic projection of the emission control signal line EM on the reference plane.

[0090] like Figure 12 and Figure 13 As shown, Figure 12 A film layer diagram of the second source and drain layer in the display panel provided in an embodiment of the present application, Figure 13 A stack diagram of an active layer, a first gate layer, a second gate layer, a first source-drain layer, and a second source-drain layer in a display panel provided in an embodiment of the present application, wherein the second source-drain layer includes a data line Data and a second power signal line VSS. The data line Data and the second power signal line VSS extend along the column direction Y and are spaced apart along the row direction X.

[0091] like Figure 14 and Figure 15 As shown, Figure 14 A film layer diagram of the anode layer in the display panel provided in an embodiment of the present application, Figure 15 A stack diagram of the active layer, first gate layer, second gate layer, first source / drain electrode layer, second source / drain electrode layer, and anode layer in a display panel provided in an embodiment of the present application is shown. The anode layer 22 includes multiple patterned anodes, including a first anode 221, a second anode 222, and a third anode 223. The first anode 221, the second anode 222, and the third anode 223 correspond to light-emitting elements of different luminous colors, respectively. The light-emitting elements EL include a red light-emitting element, a green light-emitting element, and a blue light-emitting element. The red light-emitting element includes the first anode 221, the green light-emitting element includes the second anode 222, and the blue light-emitting element includes the third anode 223. It should be noted that since the blue light-emitting element has a lower luminous efficiency and lifetime, the lifetime and luminous efficiency of the blue light-emitting element can be increased by making the area of ​​the third anode 223 larger than the areas of the first anode 221 and the second anode 222, and by making the area of ​​the light-emitting layer of the blue light-emitting device larger than the areas of the light-emitting layers of the red and green light-emitting elements.

[0092] like Figure 14 and Figure 15 As shown, the first anode 221 and the second anode 222 are arranged side by side, and the third anode 223 is arranged on one side of the first anode 221 and the second anode 222 along the column direction Y. The first anode 221, the second anode 222 and the third anode 223 are respectively electrically connected to the three adjacent pixel driving circuits in the same row of pixel driving circuits.

[0093] According to the display panel provided in the above embodiment of the present application, the embodiment of the present application further provides a display device, see Figure 16 , Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is disposed on the housing 200. The display panel 100 can be the display panel provided in any of the above embodiments. The display device provided in an embodiment of the present application can achieve the same technical effects as the display panel provided in any of the above embodiments, and will not be described in detail here.

[0094] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, the display panel including a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scanning line and a plurality of pixel driving circuits, two adjacent rows of pixel driving circuits are mirror-arranged, the pixel driving circuit including a driving transistor and a first light-emitting control transistor, by placing a first node electrically connected to the anode of the first light-emitting control transistor and the anode of the light-emitting element between the first power signal line and the light-emitting control signal line, the first node can be close to the middle area of ​​the pixel driving circuit, thereby reducing the length difference of the conduction path between the two adjacent rows of pixel driving circuits in the mirror arrangement and the anode of the light-emitting element, thereby reducing the potential difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirror arrangement, thereby reducing the brightness difference of the light-emitting elements corresponding to the two adjacent rows of pixel driving circuits in the mirror arrangement, and improving the brightness uniformity of the display panel.

[0095] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0096] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0098] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The device comprises a light-emitting element, a first power signal line, a second power signal line, a light-emitting control signal line, a first scan line, and a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in an array to form a plurality of rows of pixel driving circuits and a plurality of columns of pixel driving circuits, and the pixel driving circuits in two adjacent rows are mirror-imaged. The pixel driving circuit comprises: a driving transistor connected in series with the light emitting element between the first power signal line and the second power signal line; a first light-emitting control transistor connected in series between the driving transistor and the light-emitting element and electrically connected to the anode of the light-emitting element at a first node, wherein a first light-emitting control gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line; a first reset transistor, the first reset transistor being electrically connected to the first node and the first scan line, the orthographic projections of the first power signal line, the light-emitting control signal line, and the first scan line on a reference plane being arranged sequentially along a column direction from the driving transistor to the first reset transistor, and the reference plane being parallel to a light-emitting surface of the display panel; The orthographic projection of the first node on the reference plane is located between the orthographic projections of the first power signal line and the light emitting control signal line on the reference plane.

2. The display panel according to claim 1, wherein The first light emission control transistor includes a first light emission control active portion, one end of which is electrically connected to the anode of the light emitting element; The orthographic projection of the first light-emitting control active portion on the reference plane is located between the orthographic projections of the first power signal line and the light-emitting control signal line on the reference plane.

3. The display panel according to claim 2, wherein: An extension direction of the first light emitting control active portion is parallel to an extension direction of the light emitting control signal line, and an extension direction of the first light emitting control gate is perpendicular to an extension direction of the light emitting control signal line.

4. The display panel according to claim 2, wherein: The driving transistor includes a driving active portion, wherein the driving active portion includes a first sub-portion and a second sub-portion extending in different directions; Among them, along the direction perpendicular to the extension direction of the light-emitting control signal line, the first sub-portion partially overlaps with the first light-emitting control active portion; along the extension direction of the light-emitting control signal line, the second sub-portion partially overlaps with the first light-emitting control active portion.

5. The display panel according to any one of claims 1 to 4, wherein: The light emitting control signal line and the first light emitting control gate are arranged in different layers.

6. The display panel according to claim 5, wherein: The light emitting control signal line and the first power signal line are arranged on the same layer.

7. The display panel according to claim 5, wherein: The display panel includes: a first active layer including the first light emission control active portion; a first gate layer, disposed on the first active layer and comprising the first light-emitting control gate; The first source-drain electrode layer is disposed on the first gate layer and includes the light emitting control signal line and a first power signal line.

8. The display panel according to any one of claims 1 to 4, wherein: The pixel driving circuit includes a storage capacitor and a second light emitting control transistor, and the display panel includes: a first gate layer, comprising a first plate of the storage capacitor; a second gate layer, comprising a second plate of the storage capacitor; The display panel further includes a first connecting portion, the second electrode is electrically connected to the second light-emitting control transistor via the first connecting portion, and the orthographic projection of the second electrode on the reference plane partially overlaps with the orthographic projection of the light-emitting control signal line on the reference plane.

9. The display panel according to claim 8, wherein: The first connecting portion is provided on the same layer as the first power signal line and the light emitting control signal line, and is made of the same material; Wherein, along a direction perpendicular to an extending direction of the light-emitting control signal line, the first connecting portion is located on a side of the light-emitting control signal line away from the first power signal line.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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