Induction amplifier, data processing method, memory array structure and memory

Abstract

The embodiment of the invention provides an induction amplifier, a data processing method, a storage array structure and a memory. The induction amplifier comprises a first latch unit, an amplification unit and a second latch unit, the induction amplifier is configured in the mode that in the pre-induction stage, the first voltage end loads a first voltage, the second voltage end loads a second voltage, the amplification unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, and a first data signal and a second data signal are output to the first output data line and the second output data line respectively. The first latch unit performs data latching on the first data signal and the second data signal; and in the data latching stage, the third voltage end loads second voltage, and the second latching unit performs second data latching on the first data signal and the second data signal. According to the embodiment of the invention, the capability of resisting coupling noise between adjacent bit lines is improved, and the accuracy of data reading is improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and more specifically, to a sense amplifier, a data processing method, a storage array structure, and a memory. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The present application proposes a sense amplifier, a data processing method, a storage array structure and a memory, which can solve the technical problem that the sense amplifier is easily affected by coupling interference between adjacent bit lines, resulting in low data reading accuracy.

[0005] In a first aspect, an embodiment of the present application provides a sense amplifier, comprising: a first latch unit, an amplifying unit, and a second latch unit;

[0006] The first end of the first latch unit, the first end of the amplifying unit, and the first end of the second latch unit are respectively used to be electrically connected to the first voltage end, the second voltage end, and the third voltage end;

[0007] The second end and the third end of the amplifying unit are respectively used to be electrically connected to the bit line and the reference bit line;

[0008] The second end of the first latch unit is electrically connected to the second end of the second latch unit and the fourth end of the amplifying unit through the first output data line, and the third end of the first latch unit is electrically connected to the third end of the second latch unit and the fifth end of the amplifying unit through the second output data line;

[0009] The sense amplifier is configured such that, in a pre-sensing stage, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal; the amplification unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, outputs a first data signal and a second data signal to the first output data line and the second output data line, respectively; the first latch unit performs a first data latch on the first data signal and the second data signal; one of the first data signal and the second data signal is the same as the first voltage and the other is the same as the second voltage; in a data latching stage, the second voltage is applied to the third voltage terminal, and the second latch unit performs a second data latch on the first data signal and the second data signal.

[0010] In one possible implementation, the sense amplifier further includes:

[0011] An isolation unit, wherein the control end, the first end, and the second end are respectively used to be electrically connected to the isolation signal line, the bit line, and the reference bit line, and the third end and the fourth end are respectively electrically connected to the second output data line and the first output data line;

[0012] The isolation unit is configured such that during the data write-back phase, the first and third ends of the isolation unit are conductive, and the fourth and second ends of the isolation unit are conductive, so as to write the second data signal of the second output data line back to the storage unit through the bit line.

[0013] In one possible implementation, during the data write-back phase, the control voltage loaded on the control end of the isolation unit gradually increases to the turn-on voltage within a predetermined time and / or increases to the turn-on voltage through at least one intermediate voltage; the turn-on voltage is used to control the first and third ends of the isolation unit to be conductive, and the fourth and second ends to be conductive.

[0014] In one possible implementation, the switch device in the first latch unit is a PMOS transistor, and the switch device in the second latch unit is an NMOS transistor;

[0015] The switch device in the first latch unit is an NMOS transistor, and the switch device in the second latch unit is a PMOS transistor.

[0016] In one possible implementation, the sense amplifier further includes:

[0017] The offset cancellation unit has a control end, a first end, and a second end, respectively electrically connected to the offset cancellation signal line, the bit line, and the reference bit line, and a third end and a fourth end electrically connected to the first output data line and the second output data line, respectively;

[0018] The offset elimination unit is configured such that, in an offset elimination phase, the first voltage terminal and the second voltage terminal are conductively connected via the first output data line and the second output data line, the first terminal and the third terminal of the offset elimination unit are conductively connected, and the second terminal and the fourth terminal of the offset elimination unit are conductively connected, thereby eliminating the offset of the threshold voltage of the switching devices in the amplifying unit and the first latch unit; the offset elimination phase is located before the pre-sensing phase.

[0019] In a possible implementation, the amplification unit includes a first switch module and a second switch module;

[0020] The first end of the first switch module and the first end of the second switch module serve together as the first end of the amplifying unit;

[0021] The control end of the first switch module and the control end of the second switch module serve as the second end and the third end of the amplifying unit respectively;

[0022] The second end of the first switch module and the second end of the second switch module serve as the fourth end and the fifth end of the amplifying unit respectively.

[0023] In a possible implementation, the first latch unit includes a third switch module and a fourth switch module;

[0024] The first end of the third switch module and the first end of the fourth switch module serve together as the first end of the first latch unit;

[0025] The second end of the third switch module and the control end of the fourth switch module serve together as the second end of the first latch unit;

[0026] The control end of the third switch module and the second end of the fourth switch module serve together as the third end of the first latch unit.

[0027] In one possible implementation, the second latch unit includes a fifth switch module and a sixth switch module;

[0028] The first end of the fifth switch module and the first end of the sixth switch module serve together as the first end of the second latch unit;

[0029] The second end of the fifth switch module and the control end of the sixth switch module serve together as the second end of the second latch unit;

[0030] The control end of the fifth switch module and the second end of the sixth switch module serve together as the third end of the second latch unit.

[0031] In one possible implementation, the isolation unit includes a seventh switch module and an eighth switch module;

[0032] The control end of the seventh switch module and the control end of the eighth switch module serve together as the control end of the isolation unit;

[0033] The first end and the second end of the seventh switch module serve as the first end and the third end of the isolation unit, respectively;

[0034] The first end and the second end of the eighth switch module serve as the second end and the fourth end of the isolation unit, respectively.

[0035] In one possible implementation, the offset elimination unit includes a ninth switch module and a tenth switch module;

[0036] The control end of the ninth switch module and the control end of the tenth switch module serve together as the control end of the offset elimination unit;

[0037] The first end and the second end of the ninth switch module serve as the first end and the third end of the offset elimination unit respectively;

[0038] The first end and the second end of the tenth switch module serve as the second end and the fourth end of the offset elimination unit, respectively.

[0039] In a possible implementation, the sense amplifier further includes: a first signal switch unit and a second signal switch unit;

[0040] The control end of the first signal switch unit and the control end of the second signal switch unit are both used to be electrically connected to the first signal control line;

[0041] The first end and the second end of the first signal switch unit are respectively used to be electrically connected to the bit line and the first signal line;

[0042] The first end and the second end of the second signal switch unit are used to be electrically connected to the reference bit line and the second signal line respectively.

[0043] In a possible implementation, the sense amplifier further includes: a third signal switch unit and a fourth signal switch unit;

[0044] The control end of the third signal switch unit and the control end of the fourth signal switch unit are both used to be electrically connected to the first signal control line;

[0045] The first end and the second end of the third signal switch unit are respectively used to be electrically connected to the first output data line and the second signal line;

[0046] The first end and the second end of the fourth signal switch unit are used to be electrically connected to the second output data line and the first signal line, respectively.

[0047] In a second aspect, an embodiment of the present application provides a memory array structure, comprising: a plurality of bit lines, a plurality of word lines, a plurality of memory cells distributed in a matrix, and a plurality of sense amplifiers according to the first aspect;

[0048] One bit line is electrically connected to one column of memory cells;

[0049] One word line is electrically connected to one row of memory cells;

[0050] Each bit line is electrically connected to the second end of an amplifying unit of a corresponding sense amplifier.

[0051] In a third aspect, an embodiment of the present application provides a dynamic random access memory, comprising: a plurality of storage array structures as described in the second aspect.

[0052] In a fourth aspect, an embodiment of the present application provides an electronic device comprising: a plurality of storage array structures as in the second aspect or a plurality of dynamic random access memories as in the third aspect.

[0053] In a fifth aspect, an embodiment of the present application provides a data processing method, including:

[0054] In a pre-sensing stage, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal. The amplifying unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, outputs a first data signal and a second data signal to the first output data line and the second output data line, respectively, and the first latch unit performs a first data latch on the first data signal and the second data signal; one of the first data signal and the second data signal is the same as the first voltage, and the other is the same as the second voltage.

[0055] In the data latching stage, the third voltage terminal is loaded with the second voltage, and the second latch unit performs a second data latching on the first data signal and the second data signal;

[0056] In the data write-back phase, the second data signal of the second output data line is controlled to be written back to the memory cell through the bit line.

[0057] In one possible implementation, controlling the second data signal of the second output data line to be written back to the memory cell through the bit line includes:

[0058] The first and third terminals, and the fourth and second terminals of the isolation unit of the sense amplifier are controlled to be conductive, so as to write the second data signal of the second output data line back to the memory cell through the bit line.

[0059] In a possible implementation, before the pre-sensing stage, the following steps are further included:

[0060] In the pre-charging stage, the first and third terminals of the isolation unit are controlled to be conductive, and the fourth and second terminals are controlled to be conductive, and the first and third terminals of the offset cancellation unit of the sense amplifier are controlled to be conductive, and the second and fourth terminals are controlled to be conductive, so that the first output data line, the second output data line, the bit line, and the reference bit line are all pre-charged to a predetermined voltage;

[0061] In the offset elimination phase, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal, the first terminal and the third terminal of the isolation unit are disconnected, and the fourth terminal and the second terminal are disconnected, so as to eliminate the offset of the threshold voltage of the switching device in the amplification unit and the first latch unit;

[0062] In the charge sharing stage, the first voltage terminal is controlled to load the third voltage and the second voltage terminal is controlled to load the fourth voltage. The sense amplifier does not work, and the predetermined voltage of the bit line is charge-shared with the capacitor of the memory cell.

[0063] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0064] The sensing amplifier of the embodiment of the present application includes a first latch unit and a second latch unit, which can latch data twice. In the pre-sensing stage, the amplification unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, and outputs the first data signal and the second data signal to the first output data line and the second output data line respectively. The first latch unit can perform the first data signal and the second data signal for the first time. However, due to the coupling interference of the bit line BL to the bit line BL, it is still easy to cause data reading errors. Therefore, the embodiment of the present application adds a second latch unit on the basis of the first latch unit, and can add a data latch stage after the pre-sensing stage. The second latch unit is used to perform the second data latch on the first data signal and the second data signal, thereby increasing the ability to resist the coupling noise between adjacent bit lines and improving the accuracy of data reading.

[0065] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0067] Figure 1 A schematic structural diagram of a first sensing amplifier provided in an embodiment of the present application;

[0068] Figure 2 A schematic structural diagram of a second sensing amplifier provided in an embodiment of the present application;

[0069] Figure 3 A schematic structural diagram of a third sensing amplifier provided in an embodiment of the present application;

[0070] Figure 4 A schematic structural diagram of a fourth sensing amplifier provided in an embodiment of the present application;

[0071] Figure 5 A schematic structural diagram of a fifth sensing amplifier provided in an embodiment of the present application;

[0072] Figure 6 The embodiment of this application provides Figure 4 A timing diagram of a data processing method of the sense amplifier shown;

[0073] Figure 7 The embodiment of this application provides Figure 4 A timing diagram of another data processing method of the sense amplifier shown;

[0074] Figure 8A flowchart of a data processing method provided in an embodiment of the present application;

[0075] Figure 9 A flowchart of another data processing method provided in an embodiment of the present application;

[0076] Figure 10 A schematic diagram of the circuit principle of the pre-charging stage of the sense amplifier provided in an embodiment of the present application;

[0077] Figure 11 A schematic diagram of the circuit principle of the offset cancellation stage of the sense amplifier provided in an embodiment of the present application;

[0078] Figure 12 A schematic diagram of the circuit principle of the charge sharing stage of the sense amplifier provided in an embodiment of the present application;

[0079] Figure 13 A schematic diagram of the circuit principle of the pre-sensing stage of the sensing amplifier provided in an embodiment of the present application;

[0080] Figure 14 A schematic diagram of the circuit principle of the data latching stage of the sense amplifier provided in an embodiment of the present application;

[0081] Figure 15 A schematic diagram of the circuit principle of the data write-back stage of the sense amplifier provided in an embodiment of the present application.

[0082] 10-sensing amplifier;

[0083] 110 - amplification unit, 111 - first switch module, 112 - second switch module;

[0084] 120 - first latch unit, 121 - third switch module, 122 - fourth switch module;

[0085] 130 - second latch unit, 131 - fifth switch module, 132 - sixth switch module;

[0086] 140 - isolation unit, 141 - seventh switch module, 142 - eighth switch module;

[0087] 150 - offset elimination unit, 151 - ninth switch module, 152 - tenth switch module;

[0088] 160-first signal switch unit, 170-second signal switch unit;

[0089] 180-third signal switch unit, 190-fourth signal switch unit;

[0090] BL-bit line, BLB-reference bit line, SABL-first output data line, SABLB-second output data line. DETAILED DESCRIPTION

[0091] The present application is described in detail below. Examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0092] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0093] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0094] Research has found that adjacent bit lines (BL) in 3D memory arrays are directly opposite each other and relatively close together. This leads to strong coupling interference between the bit lines, which can cause read errors. This is primarily due to the fact that during the sensing process, if the data in the adjacent layers BLn-1 and BLn+1 above and below BLn changes in the opposite direction to BLn, the strong coupling interference between the BLs can cause BLn to be pulled off-center by BLn-1 and BLn+1, ultimately leading to read errors.

[0095] The sensing amplifier, data processing method, storage array structure and memory provided in this application are intended to solve the above technical problems in the prior art.

[0096] The following describes in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments.

[0097] The present application embodiment provides a sense amplifier, see Figure 1 As shown, the sense amplifier 10 includes a first latch unit 120 , an amplifying unit 110 and a second latch unit 130 .

[0098] The first end of the first latch unit 120 , the first end of the amplifying unit 110 , and the first end of the second latch unit 130 are respectively used to be electrically connected to the first voltage end, the second voltage end, and the third voltage end.

[0099] See also Figure 1 As shown, the voltage signal loaded on the first voltage terminal is PCS, the voltage signal loaded on the second voltage terminal is NCS1, and the voltage signal loaded on the third voltage terminal is NCS2. The first, second, and third voltage terminals are all power supply terminals that provide power signals. A switching device can be set between the first voltage terminal and the first terminal of the first latch unit 120. When the switching device is turned on, the first voltage terminal is turned on. Similarly, a switching device can be set between the first terminal and the second voltage terminal of the amplification unit 110. When the switching device is turned on, the second voltage terminal is turned on; and a switching device can be set between the first terminal and the third voltage terminal of the second latch unit 130. When the switching device is turned on, the third voltage terminal is turned on.

[0100] The second and third terminals of the amplifier unit 110 are electrically connected to the bit line BL and the reference bit line BLB, respectively. Specifically, the bit line BL is electrically connected to the memory cells of the memory array structure, thereby sharing charge with the memory cells and writing data into the memory cells.

[0101] The second end of the first latch unit 120 is electrically connected to the second end of the second latch unit 130 and the fourth end of the amplifying unit 110 through the first output data line SABL, and the third end of the first latch unit 120 is electrically connected to the third end of the second latch unit 130 and the fifth end of the amplifying unit 110 through the second output data line SABLB.

[0102] The sense amplifier 10 is configured such that, in a pre-sensing stage, a first voltage is loaded to the first voltage terminal and a second voltage is loaded to the second voltage terminal, the amplification unit 110 amplifies the output voltage of the bit line BL and the output voltage of the reference bit line BLB, and outputs a first data signal and a second data signal to the first output data line SABL and the second output data line SABLB, respectively, and the first latch unit 120 performs a first data latch on the first data signal and the second data signal; one of the first data signal and the second data signal is the same as the first voltage, and the other is the same as the second voltage; in a data latching stage, the second voltage is loaded to the third voltage terminal, and the second latch unit 130 performs a second data latch on the first data signal and the second data signal.

[0103] Specifically, in the pre-sensing phase, the first voltage terminal is loaded with a first voltage, and the second voltage terminal is loaded with a second voltage. That is, the first and second voltage terminals are powered on, the sense amplifier 10 is powered on and in an operating state, and the amplification unit 110 and the first latch unit 120 begin to operate. In the data latching phase, the first voltage terminal is loaded with the first voltage, and the third voltage terminal is loaded with the second voltage. That is, the first and third voltage terminals are powered on, the sense amplifier 10 continues to be in an operating state, and the second latch unit 130 begins to operate.

[0104] As an example, the first voltage may be a high level, and the second voltage may be a low level, for example, the first voltage is 1V, and the second voltage is 0V, or vice versa.

[0105] Optionally, one of the first data signal and the second data signal is at a high level and the other is at a low level. For example, the first data signal is at a low level and the second data signal is at a high level. The first latch unit 120 and the second latch unit 130 latch data. The first data signal is 0 and the second data signal is 1.

[0106] The sensing amplifier 10 of the embodiment of the present application includes a first latch unit 120 and a second latch unit 130, which can latch data twice. In the pre-sensing stage, the amplification unit 110 amplifies the output voltage of the bit line BL and the output voltage of the reference bit line BLB, and outputs the first data signal and the second data signal to the first output data line SABL and the second output data line SABLB respectively. The first latch unit 120 can perform a first data latch on the first data signal and the second data signal. However, due to BL-to-BL coupling interference, data reading errors are still prone to occur. Therefore, the embodiment of the present application adds a second latch unit 130 on the basis of the first latch unit 120, and a data latch stage can be added after the pre-sensing stage. The second latch unit 130 is used to perform a second data latch on the first data signal and the second data signal, thereby increasing the ability to resist BL coupling noise and improving the accuracy of data reading.

[0107] In some embodiments, see Figure 2 As shown, the sense amplifier 10 further includes an isolation unit 140. The control terminal, the first terminal, and the second terminal of the isolation unit 140 are respectively electrically connected to the isolation signal line, the bit line BL, and the reference bit line BLB. The third terminal and the fourth terminal of the isolation unit 140 are respectively electrically connected to the second output data line SABLB and the first output data line SABL.

[0108] The isolation unit 140 is configured such that during the data write-back phase, the first and third ends of the isolation unit 140 are turned on, and the fourth and second ends are turned on, so as to write the second data signal of the second output data line SABLB back to the storage unit through the bit line BL.

[0109] Optionally, the control signal loaded on the isolation signal line is ISO, and the first and third terminals of the isolation unit 140 are controlled to be on and off, and the fourth and second terminals are controlled to be on and off by controlling the voltage of ISO.

[0110] Optionally, the isolation unit 140 is further configured to control the first and third ends of the isolation unit 140 to be turned on, and the fourth and second ends to be turned on, in the pre-charging stage, so as to pre-charge the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB to a predetermined voltage.

[0111] In some embodiments, see Figure 3 As shown, the sense amplifier 10 further includes an offset cancellation unit 150 .

[0112] The control end, the first end, and the second end of the offset cancellation unit 150 are respectively used to be electrically connected to the offset cancellation signal line, the bit line BL, and the reference bit line BLB. The third end and the fourth end of the offset cancellation unit 150 are respectively electrically connected to the first output data line SABL and the second output data line SABLB.

[0113] The offset cancellation unit 150 is configured such that, in an offset cancellation phase, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal, the first terminal and the third terminal of the offset cancellation unit 150 are turned on, and the second terminal and the fourth terminal are turned on, so as to cancel the offset of the threshold voltage of the switching devices in the amplification unit 110 and the first latch unit 120; the offset cancellation phase is located before the pre-sensing phase.

[0114] Optionally, the offset cancellation unit 150 is configured to, in the pre-charging stage, have the first and third terminals of the offset cancellation unit 150 turned on, and the second and fourth terminals turned on, so as to pre-charge the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB to a predetermined voltage.

[0115] Optionally, the control signal loaded on the offset cancellation signal line is OC, and the first and third terminals of the offset cancellation unit 150 are controlled to be turned on and off, and the second and fourth terminals are controlled to be turned on and off by controlling the voltage of OC.

[0116] Optionally, the sense amplifier 10 is further configured to control the first and third terminals, the fourth and second terminals of the isolation unit 140 to be conductive, and the first and third terminals, the second and fourth terminals of the offset cancellation unit 150 of the sense amplifier 10 to be conductive, during the pre-charging phase, so as to pre-charge the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB to a predetermined voltage.

[0117] Alternatively, the precharge voltage may be an external power supply voltage. A switch device may be provided in the sense amplifier 10 and electrically connected to the charging voltage terminal. By connecting to the charging voltage terminal during the precharge phase, the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB are all precharged to a predetermined voltage. The predetermined voltage may be 0.5V.

[0118] Optionally, the sense amplifier 10 is further configured to load a first voltage to the first voltage terminal and a second voltage to the second voltage terminal during an offset cancellation phase, disconnect the first terminal and the third terminal, and disconnect the fourth terminal and the second terminal of the isolation unit 140, so as to cancel the offset of the threshold voltage of the switching devices in the amplification unit 110 and the first latch unit 120.

[0119] Optionally, the sense amplifier 10 is further configured to control the first voltage terminal to load a third voltage and the second voltage terminal to load a fourth voltage during the charge sharing phase, so that the sense amplifier 10 does not operate and charge is shared between the predetermined voltage of the bit line BL and the capacitor of the memory cell.

[0120] Optionally, the third voltage and the fourth voltage are both intermediate levels and may be the same, and the intermediate level may be 0.5V.

[0121] As an example, each memory cell in the memory array structure can be composed of a 1T1C structure. By controlling the control signal WL of the wordline (WL), the bitline BL and the capacitor of the memory cell can be controlled to share charge. The load capacitor on the bitline BL and the storage capacitor of the memory cell undergo a charge exchange process, sharing the internally stored charge on the bitline BL. For example, after charge sharing, the bitline BL is no longer the predetermined voltage of 0.5v. If the memory cell stores 0v, the voltage of the bitline BL is less than 0.5v. If the memory cell stores 1v, the voltage of the bitline BL is higher than 0.5v.

[0122] In some embodiments, see Figure 4 and Figure 5 As shown, the amplifying unit 110 includes a first switch module 111 and a second switch module 112 .

[0123] The first end of the first switch module 111 and the first end of the second switch module 112 together serve as the first end of the amplifying unit 110. The control end of the first switch module 111 and the control end of the second switch module 112 respectively serve as the second end and the third end of the amplifying unit 110. The second end of the first switch module 111 and the second end of the second switch module 112 respectively serve as the fourth end and the fifth end of the amplifying unit 110.

[0124] Alternatively, see Figure 4 and Figure 5 As shown, the first switch module 111 includes a first switch device M1A, and the second switch module 112 includes a second switch device M1B. The gate of the first switch device M1A is the control end of the first switch module 111. Among the first and second ends of the first switch module 111, one end is the source of the first switch device M1A, and the other end is the drain of the first switch device M1A; the gate of the second switch device M1B is the control end of the second switch module 112. Among the first and second ends of the second switch module 112, one end is the source of the second switch device M1B, and the other end is the drain of the second switch device M1B. Specifically, the setting of the switch device is set according to actual circuit requirements.

[0125] In some embodiments, see Figure 4 and Figure 5 As shown, the first latch unit 120 includes a third switch module 121 and a fourth switch module 122 .

[0126] The first end of the third switch module 121 and the first end of the fourth switch module 122 together serve as the first end of the first latch unit 120. The second end of the third switch module 121 and the control end of the fourth switch module 122 together serve as the second end of the first latch unit 120. The control end of the third switch module 121 and the second end of the fourth switch module 122 together serve as the third end of the first latch unit 120.

[0127] Alternatively, see Figure 4 and Figure 5As shown, the third switch module 121 includes a third switch device M2A, and the fourth switch module 122 includes a fourth switch device M2B. The gate of the third switch device M2A is the control end of the third switch module 121. Among the first and second ends of the third switch module 121, one end is the source of the third switch device M2A, and the other end is the drain of the third switch device M2A; the gate of the fourth switch device M2B is the control end of the fourth switch module 122. Among the first and second ends of the fourth switch module 122, one end is the source of the fourth switch device M2B, and the other end is the drain of the fourth switch device M2B. Specifically, the setting of the switch device is set according to actual circuit requirements.

[0128] In some embodiments, see Figure 4 and Figure 5 As shown, the second latch unit 130 includes a fifth switch module 131 and a sixth switch module 132. The first end of the fifth switch module 131 and the first end of the sixth switch module 132 together serve as the first end of the second latch unit 130. The second end of the fifth switch module 131 and the control end of the sixth switch module 132 together serve as the second end of the second latch unit 130. The control end of the fifth switch module 131 and the second end of the sixth switch module 132 together serve as the third end of the second latch unit 130.

[0129] Alternatively, see Figure 4 and Figure 5 As shown, the fifth switch module 131 includes a fifth switch device M3A, and the sixth switch module 132 includes a sixth switch device M3B. The gate of the fifth switch device M3A is the control end of the fifth switch module 131. Among the first and second ends of the fifth switch module 131, one end is the source of the fifth switch device M3A, and the other end is the drain of the fifth switch device M3A; the gate of the sixth switch device M3B is the control end of the sixth switch module 132. Among the first and second ends of the sixth switch module 132, one end is the source of the sixth switch device M3B, and the other end is the drain of the sixth switch device M3B. Specifically, the setting of the switch device is set according to the actual circuit requirements.

[0130] In some embodiments, see Figure 4 and Figure 5 As shown, the isolation unit 140 includes a seventh switch module 141 and an eighth switch module 142 .

[0131] The control end of the seventh switch module 141 and the control end of the eighth switch module 142 jointly serve as the control end of the isolation unit 140. The first and second ends of the seventh switch module 141 serve as the first and third ends of the isolation unit 140, respectively. The first and second ends of the eighth switch module 142 serve as the second and fourth ends of the isolation unit 140, respectively.

[0132] Alternatively, see Figure 4 and Figure 5 As shown, the seventh switch module 141 includes a seventh switch device M7, and the eighth switch module 142 includes an eighth switch device M8. The gate of the seventh switch device M7 is the control end of the seventh switch module 141. Among the first and second ends of the seventh switch module 141, one end is the source of the seventh switch device M7, and the other end is the drain of the seventh switch device M7; the gate of the eighth switch device M8 is the control end of the eighth switch module 142. Among the first and second ends of the eighth switch module 142, one end is the source of the eighth switch device M8, and the other end is the drain of the eighth switch device M8. Specifically, the setting of the switch device is set according to actual circuit requirements.

[0133] In some embodiments, the offset cancellation unit 150 includes a ninth switch module 151 and a tenth switch module 152. The control terminal of the ninth switch module 151 and the control terminal of the tenth switch module 152 jointly serve as the control terminal of the offset cancellation unit 150. The first and second terminals of the ninth switch module 151 serve as the first and third terminals of the offset cancellation unit 150, respectively. The first and second terminals of the tenth switch module 152 serve as the second and fourth terminals of the offset cancellation unit 150, respectively.

[0134] Alternatively, see Figure 4 and Figure 5 As shown, the ninth switch module 151 includes a ninth switch device M9, and the tenth switch module 152 includes a tenth switch device M10. The gate of the ninth switch device M9 is the control end of the ninth switch module 151. Among the first and second ends of the ninth switch module 151, one end is the source of the ninth switch device M9, and the other end is the drain of the ninth switch device M9. The gate of the tenth switch device M10 is the control end of the tenth switch module 152. Among the first and second ends of the tenth switch module 152, one end is the source of the tenth switch device M10, and the other end is the drain of the tenth switch device M10. Specifically, the setting of the switch device is set according to the actual circuit requirements.

[0135] In some embodiments, see Figure 4 As shown, the sense amplifier 10 further includes: a first signal switch unit 160 and a second signal switch unit 170 .

[0136] The control terminals of the first signal switch unit 160 and the second signal switch unit 170 are both electrically connected to the first signal control line. The first terminal and the second terminal of the first signal switch unit 160 are electrically connected to the bit line BL and the first signal line, respectively. The first terminal and the second terminal of the second signal switch unit 170 are electrically connected to the reference bit line BLB and the second signal line, respectively.

[0137] In one embodiment, the control signal loaded on the first signal control line is CSL. By controlling the voltage of CSL, the first and second terminals of the first and second signal switch units 160 and 170 are turned on and off. LIO represents the first signal line, and LIOB represents the second signal line. The signal output by the first signal line is the inverse of the signal output by the second signal line.

[0138] Alternatively, see Figure 4 As shown, the first signal switch unit 160 includes an eleventh switch device M11, and the second signal switch unit 170 includes a twelfth switch device M12. The gate of the eleventh switch device M11 is the control end of the first signal switch unit 160. Among the first and second ends of the first signal switch unit 160, one end is the source of the eleventh switch device M11, and the other end is the drain of the eleventh switch device M11; the gate of the twelfth switch device M12 is the control end of the second signal switch unit 170. Among the first and second ends of the second signal switch unit 170, one end is the source of the twelfth switch device M12, and the other end is the drain of the twelfth switch device M12. Specifically, the setting of the switch device is set according to the actual circuit requirements.

[0139] In some embodiments, see Figure 5 As shown, the sense amplifier 10 further includes a third signal switching unit 180 and a fourth signal switching unit 190 .

[0140] The control terminals of the third signal switch unit 180 and the fourth signal switch unit 190 are both electrically connected to the first signal control line. The first and second terminals of the third signal switch unit 180 are electrically connected to the first output data line SABL and the second signal line, respectively. The first and second terminals of the fourth signal switch unit 190 are electrically connected to the second output data line SABLB and the first signal line, respectively.

[0141] Alternatively, see Figure 5 As shown, the third signal switch unit 180 includes a thirteenth switch device M13, and the fourth signal switch unit 190 includes a fourteenth switch device M14. The gate of the thirteenth switch device M13 is the control end of the third signal switch unit 180. Among the first and second ends of the third signal switch unit 180, one end is the source of the thirteenth switch device M13, and the other end is the drain of the thirteenth switch device M13; the gate of the fourteenth switch device M14 is the control end of the fourth signal switch unit 190. Among the first and second ends of the fourth signal switch unit 190, one end is the source of the fourteenth switch device M14, and the other end is the drain of the fourteenth switch device M14. Specifically, the setting of the switch device is set according to the actual circuit requirements.

[0142] In another embodiment, the control signal loaded on the first signal control line is CSL, and the first and second terminals of the third signal switch unit 180 and the fourth signal switch unit 190 are turned on and off by controlling the voltage of CSL. LIO represents the first signal line, and LIOB represents the second signal line. The signal output by the first signal line is the inverse of the signal output by the second signal line.

[0143] See also Figure 5 As shown, the output data of the sense amplifier 10 is output through the first output data line SABL and the second output data line SABLB, rather than from the bit line BL and the reference bit line BLB. The output lines LIO and LIOB are respectively connected to the first output data line SABL and the second output data line SABLB through switching devices, which is different from the original circuit in which LIO and LIOB are directly connected to the bit line BL and the reference bit line BLB through switching devices. The first latch unit 120, the amplifying unit 110, and the second latch unit 130 of the embodiment of the present application can be applied to Figure 4 and Figure 5 There are two data output forms in .

[0144] In some embodiments, if the switch device in the first latch unit 120 is a PMOS transistor, the switch device in the second latch unit 130 is an NMOS transistor.

[0145] If the switch device in the first latch unit 120 is an NMOS transistor, the switch device in the second latch unit 130 is a PMOS transistor.

[0146] As an example, see Figure 4 and Figure 5 As shown, the switching devices in the first latch unit 120 are PMOS transistors, and the switching devices in the second latch unit 130 are NMOS transistors. That is, the switching devices in the third switch module 121 and the fourth switch module 122 are PMOS transistors, and the switching devices in the fifth switch module 131 and the sixth switch module 132 are NMOS transistors. In other words, the third switch device M2A and the fourth switch device M2B are PMOS transistors, and the fifth switch device M3A and the sixth switch device M3B are NMOS transistors. In this embodiment, the switching devices in the first switch module 111 and the second switch module 112 are also NMOS transistors. That is, the first switch device M1A and the second switch device M1B are NMOS transistors.

[0147] In an embodiment of the present application, an N-type latch Latch can be added to a traditional OCSA (offset cancellation senseamplifier). On the one hand, the capacitance on the first output data line SABL and the second output data line SABLB is increased, and on the other hand, the pull-down drive capability in the direction of the NMOS transistor is enhanced. Both are beneficial to improving the ability to resist BL to BL coupling interference. At the same time, the N-type latch used in the second latch unit 130 of the embodiment of the present application and the P-type latch used in the first latch unit 120 are synthesized into a complete latch Latch, which has a stronger ability to resist various other interference noises. Data can be maintained even before the first switch device M1A and the second switch device M1B are powered off and the seventh switch device M7 and the eighth switch device M8 controlled by the ISO are turned on. In addition, the anti-BL interference capability of the embodiment of the present application can be further improved by controlling the level of the ISO turn-on voltage and the speed of the turn-on time.

[0148] Specifically, the N-type latch is powered on during the data latching phase, and is powered on only after the P-type latch in the pre-sensing phase has fully formed a judgment of 0 or 1, which can effectively prevent data reading errors.

[0149] As another example, consistent with the working principle of the present application, the switching device in the first latch unit 120 is an NMOS transistor, and the switching device in the second latch unit 130 is a PMOS transistor, that is, the first switching device M1A, the second switching device M1B, the fifth switching device M3A, and the sixth switching device M3B can be replaced with PMOS, the third switching device M2A and the fourth switching device M2B can be replaced with NMOS, and NCS2 can be replaced with PCS2 accordingly. The corresponding control voltage is adjusted accordingly, which is also applicable to the circuit structure of the sensing amplifier 10 in the embodiment of the present application.

[0150] It should be noted that the circuit connection method of the present application is only an example of the sensing amplifier 10 provided in the embodiment of the present application. Each switching device can select different transistors such as PMOS or NMOS as needed, and the electrical connection method of each component in the sensing amplifier provided in the embodiment of the present application can be adaptively adjusted. The adaptively adjusted electrical connection method still falls within the protection scope of the embodiment of the present application.

[0151] In some embodiments, during the data write-back phase, the control voltage loaded on the control end of the isolation unit 140 gradually increases to the turn-on voltage within a predetermined time and / or increases to the turn-on voltage through at least one intermediate voltage; the turn-on voltage is used to control the first and third ends of the isolation unit 140 to be conductive, and the fourth and second ends to be conductive.

[0152] Optionally, the sense amplifier 10 further includes a precharge unit. The precharge unit is electrically connected to the precharge voltage terminal, which is configured to output a predetermined voltage. The precharge unit is configured to output the predetermined voltage at the precharge voltage terminal to the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB during a precharge phase.

[0153] Optionally, in the pre-charging stage, a control voltage is loaded on the control end of the pre-charging unit so that the switching device of the pre-charging unit is turned on to pre-charge the first output data line SABL, the second output data line SABLB, the bit line BL and the reference bit line BLB to a predetermined voltage; the control voltage can be a low level or a high level. Specifically, the circuit structure of the pre-charging unit and the type of switching device can be adjusted accordingly according to the actual application circuit.

[0154] See also Figure 6 As shown, it shows the embodiment of the present application based on Figure 4 The timing diagram of a data processing method of the sense amplifier shown in FIG. PRE, OC, CS, PS, LAT, and RS correspond to the pre-charge phase, offset cancellation phase, charge sharing phase, pre-sensing phase, data latch phase, and data write-back phase, respectively. V pre The voltage at which PCS operates is VDD, and the voltage at which NCS1 and NCS2 operate is VSS. In the figure, WL is used to control the conduction of the switching device in the memory cell to electrically connect the capacitor of the memory cell to the bit line BL.

[0155] like Figure 6 As shown, the dotted line controls the ISO gate voltage rising slope, gradually increasing it within a predetermined time, thereby slowly raising the ISO voltage. This allows the second output data line SABLB and the first output data line SABL to be gradually connected to the bit line BL and the reference bit line BLB, respectively. This prevents the second output data line SABLB and the first output data line SABL from being deflected by coupling interference between the BLs. Similarly, other methods of gradually increasing the ISO voltage within a predetermined time are also applicable to the embodiments of the present application.

[0156] See also Figure 7 As shown, it shows the embodiment of the present application based on Figure 4 The timing diagram of another data processing method of the sense amplifier is shown. Figure 7 The timing diagram of the data processing method shown is similar to Figure 6 The principle of the timing diagram of the data processing method shown is the same, except that Figure 7ISO is pulled up in stages in a step-by-step manner to correspondingly raise the gate voltages of the transistors (i.e., the seventh switching device M7 and the eighth switching device M8) in the isolation unit 140. For example, after passing through an intermediate voltage VISO_L1, it increases to the turn-on voltage VISO_FULL, thereby controlling the seventh switching device M7 and the eighth switching device M8 to be turned on.

[0157] The embodiments of the present application extend the ISO voltage's on-time, controlling the ISO voltage's rising slope or increasing the ISO voltage in stages. This staged increase in the embodiments of the present application can be performed twice, several times, or a combination of controlling the gate voltage's rising slope and increasing the voltage in stages, or any other method for slowly increasing the ISO voltage. The ISO voltage control method of the embodiments of the present application allows for a gradual connection between the SABL / SABLB and the BL / BLB, preventing the SABL / SABLB from being deflected by coupling interference between the BLs. The embodiments of the present application enhance anti-interference capabilities simply by slowly increasing the ISO voltage.

[0158] In the embodiment of the present application, an N-type latch can be added to the existing OCSA to increase the ability to resist BL coupling noise. The gate voltage of the transistor in the isolation unit 140 can also be adjusted to further enhance the anti-noise capability, thereby improving the overall ability of the sense amplifier 10 to resist BL to BL coupling interference, improving the accuracy of data write back, and thereby improving the accuracy of data reading.

[0159] Based on the same inventive concept, an embodiment of the present application provides a memory array structure, comprising: a plurality of bit lines BL, a plurality of word lines, a plurality of memory cells distributed in a matrix, and a plurality of sense amplifiers 10 according to an embodiment of the present application;

[0160] One bit line BL is electrically connected to one column of memory cells;

[0161] One word line is electrically connected to one row of memory cells;

[0162] Each bit line BL is electrically connected to the second terminal of the amplifying unit 110 of the sense amplifier 10 .

[0163] Optionally, the memory cell includes a switching device and a capacitor, the control end of the switching device is electrically connected to the word line WL, and the switching device is turned on and off by controlling the output control signal WL of the word line to control the connection and disconnection of the memory cell and the bit line BL.

[0164] The storage array structure of the embodiment of the present application can latch data twice through the first latch unit 120 and the second latch unit 130. In the pre-sensing stage, the amplifier unit 110 amplifies the output voltage of the bit line BL and the output voltage of the reference bit line BLB, and outputs the first data signal and the second data signal to the first output data line SABL and the second output data line SABLB respectively. After that, the first latch unit 120 can perform the first data signal and the second data signal for the first time. However, due to the BL to BL coupling interference, it is still easy to cause data reading errors. Therefore, the embodiment of the present application adds the second latch unit 130 on the basis of the first latch unit 120, and can add a data latching stage after the pre-sensing stage. The second latch unit 130 is used to perform the second data latching of the first data signal and the second data signal, thereby increasing the ability to resist BL coupling noise and improving the accuracy of data reading.

[0165] Based on the same inventive concept, an embodiment of the present application provides a dynamic random access memory, including: multiple storage array structures as described in the embodiments of the present application.

[0166] Based on the same inventive concept, an embodiment of the present application provides an electronic device, comprising: a plurality of storage array structures as in the embodiment of the present application or a dynamic random access memory as in the embodiment of the present application.

[0167] The electronic device can be a mobile terminal such as a smart phone, a laptop computer, a digital broadcast loader, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle-mounted terminal (such as a vehicle-mounted navigation terminal), a wearable device, etc., as well as a fixed terminal such as a smart TV, a desktop computer, etc.

[0168] Based on the same inventive concept, the present application provides a data processing method, see Figure 8 As shown, the data processing method includes: steps S801 to S803.

[0169] S801, pre-sensing stage, the first voltage terminal is loaded with a first voltage and the second voltage terminal is loaded with a second voltage, the amplifying unit 110 amplifies the output voltage of the bit line BL and the output voltage of the reference bit line BLB, and outputs the first data signal and the second data signal to the first output data line SABL and the second output data line SABLB respectively, and the first latch unit 120 performs a first data latch on the first data signal and the second data signal; of the first data signal and the second data signal, one is the same as the first voltage, and the other is the same as the second voltage.

[0170] S802 , data latching stage: the third voltage terminal is loaded with a second voltage, and the second latch unit 130 performs a second data latching on the first data signal and the second data signal.

[0171] S803, data write-back stage, controlling the second data signal of the second output data line SABLB to be written back to the memory cell through the bit line BL.

[0172] In some embodiments, controlling the second data signal of the second output data line SABLB to be written back to the memory cell through the bit line BL includes:

[0173] The first and third terminals, and the fourth and second terminals of the isolation unit 140 of the sense amplifier 10 are controlled to be conductive, so as to write the second data signal of the second output data line SABLB back to the memory cell through the bit line BL.

[0174] In some embodiments, before the pre-induction stage, the method further includes:

[0175] In the pre-charging stage, the first and third terminals, the fourth and second terminals of the isolation unit 140 are connected, and the first and third terminals, and the second and fourth terminals of the offset cancellation unit 150 of the sense amplifier 10 are connected, so that the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB are all pre-charged to a predetermined voltage.

[0176] In the offset cancellation stage, the first voltage terminal is loaded with a first voltage and the second voltage terminal is loaded with a second voltage, and the first and third terminals, and the fourth and second terminals of the isolation unit 140 are disconnected, so as to cancel the offset of the threshold voltages of the switching devices in the amplification unit 110 and the first latch unit 120;

[0177] In the charge sharing stage, the first voltage terminal is controlled to load the third voltage and the second voltage terminal is controlled to load the fourth voltage, the sense amplifier 10 does not work, and the predetermined voltage of the bit line BL is charge-shared with the capacitor of the memory cell.

[0178] As an example, the present application also provides a data processing method, see Figure 9 As shown, the data processing method includes:

[0179] S901, pre-charging stage, controlling the first and third terminals, the fourth and second terminals of the isolation unit 140 to be conductive, the first and third terminals, and the second and fourth terminals of the offset cancellation unit 150 of the sense amplifier 10 to be conductive, and the first and third terminals to be conductive, and the second and fourth terminals to be conductive, and pre-charging the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB to a predetermined voltage.

[0180] S902, in the offset elimination stage, the first voltage terminal is loaded with a first voltage and the second voltage terminal is loaded with a second voltage, the first terminal and the third terminal of the isolation unit 140 are disconnected, and the fourth terminal and the second terminal are disconnected, so as to eliminate the offset of the threshold voltage of the switching device in the amplification unit 110 and the first latch unit 120.

[0181] S903 , charge sharing stage: controlling the first voltage terminal to load the third voltage and the second voltage terminal to load the fourth voltage; the sense amplifier 10 does not work; and charge sharing is performed between the predetermined voltage of the bit line BL and the capacitor of the memory cell.

[0182] S904, in the pre-sensing stage, the first voltage terminal is loaded with the first voltage and the second voltage terminal is loaded with the second voltage, the amplifying unit 110 amplifies the output voltage of the bit line BL and the output voltage of the reference bit line BLB, and outputs the first data signal and the second data signal to the first output data line SABL and the second output data line SABLB respectively, and the first latch unit 120 performs the first data latching on the first data signal and the second data signal; of the first data signal and the second data signal, one is the same as the first voltage, and the other is the same as the second voltage.

[0183] S905 , data latching stage: the third voltage terminal is loaded with a second voltage, and the second latch unit 130 performs a second data latching on the first data signal and the second data signal.

[0184] S906 , data write-back stage: controlling the first and third terminals, and the fourth and second terminals of the isolation unit 140 of the sense amplifier 10 to be conductive, so as to write the second data signal of the second output data line SABLB back to the memory cell through the bit line BL.

[0185] Optionally, controlling the first and third terminals, and the fourth and second terminals, of the isolation unit 140 of the sensing amplifier 10 to be turned on includes: controlling a control voltage loaded on the control terminal of the isolation unit 140 to gradually increase to a turn-on voltage within a predetermined time and / or to increase to the turn-on voltage through at least one intermediate voltage, and controlling the first and third terminals, and the fourth and second terminals of the isolation unit 140 to be turned on.

[0186] The data processing method of the present embodiment can also extend the ISO voltage on-time, control the ISO voltage rise slope, or increase the ISO voltage in a step-by-step manner. The step-by-step increase in the present embodiment can be performed twice, several times, or a combination of controlling the gate voltage rise slope and step-by-step increase, or any other method for slowly increasing the ISO voltage. The ISO voltage control method of the present embodiment can slowly connect the SABL / SABLB to the BL / BLB, preventing the SABL / SABLB from being deflected by coupling interference between the BLs. The present embodiment can enhance anti-interference capabilities simply by slowly increasing the ISO voltage.

[0187] Combine Figure 6 and Figure 7 Based on the shown Figure 4 The timing diagrams of the two data processing methods of the sense amplifier are shown. Figures 10 to 15 , which shows the Figure 4 The circuit principle diagram of the sense amplifier shown is the pre-charge stage, offset cancellation stage, charge sharing stage, pre-sensing stage, data latch stage, and data write-back stage. Figure 6 and Figure 7 PRE, OC, CS, PS, LAT, and RS correspond to the pre-charge stage, offset cancellation stage, charge sharing stage, pre-sensing stage, data latch stage, and data write-back stage, respectively.

[0188] See also Figure 10 As shown, the sense amplifier 10 is in the pre-charge stage, ISO and OC are high, and the voltages of PCS, NCS1 and NCS2 are all V pre , the seventh switching device M7, the eighth switching device M8, the ninth switching device M9, and the tenth switching device M10 are turned on, the sense amplifier 10 is in a non-working state, the amplifying unit 110, the first latch unit 120, and the second latch unit 130 are not powered on, the switching device of the pre-charging unit is turned on, and the first output data line SABL, the second output data line SABLB, the bit line BL, and the reference bit line BLB are all pre-charged to a predetermined voltage.

[0189] See also Figure 11As shown, the sense amplifier 10 is in the offset cancellation stage, ISO becomes a low level, OC remains at a high level, the switch device of the pre-charging unit is turned off, the pre-charging unit does not work, the seventh switch device M7 and the eighth switch device M8 are turned off, the ninth switch device M9 and the tenth switch device M10 remain on, the PCS voltage becomes VDD, the NCS1 voltage becomes VSS, the sense amplifier 10 is powered on, the amplifying unit 110 and the first latch unit 120 are powered on and work, and the offset of the threshold voltages of the first switch device M1A, the second switch device M1B, the third switch device M2A and the fourth switch device M2B is cancelled.

[0190] See also Figure 12 As shown, the sense amplifier 10 is in the charge sharing stage, OC becomes low, the ninth switch device M9 and the tenth switch device M10 are turned off, WL becomes high, and the voltages of PCS, NCS1 and NCS2 are all V pre , the predetermined voltage of the bit line BL shares charge with the capacitance of the memory cell.

[0191] See also Figure 13 As shown, the sense amplifier 10 is in the pre-sensing stage, the PCS voltage becomes VDD, the NCS1 voltage becomes VSS, the sense amplifier 10 is powered on, the amplifying unit 110 and the first latch unit 120 are powered on and work, the amplifying unit 110 amplifies the difference between the voltage signals of the bit line BL and the reference bit line BLB, and outputs the first data signal and the second data signal to the first output data line SABL and the second output data line SABLB respectively, and the first latch unit 120 performs a first data latch on the first data signal and the second data signal.

[0192] See also Figure 14 As shown, the sense amplifier 10 is in the data latching stage, the voltage NCS2 becomes VSS, and the second latch unit 130 starts to work and performs a second data latch on the first data signal and the second data signal.

[0193] See also Figure 15 As shown, the sense amplifier 10 is in the data write-back stage, ISO becomes high, the seventh switch device M7 and the eighth switch device M8 are both turned on, and the second data signal of the second output data line SABLB is written back to the memory cell through the bit line BL.

[0194] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0195] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0196] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0197] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0198] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0199] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0200] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A sense amplifier, characterized in that: include: a first latch unit, an amplifying unit, and a second latch unit; The first end of the first latch unit, the first end of the amplifying unit, and the first end of the second latch unit are respectively used to be electrically connected to the first voltage end, the second voltage end, and the third voltage end; The second end and the third end of the amplifying unit are respectively used to be electrically connected to the bit line and the reference bit line; The second end of the first latch unit is electrically connected to the second end of the second latch unit and the fourth end of the amplifying unit through the first output data line, and the third end of the first latch unit is electrically connected to the third end of the second latch unit and the fifth end of the amplifying unit through the second output data line; The sense amplifier is configured such that, in a pre-sensing phase, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal; the amplification unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, outputs a first data signal and a second data signal to the first output data line and the second output data line, respectively; the first latch unit performs a first data latch on the first data signal and the second data signal; one of the first data signal and the second data signal is the same as the first voltage, and the other is the same as the second voltage; in a data latching phase, a second voltage is applied to the third voltage terminal, and the second latch unit performs a second data latch on the first data signal and the second data signal.

2. The sense amplifier according to claim 1, wherein: Also includes: an isolation unit, wherein the control end, the first end, and the second end are respectively used to be electrically connected to the isolation signal line, the bit line, and the reference bit line, and the third end and the fourth end are respectively electrically connected to the second output data line and the first output data line; The isolation unit is configured such that during the data write-back phase, the first and third ends of the isolation unit are conductive, and the fourth and second ends of the isolation unit are conductive, so as to write the second data signal of the second output data line back to the storage unit through the bit line.

3. The sense amplifier according to claim 2, wherein: During the data write-back phase, the control voltage loaded on the control end of the isolation unit gradually increases to the turn-on voltage within a predetermined time and / or increases to the turn-on voltage through at least one intermediate voltage; the turn-on voltage is used to control the first and third ends of the isolation unit to be conductive, and the fourth and second ends to be conductive.

4. The sense amplifier according to claim 1, wherein: The switching device in the first latch unit is a PMOS transistor, and the switching device in the second latch unit is an NMOS transistor; or, The switch device in the first latch unit is an NMOS transistor, and the switch device in the second latch unit is a PMOS transistor.

5. The sense amplifier according to claim 1, wherein: Also includes: An offset cancellation unit, comprising a control end, a first end, and a second end, each of which is electrically connected to the offset cancellation signal line, the bit line, and the reference bit line, and a third end and a fourth end of which are electrically connected to the first output data line and the second output data line, respectively; The offset cancellation unit is configured such that, in an offset cancellation phase, the first voltage terminal and the second voltage terminal are connected via the first output data line and the second output data line, the first terminal and the third terminal of the offset cancellation unit are connected, and the second terminal and the fourth terminal of the offset cancellation unit are connected, thereby canceling the offset of the threshold voltage of the switching devices in the amplifying unit and the first latch unit; the offset cancellation phase is located before the pre-sensing phase.

6. The sense amplifier according to claim 1, wherein: The amplifying unit includes a first switch module and a second switch module; The first end of the first switch module and the first end of the second switch module serve together as the first end of the amplifying unit; The control end of the first switch module and the control end of the second switch module serve as the second end and the third end of the amplifying unit respectively; The second end of the first switch module and the second end of the second switch module serve as the fourth end and the fifth end of the amplifying unit, respectively.

7. The sense amplifier according to claim 1, wherein: The first latch unit includes a third switch module and a fourth switch module; The first end of the third switch module and the first end of the fourth switch module serve together as the first end of the first latch unit; The second end of the third switch module and the control end of the fourth switch module serve together as the second end of the first latch unit; The control end of the third switch module and the second end of the fourth switch module serve together as the third end of the first latch unit.

8. The sense amplifier according to claim 7, wherein: The second latch unit includes a fifth switch module and a sixth switch module; The first end of the fifth switch module and the first end of the sixth switch module serve together as the first end of the second latch unit; The second end of the fifth switch module and the control end of the sixth switch module serve together as the second end of the second latch unit; The control end of the fifth switch module and the second end of the sixth switch module serve together as the third end of the second latch unit.

9. The sense amplifier according to claim 2, wherein: The isolation unit includes a seventh switch module and an eighth switch module; The control end of the seventh switch module and the control end of the eighth switch module serve together as the control end of the isolation unit; The first end and the second end of the seventh switch module serve as the first end and the third end of the isolation unit respectively; The first end and the second end of the eighth switch module serve as the second end and the fourth end of the isolation unit, respectively.

10. The sense amplifier according to claim 5, wherein: The offset elimination unit includes a ninth switch module and a tenth switch module; The control end of the ninth switch module and the control end of the tenth switch module serve together as the control end of the offset elimination unit; The first end and the second end of the ninth switch module serve as the first end and the third end of the offset elimination unit respectively; The first end and the second end of the tenth switch module serve as the second end and the fourth end of the offset elimination unit, respectively.

11. The sense amplifier according to claim 1, wherein: Also includes: a first signal switching unit and a second signal switching unit; The control end of the first signal switch unit and the control end of the second signal switch unit are both used to be electrically connected to the first signal control line; The first end and the second end of the first signal switch unit are respectively used to be electrically connected to the bit line and the first signal line; The first end and the second end of the second signal switch unit are used to be electrically connected to the reference bit line and the second signal line, respectively.

12. The sense amplifier according to claim 1, wherein: Also includes: a third signal switch unit and a fourth signal switch unit; The control end of the third signal switch unit and the control end of the fourth signal switch unit are both used to be electrically connected to the first signal control line; The first end and the second end of the third signal switch unit are respectively used to be electrically connected to the first output data line and the second signal line; The first end and the second end of the fourth signal switch unit are used to be electrically connected to the second output data line and the first signal line, respectively.

13. A storage array structure, characterized in that: include: A plurality of bit lines, a plurality of word lines, a plurality of memory cells distributed in a matrix, and a plurality of sense amplifiers according to any one of claims 1 to 12; One of the bit lines is electrically connected to a column of memory cells; One of the word lines is electrically connected to a row of memory cells; Each of the bit lines is electrically connected to a second end of an amplifying unit of the sense amplifier.

14. A dynamic random access memory, characterized in that: include: A plurality of memory array structures as claimed in claim 13.

15. An electronic device, characterized in that: include: A plurality of memory array structures according to claim 13 or a dynamic random access memory according to claim 14.

16. A data processing method, characterized in that: Applied to the storage array structure of claim 13, the method comprising: In a pre-sensing stage, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal. The amplification unit amplifies the output voltage of the bit line and the output voltage of the reference bit line, outputs a first data signal and a second data signal to the first output data line and the second output data line, respectively, and the first latch unit performs a first data latch on the first data signal and the second data signal. One of the first data signal and the second data signal is the same as the first voltage, and the other is the same as the second voltage. In the data latching stage, the third voltage terminal is loaded with a second voltage, and the second latch unit performs a second data latching on the first data signal and the second data signal; In the data write-back phase, the second data signal of the second output data line is controlled to be written back to the storage unit through the bit line.

17. The data processing method according to claim 16, characterized in that: The step of controlling the second data signal of the second output data line to be written back to the memory cell via the bit line comprises: The first and third terminals, and the fourth and second terminals of the isolation unit of the sense amplifier are controlled to be conductive, so as to write the second data signal of the second output data line back to the memory cell through the bit line.

18. The data processing method according to claim 17, characterized in that: Before the pre-induction stage, it also includes: In a precharging phase, the first and third terminals, the fourth and second terminals of the isolation unit are controlled to be conductive, the first and third terminals, and the second and fourth terminals of the offset cancellation unit of the sense amplifier are controlled to be conductive, and the first and third terminals, and the second and fourth terminals, of the offset cancellation unit of the sense amplifier are controlled to be conductive, and the first output data line, the second output data line, the bit line, and the reference bit line are all precharged to a predetermined voltage; In an offset cancellation stage, a first voltage is applied to the first voltage terminal and a second voltage is applied to the second voltage terminal, the first terminal and the third terminal of the isolation unit are disconnected, and the fourth terminal and the second terminal are disconnected, so as to cancel the offset of the threshold voltage of the switching device in the amplification unit and the first latch unit; In the charge sharing stage, the first voltage terminal is controlled to load a third voltage and the second voltage terminal is controlled to load a fourth voltage, the sense amplifier is not operated, and the predetermined voltage of the bit line is charge-shared with the capacitor of the memory cell.

Images