System and method for operating memory device

Abstract

The invention relates to a method and device for performing read operations in a memory. In one example, a method for operating a memory device includes performing a sensing operation on memory cells of the memory device based on at least one voltage or at least one development time. The memory cell is coupled to a word line. The method also includes identifying a read offset based on a result of the sensing operation. The read offset may include a read voltage selected from the at least one voltage, or a read development time selected from the at least one development time. The method also includes storing the read offset in the memory device for direct application in a read operation on the memory cell.

Description

Technical Field

[0001] The present description relates generally to the field of semiconductor technology, and more particularly, to systems and methods for operating memory devices. Background Art

[0002] As memory devices shrink to smaller die sizes, manufacturing costs decrease and storage density increases. In addition to scaling memory cells horizontally in a single layer, three-dimensional (3D) memory architectures can be used to vertically stack multiple layers of memory cells, which increases storage density per unit area.

[0003] Vertically stacked memory cells can form memory strings, and in each memory string, the channels of the memory cells are connected. Each memory cell can be addressed by a word line and a bit line. The data (i.e., logic state) of memory cells sharing the same word line can be read or programmed at the page level. However, when performing aggressive scaling, reliability (e.g., threshold voltage (V th )Distribution drift) may be a concern for memory devices. Summary of the Invention

[0004] The present disclosure relates to methods for operating a single memory device, multiple memory devices, and a memory system. In one example, a method for operating a memory device includes performing a sensing operation on a memory cell of the memory device based on at least one voltage or at least one development time. The memory cell is coupled to a word line. The method also includes identifying a read offset based on a result of the sensing operation. The read offset may include a read voltage selected from the at least one voltage or a read development time selected from the at least one development time. The method also includes storing the read offset in the memory device. The read offset may be directly applied to a read operation on the memory cell.

[0005] Although generally described as computer-implemented software implemented on a tangible medium for processing and converting corresponding data, some or all aspects may be computer-implemented methods, or further included in corresponding systems or other devices for performing the functions described. These and other aspects and implementation details of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, as well as from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 、 Figure 2 and Figure 3 A storage system having one or more memory devices according to some aspects of the present disclosure is shown.

[0007] Figure 4A schematic diagram of a memory device according to some aspects of the present disclosure is shown.

[0008] Figure 5 Shown are schematic illustrations of example threshold voltage distributions for a memory device according to aspects of the present disclosure.

[0009] Figure 6A An example schematic circuit diagram of a memory device according to some aspects of the present disclosure is shown.

[0010] Figure 6B An example schematic illustration of a page buffer of a memory device according to some aspects of the present disclosure is shown.

[0011] Figures 7A-7B An example page buffer of a memory device according to some aspects of the present disclosure is shown.

[0012] Figure 8 Example sense node voltages are shown for various sense operations according to aspects of the present disclosure.

[0013] Figure 9 An example automatic valley detection (AVD) method according to some aspects of the present disclosure is shown.

[0014] Figure 10 An example data structure storing read offsets according to some aspects of the present disclosure is shown.

[0015] Figure 11 An example data structure provided by a user to a memory device is shown in accordance with some aspects of the present disclosure.

[0016] Figure 12 An example flow chart illustrating applying a read offset in a read operation according to aspects of the present disclosure is shown.

[0017] Figure 13 An example flow chart for operating a memory device according to some aspects of the present disclosure is shown.

[0018] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0019] In high-density memory devices such as NAND memory, the threshold voltage (V th ) distribution drift may be affected by many factors such as charge loss in programmed cells, noise, long service time, etc. th After the distribution drifts, the predefined read level can no longer track V th distribution, which may cause read failures. Therefore, it is necessary to track V thDistribute and adjust read levels to improve NAND memory reliability.

[0020] In some embodiments, automated valley detection (AVD) can be used to track V by performing a sensing operation on the memory cell. th The sensing operation may generate a read offset including a read voltage or a read development time. The read offset may represent a V th Distributed in V th The present disclosure provides techniques for performing a sensing operation to obtain a read offset and performing a read operation based on the obtained read offset. In some embodiments, the read offset obtained from the sensing operation can be stored in an SRAM of a memory device. This allows the memory device to directly apply the read offset in the SRAM to subsequent read operations, which can improve the efficiency and feasibility of the memory device.

[0021] Figure 1 A block diagram of an electronic device having a storage system 10 according to some aspects of the present disclosure is shown. In some embodiments, the electronic device can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system 10 (e.g., a NAND storage system) can include a memory controller 20 and one or more memory devices 25-1, 25-2, 25-3, ..., 25-n. Each memory device 25 can be a NAND memory device. The storage system 10 can communicate with a host 15 through the memory controller 20. The memory controller 20 can manage the one or more memory devices 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n.

[0022] In some embodiments, host 15 (e.g., a host computer) may include a processor of an electronic device, such as a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). Host 15 may send data to be stored in storage system 10 and retrieve data from storage system 10.

[0023] In some embodiments, the memory controller 20 can be configured to perform various tasks, including processing I / O requests received from the host 15, ensuring data integrity and efficient storage, and managing the memory devices 25. To perform these tasks, the memory controller 20 can include one or more processors 22 (e.g., microcontroller units, CPUs) to run firmware 21. For example, the memory controller 20 can run firmware 21 to map logical addresses (e.g., addresses used by the host to associate with host data) to physical addresses in the memory devices 25 (e.g., the actual locations where the data is stored). The memory controller 20 can also run firmware 21 to manage defective memory blocks in the memory devices 25. For example, the firmware 21 can remap logical addresses to different physical addresses (i.e., move data from a defective memory block to another memory block). The memory controller 20 can also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can perform error recovery via an error correction code (ECC) engine 29. The ECC engine 29 can detect and correct raw bit errors that occur within each memory device 25.

[0024] In some embodiments, the memory controller 20 communicates with each memory device 25 through a memory channel 30 via a data bus. The memory controller 20 can select one of the memory devices 25 according to a device enable signal.

[0025] In some embodiments, Figure 1 Each memory device 25 in may include one or more memory dies 100 , where the memory dies may be NAND memory dies.

[0026] In some embodiments, the memory controller 20 and the one or more memory devices 25 can be integrated into various types of storage packages. For example, they can be included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. In this way, the storage system 10 can be implemented and incorporated into different types of electronic products. Figure 2 In the example shown, the storage controller 20 and the single memory device 25 may be integrated into a memory card 26. The memory card 26 may include a PC card (i.e., a PCMCIA card, where PCMCIA is the abbreviation of the Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (including SD, miniSD, microSD, SDHC, etc.), a UFS, etc. The memory card 26 may also include a memory card that connects the memory card 26 to a host (e.g., Figure 1 The host 15) is coupled to the memory card connector 24. Figure 3 In another example shown, the memory controller 20 and the plurality of memory devices 25 may be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a computer that interfaces the SSD 27 with a host (e.g., Figure 1 The SSD connector 28 is coupled to the host 15).

[0027] Figure 4 A schematic diagram of a memory device 25 according to some aspects of the present disclosure is shown. In some embodiments, the memory device 25 may include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 may include multiple memory strings 212. Each memory string 212 may include multiple memory cells 340. Memory cells 340 in different memory strings may share the same word line 333. The memory strings 212 may include at least one field-effect transistor (e.g., MOSFET) at each end, controlled by a lower select gate ("LSG") 332 and a top select gate ("TSG") 334, respectively. The lower select gate ("LSG") may also be referred to as a bottom select gate ("BSG"). The drain terminal of the TSG 334 may be connected to a bit line 341, and the source terminal of the LSG 332 may be connected to an array common source ("ACS") 430. The ACS 430 may be shared by the memory strings 212 in the entire memory block and is also referred to as a common source line.

[0028] In some embodiments, the memory device 25 may include peripheral circuits, which may include a number of digital, analog, and / or mixed-signal circuits to support the functions of the memory block 103. For example, the peripheral circuits may include a page buffer 52, a row decoder 40 (i.e., a word line driver), a column decoder 50 (i.e., a bit line driver), a voltage generator 65, an input / output buffer 55, a control logic 70, a register 75, and an SRAM 77. The control logic 70 may include one or more control circuits. These control circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to one of ordinary skill in the art.

[0029] In some embodiments, the memory block 103 can be coupled to the row decoder / word line driver 40 via a word line ("WL") 333. The memory block 103 can be coupled to the page buffer 52 via a bit line ("BL") 341. The row decoder / word line driver 40 can be configured to select or deselect one of the memory blocks 103 of the memory device 25 in response to an X-path control signal provided by the control logic 70. The row decoder / word line driver 40 can transmit the voltage generated by the voltage generator 65 to one or more selected word lines according to the X-path control signal. For example, during a read or program operation, based on the X-path control signal, the row decoder / word line driver 40 can select a read voltage V read Or programming voltage V pgm is transmitted to the selected word line and passes the voltage V pgm transferred to the unselected word lines.

[0030] In some embodiments, the column decoder / bit line driver 50 can be configured to select or deselect one or more memory strings 212 in response to a Y path control signal from the control logic 70. For example, based on the Y path control signal, the column decoder / bit line driver 50 can select or deselect the inhibit voltage V inhibit In some embodiments, to increase the efficiency of the write operation, the column decoder / bit line driver 50 can set the bias voltage V to 0 based on the Y path control signal from the control logic 70. bias is transferred to the selected bit line. The page buffer 52 can be configured to read data from the memory block 103 and program (write) data to the memory block 103 according to the Y path control signal. In another example, the page buffer 52 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell. In yet another example, during a read operation, the page buffer 52 can sense the current flowing through the bit line 341, which reflects the logic state (i.e., data) of the memory cell coupled to the bit line, and can amplify the small signal to a measurable amplification rate for further processing.

[0031] In some embodiments, read operations and program (write) operations may be performed at a page level, and erase operations may be performed at a block level.

[0032] In some embodiments, the input / output buffer 55 can transfer I / O data from or to the page buffer 52, and transfer addresses (ADDR) or commands (CMD) to the control logic 70. In some embodiments, the input / output buffer 55 can serve as a communication interface between the memory device 25 and the memory controller (e.g., Figure 1 The interface between the memory controller 20).

[0033] The control logic 70 can control the operation of peripheral circuits. In some embodiments, the control logic 70 can control the page buffer 52 and the row decoder / word line driver 40 in response to commands transmitted by the input / output buffer 55. For example, during a program or read operation, the control logic 70 can control the row decoder / word line driver 40 and the page buffer 52 to program data into a selected memory cell or read data from a selected memory cell. The control logic can generate an X-path control signal including a row address X-ADDR and a Y-path control signal including a column address Y-ADDR. The combination of the row address X-ADDR and the column address Y-ADDR can be used to locate a selected memory cell in the memory block 103.

[0034] In some implementations, registers 75 may be coupled to control logic 70. Registers 75 may include status registers, command registers, feature registers, and address registers for storing status information, command operation codes (OP codes), configuration features, and command addresses.

[0035] In some embodiments, SRAM 77 can be coupled to control logic 70. For example, SRAM 77 can be used as a cache to store data and instructions frequently accessed by control logic 70. For another example, SRAM 77 can be used as a memory controller (e.g., Figure 1 A buffer between the memory controller 20 in FIG. 1 and the memory array including the memory block 103 is used to synchronize data transfer.

[0036] In some embodiments, the voltage generator 65 may generate voltages to be provided to the word lines and bit lines under the control of the control logic 70. The voltages generated by the voltage generator 65 may include a read voltage V read , programming voltage V pgm , through voltage V pass , prohibit voltage V inhibit , bit line bias voltage V bias wait.

[0037] It should be noted that Figure 1-4 The arrangement of electronic components in storage system 10 and memory device 25 is shown as a non-limiting example. In some embodiments, storage system 10 and memory device 25 can have other layouts and can include additional components. Figure 4 Some components of the illustrated memory device 25 (eg, control logic 70 , input / output buffer 55 ) may also be removed from the memory device 25 and provided as separate electrical components in the storage system 10 . Figure 4Some components of the illustrated memory device 25 (e.g., control logic 70, input-output buffers 55) may also be integrated with other components in the storage system 10. For example, portions of the control logic 70 may be combined with the memory controller 20, and vice versa.

[0038] Figure 5 Shown are schematic illustrations of example threshold voltage distributions for a memory device according to aspects of the present disclosure.

[0039] Return Reference Figure 4 In some embodiments, the memory block 103 may be formed based on floating gate technology. In other embodiments, the memory block 103 may be formed based on charge trapping technology. NAND flash memory based on charge trapping technology may provide high storage density and high intrinsic reliability. In NAND flash memory, the logic state (i.e., data) of the memory cell 340 in the memory block 103 may be determined by the threshold voltage V th The threshold voltage is determined by the number of charge carriers trapped in the storage film of the memory cell 340 .

[0040] In some embodiments, the NAND flash memory can be configured to operate in a single-level cell (SLC) mode. The memory cell 340 can be in an erased state ER or a programmed state P1. Initially, the memory cell 340 in the memory block 103 can be reset to the erased state ER as a logic "1" by removing trapped charge carriers in the memory film of the memory cell 340. The trapped charge carriers can be removed by achieving a negative voltage difference between the control gate of the memory cell 340 and the channel of the memory cell. In some embodiments, the erased state ER can be reset by setting the control gate of the memory cell 340 to ground and applying a high positive voltage (i.e., the erase voltage V erase ) is applied to ACS 430 to achieve a negative voltage difference. In the erased state ER (“state ER”), the threshold voltage V th Can be reset to the lowest value.

[0041] Memory cell 340 can be programmed from state ER to programmed state P1 ("state P1" or logic "0"). In some embodiments, during a programming operation, a positive voltage difference can be achieved between the control gate and the channel of memory cell 340. For example, the programming voltage V pgm A positive voltage pulse (e.g., between 10V and 20V) is applied to the control gate, and the corresponding bit line 341 connected to the memory cell 340 can be connected to ground. As a result, charge carriers can be injected into the storage film of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. thTherefore, memory cell 340 can be programmed to state P1.

[0042] In some embodiments, a sensing operation may be performed to measure or sense the threshold voltage V of the memory cell 340. th To determine the state of the memory cell 340 (eg, state ER or state P1). During the sensing operation, the reference voltage V R can be applied to the control gate of the selected memory cell, and the voltage V pass A current flowing through the memory cells can be measured at bit line 341 .

[0043] In some embodiments, to increase storage capacity, the NAND flash memory can also be configured to operate in a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, a quad-level cell (QLC) mode, or a combination of any of these modes. In SLC mode, a memory cell stores 1 bit of data and has two logic states, namely, logic {1 and 0}, i.e., states ER and P1. In MLC mode, a memory cell stores 2 bits of data and has four logic states, i.e., logic {11, 10, 01, and 00}, i.e., states ER, P1, P2, and P3. In TLC mode, a memory cell stores 3 bits of data and has eight logic states, i.e., logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., state ER and states P1-P7. In the QLC mode, the memory cell stores 4 bits of data and has 16 logic states, namely, logic {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000}, namely, state ER and states P1-P15. The memory controller 20 of the storage system 10 (see Figure 1 ) can convert data received from the host 15 into corresponding logic states of memory cells in the memory device 25, and vice versa. In some embodiments, memory cells of MLC, TLC, and QLC can be programmed to different program states by using an incremental step pulse programming (ISPP) scheme. The ISPP scheme may include multiple programming voltages V starting from a starting programming voltage V pgm, each subsequent programming voltage increases by a voltage increment ΔV. For example, the ISPP scheme can be used to program the QLC state from state ER having the lowest threshold voltage to state P15 having the highest threshold voltage. In some embodiments, each logical state of the memory cell can correspond to a threshold voltage V th A specific range, where the threshold voltage of each state V th A distribution can be represented by a probability density.

[0044] In some embodiments, after programming a QLC memory cell, states P1-P15 can be verified by using one or more predefined read reference voltages in a verification process. By applying one or more predefined read reference voltages to the control gate of a target memory cell, the threshold voltage V of the memory cell can be determined. th Falling into the range.

[0045] For example, the read reference voltage VR1 can be used to verify whether the memory cell is in state ER. Specifically, if the target memory cell is in state ER, the threshold voltage V th Should be lower than the reading reference voltage V R1 , and the target memory cell should be turned on to form a conductive path in the channel. If the target memory cell is in any of the states P1–P15, the threshold voltage V th Should be higher than the predefined read reference voltage V R1 , and the target memory cell should remain off. By measuring or sensing the current through the target memory cell at the corresponding bit line via the page buffer 52, the threshold voltage Vth or state of the target memory cell can be verified. For example, as shown in diagram 510, in order to determine the states P1-P15 of the QLC mode, a predefined read reference voltage V R2 、V R3 ,……,V R13 、V R14 and V R15 For example, in QLC mode, the threshold voltage V th Lower than V R2 (but higher than V used to verify the status ER R1 ); V of P2 th In V R2 and V R3 Between; ...; P13 V th In V R13 and V R14 Between; P14 V th In V R14 and V R15 Between; and P15 V thHigher than V R15 .

[0046] As shown in diagram 520, the threshold voltage V th The distribution can drift over time. In some cases, the threshold voltage distributions of memory cells in different programming states can drift in different ways. For example, in the case of lower programming states P1, P2, and P3, V th The distribution tends to drift slightly to the right, where V th In the case of higher programming states P12, P13, P14 and P15, V th The distribution tends to drift slightly to the left, where V th In some cases, at V th After the distribution drifts, the V th The distribution can be V with its adjacent state th The distributions intersect. The V of adjacent states th The intersection of the distributions can form valleys. For example, as shown in diagram 520, the V th After the distribution drift, the V th Distribution and state P15 V th The distributions intersect, thereby forming a valley 530 .

[0047] In V th After the distribution drifts, the predefined read level may not accurately track V th distribution, thereby causing read failures in the memory device. For example, as shown in diagram 520, due to V th Distribution drift, V of some memory cells in state P14 th can be reduced to below the predefined read reference voltage V R14 , and some memory cells in state P15 have V th can be reduced to below the predefined read reference voltage V R15 By including V R1 、V R2 ,……,V R13 、V R14 and V R15 The predefined read reference voltage is applied to the control gate of the target memory cell, the V th In V R14 With V R15 The results between may no longer reflect that the target memory cell is in state P14.

[0048] Figure 6AAn example schematic circuit diagram 600 of a memory device according to aspects of the present disclosure is shown. The example schematic circuit diagram 600 includes a memory block 604 and peripheral circuitry 602. In some embodiments, the example schematic circuit diagram 600 includes a plurality of memory strings 610, 620, and 630. Each of the memory strings 610, 620, and 630 has a plurality of memory cells 608. The memory strings 610 also include at least one field-effect transistor (e.g., a MOSFET) at each end, which are controlled by a lower select gate (LSG) 612 and a top select gate (TSG) 614, respectively. The memory cells 608 can be controlled by control gates, which can be connected to a word line 640 of the example schematic circuit diagram 600. The drain terminal of the TSG 614 can be connected to a bit line 618, and the source terminal of the LSG 612 can be connected to an ACS 616. The ACS 616 can be shared by the memory strings 610 in the entire memory block and is also referred to as a common source line. In some examples, memory string 620 may be associated with bit line 628 , and memory string 630 may be associated with bit line 638 .

[0049] In some embodiments, the memory block 604 can be a three-dimensional (3D) memory device, and the example schematic circuit diagram 600 can be a 3D memory array in which the memory cells 608 can be vertically stacked on top of each other. In some embodiments, the example schematic circuit diagram 600 can be formed based on charge trapping technology. The storage data or logic state (e.g., the threshold voltage V th ) depends on the amount of charge trapped in the storage layer of the memory cell 608. NAND flash memory based on charge trapping can provide high storage density and high intrinsic reliability.

[0050] In a NAND memory, the memory cells 608 can be in an erased state ER or a programmed state P1. Initially, all of the memory cells 608 in the example schematic circuit diagram 600 can be reset to the erased state ER, which is a logic "1," by implementing a negative voltage difference between the control gate and source terminals (e.g., ACS 616) of the memory cells, thereby removing all trapped electron charges in the storage layers of the memory cells 608. For example, the negative voltage difference can be induced by setting the control gate of the memory cell 608 to ground and applying a high positive voltage to the ACS 616. In the erased state ER ("State ER"), the threshold voltage V th may be reset to a lowest value and may be measured or sensed at bit line 618 .

[0051] During programming (i.e., writing), a programming voltage Vpgm (e.g., a positive voltage pulse between 10V and 20V) may be applied to the control gate, so that electronic charge (e.g., electrons) may be injected into the storage layer of the memory cell 608 and thereby increase the threshold voltage V th Thus, memory cell 608 is programmed to state P1. In some examples, memory cell 608 can be programmed to different states, such as P1-P7 in TLC mode, or P15 in QLC mode.

[0052] Figure 6B An example schematic diagram of a page buffer of a memory device according to some aspects of the present disclosure is shown. Figure 4 The page buffer 52 and Figure 1-6A Elements to describe Figure 6B However, not all of the components depicted may be used, and one or more embodiments may include additional components not shown in the figures. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims described herein. Additionally, different or fewer components may be provided.

[0053] like Figure 6B As shown, the page buffer 52 includes a first page buffer structure 658, a second page buffer structure 668, and a third page buffer structure 678. In some examples, the first page buffer structure 658 is formed by Figure 6A The bit lines 618 of the memory string 610 are connected. In some examples, the second page buffer structure 668 is connected to the memory string 610 by Figure 6A The bit lines 628 of the memory string 620 are connected. In some examples, the third page buffer structure 678 is connected to the memory string 620 by Figure 6A The bit line 638 is connected to the memory string 630.

[0054] like Figure 6B As shown, the first page buffer structure 658 may include a sense node (i.e., a sense-out node, or SO) 650, a precharge path 652, an SO discharge path 654, an L latch 682, and a sense latch 656. The second page buffer structure 668 includes a sense node (SO) 660, a precharge path 662, an SO discharge path 664, an L latch 684, and a sense latch 666. The third page buffer structure 678 includes a sense node (SO) 670, a precharge path 672, an SO discharge path 674, an L latch 686, and a sense latch 676. Each of the page buffer structures 658, 668, and 678 may also include a cache latch and one or more data latches (e.g., Figure 7B cache latch 710 and data latches 706 and 708).

[0055] As reference Figure 4 As described above, during a read operation, the row decoder / word line driver 40 may set the read voltage V read is transmitted to the selected word line and passes the voltage V pass The page buffer 52 can be configured to read data from and to the memory block 103 according to the Y path control signal from the control logic 70. During a read operation, the page buffer 52 can sense the current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification rate.

[0056] During a read operation, the first page buffer structure 658 can precharge the bit line 618 via the precharge path 652 by a control circuit (e.g., control logic 70), and can sense whether the selected memory cell is turned on or off at SO 650. The second page buffer structure 668 and the third page buffer structure 678 can precharge the bit lines connected thereto based on the same process as the precharge operation of the first page buffer structure 658.

[0057] During a read operation, the bit line 618 and the SO 650 may be precharged to a predetermined level during a precharge period. Current may be generated (e.g., in a channel) to flow into the first page buffer structure 658 via the bit line 618. During a development period with a development time, when a selected memory cell is in a first state (e.g., turned on), the charge charged at the SO 650 may be discharged to the ACS 616 via the bit line 618 and the channel of the cell string through the SO discharge path 654. In this case, because the current flowing into the first page buffer structure 658 is relatively large, the speed at which the voltage at the SO 650 drops may be relatively fast. On the other hand, during a development period with a development time, when the selected memory cell is in a second state (e.g., turned off), the charge charged at the SO 650 may have difficulty discharging to the ACS 616 via the bit line 618. Therefore, because the current flowing into the first page buffer structure 658 is relatively small, the speed at which the voltage at the SO 650 drops may be relatively slow.

[0058] During the latching period, the state of the SO 650 associated with the selected memory cell can be latched into the sense latch 656 as the first state of the selected memory cell (i.e., having a logic value of 1). Alternatively, the state of the SO 650 associated with the selected memory cell can be latched into the sense latch 656 as the second state of the selected memory cell (i.e., having a logic value of 0). In some examples, the threshold voltage V of the selected memory cell in the first state is th Greater than the read voltage V in the read operation read , and the threshold voltage V th is less than the read voltage V in the read operation read In some examples, if the memory cell is turned on when the read voltage level is applied, the memory cell may be determined to be in the first state, and if the memory cell is turned off when the read voltage level is applied, the memory cell may be determined to be in the second state.

[0059] In some examples, based on the same process as the operation of the above-mentioned first page buffer structure 658, the second page buffer structure 668 and the third page buffer structure 678 can respectively discharge the bit lines connected thereto, sense the state of the sensing node, and determine the state of the selected memory cell as the first state or the second state.

[0060] In some examples, during a read operation, the development time during the development period can be different for each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678. In some examples, the sense node, precharge path, SO discharge path, and sense latch associated with each of the first page buffer structure 658, the second page buffer structure 668, and the third page buffer structure 678 can be individually controlled.

[0061] Figures 7A-7B An example page buffer 700 of a memory device according to some aspects of the present disclosure is shown. The page buffer 700 may be Figure 4708. The page buffer 700 includes a sense latch 702, an L latch 704, data latches 706 and 708, and a cache latch 710. The sense latch 702 can be configured to store the result of a sense operation. The L latch 704 can be configured to support a fail bit count (FBC) function. In some embodiments, a multi-level cell (MLC) coupled to the same word line can have multiple pages. Each page can be read using multiple read levels. The data latches 706 and 708 can be configured to store the result of a sense operation for each of the multiple read levels of the page of the MLC. The cache latch 710 can be configured to cache the data before it is sent out. Figures 7A-7B As shown, page buffer 700 further includes transistors 712 and 714. Transistor 712 is coupled between the precharge circuit and a sense node 716. Transistor 714 is coupled between the sense node 716 and a corresponding bit line 718. Transistors 712 and 714 can be used to determine the length of a development time. The development time can be the delay between when transistor 712 turns off and when transistor 714 turns off.

[0062] Figure 8 8 shows example sensing node voltages for various sensing operations according to aspects of the present disclosure. Waveform 802 can be used to illustrate when the read voltage V rd1 (V rd1 >V th ) is applied to a memory cell (eg, a gate of a memory cell or a word line coupled to a memory cell), coupled to a gate having a threshold voltage V th Example of voltage levels at the sensing node (SO) of a memory cell (Example 1). As shown in waveform 802, before time 806, SO is precharged to a higher voltage level V charge SO begins to discharge at time 806 (ie, Figure 7A The transistor 712 of the transistor 712 is turned off), and thus the voltage at SO (also referred to as the SO voltage) begins to decrease. At time 808 (i.e., Figure 7A The SO voltage can be measured and compared with the trip voltage (V trip ) is compared. The result of this sensing operation (e.g., a logic value of 0 or 1) can be stored in a sense latch coupled to SO. For example, if the SO voltage at time 808 is lower than V trip , the result of this sensing operation is a logic value of 1. Otherwise, if the SO voltage at time 808 is higher than V trip , the result of this sensing operation is a logic value of 0. The time when the discharge starts (eg, time 806) and the SO voltage is measured and compared with V tripThe time duration (eg, development time 810) between the times being compared (eg, time 808) may be referred to as the development time. rd1 (V rd1 >V th ) and development time T d1 When the memory cell is turned on, the SO voltage drops rapidly. Therefore, the result of the sensing operation in Example 1 is a logic value of 1.

[0063] Waveform 804 shows that when another read voltage V rd2 (V rd2 <V th ) is applied to the memory cell. In Example 2, the memory cell is at V rd2 As a result, the SO voltage slowly decreases in waveform 804. If the same development time 810 is applied, the result of the sensing operation in Example 2 is a logic value of 0, which is different from the result in Example 1.

[0064] In another example (Example 3), the voltage V is read rd2 (V rd2 <V th ) is applied to the memory cell, but a different development time is applied (between time 806 and time 812, which may be referred to as development time 814). Figure 8 As shown, the development time 814 is longer than the development time 810. Therefore, the SO voltage keeps decreasing after time 808. When measured at time 812, the SO voltage is lower than V trip Therefore, the result of the sensing operation in Example 3 is a logic value of 1, which is the same as the result in Example 1.

[0065] Figure 8 shows that using a lower read voltage (e.g., V rd2 ) and a longer development time (eg, development time 814) may yield similar results to those obtained using a higher read voltage (eg, V rd1 ) and a shorter development time (e.g., development time 810) yields substantially the same results as another sensing operation (e.g., Example 1) using a fixed read voltage and a shorter development time. In other words, in both sensing and reading operations, fixing the read voltage and varying the development time can have the same effect as varying the read voltage and fixing the development time. Therefore, in some embodiments, sensing operations using different read voltages and the same development time can be replaced by sensing operations using the same read voltage but a different development time.

[0066] Figure 9An example automatic valley detection (AVD) method in accordance with some aspects of the present disclosure is shown. The curve 904 in illustration 902 includes two threshold voltage distributions for two adjacent states of memory cells in a memory device. The memory cells are coupled to the same word line. In some embodiments, the memory cells may belong to one or more memory pages. The AVD method may include a sensing operation to determine a valley on the curve 904 between the two threshold voltage distributions. The valley may be used as a read voltage in a read operation. In some embodiments, the AVD method includes determining a set of voltage ranges around the valley and determining the number of each of the set of voltage ranges. The number of each voltage range represents the number of memory cells whose threshold voltage falls within the voltage range. The valley is located in the voltage range having the smallest number. For example, as Figure 9 shown, four reference voltages V1, V2, V3, and V4 (V1 < V2 < V3 < V4) may be used to generate three voltage ranges (R1, R2, and R3) around the valley.

[0067] In some embodiments, as Figure 9 shown in illustration 906, the number of each voltage range may be determined by performing sensing operations based on different reference voltages and the same default development time. For example, the number of memory cells whose threshold voltage is higher than the reference voltage V i may be determined by applying Vi to the memory cells (e.g., the word line coupled to the memory cells), and then measuring the SO voltage on the sense node coupled to the memory cells through the corresponding bit line (referred to as S i , 1 ≤ i ≤ 4). These sensing operations may use the same default development time (e.g., the default development time T as Figure 9 shown) for different reference voltages. Then, the number of each voltage range (R i , 1 ≤ i ≤ 3), i.e., the number of memory cells (C i , 1 ≤ i ≤ 3) whose threshold voltage falls within each voltage range (R i ), may be determined based on the numbers N1, N2, N3, and N4. For example, C<​​​​​​​In the example of illustration 902, C2 is the minimum among C1, C2, and C3. Thus, the sensing operation can determine that the valley is in voltage range R2. In some embodiments, the reference voltage V2 (i.e., the lower limit of voltage range R2) can be determined as the valley of the threshold voltage distribution curve 904. The result of the sensing operation (also referred to as the read offset) can include the reference voltage V2, which can be stored in the memory device and can be used as a read voltage in subsequent read operations. In some embodiments, any other suitable value determined based on voltage range R2 (such as the upper limit V3, or the average of V2 and V3) can be determined as the valley of the threshold voltage distribution curve 904.

[0069] The AVD method shown in illustration 906 can be time-consuming because determining each of the quantities N1, N2, N3, and N4 may require applying different reference voltages to the word lines coupled to the memory cells. As described with respect to Figure 8 what is described, a sensing operation using the same reference voltage but different development times can have a similar effect to a sensing operation using different reference voltages and the same development time. Thus, in some embodiments, as shown in illustration 908, the AVD method can be performed based on sensing operations using the same reference voltage and different development times. The sensing operations using different development times can be performed in parallel, which can make the AVD method more efficient.

[0070] The AVD method shown in illustration 908 can use four development times T1, T2, T3, and T4 (T1 < T2 < T3 < T4). Each development time Ti (1 ≤ i ≤ 4) corresponds to a respective reference voltage (e.g., the reference voltage Vi described with respect to illustration 906) and can be determined based on the respective reference voltage (e.g., the reference voltage Vi described with respect to illustration 906). For example, T1 corresponds to V1, T2 corresponds to V2, T3 corresponds to V3, and T4 corresponds to V4. Referring back to illustration 902, in some embodiments, voltage ranges R1, R2, and R3 can have the same magnitude, and thus any two adjacent reference voltages among V i (1 ≤ i ≤ 4) have the same voltage difference. In other words, Vi = V1 + (i - 1) × ΔV (1 ≤ i ≤ 4), where ΔV is a predetermined voltage difference. In illustration 908, the following development times can be used for practical embodiments: Ti = T1 + (i - 1) × ΔT (1 ≤ i ≤ 4), where ΔT is a predetermined time difference, and Ti and ΔT can be determined based on the reference voltage Vi. For example, the sensing operation can use T1 = 0.5 μs, T2 = 0.6 μs, T3 = 0.7 μs, and T4 = 0.8 μs (ΔT = 0.1 μs).

[0071] In some embodiments, the same reference voltage Vref can be applied to the word lines coupled to the memory cells. The threshold voltage can be determined to be higher than the reference voltage V by applying Vref to the memory cells and measuring the SO voltage on the sense node coupled to the memory cells after the development time Ti. i (V i Corresponding to T i ) of the memory cells (called S i , 1≤i≤4). Each voltage range (R i , 1≤i≤3), that is, the threshold voltage falls within each voltage range (R i ) in the number of memory cells (C i , 1≤i≤3). For example, C i =S i -S i+1 (1≤i≤3). In a practical implementation, this comparison may be performed using a logical operation XOR based on the result stored in a sense latch coupled to the sense node.

[0072] In some embodiments, corresponding to the reference voltage V J Development time (e.g., T J ) can represent a valley. J Can be used as a read development time in a subsequent read operation. In the example of diagram 902, C2 is the minimum number of C1, C2, and C3. Therefore, the sensing operation determines that the valley is in the voltage range R2. In some embodiments, T2 corresponding to V2 (i.e., the lower limit of the voltage range R2) can represent the valley of the threshold voltage distribution curve 904. The result of the sensing operation (also referred to as a read offset) can include a development time T2, which can be stored in the memory device and can be later used as a read development time during a read operation of the memory cell. In some embodiments, any other suitable development time determined based on the voltage range R2 (such as, T3, or an average of T2 and T3) can be determined to represent a valley and stored as a read offset.

[0073] There is a development time T applied in the read operation after the sensing operation of the AVD method. J (ie, the read offset identified by the AVD method in diagram 908). For example, the memory device may develop the time T J Convert to the corresponding reference voltage V J , and the memory controller can V J Sent to the user (e.g., host computer). In a subsequent read operation, the user can apply V JAs the reading voltage and use the default development time. Alternatively, the user can set V J Convert back to T J , and use T J As the read development time, a predefined read reference voltage is applied simultaneously. For another example, the memory device may use T J is stored in the memory (e.g., SRAM) of the memory device. In a subsequent read operation, the memory device can directly apply T J As the read development time. In the read operation, T is directly applied J Potential inaccuracies caused by conversion between development time and corresponding reference voltage can be avoided.

[0074] In some embodiments, the AVD method may include dividing the memory cells coupled to the word line into a plurality of subgroups of equal size and performing some sensing operations on selected groups of memory cells. For example, a sensing operation is performed on a subgroup of memory cells (e.g., Group i) to determine whether the threshold voltage of the memory cells falls within a corresponding voltage range (e.g., R i ) within the memory cell number (e.g., C i ).

[0075] Figure 10 An example data structure 1000 including a read offset (i.e., the result of a sensing operation of an AVD) according to some aspects of the present disclosure is shown. In some embodiments, the data structure 1000 has four bytes and includes development times 1002, 1004, and 1006 for multiple read levels of a TLC page. For example, a TLC memory cell may have three pages per word line, including an upper page, a middle page, and a lower page. Level 2 (e.g., V rd2 ) provides development time 1002. It can be used for level 4 (e.g. V rd4 ) provides development time 1004. It can be used for level 6 (e.g. V rd6 ) provides a development time 1006. In another example, the level 3 of the upper page (eg, V rd3 ) provides development time 1002, which can be the level 7 of the upper page (for example, V rd7 ) provides the development time 1004, and the development time 1006 may be empty. The development times 1002, 1004, and 1006 each have a size of one byte.

[0076] It should be noted that Figure 10The data structure 1000 is shown for illustration only. For example, any suitable number of development times can be stored as read offsets in the data structure 1000. The development times in the data structure can be identified by sensing operations using different development times and the same reference voltage (e.g., Figure 9 For another example, the data structure may store any suitable number of reference voltages as read offsets. The reference voltages in the data structure may be identified by sensing operations using different reference voltages and the same development time (e.g., as shown in FIG. 908 ). Figure 9 AVD method shown in Figure 906).

[0077] In some embodiments, the data structure 1000 storing the read offset may further include a dynamic enable bit. Enabling the dynamic enable bit 1008 may indicate that a new development time (e.g., development times 1002, 1004, and 1006) will be applied during a read operation instead of the default development time. In some embodiments, the data structure 1000 may further include some reserved bits 1010.

[0078] In some embodiments, the data structure 1000 storing the read offset may be stored in a memory device. For example, the read offset may be stored in an SRAM of the memory device (e.g., Figure 4 In some embodiments, the data stored in the SRAM cannot be accessed by the user. To apply a read offset in a read operation, the memory device (e.g., via the control logic 70 of the memory device) can access the SRAM and obtain the read offset stored therein. For another example, the read offset can be stored in a memory array (e.g., a NAND memory array) of the memory device. To apply a read offset in a read operation, the memory device (e.g., via the control logic 70 of the memory device) can load the read offset from the memory array to the SRAM of the memory device.

[0079] Figure 11An example data structure 1100 for storing configuration data provided by a user to a memory device according to some aspects of the present disclosure is shown. The data structure 1100 storing the configuration data can indicate to the memory device whether to apply a read offset (e.g., a read voltage or read development time identified from a previous sensing operation) or a predefined read level (e.g., a predefined read reference voltage and a default development time) in a read operation. In some embodiments, the configuration data can be a collection feature for automatic valley detection (AVD) configuration and status. The data structure 1100 has four bytes and can include a predetermined bit 1102 for AVD_APPLY, a predetermined bit 1104 for AVD_RETRY, and a predetermined bit 1106 for AVD_ENABLE. For example, the predetermined bits 1102, 1104, and 1106 can occupy bits at P1[2], P1[1], and P1[0], respectively, in the data structure 1100.

[0080] In some embodiments, the predetermined bit 1106 for AVD_ENABLE indicates whether a sensing operation is performed to detect a threshold voltage V th When the bit 1106 for AVD_ENABLE is enabled (e.g., the value of the predetermined bit 1106 is 1), in response to receiving a read command from the memory controller to read data from one or more pages, the memory device may first perform a sensing operation on the page to obtain a read offset representing the valley of the threshold voltage distribution, and store the read offset in the memory device. In some embodiments, the memory device may then apply the read offset in a read operation (e.g., as Figure 10 ) to read data from the page. When the predetermined bit 1106 for AVD_ENABLE is disabled (for example, the value of the predetermined bit 1106 is 0), in response to receiving a read command from the memory controller to read data from one or more pages, the memory device can perform a normal read operation on the page without first performing a sense operation for the AVD.

[0081] In some embodiments, the predetermined bit 1104 for AVD_RETRY indicates whether to re-perform the sensing operation for the AVD. When the predetermined bit 1104 for AVD_RETRY is enabled (e.g., the value of the predetermined bit 11029 is 1), the memory device can perform a new round of sensing operations and store the read offset generated by the new round of sensing operations in the memory device.

[0082] In some embodiments, a predetermined bit 1102 for AVD_APPLY indicates whether a read offset stored in the memory device is applied in a read operation. When the predetermined bit 1102 for AVD_APPLY is enabled (e.g., the value of the predetermined bit 1102 is 1) and the predetermined bit 1106 for AVD_ENABLE is disabled, in response to receiving a read command from the memory controller to read data from one or more pages, the memory device may perform a read operation on the page based on the read offset stored in the memory device. The read offset stored in the memory device may be generated by a previous sensing operation for AVD. For example, if the read offset includes a read voltage, the memory device will use the read voltage as the read reference voltage V read And use the default development time as the development time T develop For another example, if the read offset includes a read development time, the memory device will use the read development time as T develop and use the predefined read reference voltage as V read When the predetermined bit 1102 for AVD_APPLY is disabled (e.g., the value of the predetermined bit 1101 is 0) and the predetermined bit 1106 for AVD_ENABLE is also disabled, in response to receiving a read command from the memory controller to read data from one or more pages, the memory device may perform a normal read operation on the pages using a predefined read reference voltage and a default development time.

[0083] In some embodiments, when both the predetermined bit 1102 for AVD_APPLY and the predetermined bit 1106 for AVD_ENABLE are enabled, the predetermined bit 1106 for AVD_ENABLE is pre-empted. That is, the memory device may first perform a sense operation for AVD to obtain a read offset, rather than first performing a read operation based on a read offset already stored in the memory device (e.g., from a previous sense operation).

[0084] In some embodiments, the data structure 1100 storing configuration data may be stored in a memory device. For example, after the memory device receives configuration data from a user via a memory controller, the memory device may store the configuration data in a feature register of the memory device (e.g., Figure 4 When the memory device receives a read command from the memory controller, the memory device may first check the configuration data in the feature register and determine the state of bits 1102, 1104, and 1106 (e.g., whether the value is 0 or 1). The memory device may then perform a sensing operation or a read operation based on the indication of bits 1102, 1104, and 1106.

[0085] It should be noted that Figure 11 The data structure 1100 shown in FIG. 1 is for illustration only. Instructions to the memory device for performing a sensing operation or applying a read offset in a read operation may be configured in other data forms or may use different bits of the data structure 1100 .

[0086] Figure 12 An example flow chart for applying a read offset in a read operation according to some aspects of the present disclosure is shown. The method 1200 may be implemented by a memory controller (e.g., Figure 1-3 ) and one or more memory devices appropriately programmed according to the present disclosure (e.g., in Figure 1-3 , the memory system of the memory device 25) is executed.

[0087] At operation 1202, a user (eg, a host computer) may set configuration data (eg, Figure 11 1100) and sends the configuration data to the memory device through the memory controller. In some embodiments, the user can enable AVD_ENABLE by setting the predetermined bit 1106 to 1 and can enable AVD_APPLY by setting the predetermined bit 1102 to 1. The configuration data received by the memory device can be stored in a register (e.g., a feature register) of the memory device.

[0088] At operation 1204, in response to receiving the read command, the memory device performs a sense operation for the AVD (e.g., a sense operation as shown in diagram 906 or 908) before performing the read operation. The read offset, i.e., the result of the sense operation representing the valley of the threshold voltage distribution, may be stored in the SRAM (e.g., Figure 4 In some implementations, the memory device then performs a read operation based on the read offset identified by the sensing operation.

[0089] At operation 1206, the user can reconfigure the configuration data (e.g., data structure 1100) to change some of its features. For example, the user can disable AVD_ENABLE by setting the predetermined bit 1106 to 0 while keeping AVD_APPLY enabled. The memory controller can send the configuration data to the memory device. The memory device can store the configuration data in a feature register of the memory device. In some embodiments, the configuration data received later overwrites the configuration data received earlier in the feature register.

[0090] In response to receiving the read command, the memory device performs a read operation using the read offset stored in the SRAM at operation 1208. In some embodiments, as long as the configuration data in the feature register remains unchanged, the memory device will perform all subsequent read operations based on the read offset stored in the SRAM of the memory device.

[0091] Figure 13 A method for operating a memory device (e.g., Figure 1-3 An example flow chart of a memory device 25).

[0092] In operation 1302, a user (e.g. Figure 1 Host 15 in the configuration data 1312 (e.g. Figure 11 1100 in the data structure). In some embodiments, a user can set the predetermined bit 1102 for AVD_APPLY, the predetermined bit 1104 for AVD_RETRY, and the predetermined bit 1106 for AVD_ENABLE according to the actual needs of operating the memory device. As an example, after detecting a read failure in the memory device, the user can enable AVD_ENABLE so that the memory device can perform a sensing operation for AVD to track a drifting threshold voltage distribution, which may be the cause of the read failure. The user can send configuration data 1312 to the memory device via the memory controller. In some embodiments, the configuration data can be stored in a register 1308 (e.g., a feature register) of the memory device.

[0093] At operation 1304, the memory device may perform a sensing operation on the AVD to obtain a read offset 1314 (eg, Figure 10 For example, a read offset 1314 including a read voltage may be identified by performing a sensing operation based on different reference voltages and the same development time, such as Figure 9 As shown in the diagram 906 in FIG. For another example, a read offset including a read development time can be identified by performing a sensing operation using the same reference voltage and different development times, such as Figure 9 908 in FIG. In some embodiments, the read offset 1314 can be stored in the SRAM 1310 of the memory device. In other embodiments, the read offset 1314 can be stored in the memory array of the memory device and can be loaded into the SRAM 1310 when needed.

[0094] In operation 1306, when the memory device receives a read command from the memory controller, the memory device may first check the configuration data 1312 stored in the register 1308. For example, if the configuration data 1312 indicates that a read offset is applied (e.g., the predetermined bit 1102 for AVD_APPLY is 1 and the predetermined bit 1106 for AVD_ENABLE is 0), the memory device will perform a read operation based on the read offset 1314 in the SRAM 1310. For example, if the configuration data 1312 indicates that automatic valley detection is performed (e.g., the predetermined bit 1102 for AVD_APPLY is 1 and the predetermined bit 1106 for AVD_ENABLE is 1), the memory device will perform a sensing operation to obtain a read offset, which may be stored in the SRAM 1310. In some embodiments, the read offset identified by the new sensing operation may overwrite the read offset in the SRAM 1310 from the previous sensing operation.

[0095] Specific embodiments of the subject matter have been described. Other embodiments, modifications, and permutations of the described embodiments are within the scope of the following claims and will be apparent to those skilled in the art. Although operations are described in a particular order in the drawings or claims, these operations need not be performed in the particular order or sequential order shown, or that all illustrated operations must be performed (some operations may be considered optional) to achieve the desired results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as deemed appropriate.

[0096] Furthermore, not all embodiments require the separation or integration of the various system modules and components of the previously described embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0097] Therefore, the example embodiments described above do not define or constrain the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

[0098] According to one aspect of the present disclosure, a method for operating a memory device is provided. The method includes performing a sensing operation on a memory cell of the memory device. The memory cell is coupled to a word line. The method also includes identifying a read offset comprising at least one of a read voltage or a read development time based on a result of the sensing operation. The read voltage is selected from at least one voltage, and the read development time is selected from at least one development time. The method also includes storing the read offset in the memory device.

[0099] In some implementations, the read offset is stored in an SRAM of the memory device.

[0100] In some embodiments, the method further includes receiving configuration data from a memory controller. The method further includes, in response to receiving a read command from the memory controller, determining that the configuration data indicates that the read offset is to be applied, and performing a read operation on the memory cell based on the read offset stored in the memory device.

[0101] In some embodiments, the configuration data has four bytes, the four bytes include a predetermined bit, and when the value of the predetermined bit is 1, the predetermined bit indicates that the read offset is to be applied.

[0102] In some implementations, the configuration data is stored in a register of the memory device.

[0103] In some embodiments, the sensing operation is based on a fixed development time and includes V1, V2, ..., V N (V1 <V2<……<V N ) represents the at least one voltage of the N voltages. The sensing operation includes: for each voltage V i (1≤i≤N), V i is applied to the word line, and when a sense node coupled to the memory cell is discharged for the fixed development time, a size S of a subset of the memory cells of the memory cell is determined i The voltage at the sensing node coupled to the subset of memory cells is higher than a predetermined threshold. Identifying the read offset includes: i (1≤i≤N-1), select voltage V from the N voltages J As the read voltage, where C i =S i -S i+1 (1≤i≤N-1), and C J It is C i The minimum number in .

[0104] In some embodiments, the sensing operation is based on a fixed voltage and a circuit including T1, T2, ..., T N (T1 <T2<……<T N ) represents the at least one development time of the N development times. The sensing operation includes: applying the fixed voltage to the word line; and for each development time T i (1≤i≤N), the sensing node coupled to the memory cell is discharged for T i When the size S of the memory cell subset of the memory cell is determinedi The voltage at the sensing node coupled to the subset of memory cells is higher than a predetermined threshold. Identifying the read offset includes: i (1≤i≤N-1), select the development time T from the N development times J As the read development time, where C i =S i -S i+1 (1≤i≤N-1), and C J It is C i The minimum number in .

[0105] In some embodiments, the method further includes performing a read operation on the memory cell based on the read offset, wherein the read operation includes applying the fixed voltage to the word line and sensing data from a sense node coupled to the memory cell while discharging the sense node for the read development time TJ.

[0106] According to another aspect of the present disclosure, a method for operating a memory system is disclosed. The method includes: transmitting configuration data indicating whether to apply a read offset from a memory controller to a memory device. The read offset is stored in the memory device and includes at least one of a read voltage or a read development time. The method also includes: in response to the memory device receiving a read command from the memory controller, determining, by the memory device, that the configuration data indicates that the read offset is to be applied, and performing a read operation by the memory device based on the read offset.

[0107] In some implementations, the read offset is stored in an SRAM of the memory device.

[0108] In some implementations, the method further includes storing the configuration data in a register of the memory device.

[0109] In some embodiments, the configuration data has four bytes, and the four bytes include a first predetermined bit, and when the value of the first predetermined bit is 1, the first predetermined bit indicates that the read offset is to be applied.

[0110] In some embodiments, the four bytes further include a second predetermined bit. When a value of the second predetermined bit is 1, the second predetermined bit indicates that a sensing operation is to be performed, and the read offset is generated from the sensing operation.

[0111] In some embodiments, the method further includes: in response to determining that the value of the second predetermined bit is 1, performing a sensing operation by the memory device to obtain the read offset. The method further includes setting the value of the second predetermined bit to 0 by the memory controller after performing the sensing operation.

[0112] In some embodiments, the sensing operation is based on a fixed development time and includes V1, V2, ..., V N (V1 <V2<……<V N ) represents the at least one voltage of the N voltages. The sensing operation includes: for each voltage V i (1≤i≤N), V i is applied to a word line, and upon discharging a sense node coupled to the memory cell for the fixed development time, determines a size S of a subset of the memory cells of the memory cell i The voltage at the sensing node coupled to the subset of memory cells is above a predetermined threshold. i (1≤i≤N-1), select voltage V from the N voltages J As the read voltage, where C i =S i -S i+1 (1≤i≤N-1), and C J It is C i The minimum number in .

[0113] In some embodiments, the sensing operation is based on a fixed voltage and a circuit including T1, T2, ..., T N (T1 <T2<……<T N ) represents the at least one development time of the N development times. The sensing operation includes: applying the fixed voltage to the word line; and for each development time T i (1≤i≤N), the sensing node coupled to the memory cell is discharged for T i When the size S of the memory cell subset of the memory cell is determined i The voltage at the sensing node coupled to the subset of memory cells is above a predetermined threshold. i (1≤i≤N-1), select the development time T from the N development times J As the read development time, where C i =S i -S i+1 (1≤i≤N-1), and C J It is C i The minimum number in .

[0114] In some implementations, the read operation includes: applying the fixed voltage to the word line; and sensing data from a sense node coupled to the memory cell while discharging the sense node for the read development time.

[0115] According to another aspect of the present disclosure, a memory system is provided. The memory system includes a memory controller configured to send configuration data indicating whether a read offset is to be applied, wherein the read offset includes at least one of a read voltage or a read development time. The memory system also includes a memory device coupled to the memory controller. The memory device is configured to: store the configuration data received from the memory controller; determine that the configuration data indicates that the read offset is to be applied; and perform a read operation based on the read offset.

[0116] In some implementations, the memory device is further configured to perform the read operation in response to receiving a read command from the memory controller.

[0117] In some embodiments, the configuration data has four bytes, the four bytes including a predetermined bit, wherein when a value of the predetermined bit is 1, the predetermined bit indicates that the read offset is to be applied.

[0118] Although specific configurations and arrangements have been discussed, it will be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0119] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," and "some embodiments" indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to affect such feature, structure, or characteristic in conjunction with other embodiments.

[0120] In general, terms can be understood, at least in part, from usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular usage or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but rather can allow for the presence of other factors that are not necessarily explicitly described, again, depending, at least in part, on the context.

[0121] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0122] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire underlying or overlying structure, or can have a range that is smaller than the range of the underlying or overlying structure. In addition, a layer can be an area of ​​a uniform or uneven continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between or between any set of horizontal planes between the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (wherein contact portions, interconnect lines and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0123] As used herein, the term "about" or "approximately" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" or "approximately" may indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0124] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0125] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A method for operating a memory device, comprising: performing a sensing operation on a memory cell of the memory device, wherein the memory cell is coupled to a word line; identifying a read offset comprising at least one of a read voltage or a read development time based on a result of the sensing operation, wherein the read voltage is selected from at least one voltage, and wherein the read development time is selected from at least one development time; and The read offset is stored in the memory device.

2. The method according to claim 1, further comprising: receiving configuration data from a memory controller; as well as In response to receiving a read command from the memory controller: determining that the configuration data indicates that the read offset is to be applied; as well as A read operation is performed on the memory cell based on the read offset stored in the memory device.

3. The method according to claim 2, wherein: The configuration data has four bytes, wherein the four bytes include a predetermined bit, and wherein when a value of the predetermined bit is 1, the predetermined bit indicates that the read offset is to be applied.

4. The method according to claim 2 or 3, wherein: The configuration data is stored in registers of the memory device.

5. The method according to any one of claims 1 to 4, wherein The sensing operation is based on a fixed development time and includes V1, V2, ..., V N (V1 <V2<……<V N ), wherein the sensing operation comprises: For each voltage V i (1≤i≤N): V i applied to the word line; and When the sensing node coupled to the memory cell is discharged for the fixed development time, a size S of the memory cell subset of the memory cell is determined. i , wherein a voltage at a sense node coupled to the subset of memory cells is above a predetermined threshold, and wherein identifying the read offset comprises: C-based i (1≤i≤N-1), select voltage V from the N voltages J As the read voltage, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

6. The method according to any one of claims 1 to 4, wherein The sensing operation is based on a fixed voltage and includes T1, T2, ..., T N (T1 <T2<……<T N ), wherein the sensing operation comprises: applying the fixed voltage to the word line; and For each development time T i (1≤i≤N), the sensing node coupled to the memory cell is discharged for T i When the size S of the memory cell subset of the memory cell is determined i , wherein a voltage at a sense node coupled to the subset of memory cells is above a predetermined threshold, and wherein identifying the read offset comprises: C-based i (1≤i≤N-1), select the development time T from the N development times J As the read development time, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

7. The method according to claim 6, further comprising: Performing a read operation on the memory cell based on the read offset, wherein the read operation comprises: applying the fixed voltage to the word line; and After discharging the sensing node coupled to the memory cell for the read development time T J When , data is sensed from the sensing node.

8. The method according to any one of claims 1 to 7, wherein The read offset is stored in an SRAM of the memory device.

9. A method for operating a memory system comprising a memory device and a memory controller, the method comprising: sending, from the memory controller to the memory device, configuration data indicating whether to apply a read offset, wherein the read offset is stored in the memory device and includes at least one of a read voltage or a read development time; and In response to the memory device receiving a read command from the memory controller: determining, by the memory device, that the configuration data indicates that the read offset is to be applied; and A read operation is performed by the memory device based on the read offset.

10. The method according to claim 9, further comprising: The configuration data is stored in a register of the memory device.

11. The method according to claim 9 or 10, wherein: The configuration data has four bytes, wherein the four bytes include a first predetermined bit, wherein when a value of the first predetermined bit is 1, the first predetermined bit indicates that the read offset is to be applied.

12. The method according to claim 11, wherein The four bytes further include a second predetermined bit, wherein when a value of the second predetermined bit is 1, the second predetermined bit indicates that a sensing operation is to be performed, and wherein the read offset is generated from the sensing operation.

13. The method according to claim 12, further comprising: In response to determining that the value of the second predetermined bit is 1, performing a sensing operation by the memory device to obtain the read offset; as well as After performing the sensing operation, the value of the second predetermined bit is set to 0 by the memory controller.

14. The method according to claim 12, wherein: Based on fixed development time and V1, V2, ..., V N (V1 <V2<……<V N ) to perform the sensing operation, wherein the sensing operation includes: For each voltage V i (1≤i≤N): V i applied to a word line, wherein the word line is coupled to a memory cell of the memory device; and When the sensing node coupled to the memory cell is discharged for the fixed development time, a size S of the memory cell subset of the memory cell is determined. i , wherein the voltage at the sensing node coupled to the subset of memory cells is above a predetermined threshold, wherein based on C i (1≤i≤N-1), select voltage V from the N voltages J As the read voltage, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

15. The method according to claim 12, wherein: Based on fixed voltage and T1, T2, ..., T N (T1 <T2<……<T N ) represents N development times to perform the sensing operation, wherein the sensing operation includes: applying the fixed voltage to a word line, wherein the word line is coupled to a memory cell of the memory device; and For each development time T i (1≤i≤N), the sensing node coupled to the memory cell is discharged for T i When the size S of the memory cell subset of the memory cell is determined i , wherein a voltage at a sense node coupled to the subset of memory cells is above a predetermined threshold, Among them, based on C i (1≤i≤N-1), select the development time T from the N development times J As the read development time, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

16. The method according to claim 15, wherein The read operation includes: applying the fixed voltage to the word line; and While a sense node coupled to the memory cell is discharged for the read development time, data is sensed from the sense node.

17. The method according to any one of claims 9 to 16, wherein The read offset is stored in an SRAM of the memory device.

18. A memory system comprising: a memory controller configured to send configuration data indicating whether a read offset is to be applied, wherein the read offset comprises at least one of a read voltage or a read development time; and a memory device coupled to the memory controller and configured to: storing the configuration data received from the memory controller; determining that the configuration data indicates that the read offset is to be applied; and A read operation is performed based on the read offset.

19. The memory system of claim 18, wherein: The memory device is further configured to perform the read operation in response to receiving a read command from the memory controller.

20. The memory system according to claim 18 or 19, wherein: The configuration data has four bytes including a predetermined bit, wherein when a value of the predetermined bit is 1, the predetermined bit indicates that the read offset is to be applied.

21. The memory system of claim 18, wherein: The memory device is further configured to: performing a sensing operation on a memory cell of the memory device, wherein the memory cell is coupled to a word line; identifying the read offset based on a result of the sensing operation, the read offset comprising at least one of the read voltage or the read development time, wherein the read voltage is selected from at least one voltage, and wherein the read development time is selected from at least one development time; and The read offset is stored in the memory device.

22. The memory system of claim 21, wherein: The sensing operation is based on a fixed development time and includes V1, V2, ..., V N (V1 <V2<……<V N ) is performed by using at least one of the N voltages represented by ), wherein the sensing operation includes: For each voltage V i (1≤i≤N): V i applied to the word line; and When the sensing node coupled to the memory cell is discharged for the fixed development time, a size S of the memory cell subset of the memory cell is determined. i , wherein the voltage at the sensing node coupled to the subset of memory cells is above a predetermined threshold, wherein based on C i (1≤i≤N-1), select voltage V from the N voltages J As the read voltage, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

23. The memory system of claim 21, wherein: The sensing operation is based on a fixed voltage and a pair of transistors T1, T2, ..., T N (T1 <T2<……<T N ) is performed at N development times represented by ), wherein the sensing operation includes: applying the fixed voltage to a word line, wherein the word line is coupled to a memory cell of the memory device; and For each development time T i (1≤i≤N), the sensing node coupled to the memory cell is discharged for T i When the size S of the memory cell subset of the memory cell is determined i , wherein a voltage at a sense node coupled to the subset of memory cells is above a predetermined threshold, Among them, based on C i (1≤i≤N-1), select the development time T from the N development times J As the read development time, where C i =S i -S i+1 (1≤i≤N-1), and among them, C J It is C i The minimum number in .

24. The memory system according to any one of claims 18 to 23, wherein: The read offset is stored in an SRAM of the memory device.

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