OTP control circuit and application and control method thereof

Abstract

The invention relates to the field of integrated circuits, in particular to an OTP (One Time Programmable) control circuit and application and control method thereof, and the circuit comprises a double-track power supply which comprises a programming power supply switch and a reading power supply switch, one ends of the two switches are connected with a switch network, and the other ends of the two switches are respectively connected with an OTP programming power supply and an OTP reading power supply; the switch network comprises N OTP storage units arranged in parallel and corresponding control switches, one end of each OTP storage unit is connected with the double-track power supply control circuit, and the other end of each OTP storage unit is connected with the corresponding control switch; the other ends of all the control switches are respectively connected with the double-output-bit circuit and the analog state selection circuit; the double-output-bit circuit comprises a first output switch and a second output switch and is used for controlling the turn-off of two output bits; the analog state power supply circuit comprises two switches which are respectively used for controlling a grounding end signal and a power supply end signal. According to the invention, the possibility of data writing or reading errors caused by time sequence chaos of OTP operation is solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an OTP control circuit and an application and a control method thereof. Background Art

[0002] The development of one-time programmable non-volatile memory (OTP) stems from the continuous advancement of semiconductor memory technology. Traditional mask ROM lacks flexibility, and erasable non-volatile memories such as EEPROM and Flash are costly and limited in speed. The development of process technologies such as photolithography and thin film deposition has provided a manufacturing basis for it. In terms of application needs, consumer electronics products such as smart bracelets and small Bluetooth speakers, industrial automation production line controllers in the industrial control field, and engine control units in the automotive electronics field all require memories that can be written once while controlling costs and ensuring security and stability. OTP can meet these needs. At the same time, its development also draws on related technologies of EEPROM and Flash. For example, based on the charge storage principle, it has references in cell design and voltage control. OTP has both flexibility and low cost advantages, and can adapt to the storage requirements of many specific scenarios.

[0003] Currently, mainstream implementations of OTP control circuits include register-based control architectures and timing control circuits. Register-based control architectures use multiple internal registers to store and configure key OTP operation parameters, such as address registers for setting the operation location and data registers for temporary data storage. Values ​​written by an external controller are used to generate control signals to guide OTP operations, improving operational flexibility. However, this approach relies on frequent interaction with the external controller, increasing system complexity and latency. Furthermore, register read and write operations are susceptible to interference, leading to configuration errors. Timing control circuits generate precise and ordered timing signals, strictly regulating programming pulse widths and intervals to ensure that OTP operations are executed in the correct order. However, circuit failures, such as clock signal anomalies, can disrupt the entire OTP operation sequence, leading to data write or read errors. Furthermore, timing adjustment flexibility is limited, making it difficult to quickly adapt to changes in different processes and application scenarios. Therefore, to maximize the OTP's functionality, SoCs require the design of appropriate control circuits to implement simulation, programming, and read operations to prevent misoperation or failure. Summary of the Invention

[0004] To overcome the difficulties of traditional circuits in OTP state control, achieve accurate and efficient control of the three states of simulation, programming, and readout, comprehensively improve the reliability and stability of the circuit, and at the same time strive to simplify the circuit structure, enhance integration, and reduce overall cost, the present invention proposes an OTP control circuit, including a dual-rail power supply, a switching network, dual output bits, and a dual current source, wherein:

[0005] A dual-rail power supply, including a power control circuit and an analog state power circuit. The power control circuit is used to control the on / off connection between the OTP programming power supply, the OTP reading power supply, and one end of the switch network. The analog state power circuit is used to control the on / off connection between the ground terminal signal and the power terminal signal and the other end of the switch network.

[0006] The switch network includes N parallel-connected OTP storage units and corresponding control switches, wherein one end of each OTP storage unit is connected to the dual-rail power supply control circuit, and the other end is connected to the corresponding control switch; the other end of each control switch is connected to the dual-output bit circuit and the analog state selection circuit respectively;

[0007] The dual output bit circuit includes a first output switch and a second output switch for controlling the shutoff of two output bits;

[0008] Dual current sources are used to provide driving current for output signals.

[0009] Furthermore, the dual-channel current source includes two current sources, the first output switch of the dual-output bit circuit is connected to one current source, the other end of the current source is grounded, and the current source and the switch serve as the read-out output bit; the second output switch of the dual-output bit circuit is connected to another current source, the other end of the current source is grounded, and the current source and the switch serve as the state output bit.

[0010] The present invention also proposes an application of an OTP control circuit, including M cascaded OTP control circuits, wherein the first output switches of all the OTP control circuits are connected together, and the first output switches of all the OTP control circuits are connected together and serve as the input of a D flip-flop, and the output of the D flip-flop is used as the circuit output.

[0011] Furthermore, the dual current source includes an N-type MOS transistor and a variable current source (i.e., a current source IBIAS1 with an adjustable current value). The first output switches are connected together and connected to the drain of the N-type MOS transistor. The source of the N-type MOS transistor is grounded, and the on and off of the gate of the N-type MOS transistor is controlled by the bias current. The second output switches of all OTP control circuits are connected together and connected to a variable current source. The other end of the variable current source is grounded.

[0012] The present invention also proposes an application of an OTP control circuit, comprising X OTP control circuits formed by cascading M OTP control circuits to form an OTP control array cascade circuit, wherein different cascade circuits obtain X state serial outputs through triggers under the control of a clock CLK.

[0013] The present invention also proposes a control method for an OTP control circuit, which is used to control an OTP control circuit. The method controls whether an OTP programming power supply or an OTP reading power supply is connected by controlling the on-off control of a switch in a dual-rail power supply. If the OTP programming power supply is connected, the OTP storage unit performs a programming operation, and if the OTP reading power supply is connected, the OTP storage unit performs a reading operation; the method controls the on-off control of switches in a switch network to select a corresponding OTP storage unit to perform a selected operation; and the method determines the output bit by controlling the on-off control of two switches in a dual-output bit circuit.

[0014] Preferably, when one of the switches of the analog state selection circuit is closed and the first output switch is closed, the port corresponding to the switch outputs an analog signal.

[0015] Preferably, the corresponding OTP memory cell is selected by closing the switch in the control switch network, and the programming current flows through the selected OTP memory cell to complete data writing. When the second output switch is closed, the output end controlled by the switch feeds back the programming status in real time.

[0016] Preferably, when the read power switch is closed, the corresponding OTP storage cell is selected by controlling the closure of the switch in the switch network, and the programming current converts the data into an electrical signal when flowing through the selected OTP storage cell. When the first output switch is closed, the output of the port corresponding to the switch is provided to the external circuit for processing.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The innovative features of the OTP control circuit of the present invention include a highly integrated design that integrates multiple OTP control functions, a concise and clear state switching method, and a simple circuit structure that works in conjunction with a switch network to achieve rapid switching between three states. Furthermore, signal transmission during the switching process is stable and jitter-free, eliminating operational errors caused by switching delays or signal disturbances and ensuring the consistency of data processing.

[0019] 2. The OTP control circuit in the present invention has the characteristics of simple structure, easy control mode, small area and strong reusability. It solves the possibility of data writing or reading errors caused by OTP operation timing disorder, and ensures stable operation of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of an OTP control circuit structure of the present invention;

[0021] Figure 2 Schematic diagram of a cascade circuit composed of an OTP control circuit in the present invention;

[0022] Figure 3 Schematic diagram of an array cascade circuit composed of an OTP control circuit in the present invention;

[0023] Figure 4 This is a timing diagram of a control method for an OTP control circuit of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0025] The present invention proposes an OTP control circuit, including a dual-rail power supply, a switch network, dual output bits and a dual current source, wherein:

[0026] A dual-rail power supply control circuit includes a programming power switch and a reading power switch. One end of the two switches is connected to the switch network, and the other end is connected to the OTP programming power supply and the OTP reading power supply respectively.

[0027] The switch network includes N parallel-connected OTP storage units and corresponding control switches, wherein one end of each OTP storage unit is connected to the dual-rail power supply control circuit, and the other end is connected to the corresponding control switch; the other end of each control switch is connected to the dual-output bit circuit and the analog state selection circuit respectively;

[0028] The dual output bit circuit includes a first output switch and a second output switch for controlling the shutoff of two output bits;

[0029] The analog state selection circuit includes two switches, which are used to control the ground terminal signal and the power terminal signal respectively.

[0030] In the present invention, a dual-rail power supply control circuit is used to control the on-off between the two power supply groups, the OTP programming power supply and the OTP reading power supply, and the switch network. The OTP programming power supply is specifically designed to provide an adaptive high-energy pulse voltage for the programming link, ensuring that data can be stably and accurately written into the OTP storage unit; the reading power supply uses a stable voltage in the reading state to ensure that the stored data can be accurately converted into an electrical signal output. The two perform their respective functions, greatly optimizing the power management mechanism.

[0031] The switch network is a complex network of numerous switches, including analog state switches, programming state switches, and readout state switches. These switches control the flow of signals in the circuit, precisely opening or closing the circuit path according to the required state. During analog state switching, the switches work together to ensure fast and smooth transitions in the signal transmission path. During programming, by connecting to the programming power supply, the switches select specific OTP cells as needed, achieving precise programming control. During readout, the OTP state is read out through the switches using the readout power supply.

[0032] This invention uniquely designs an OTP analog state and readout output bit, along with a status output bit. This dual-output circuit includes a first output switch and a second output switch. In the analog state, it outputs precise signals, providing a key basis for OTP functional verification and testing. In the readout state, it accurately reflects OTP stored data information. Under programming, it provides highly sensitive feedback on the OTP's internal state. This dual-output design significantly enhances the comprehensiveness and effectiveness of circuit information exchange.

[0033] In this embodiment, the two groups of current sources work closely together to provide a constant and appropriate driving current for programming operations and output signals, thereby overcoming the attenuation and interference problems during signal transmission and ensuring high quality and reliability of the output signals.

[0034] The OTP control circuit can be used as a basic unit to achieve expansion, and an array-type OTP control circuit can be built by matching requirements through IP multiplexing.

[0035] Example 1

[0036] like Figure 1 As shown, in this embodiment, an OTP control circuit 104 includes a dual-rail power supply, a switch network, dual output bits and a dual current source, wherein:

[0037] The dual-rail power supply consists of a power control circuit 101 and an analog state power circuit 103. Power control circuit 101 controls the connection between the OTP programming power supply, the OTP reading power supply, and one end of the switch network. Analog state power circuit 103 controls the connection between the ground and power signals and the other end of the switch network. The OTP programming power supply VP provides a high-energy pulse voltage suitable for programming, ensuring that data is securely and accurately written to the OTP memory cells. During the reading phase, the power supply signal VDD maintains a stable voltage to ensure that stored data is accurately converted into an electrical output signal. These two circuits each perform their respective functions, significantly optimizing power management.

[0038] In this embodiment, the OTP programming power supply and the switch network 102 are connected and disconnected via the switch SA. <1> Control, OTP reads the power supply and the switch network through the switch SA <2> Control, the dual current source uses two current sources, namely the first current source I1 and the second current source I2; the ground terminal signal and the switch network are connected and disconnected through the switch SB <2> Control, the power supply signal and the switch network are connected and disconnected through the switch SB <1> Control; the switch network includes N OTP storage units and N switches, each OTP storage unit OPT <n>Through its corresponding switch control, that is, the Nth OTP storage unit OPT <n>Through its corresponding switch SC <n>Control and analog state power supply circuit, dual output bit circuit between the on-off; dual output bit circuit first output switch SE1 <1> Used to control whether the first output bit Q1 has a signal output, and the second output switch SD1 <1> Used to control whether the second output position Q2 has a signal output; the first output switch SE1 <1> , the second output switch SD1 <1> A first current source I1 and a second current source I2 are respectively provided between the first current source I1 and the ground terminal GND.

[0039] In the present invention, the switch controls the direction of the circuit signal and accurately opens or cuts off the circuit path according to different state requirements. For example, when programming, the switch SA <1> When closed, it indicates that the OTP programming power supply VP is connected. By closing the SC series switch, a specific OTP unit is selected to achieve precise programming control. When the analog state is switched, the switches work together to ensure that the signal transmission path is quickly and smoothly converted.

[0040] This embodiment is uniquely designed with a first output bit Q1 for OTP simulation state and readout output, and a second output bit Q2 for output state. In the simulation state, the first output bit Q1 outputs a precise analog signal, providing a key basis for OTP function verification and testing; in the readout state, the first output bit Q1 accurately feeds back OTP stored data information; under programming, the second output bit Q2 feeds back the internal state of the OTP with high sensitivity. The dual-output bit design greatly improves the comprehensiveness and effectiveness of circuit information interaction.

[0041] This embodiment is also equipped with a first current source I1 and a second current source I2, which work closely with the first output position Q1 and the second output position Q2 respectively. They act as a stable power source, providing a constant and appropriate driving current for the output signal, overcoming the attenuation and interference problems during signal transmission, and ensuring the high quality and high reliability of the output signal.

[0042] Example 2

[0043] This embodiment is improved on the basis of embodiment 1.

[0044] In this embodiment, an application circuit 209 is composed of M OTP control groups, which include the first OTP control group 204, ..., the Mth OTP control group 208. Each OTP control group includes an OTP storage resource number, forming an OTP control cascade circuit 209. Figure 2 The first OTP control group 204 includes a first power control circuit 201, a first analog state power circuit 203, and a first switch network 202. The Mth OTP control group 208 includes a second power control circuit 205, a first analog state power circuit 207, and a first switch network 206. The number of storage resources of the OTP reaches M×N.

[0045] In Example 2, the dual current source includes an N-type MOS transistor and a variable current source. The first output switch of each OTP control circuit is connected to the drain of the N-type MOS transistor, the source of the N-type MOS transistor is grounded, and the gate is controlled by the bias current port PRG; the second output switch of each OTP control circuit is connected to a variable current source, the other end of the current source is grounded, and the output between the output switch and the current source is used as the input of the D flip-flop. By controlling the clock input to the D flip-flop, the output end of the D flip-flop obtains a state serial output, and the state serial output STATE1 is realized by the flip-flop under the control of the clock CLK.

[0046] Example 3

[0047] This embodiment is improved on the basis of embodiment 2.

[0048] X OTP control cascade circuits are included, including the first OTP control cascade circuit 309, ..., the Xth OTP control cascade circuit 319. Each OTP control cascade circuit is composed of M OTP control groups, forming an OTP control array cascade circuit 310. The number of OTP storage resources reaches X × M × N. Different cascade circuits implement state serial output STATE1 to STATEX through triggers under the control of clock CLK.

[0049] Example 4

[0050] In this embodiment, a timing control of an OTP control circuit is provided, such as Figure 4 , including the following workflow:

[0051] 1. Simulation state (t0 to t2): When entering the simulation state, close switch SB <1> Or switch SB <2> The switch connects the power supply signal VDD and the ground signal GND to the status simulation module. The module simulates the OTP working condition according to the internal settings. The first output bit Q1 outputs the corresponding analog signal for OTP function testing and verification;

[0052] 2. Programming state (t2 to t4): Enter the programming state and close the switch SA <1> The switch is connected to the OTP programming power supply VP, and the control switch SC <1> To SC <n>The switch selects the OTP memory cell to be programmed in turn. The programming current flows through the selected cell under the action of the OTP programming power supply VP to complete the data writing. The second output bit Q2 provides real-time feedback on the programming status.

[0053] 3. Reading state (t4 to t6): When in the reading state, close switch SA <2> The switch is connected to the power supply signal VDD, and the switch SC <1> To switch SC <n>The switch sequentially selects the OTP memory cell to be read, and the read current passes through the cell to convert the data into an electrical signal, which is output by the first output bit Q1 for external circuit processing;

[0054] The above switches are closed when the level is high and open when the level is low. In this embodiment, the switch SA <1> The high level of refers to the access to the OTP programming power supply VP, the high level of other switches refers to the access to the power supply terminal VDD, and the low level of this embodiment refers to the access to the ground terminal GND.

[0055] Through the OTP control circuit and control method in this embodiment, a simple circuit structure is coordinated with the switch network to achieve rapid switching of the three states, and the signal transmission during the switching process is stable and jitter-free, eliminating operational errors caused by switching delays or signal disorder and ensuring the continuity of data processing.

[0056] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation plans of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the scope of protection of the present invention.< / n> < / n> < / n> < / n> < / n>

Claims

1. An OTP control circuit, characterized in that: Includes a dual-rail power supply, a switching network, dual output bits, and dual current sources, including: A dual-rail power supply, including a power control circuit and an analog state power circuit. The power control circuit is used to control the on / off connection between the OTP programming power supply, the OTP reading power supply, and one end of the switch network. The analog state power circuit is used to control the on / off connection between the ground terminal signal and the power terminal signal and the other end of the switch network. The switch network includes N parallel-connected OTP storage units and corresponding control switches, wherein one end of each OTP storage unit is connected to the dual-rail power supply control circuit, and the other end is connected to the corresponding control switch; the other end of each control switch is connected to the dual-output bit circuit and the analog state selection circuit respectively; The dual output bit circuit includes a first output switch and a second output switch for controlling the shutoff of two output bits; Dual current sources are used to provide driving current for output signals.

2. An OTP control circuit according to claim 1, characterized in that, The dual-channel current source includes two current sources. The first output switch of the dual-output bit circuit is connected to one current source, the other end of the current source is grounded, and the area between the current source and the switch serves as a read-out output bit. The second output switch of the dual-output bit circuit is connected to another current source, the other end of the current source is grounded, and the area between the current source and the switch serves as a state output bit.

3. An application of an OTP control circuit, characterized in that: An OTP control circuit according to claim 1 comprising M cascaded circuits, wherein the first output switches of all the OTP control circuits are connected together, the first output switches of all the OTP control circuits are connected together and serve as inputs of a D flip-flop, and the output of the D flip-flop is used as the circuit output.

4. The application of an OTP control circuit according to claim 3, characterized in that: The dual current source includes an N-type MOS tube and a variable current source. The first output switches are connected together and connected to the drain of the N-type MOS tube. The source of the N-type MOS tube is grounded. The on and off of the gate of the N-type MOS tube is controlled by the bias current. The second output switches of all OTP control circuits are connected together and connected to a variable current source. The other end of the variable current source is grounded.

5. An application of an OTP control circuit, characterized in that: An OTP control circuit according to claim 3 or 4 comprising X cascades forms an OTP control array cascade circuit, and different cascade circuits obtain X state serial outputs through triggers under the control of a clock CLK.

6. A control method for an OTP control circuit, characterized in that: Used to control an OTP control circuit as described in any one of claims 1 to 5, by controlling the on-off control of switches in a dual-rail power supply to connect to an OTP programming power supply or an OTP reading power supply, if the OTP programming power supply is connected, the OTP storage unit performs a programming operation, and if the OTP reading power supply is connected, the OTP storage unit performs a reading operation; by controlling the on-off control of switches in a switch network, a corresponding OTP storage unit is selected to perform a selected operation; and the output bit is determined by the on-off control of two switches in a dual-output bit circuit.

7. The control method according to claim 6, characterized in that: When one of the switches of the analog state selection circuit is closed and the first output switch is closed, the port corresponding to the switch outputs an analog signal.

8. The control method according to claim 6, characterized in that: When the programming power switch is closed, the corresponding OTP storage unit is selected by controlling the closure of the switch in the switch network. The programming current flows through the selected OTP storage unit to complete data writing. When the second output switch is closed, the output end controlled by the switch feeds back the programming status in real time.

9. The control method according to claim 6, characterized in that: When the read power switch is closed, the corresponding OTP storage cell is selected by controlling the closure of the switch in the switch network. The programming current converts the data into an electrical signal when flowing through the selected OTP storage cell. When the first output switch is closed, the output of the port corresponding to the switch is provided to the external circuit for processing.

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