Screening methods for failed chips

Abstract

This invention provides a method for screening failed chips, comprising: providing a chip to be tested, the chip including a substrate, gate structures located on the substrate, and ion implantation regions, each gate structure including: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate; multiple word line gates in the same row are connected to form a word line; multiple control gates in the same row are connected to form a control line; ion implantation regions in the same column are connected to form a bit line; a word line gate, a control gate, a floating gate, and an ion implantation region on one side constitute a memory cell; performing an erase operation on the memory cell; applying a first voltage and a second voltage to the bit line and the control line, the voltage difference between the first voltage and the second voltage being greater than 8.2V and the voltage difference between the first voltage and the floating gate voltage being less than the breakdown voltage of the gate oxide layer, the first voltage being greater than 0, and the second voltage being less than 0; performing a write 00 operation and a read 00 operation on the memory cell; if the read value is not 00, the chip is considered failed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for screening failed chips. Background Technology

[0002] During chip manufacturing, a small number of defective chips may occur due to process or design issues. If these defective chips cannot be effectively screened out and reach the customer, it will increase the difficulty of resolving the problem and increase costs later on. NORD flash memory is a component in a chip, and its failure can directly cause the chip to fail. Multiple NORD flash memory chips exist simultaneously on a single wafer, arranged in multiple rows and columns.

[0003] Please refer to Figure 1 The prior art NORD flash memory includes: a substrate 101, and a plurality of gate structures spaced apart on the substrate 101. The plurality of gate structures are arranged in multiple rows in a first direction and in multiple columns in a second direction, with the first and second directions being perpendicular to each other. Each gate structure includes: a gate oxide layer 102, a floating gate 103, an ONO layer 104, a control gate 105, a word line gate 106, a first sidewall 107, and a second sidewall 108. The gate oxide layer 102 is located on the surface of the substrate 101, and the floating gate 103, the ONO layer 104, and the control gate 105 are located on a portion of the surface of the gate oxide layer 102. Word line openings are formed in the floating gate 103, the ONO layer 104, and the control gate 105, and the word line gate 106 is located within the word line openings. The word line gate 106 is separated from the sidewalls of the floating gate 103 and the ONO layer 104 by the first sidewall 107. The word line gate 106 is also separated from the sidewall of the control gate 105 by a first sidewall 107 and a second sidewall 108. It also includes a first ion implantation region 109 and a second ion implantation region 110. The first ion implantation region 109 is located within the substrate 101 on one side of the gate structure, and the second ion implantation region 110 is located within the substrate 101 on the other side of the gate structure. Word line gates 106 connected in the same row in a first direction form word lines, and control gates 105 connected in the same row form control lines, with one control line on each side of each word line. First ion implantation regions 109 connected in the same column in a second direction form first bit lines, and second ion implantation regions 110 connected in the same column in a second direction form second bit lines.

[0004] However, as device areas become smaller, the distance between the control gate and bit lines becomes closer, which may lead to weak connections between the control gate and bit lines, reducing chip quality and yield. Summary of the Invention

[0005] The purpose of this invention is to provide a method for screening failed chips, which can identify chips with weak connections in the control gate and bit lines in advance, thereby improving chip quality and yield.

[0006] To achieve the above objectives, the present invention provides a method for screening failed chips, comprising:

[0007] A chip to be tested is provided. The chip includes a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions located on both sides of each gate structure within the substrate. Each gate structure includes a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate. The gate oxide layer is located on the surface of the substrate. The floating gate, ONO layer, and control gate are sequentially located on the surface of a portion of the gate oxide layer. A word line gate is formed within the floating gate, ONO layer, and control gate. Multiple word line gates in the same row are connected to form a word line. Multiple control gates in the same row are connected to form a control line. Ion implantation regions in the same column are connected to form a bit line. One word line gate, along with one control gate, one floating gate, and one ion implantation region on one side, constitutes a memory cell.

[0008] An erase operation is performed on all the memory cells so that the charge of all the floating gates is positive.

[0009] A first voltage and a second voltage are applied to the bit line and the control line respectively, the voltage difference between the first voltage and the second voltage is greater than 8.2V and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0;

[0010] All the aforementioned memory cells are sequentially written to with a 00 value and read from with a 00 value. If the read value is not 00, the chip is considered to be faulty.

[0011] Optionally, in the method for screening failed chips, the gate structure further includes a first sidewall and a second sidewall. The word line gate is separated from the sidewall of the floating gate and the sidewall of the ONO layer by the first sidewall. The word line gate is also separated from the sidewall of the control gate by the first sidewall and the second sidewall, respectively.

[0012] Optionally, in the method for screening failed chips, the first voltage is 0 to 8V.

[0013] Optionally, in the method for screening failed chips, the second voltage is 0 to -20V.

[0014] Optionally, in the method for screening failed chips, the calculation method for the voltage difference between the first voltage and the floating gate voltage includes: V = -Vcg*CR + Vfg + Vbl, where V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is the voltage coupling rate from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is the absolute value of the first voltage.

[0015] Optionally, in the method for screening failed chips, the voltage coupling rate from the control gate to the floating gate is 30% to 40%.

[0016] Optionally, in the method for screening failed chips, the breakdown voltage of the gate oxide layer is 7.5V to 10V.

[0017] Optionally, in the method for screening failed chips, reading a value other than 00 includes reading a value of 01 or 11.

[0018] Optionally, in the method for screening failed chips, the method for erasing the memory cell includes:

[0019] A voltage of 0V is applied to the control gate.

[0020] Optionally, in the method for screening failed chips, if the value of the storage unit is "00", the chip is considered to be qualified.

[0021] The method for screening failed chips provided by this invention includes: providing a chip to be tested, the chip including a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions located on both sides of each gate structure within the substrate. Each gate structure includes: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate. The gate oxide layer is located on the surface of the substrate, and the floating gate, ONO layer, and control gate are sequentially located on a portion of the surface of the gate oxide layer. A word line gate is formed within the floating gate, ONO layer, and control gate. Multiple word line gates in the same row are connected to form word lines, and multiple control gates in the same row are connected to form control lines. The ion-implanted regions are connected to form bit lines. A word line gate, a control gate, a floating gate, and an ion-implanted region on one side constitute a memory cell. All memory cells are erased to make all floating gates positively charged. A first voltage and a second voltage are applied to the bit lines and control lines respectively. The voltage difference between the first and second voltages is greater than 8.2V, and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer. The first voltage is greater than 0, and the second voltage is less than 0. All memory cells are sequentially written with 00 and read with 00. If the read value is not 00, the chip fails. By performing voltage tests on the bit lines and control gates in advance, chips with weak connections in the control gate and bit lines are screened out, thereby improving chip quality and yield. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of existing NORD flash memory;

[0023] Figure 2 This is a flowchart of a method for screening failed chips according to an embodiment of the present invention;

[0024] 101-Substrate, 102-Gate oxide layer, 103-Floating gate, 104-ONO layer, 105-Control gate, 106-Word line gate, 107-First sidewall, 108-Second sidewall, 109-First ion implantation region, 110-Second ion implantation region. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0026] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0027] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0028] Please refer to Figure 2 This invention provides a method for screening failed chips, comprising:

[0029] S11: Provide a chip to be tested. The chip includes a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions located on both sides of each gate structure within the substrate. Each gate structure includes: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate. The gate oxide layer is located on the surface of the substrate. The floating gate, ONO layer, and control gate are sequentially located on the surface of a portion of the gate oxide layer. Word line gates are formed within the floating gate, ONO layer, and control gate. Multiple word line gates in the same row are connected to form a word line. Multiple control gates in the same row are connected to form a control line. Ion implantation regions in the same column are connected to form a bit line. A word line gate, a control gate, a floating gate, and an ion implantation region on one side constitute a memory cell.

[0030] S12: Perform an erase operation on all memory cells so that all floating gates are positively charged;

[0031] S13: Apply a first voltage and a second voltage to the alignment line and the control line respectively. The voltage difference between the first voltage and the second voltage is greater than 8.2V and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer. The first voltage is greater than 0 and the second voltage is less than 0.

[0032] S14: Perform write 00 and read 00 operations sequentially on all memory cells. If the read value is not 00, the chip fails.

[0033] First, a chip to be tested is provided. The chip includes memory cells arranged in multiple rows and columns. Typically, a word line gate, a control gate on one side, a floating gate, and an ion implantation region constitute a memory cell. Therefore, please refer to... Figure 1 Specifically, the system includes a substrate 101, and a plurality of gate structures spaced apart on the substrate 101. The gate structures are arranged in multiple rows in a first direction and multiple columns in a second direction, with the first and second directions perpendicular to each other. Each gate structure includes: a gate oxide layer 102, a floating gate 103, an ONO layer 104, a control gate 105, a word line gate 106, a first sidewall 107, and a second sidewall 108. The gate oxide layer 102 is located on the surface of the substrate 101. The floating gate 103, ONO layer 104, and control gate 105 are located on a portion of the surface of the gate oxide layer 102. Word line openings are formed within the floating gate 103, ONO layer 104, and control gate 105. The word line gate 106 is located within the word line openings and is separated from the sidewalls of the floating gate 103 and the ONO layer 104 by the first sidewall 107. The word line gate 106 is also separated from the sidewall of the control gate 105 by the first sidewall 107 and the second sidewall 108. It also includes a first ion implantation region 109 and a second ion implantation region 110. The first ion implantation region 109 is located within the substrate 101 on one side of the gate structure, and the second ion implantation region 110 is located within the substrate 101 on the other side of the gate structure. Word line gates 106 connected in the same row in a first direction become word lines, and control gates 105 connected in the same row become control lines. Each word line has one control line on each side. First ion implantation regions 109 connected in the same column in a second direction become first bit lines, and second ion implantation regions 110 connected in the same column in a second direction become second bit lines. A word line gate 106, together with a control gate 105, a floating gate 103, and a first ion implantation region 109 on one side, constitutes a memory cell. Two memory cells can share a single word line gate 106.

[0034] Next, all memory cells are erased, and all memory cells are set to "FF", so that the charge of all floating gates is at positive potential. This can avoid breakdown between the bit line and the floating gate when a first voltage is applied to the pull-up line. A method for erasing memory cells includes: applying a voltage of 0V to the control gate.

[0035] Next, a first voltage and a second voltage are applied to a bit line and a control line respectively, wherein a voltage difference between the first voltage and the second voltage is greater than 8.2V and a voltage difference between the first voltage and a floating gate voltage is less than a breakdown voltage of a gate oxide layer, the first voltage is greater than 0, and the second voltage is less than 0. Wherein, the first voltage is 0~8V, and the second voltage is 0~-20V. A calculation method for the voltage difference between the first voltage and the floating gate voltage comprises: V=-Vcg*CR+Vfg+Vbl, wherein V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is a voltage coupling ratio from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is an absolute value of the first voltage. Wherein, the voltage coupling ratio from the control gate to the floating gate is 30% to 40%, and the breakdown voltage of the gate oxide layer is 7.5V to 10V.

[0036] Next, a write 00 operation and a read 00 operation are sequentially performed on all memory cells, because if there is a weak connection between the bit line and the control gate, a write 00 failure will occur once breakdown occurs. Therefore, if the read value is not 00, it proves that there is a weak connection between the bit line and the control gate, and the chip can be judged to be invalid at this time, and the chip is screened out in advance. Wherein, the read value that is not 00 includes that the read value is 01 or 11, and as long as the read value is 01 or 11, the chip can be judged to be invalid; as long as there is any memory cell whose value is not 00, the chip is considered invalid. If the values of all read memory cells are 00, it proves that there is no weak connection between the bit line and the control gate, and the chip is considered qualified. The chip can flow to the use terminal. Therefore, performing this chip test in advance before the chip flows to the use terminal can improve the quality of the chip and reduce the probability of weak connection between the bit line and the control gate in the terminal.

[0037] In summary, the method for screening failed chips provided in this embodiment of the invention includes: providing a chip to be tested, the chip including a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions located on both sides of each gate structure within the substrate. Each gate structure includes: a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate. The gate oxide layer is located on the surface of the substrate, and the floating gate, ONO layer, and control gate are sequentially located on a portion of the surface of the gate oxide layer. Word line gates are formed within the floating gate, ONO layer, and control gate. Multiple word line gates in the same row are connected to form word lines, and multiple control gates in the same row are connected to form control lines. Ion implantation regions in the same column are connected to form bit lines. A word line gate, a control gate, a floating gate, and an ion implantation region on one side constitute a memory cell. All memory cells are erased to ensure all floating gates are positively charged. A first voltage and a second voltage are applied to the bit lines and control lines, respectively. The voltage difference between the first and second voltages is greater than 8.2V, and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer. The first voltage is greater than 0, and the second voltage is less than 0. All memory cells are sequentially written to (00) and read from (00). If the read value is not 00, the chip fails. By performing voltage tests on the bit lines and control gates in advance, chips with weak connections in the control gate and bit lines are screened out, thereby improving chip quality and yield.

[0038] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.

Claims

1. A method for screening failed chips, characterized in that, include: A chip to be tested is provided. The chip includes a substrate, gate structures arranged in multiple rows and columns on the substrate, and ion implantation regions located on both sides of each gate structure within the substrate. Each gate structure includes a gate oxide layer, a floating gate, an ONO layer, a control gate, and a word line gate. The gate oxide layer is located on the surface of the substrate. The floating gate, ONO layer, and control gate are sequentially located on the surface of a portion of the gate oxide layer. A word line gate is formed within the floating gate, ONO layer, and control gate. Multiple word line gates in the same row are connected to form a word line. Multiple control gates in the same row are connected to form a control line. Ion implantation regions in the same column are connected to form a bit line. One word line gate, along with one control gate, one floating gate, and one ion implantation region on one side, constitutes a memory cell. An erase operation is performed on all the memory cells so that the charge of all the floating gates is positive. A first voltage and a second voltage are applied to the bit line and the control line respectively, the voltage difference between the first voltage and the second voltage is greater than 8.2V and the voltage difference between the first voltage and the floating gate voltage is less than the breakdown voltage of the gate oxide layer, wherein the first voltage is greater than 0 and the second voltage is less than 0; All the aforementioned memory cells are sequentially written to with a 00 value and read from with a 00 value. If the read value is not 00, the chip is considered to be faulty.

2. The method for screening failed chips as described in claim 1, characterized in that, The gate structure further includes a first sidewall and a second sidewall. The word line gate is separated from the sidewall of the floating gate and the sidewall of the ONO layer by the first sidewall. The word line gate is also separated from the sidewall of the control gate by the first sidewall and the second sidewall, respectively.

3. The method for screening failed chips as described in claim 1, characterized in that, The first voltage is 0 to 8V.

4. The method for screening failed chips as described in claim 1, characterized in that, The second voltage is 0 to -20V.

5. The method for screening failed chips as described in claim 1, characterized in that, The method for calculating the voltage difference between the first voltage and the floating gate voltage includes: V = -Vcg*CR + Vfg + Vbl, where V is the voltage difference between the first voltage and the floating gate voltage, Vcg is the second voltage, CR is the voltage coupling rate from the control gate to the floating gate, Vfg is the floating gate voltage, and Vbl is the absolute value of the first voltage.

6. The method for screening failed chips as described in claim 5, characterized in that, The voltage coupling rate from the control gate to the floating gate is 30% to 40%.

7. The method for screening failed chips as described in claim 1, characterized in that, The breakdown voltage of the gate oxide layer is 7.5V to 10V.

8. The method for screening failed chips as described in claim 1, characterized in that, The non-zero value read includes: the value read is 01 or 11.

9. The method for screening failed chips as described in claim 1, characterized in that, The method for erasing the storage unit includes: A voltage of 0V is applied to the control gate.

10. The method for screening failed chips as described in claim 1, characterized in that, If the value of the storage unit is "00", the chip is considered to be qualified.

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