Chip packaging method, packaged chip and wearable device

Abstract

The invention provides a chip packaging method, a packaged chip and wearable equipment, and relates to the field of packaging. The chip packaging method comprises the following steps: obtaining a first crystal grain, a second crystal grain and a substrate; arranging the first crystal grains on the surface of the substrate; wherein the first surface of the first crystal grain is attached to the substrate; connecting the second surface of the first crystal grain with the substrate through lead bonding to obtain a first connection structure; wherein the second surface and the first surface are two opposite surfaces; welding the second surface of the second crystal grain with the second surface of the first crystal grain to obtain a second connection structure; and packaging the second connection structure to obtain a packaged chip. The packaging method is beneficial to miniaturization of the size of the packaged chip.

Description

Technical Field

[0001] The present application relates to the field of chip packaging, and specifically, provides a chip packaging method, a packaged chip, and a wearable device. Background Art

[0002] System-in-package technology integrates multiple dies into a single package to increase chip integration. To further shorten the electrical interconnect path, some chips are packaged using a die-to-die approach, where the metal bumps of different dies within the same package are soldered together to interconnect the two dies.

[0003] Currently, in the die-to-die packaging process, the first die is typically soldered to the second die before the soldered first die is electrically connected to the substrate via wire bonding (also known as "wire bonding"). Therefore, to prevent the first die from being obscured by the second die during wire bonding, the first die attached to the substrate must be larger than the second die away from the substrate. This allows for placement of the bonding pad (pin pad) on the first die. Furthermore, a safe distance must be maintained above the first die to prevent contamination of the pad during the adhesive dispensing process and to prevent damage to the second die during the bonding process by the bonding tool.

[0004] Therefore, the current chip packaging process is not conducive to further miniaturization of chip size. Summary of the Invention

[0005] In view of this, the present application aims to provide a chip packaging method, a packaged chip, and a wearable device to improve the miniaturization of the system-level packaged chip.

[0006] First, an embodiment of the present application provides a chip packaging method, including: obtaining a first crystal grain, a second crystal grain and a substrate; setting the first crystal grain on the surface of the substrate; wherein the first surface of the first crystal grain is bonded to the substrate; connecting the second surface of the first crystal grain to the substrate by wire bonding to obtain a first connection structure; wherein the second surface and the first surface are two opposite surfaces; welding the second surface of the second crystal grain to the second surface of the first crystal grain to obtain a second connection structure; and packaging the second connection structure to obtain a packaged chip. In an embodiment of the present application, during packaging, the first die is first wire-bonded to the substrate, and then the first die is welded to the second die. Therefore, there is no need to worry about the first die being blocked by the second die when bonding to the substrate, and the restriction that the size of the first die must be larger than the size of the second die can be avoided. At the same time, because the first die has been wire-bonded to the substrate before the first die and the second die undergo the glue dispensing process, even if the glue contaminates the pad, it will not affect the pad, so there is no need to reserve a safety distance for the glue dispensing process. Similarly, because the second die is not on the first die during wire bonding, there is no need to worry about the bonding tool damaging the second die, so the safety distance can be reduced. Based on the above reasons, the restriction on the size of the first die can be reduced, making the size of the first die smaller, and realizing further miniaturization of the system-level packaging chip.

[0007] In one embodiment, the second surface of each of the first grain and the second grain includes a metal bump; and welding the second surface of the second grain to the second surface of the first grain to obtain a second connection structure includes: using a no-clean flux to weld the second grain to the metal bumps of the first grain to obtain the second connection structure.

[0008] Soldering the first and second crystals will leave residual flux on the metal bumps, which usually requires cleaning. In the embodiment of the present application, the first crystal and the substrate are first wire-bonded, and then the first and second crystals are welded. On the one hand, the second connection structure including the substrate needs to be cleaned during cleaning. Compared with cleaning only the first and second crystals, the wire-bonding method first makes cleaning more difficult. On the other hand, since the metal wires used for wire bonding are usually thin, the metal wires may bend or break during the cleaning process, affecting the electrical performance and making cleaning more difficult. In addition, if the second connection structure is scrapped during the cleaning process, the wire-bonding method first and then welding will also result in higher cost waste compared to scrapping only the first and second crystals. In the embodiment of the present application, the use of a no-clean flux for welding can effectively avoid flux residue, thereby eliminating the need for cleaning, reducing process steps, reducing packaging difficulty, and improving the packaging yield.

[0009] In one embodiment, after obtaining the second connection structure, the method further includes: filling an insulating medium between the first die and the second die.

[0010] In the embodiments of the present application, by filling the insulating medium, the copper pillars formed by the metal bump welding between the first and second die can be effectively protected, the influence of stress can be reduced, and the reliability of the packaged chip can be improved. Specifically, because the first die and the substrate are wire-bonded first and the first and second die are welded later, the insulating medium is filled after the wire bonding. Therefore, when filling the insulating medium, there is no need to worry about the insulating medium contaminating the pad, thereby effectively reducing the difficulty of filling the insulating medium, thereby reducing process requirements and helping to improve packaging efficiency and packaging yield. On the other hand, there is no need to reserve a safe distance on the first die for filling the insulating medium, which helps to further miniaturize the packaged chip.

[0011] In one embodiment, the metal bumps are made of copper, gold, or tin-silver alloy.

[0012] In one embodiment, the second surface of each of the first grain and the second grain includes a metal bump; after obtaining the first grain, the second grain and the substrate, the method further includes: gold plating or nickel plating on the second surface of the first grain and the second surface of the second grain.

[0013] In the embodiment of the present application, since the flux and oxide residues after welding the first grain and the second grain are difficult to clean or easily damage the metal lead during cleaning, the second surface of each of the first grain and the second grain can be gold-plated or nickel-plated to improve the oxidation resistance of the second surface of each of the first grain and the second grain, thereby reducing the generation and residue of oxides during welding.

[0014] In one embodiment, the second surface of each of the first crystal grain and the second crystal grain includes a metal bump; welding the second surface of the second crystal grain to the second surface of the first crystal grain to obtain a second connection structure includes: using a water-soluble flux to weld the second surface of the second crystal grain to the second surface of the first crystal grain; washing the second surface of the second crystal grain and the second surface of the first crystal grain with water to obtain the second connection structure.

[0015] When soldering the first and second die, residual flux may remain. However, the space between the first and second die after soldering is narrow, making it difficult to remove the residual flux. Therefore, in the embodiments of the present application, a water-soluble flux is used for soldering, allowing the flux to be removed by washing with water, thereby reducing the difficulty of cleaning the flux and minimizing the residual flux, thereby reducing the impact of residual flux on the performance of the packaged chip. Compared to no-clean flux, water-soluble flux is more effective in removing oxides during washing, further helping to reduce residual oxides and flux during soldering.

[0016] In one embodiment, the size of the second grain is greater than or equal to the size of the first grain.

[0017] In the embodiment of the present application, because the first grain and the substrate are wire-bonded first and the first grain and the second grain are welded later, there is no need to reserve a wire-bonding pad for the first grain, so that the size of the second grain does not need to be smaller than the size of the first grain, so that the size of the second grain can be greater than or equal to the size of the first grain, thereby meeting the system-level packaging requirements of grains of different sizes from the packaging point of view, making the chip design more flexible.

[0018] In one embodiment, there are a plurality of the second grains, and the sum of sizes of the plurality of the second grains is greater than or equal to the size of the first grain.

[0019] In the embodiments of this application, because the first die is wire-bonded to the substrate first and then soldered to the second die, no wire-bonding pads are required for the first die, and thus the size of the second die does not need to be smaller than that of the first. This packaging approach eliminates the restriction that the sum of the sizes of multiple second dies must be smaller than the size of the first die, allowing for greater freedom and flexibility in chip design.

[0020] In a second aspect, an embodiment of the present application provides a packaged chip, comprising: a first die, a second die, and a substrate; the first die, the second die, and the substrate are packaged by the chip packaging method as described in any one of the first aspects.

[0021] In one embodiment, the packaged chip is a processor chip or a memory chip.

[0022] In a third aspect, an embodiment of the present application provides a wearable device comprising a packaged chip as described in any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For those skilled in the art, other relevant drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 This is a schematic structural diagram of a packaged chip provided in one embodiment of the present application; Figure 2 A flowchart of a chip packaging method provided in one embodiment of the present application; Figure 3 It is a schematic diagram of the packaging process of the prior art; Figure 4 This is a schematic diagram of the packaging process provided in an embodiment of the present application.

[0025] Icons: first die 110 ; second die 120 ; substrate 130 ; housing 140 ; ​​metal pillar 150 ; pin 160 . DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0027] For easier understanding, we first explain SIP (System In a Package) and the resulting packaged chip. SIP is a packaging technology that can package multiple dies in the same package. Figure 1 , Figure 1 This is a schematic diagram of a packaged chip provided in one embodiment of the present application. The packaged chip includes two dies, a first die 110 and a second die 120. The metal bumps of the first die 110 and the metal bumps of the second die 120 are welded together, connecting the first die 110 and the second die 120 and achieving electrical interconnection between them. This method is also known as die-to-die. Metal pillars 150 are formed at the welds between the first die 110 and the second die 120. For example, if the metal bumps are made of copper, copper pillars are formed.

[0028] The surface of the first die 110 where the metal pillar 150 is located is also connected to the substrate 130 through wire bonding, so that the circuit of the first die 110 can be led to the substrate 130 through the wires. Correspondingly, the circuit of the second die 120 can also be led to the substrate 130 through the metal pillar 150, the first die 110 and the wires.

[0029] In addition, the packaged chip further includes a housing 140 . The cavity formed by the housing 140 and the substrate 130 can be filled with epoxy resin. Balls can be planted on the other surface of the substrate 130 to lead out the circuit to obtain pins 160 .

[0030] The above is only a schematic diagram of a flip-chip packaged chip through a system-level package provided in an embodiment of the present application. The packaged chip may also include more structures. For details, please refer to the existing technology and will not be elaborated here.

[0031] See also Figure 2 , Figure 2 This is a flow chart of a chip packaging method provided in one embodiment of the present application. The chip packaging method includes: S110 , obtaining a first die, a second die, and a substrate.

[0032] In this embodiment, the first die 110 and the second die 120 are die to be packaged, and are packaged in the same package body.

[0033] In an embodiment of the present application, first die 110 and second die 120 include a first surface and a second surface, the first surface and the second surface being opposite each other. First die 110 and second die 120 are flip-chip (FC) packages, and metal bumps are grown on second die 120 and second surfaces of second die 120.

[0034] In the embodiment of the present application, before obtaining the first crystal grain 110 and the second crystal grain 120 , a bumping process may be performed on the first crystal grain 110 and the second crystal grain 120 to grow metal bumps on the second surfaces of the first crystal grain 110 and the second crystal grain 120 .

[0035] Therefore, in some embodiments of the present application, obtaining the first crystal grain 110 or the second crystal grain 120 may include: first forming a metallization layer on an uncut wafer by sputtering, evaporation, chemical plating, or the like, leading out the inner layer circuit in the wafer, then forming metal bumps on the metallization layer, and finally cutting the wafer to obtain crystal grains. If the wafer is a wafer containing the first crystal grain 110, the crystal grain obtained by cutting is the first crystal grain 110 with the metal bumps grown on the second surface; if the wafer is a wafer containing the second crystal grain 120, the crystal grain obtained by cutting is the second crystal grain 120 with the metal bumps grown on the second surface.

[0036] In the embodiment of the present application, the material of the metal bump is copper, gold or tin-silver alloy.

[0037] In the embodiment of the present application, the first die 110 is a die that needs to be connected to the substrate 130 . Therefore, a pad is further provided on the second surface of the first die 110 to electrically connect to the substrate 130 through the pad.

[0038] In the embodiment of the present application, the first crystal grain 110 and the second crystal grain 120 may be crystal grains prepared in advance and can be directly used. The method of obtaining the first crystal grain 110 and the second crystal grain 120 is not limited here.

[0039] Accordingly, the preparation of the substrate 130 may refer to the existing technology, and the substrate 130 may also be prepared in advance and can be used directly, which is not limited here.

[0040] S120 , disposing a first die on a surface of a substrate.

[0041] In the embodiment of the present application, the first die 110 is disposed on the surface of the substrate 130 , and the first surface of the first die 110 is bonded to the substrate 130 . There are no metal contacts and pads on the first surface of the first die 110 . Therefore, there is no electrical connection between the first surface of the first die 110 and the substrate 130 .

[0042] S130 , connecting the second surface of the first crystal grain to the substrate through wire bonding to obtain a first connection structure.

[0043] In the embodiment of the present application, a pad is provided on the surface of the first crystal grain 110. The pad and the substrate 130 can be connected through a wire by wire bonding. The implementation method of wire bonding can refer to the existing technology or the existing bonding equipment, which will not be elaborated here.

[0044] S140 , welding the second surface of the second crystal grain to the second surface of the first crystal grain to obtain a second connection structure.

[0045] In the embodiment of the present application, welding the second surface of the second die 120 to the second surface of the first die 110 refers to welding the metal bumps on the second surface of the second die 120 to the metal bumps on the second surface of the first die 110 correspondingly.

[0046] When welding the first die 110 and the second die 120 , flux is used. Some flux residue may remain after welding. To prevent the flux from affecting chip performance, the flux usually needs to be cleaned.

[0047] See also Figure 3 and Figure 4 , Figure 3 It is a schematic diagram of the packaging process of the prior art. Figure 4 This is a schematic diagram of the packaging process provided in the embodiment of this application. Figure 3 As shown, in the prior art, the first die 110 and the second die 120 are usually welded, and then the first die 110 and the substrate 130 are wire-bonded. In the packaging method provided in this application, as shown in FIG. Figure 4 As shown, the present application first performs wire bonding on the first die 110 and the substrate 130 , and then welds the second die 120 and the first die 110 .

[0048] Compared to the method of first soldering the first die 110 and the second die 120 and then performing wire bonding, in the packaging method provided in this application, the first die 110 and the second die 120 are already wire-bonded before soldering the first die 110 and the second die 120. The wire is a thin metal wire, and when removing residual flux, it is necessary to avoid damaging the wire, which greatly increases the difficulty of cleaning the residual solder and flux.

[0049] Meanwhile, since the first die 110 has been wire-bonded to the substrate 130 , if any of the first die 110 , the second die 120 , or the wires is damaged during the cleaning process, the substrate 130 will also be scrapped.

[0050] Based on the above two reasons, the method of first wire bonding the first die 110 and the substrate 130 and then soldering the first die 110 and the second die 120 will increase the packaging difficulty, reduce the yield rate, and reduce the cost.

[0051] In view of this, in one embodiment of the present application, the second surface of the second grain 120 is welded to the second surface of the first grain 110 to obtain a second connection structure, which may include: using a water-soluble flux to weld the second surface of the second grain 120 to the second surface of the first grain 110; washing the second surface of the second grain 120 and the second surface of the first grain 110 with water to obtain the second connection structure.

[0052] When soldering the first die 110 and the second die 120, residual flux may remain. However, the narrow space between the first die 110 and the second die 120 after soldering makes it difficult to remove the residual flux. Therefore, in the embodiments of the present application, a water-soluble flux is used for soldering, which can be removed by washing with water. This helps to reduce the difficulty of cleaning the flux and minimize the residual flux, thereby reducing the impact of residual flux on the performance of the packaged chip. Furthermore, washing with water has a stronger ability to clean residual flux, effectively reducing the residual water-soluble flux and oxide, and improving the reliability of the packaged chip.

[0053] Some water-washing cleaning tools use high-speed water flow to dissolve and wash away the flux, but the high-speed water flow may also cause the metal wires to bend. Bent leads may affect the performance of the packaged chip. For example, different leads may be too close to each other or even fit together. In addition, high current heat may be more severe when the lead has certain shapes, affecting the yield rate.

[0054] Therefore, in other embodiments of the present application, welding the second surface of the second grain 120 to the second surface of the first grain 110 to obtain a second connection structure may also include: using a no-clean flux to weld the second grain 120 to the metal bumps of the first grain 110 to obtain a second connection structure.

[0055] No-clean flux is a chemical agent used to remove metal oxides, maintain a clean soldering surface, and enhance solder wettability. Its primary function is to remove oxides from the solder and base metal surfaces, preventing re-oxidation during soldering, reducing solder surface tension, and improving soldering performance. The composition of no-clean flux can be referenced in existing technology and will not be detailed here.

[0056] In this embodiment of the present application, the use of a no-clean flux effectively reduces flux and solder residue. This eliminates the need to clean the solder joint between the first die 110 and the second die 120, effectively preventing the metal leads from being bent during cleaning. Furthermore, the elimination of the need for cleaning simplifies the packaging process and helps improve packaging efficiency.

[0057] In some embodiments, after obtaining the first crystal grain and the second crystal grain, the second surface of the first crystal grain and the second surface of the second crystal grain may be plated with gold or nickel.

[0058] After the surface of the grain is plated with gold or nickel, the oxidation resistance of the surface of the grain can be effectively improved. Therefore, the second surface of the first grain and the second surface of the second grain are plated with gold or nickel, so that the oxidation resistance of the second surface of the first grain and the second surface of the second grain is improved, effectively reducing the oxides generated when the two are welded, thereby reducing the difficulty of cleaning, and when using a no-clean flux, even no cleaning is required.

[0059] In some embodiments of the present application, after the second connection structure is obtained, an insulating medium may be filled between the first die 110 and the second die 120 .

[0060] After the first crystal grain 110 and the second crystal grain 120 are welded, the metal bumps of the two will form a metal column 150 due to welding. In order to reduce the influence of external stress on the metal column 150, such as the stress caused by high temperature, pressure, collision, etc., it is necessary to fill an insulating medium between the first crystal grain 110 and the second crystal grain 120, thereby reducing the occurrence of cracks, fractures, etc. in the metal column 150 due to the influence of external stress, reducing the influence of external stress on the electrical performance of the packaged chip, and improving the electrical performance of the packaged chip.

[0061] The insulating medium may be insulating glue or epoxy resin, etc. For details, reference may be made to the dispensing process in the prior art, and no limitation is made here.

[0062] The space formed by soldering the first die 110 and the second die 120 is narrow, and there is also metal pillar 150 formed by the solder bump. Therefore, the insulating dielectric filling has fluidity, allowing the dielectric to flow into the middle part. However, due to the dielectric fluidity, the insulating dielectric may flow onto the pad of the first die 110, thereby blocking the pad.

[0063] In the prior art, first die 110 and second die 120 are soldered together, followed by filling an insulating medium between the first die 110 and the second die 120. Finally, wire bonding is performed between the first die 110 and the substrate 130. However, if the pad of the first die 110 is blocked by the insulating medium, wire bonding may not be possible. Therefore, prior art generally requires that sufficient distance be left between the pad of the first die 110 and the metal contact to reduce or prevent the insulating medium from flowing onto the pad.

[0064] In the embodiment of the present application, wire bonding is first performed on the first die 110 and the substrate 130, and then the first die 110 and the second die 120 are soldered. Therefore, in the packaging method provided by the present application, the insulating dielectric is actually filled after the wire bonding process. Accordingly, because the pad of the first die 110 has already been wire bonded, the insulating dielectric flowing onto the pad in a timely manner will not have any impact. Therefore, the problem of insulating dielectric contamination of the pad can be effectively solved. On this basis, there is no need to pre-set a certain distance for the insulating dielectric flow, thereby reducing the size of the first die 110 and meeting the requirements of miniaturization of the packaged chip in the packaging process.

[0065] S150 , packaging the second connection structure to obtain a packaged chip.

[0066] After the second connection structure is obtained, the second connection structure may be subsequently packaged, including but not limited to injection molding, ball planting, testing, etc. For details, reference may be made to the prior art and will not be elaborated here.

[0067] First, in the embodiment of the present application, during packaging, wire bonding is first performed between the first die 110 and the substrate 130, and then the first die 110 and the second die 120 are welded. Therefore, there is no need to worry about the first die 110 being blocked by the second die 120 during wire bonding with the substrate 130, and the restriction that the size of the first die 110 must be larger than the size of the second die 120 can be avoided.

[0068] Next, because the first die 110 has been wire-bonded to the substrate 130 before the first die 110 and the second die 120 are subjected to the dispensing process, even if the glue contaminates the pad, it will not affect the pad. Therefore, there is no need to reserve distance for the dispensing process.

[0069] Finally, because the second die 120 is not on the first die 110 during wire bonding, there is no need to worry about the wire bonding tool damaging the second die 120 , and thus the safety distance can be reduced.

[0070] Based on the above reasons, the restriction on the size of the first die 110 can be reduced, so that the size of the first die 110 is smaller, thereby achieving further miniaturization of the system-in-package chip.

[0071] At the same time, since the present application first performs wire bonding between the first die 110 and the substrate 130 and then welds the first die 110 and the second die 120 , the size of the second die 120 can be greater than or equal to the size of the first die 110 .

[0072] like Figure 3 As shown, when first soldering the first die 110 and the second die 120, and then wire bonding the first die 110 to the substrate 130, a pad must be reserved on the first die 110 for wire bonding after soldering the first die 110 and the second die 120, so that the first die 110 can be wire bonded to the substrate 130. Furthermore, wire bonding is a vertical tool, and during the process, it is necessary to avoid the tool from touching the second die 120 as much as possible to avoid damaging the second die 120. Therefore, the pad must be kept as far away from the second die 120 as possible. Therefore, due to the above two reasons, the size of the first die 110 needs to be larger than the second die 120, and the reserved distance will make the size of the first die 110 larger.

[0073] And as Figure 4 As shown, the present application first solders the first die 110 to the substrate 130. Therefore, there is no need to worry about the wire bonding tool damaging the second die 120, and there is no need to keep the pad away from the metal bumps on the first die 110. Therefore, the size of the first die 110 can be appropriately reduced.

[0074] At the same time, since the welding process is performed after the wire bonding process, the size of the second die 120 can also be greater than or equal to the size of the first die 110, and there is no need to worry about the second die 120 blocking the pad and making wire bonding impossible.

[0075] Therefore, the packaging method provided in the present application can satisfy the design solution that the size of the second die 120 is larger than the size of the first die 110 during the packaging stage, thereby enabling the chip design end to perform more free and flexible design.

[0076] In some embodiments of the present application, if there are multiple second dies 120 , the sum of the sizes of the multiple second dies 120 may be greater than or equal to the size of the first die 110 .

[0077] In the embodiment of the present application, because the second die 120 and the first die 110 need to be soldered to metal bumps, if the same packaged chip needs to package multiple second dies 120, the size of each second die 120 does not exceed the size of the first die 110, but the sum of the sizes of the multiple second dies 120 can be greater than or equal to the size of the first die 110. This packaging method removes the restriction that the sum of the sizes of the multiple second dies 120 must be smaller than the size of the first die 110, allowing for greater freedom and flexibility in chip design.

[0078] Based on the same inventive concept, an embodiment of the present application provides a packaged chip, which may include a first die 110, a second die 120, and a substrate 130. The first die 110, the second die 120, and the substrate 130 are packaged using the chip packaging method provided in the aforementioned embodiment.

[0079] In an embodiment of the present application, the packaged chip may be a processor chip or a memory chip.

[0080] The packaged chips of processors and memories usually require multiple dies to be packaged. Packaging the processor chip or memory chip based on the above packaging method can help further reduce the size of the processor or memory, or more dies can be packaged inside under the same size to further improve performance.

[0081] Based on the same inventive concept, an embodiment of the present application further provides a wearable device, which includes a packaged chip packaged by the packaging method provided in the aforementioned embodiment.

[0082] In the embodiments of the present application, the wearable device may be headphones, smart glasses, smart watches, smart bracelets, etc., which are not limited here.

[0083] Wearable devices have certain size restrictions to ensure they are easy for users to wear. Therefore, the chip size used needs to be as small as possible while maintaining the same performance, or the performance needs to be higher while maintaining the same size.

[0084] The above packaging method helps to meet the miniaturization requirements of multi-die flip-chip system-level packaging during the packaging stage, thereby meeting the requirements of wearable devices for packaged chip size.

[0085] The above embodiments can be freely combined without conflict, and the embodiments obtained by the combination are included in the protection scope of this application.

[0086] The above detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments derived by persons of ordinary skill in the art based on the embodiments in the present application without creative effort shall fall within the scope of protection of the present application.

[0087] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0088] It should also be noted that, in the description of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, it can mean a fixed connection, a detachable connection, or an integral connection; it can mean an electrical connection; it can mean a direct connection, an indirect connection through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0089] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A chip packaging method, characterized in that: include: obtaining a first die, a second die, and a substrate; Disposing the first crystal grain on the surface of the substrate; wherein the first surface of the first crystal grain is bonded to the substrate; Connecting the second surface of the first die to the substrate by wire bonding to obtain a first connection structure; wherein the second surface and the first surface are two opposite surfaces; welding the second surface of the second crystal grain to the second surface of the first crystal grain to obtain a second connection structure; The second connection structure is packaged to obtain a packaged chip.

2. The method according to claim 1, characterized in that The second surface of each of the first crystal grain and the second crystal grain comprises a metal bump; and the second surface of the second crystal grain is welded to the second surface of the first crystal grain to obtain a second connection structure, comprising: The second crystal grain is welded to the metal bump of the first crystal grain using a no-clean flux to obtain the second connection structure.

3. The method according to claim 2, characterized in that After obtaining the second connection structure, the method further includes: An insulating medium is filled between the first grain and the second grain.

4. The method according to claim 2, characterized in that The material of the metal bumps is copper, gold or tin-silver alloy.

5. The method according to claim 2, characterized in that The second surface of each of the first crystal grain and the second crystal grain includes a metal bump; after obtaining the first crystal grain, the second crystal grain and the substrate, the method further includes: The second surface of the first crystal grain and the second surface of the second crystal grain are plated with gold or nickel.

6. The method according to claim 1, characterized in that The second surface of each of the first crystal grain and the second crystal grain comprises a metal bump; and the second surface of the second crystal grain is welded to the second surface of the first crystal grain to obtain a second connection structure, comprising: welding the second surface of the second crystal grain to the second surface of the first crystal grain using a water-soluble flux; The second surface of the second crystal grain and the second surface of the first crystal grain are washed with water to obtain the second connection structure.

7. The method according to any one of claims 1 to 6, characterized in that The size of the second grain is greater than or equal to the size of the first grain.

8. The method according to any one of claims 1 to 6, characterized in that There are multiple second grains, and the sum of sizes of the multiple second grains is greater than or equal to the size of the first grain.

9. A packaged chip, characterized in that: include: a first die, a second die, and a substrate; The first die, the second die, and the substrate are packaged by the chip packaging method according to any one of claims 1 to 8.

10. The packaged chip according to claim 9, wherein: The packaged chip is a processor chip or a memory chip.

11. A wearable device, characterized in that: include: The packaged chip according to claim 9 or 10.

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