Chip structure and connection method of chip and heat dissipation substrate

Abstract

The embodiment of the invention provides a chip structure and a connection method of a chip and a heat dissipation substrate. The chip structure comprises a chip and a heat dissipation substrate used for conducting heat dissipation on the chip, a first metal layer structure is arranged on the upper surface of the chip, a second metal layer structure is arranged on the lower surface of the heat dissipation substrate, and the first metal layer structure and the second metal layer structure are adjacent and stacked. The chip and the heat dissipation substrate are connected together through the first metal layer structure and the second metal layer structure. Through the embodiment of the invention, the problem that the bonding difficulty between the chip and the heat dissipation substrate is increased due to the warping of the heat dissipation substrate in the related technology is solved, and the effect of improving the bonding reliability between the chip and the heat dissipation substrate is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of chip heat dissipation, and in particular to a chip structure and a method for connecting a chip to a heat dissipation substrate. Background Art

[0002] To achieve a connection between the chip and the heat sink substrate while ensuring a low interfacial thermal resistance at the bonding interface, surface activated bonding and thermal compression bonding are commonly used. However, both methods place extremely high demands on the flatness of the heat sink substrate. Warpage of the heat sink substrate will affect the bonding interface defects, thermal resistance, strength, and yield. For example, diamond grown using chemical vapor deposition (CVD) technology experiences a warpage of approximately 300 μm due to the difference in thermal expansion coefficient (CTE) between the diamond and the substrate, increasing the difficulty of bonding the diamond to the chip. Summary of the Invention

[0003] The embodiments of the present invention provide a chip structure and a method for connecting the chip to a heat dissipation substrate, so as to at least solve the problem in the related art that the warping of the heat dissipation substrate increases the difficulty of bonding between the chip and the heat dissipation substrate.

[0004] According to one embodiment of the present invention, a chip structure is provided, comprising: a chip and a heat dissipation substrate for dissipating heat from the chip, wherein a first metal layer structure is provided on the upper surface of the chip, and a second metal layer structure is provided on the lower surface of the heat dissipation substrate, wherein the first metal layer structure and the second metal layer structure are adjacent to and stacked with each other, and the chip and the heat dissipation substrate are connected together via the first metal layer structure and the second metal layer structure.

[0005] According to another embodiment of the present invention, a method for connecting a chip to a heat dissipation substrate is provided, comprising: providing a first metal layer structure on a chip, and providing a second metal layer structure on a heat dissipation substrate; performing plasma activation on the chip provided with the first metal layer structure and the heat dissipation substrate provided with the second metal layer structure; when the chip and the heat dissipation substrate have been subjected to the plasma activation, the first metal layer structure and the second metal layer structure are provided to be adjacent to and stacked, and pressure and temperature are applied to the chip and the heat dissipation substrate to cause an alloying reaction and atomic diffusion to occur between the first metal layer structure and the second metal layer structure, so as to connect the chip and the heat dissipation substrate.

[0006] Through the above-mentioned embodiments of the present invention, since a metal layer structure is provided on the chip and the heat dissipation substrate, the chip and the heat dissipation substrate are made flatter, and the influence of the warping of the heat dissipation substrate on the bonding can be reduced. Therefore, the problem in the related art that the warping of the heat dissipation substrate increases the difficulty of bonding between the chip and the heat dissipation substrate can be solved, thereby achieving the effect of improving the reliability of the bonding between the chip and the heat dissipation substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a chip structure provided by an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of a chip structure according to another embodiment of the present invention;

[0012] Figure 6 is a schematic diagram of a method for connecting a chip and a heat dissipation substrate according to an embodiment of the present invention;

[0013] Figure 7 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention;

[0014] Figure 8 is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention;

[0015] Figure 9 is a schematic diagram of a method for connecting a chip and a heat dissipation substrate according to an embodiment of the present invention;

[0016] Figure 10 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention;

[0017] Figure 11 FIG. 4 is a schematic diagram of a semiconductor package structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0019] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] For chips with high power and heat flux density, if a heat dissipation substrate with high thermal conductivity is connected to its surface, the chip can be effectively and quickly dissipated to reduce the temperature difference on the chip.

[0021] In order to meet the heat dissipation and connection reliability requirements of the chip, low thermal resistance, high bonding strength and high yield of the bonding interface between the chip and the heat dissipation substrate are key. An embodiment of the present invention proposes sputtering or evaporating a metal layer structure comprising multiple metal layers on the surface of the heat dissipation substrate and the chip. The multiple metal layers in the metal layer structure are multiple metal layers of different thicknesses and different metal materials, which may include an adhesion layer, a bonding layer, a barrier layer and a diffusion layer, and then bonding the chip with the metal layer structure to the heat dissipation substrate. Compared with other methods, by sputtering the metal layer structure, the effect of warping on bonding can be reduced or even eliminated, and the surface flatness of the heat dissipation substrate and the chip is smoother, which can avoid defects in the bonding interface between the heat dissipation substrate and the chip, and improve the bonding strength and yield. Moreover, using this metal layer structure, during the bonding heating and insulation stages, the bonding layer, barrier layer and diffusion layer undergo alloying reactions, as well as atomic diffusion between the metal layers in contact with the chip and the heat dissipation substrate, thereby further improving the bonding strength and avoiding defects in the bonding interface.

[0022] Figure 1 is a schematic diagram of a chip structure provided by an embodiment of the present invention, such as Figure 1 As shown, the chip structure includes: a chip and a heat dissipation substrate for dissipating heat from the chip, the upper surface of the chip is provided with a first metal layer structure, the lower surface of the heat dissipation substrate is provided with a second metal layer structure, the first metal layer structure and the second metal layer structure are adjacent to and stacked, and the chip and the heat dissipation substrate are connected together through the first metal layer structure and the second metal layer structure.

[0023] In the embodiments of the present invention, the terms "upper surface" and "lower surface" are used to describe the spatial relationship between the chip and the heat sink substrate, rather than to define fixed orientations. In some embodiments, the installation or use of the chip and heat sink substrate may cause the definition of "upper surface" and "lower surface" to vary depending on the environment or posture. However, in all cases, these terms are intended to describe a relative positional relationship, namely, the position of one surface relative to another, and this relationship is not affected by changes in the external reference coordinate system.

[0024] In this embodiment, the chip is a bare chip, which refers to the product form of a semiconductor component after it is manufactured and before it is packaged. The bare chip has an active side and a passive side. The active side is the side where the integrated circuit pattern is located, and the passive side is the side opposite the active side.

[0025] In this embodiment, the chip may include but is not limited to one of Si, SiC, GaN, and InP.

[0026] In this embodiment, the heat dissipation substrate includes but is not limited to one of the following: diamond on silicon substrate, bare diamond, diamond copper metal matrix composite material, diamond aluminum metal matrix composite material, silicon, silicon carbide, and gallium nitride.

[0027] In one embodiment, the silicon-based diamond includes but is not limited to one of the following: silicon-based single crystal diamond, silicon-based polycrystalline diamond, and silicon-based diamond heat sink.

[0028] In one embodiment, the bare diamond includes, but is not limited to, one of the following: single crystal diamond, polycrystalline diamond, and diamond heat sink.

[0029] In one embodiment, the first metal layer structure or the second metal layer structure includes one or more metal layers.

[0030] In one embodiment, the metal materials of any two adjacent metal layers in the multilayer metal layers of the first metal layer structure or the multilayer metal layers of the second metal layer structure are different, and the metal materials of the two metal layers in contact with the first metal layer structure and the second metal layer structure are the same.

[0031] Figure 2 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 2 As shown, the first metal layer structure and the second metal layer structure respectively include bonding layers, the bonding layer of the first metal layer structure is arranged on the chip, and the bonding layer of the second metal layer structure is arranged on the heat dissipation substrate, the bonding layer of the first metal layer structure is arranged adjacent to the bonding layer of the second metal layer structure, and the bonding layer of the first metal layer structure and the bonding layer of the second metal layer structure are connected together through atomic diffusion.

[0032] In one embodiment, the first metal layer structure includes a bonding layer and an adhesion layer. The adhesion layer of the first metal layer structure is arranged on the upper surface of the chip. The bonding layer of the first metal layer structure is arranged on the adhesion layer of the first metal layer structure. The adhesion layer of the first metal layer structure is used to enhance the bonding force between the bonding layer of the first metal layer structure and the chip.

[0033] In one embodiment, the second metal layer structure includes a bonding layer and an adhesion layer. The adhesion layer of the second metal layer structure is arranged on the lower surface of the heat dissipation substrate, and the bonding layer of the second metal layer structure is arranged on the adhesion layer of the second metal layer structure; the adhesion layer of the second metal layer structure is used to enhance the bonding force between the bonding layer of the second metal layer structure and the heat dissipation substrate.

[0034] In this embodiment, the bonding layer of the chip contacts the bonding layer of the heat dissipation substrate. A certain pressure and temperature are applied to the chip and the heat dissipation substrate by a bonding machine to cause atomic diffusion between the two bonding layers, thereby connecting the chip and the heat dissipation substrate.

[0035] Figure 3 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 3 As shown, except Figure 2 In addition to the bonding layer in the embodiment, the first metal layer structure may further include an adhesion layer, that is, the first metal layer structure may include an adhesion layer and a bonding layer, and the second metal layer structure may include an adhesion layer and a bonding layer.

[0036] Figure 4 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 4 As shown, except Figure 2 In addition to the bonding layer, the second metal layer structure may further include an adhesion layer, that is, the first metal layer structure may include an adhesion layer, and the second metal layer structure may include an adhesion layer and a bonding layer.

[0037] Figure 5 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 5 As shown, except Figure 2 In addition to the bonding layer, the first metal layer structure and the second metal layer structure may further include an adhesion layer, that is, the first metal layer structure may include an adhesion layer and a bonding layer, and the second metal layer structure may include an adhesion layer and a bonding layer.

[0038] Figure 6 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 6 As shown, except Figure 5 In addition to the metal layer shown, the first metal layer structure is also provided with a barrier layer and a diffusion layer in addition to the adhesion layer and the bonding layer. The barrier layer of the first metal layer structure is arranged on the bonding layer of the first metal layer structure to slow down the atomic diffusion rate between the bonding layer of the first metal layer structure and the diffusion layer of the first metal layer structure; the diffusion layer of the first metal layer structure is arranged on the barrier layer of the first metal layer structure to enhance the atomic diffusion performance between the second metal layer structure and the first metal layer structure, and the diffusion layer of the first metal layer structure is arranged adjacent to the second metal layer structure.

[0039] In this embodiment, the diffusion layer of the chip is in contact with the bonding layer of the heat dissipation substrate. A certain pressure and temperature are applied to the chip and the heat dissipation substrate by a bonding machine, so that atomic diffusion occurs between the diffusion layer of the chip and the bonding layer of the heat dissipation substrate, thereby connecting the chip and the heat dissipation substrate.

[0040] Figure 7 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 7 As shown, except Figure 5In addition to the metal layer shown, the second metal layer structure is also provided with a barrier layer and a diffusion layer in addition to the adhesion layer and the bonding layer. The barrier layer of the second metal layer structure is arranged on the bonding layer of the second metal layer structure to slow down the atomic diffusion rate between the bonding layer of the second metal layer structure and the diffusion layer of the second metal layer structure; the diffusion layer of the second metal layer structure is arranged on the barrier layer of the second metal layer structure to enhance the atomic diffusion performance between the second metal layer structure and the first metal layer structure. The bonding layer of the second metal layer structure is arranged adjacent to the first metal layer structure.

[0041] In this embodiment, the bonding layer of the chip is in contact with the diffusion layer of the heat dissipation substrate. A certain pressure and temperature are applied to the chip and the heat dissipation substrate by a bonding machine, so that atomic diffusion occurs between the bonding layer of the chip and the diffusion layer of the heat dissipation substrate, thereby connecting the chip and the heat dissipation substrate.

[0042] Figure 8 FIG. 1 is a schematic diagram of a chip structure according to another embodiment of the present invention. Figure 8 As shown, except Figure 5 In addition to the metal layer shown, the first metal layer structure and the second metal layer structure also include a barrier layer and a diffusion layer, respectively. The barrier layer of the first metal layer structure is arranged on the bonding layer of the second metal layer structure, and the barrier layer of the second metal layer structure is arranged on the bonding layer of the second metal layer structure. The diffusion layer of the first metal layer structure is arranged on the barrier layer of the first metal layer structure, and the diffusion layer of the second metal layer structure is arranged on the barrier layer of the second metal layer structure. The diffusion layer of the first metal layer structure is in contact with the diffusion layer of the second metal layer and is connected together through atomic diffusion.

[0043] In this embodiment, the diffusion layer of the chip contacts the diffusion layer of the heat dissipation substrate. A certain pressure and temperature are applied to the chip and the heat dissipation substrate by a bonding machine, so that atomic diffusion occurs between the diffusion layer of the chip and the diffusion layer of the heat dissipation substrate, thereby connecting the chip and the heat dissipation substrate.

[0044] In an embodiment of the invention, the diffusion layer and / or the barrier layer may also be based on Figure 2-4 Set the structure in any one, that is, Figure 2-4 A diffusion layer and / or a barrier layer may be further provided on the basis of any structure. The specific provision method may refer to the above embodiment, and will not be described in detail in this embodiment.

[0045] In one embodiment, the material of the adhesion layer or the barrier layer in the first metal layer structure or the second metal layer structure is one of the following: titanium, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron, or cobalt.

[0046] In one embodiment, the material of the bonding layer of the first metal layer structure or the second metal layer structure is one of the following: gold, copper, silver or aluminum.

[0047] In one embodiment, the material of the diffusion layer of the first metal layer structure or the second metal layer structure is one of the following: gold, copper, silver or tin.

[0048] In one embodiment, the thickness of the barrier layer in the first metal layer structure or the second metal layer structure is smaller than the thickness of the adhesion layer.

[0049] In one embodiment, the thickness of any metal layer in the first metal layer structure or the second metal layer structure is nanometer scale.

[0050] In one embodiment, any metal layer in the first metal layer structure or the second metal layer structure is provided by sputtering or evaporation.

[0051] Through the above-mentioned embodiments, since a metal layer structure is provided on the chip and the heat dissipation substrate, the chip and the heat dissipation substrate are made flatter, and the influence of the warping of the heat dissipation substrate on the bonding can be reduced. Therefore, the problem in the related art that the warping of the heat dissipation substrate increases the difficulty of bonding between the chip and the heat dissipation substrate can be solved, thereby improving the reliability of the bonding between the chip and the heat dissipation substrate.

[0052] Embodiments of the present invention provide a method for connecting a chip to a heat sink substrate, combining the advantages of low interfacial thermal resistance, high bonding strength, and bonding reliability. In this method, the chip and heat sink substrate comprise a metal layer structure. Specifically, two or four nanometal layers are sputtered or evaporated onto the surfaces of the chip and heat sink substrate. The chip and heat sink substrate are then plasma activated and then bonded together. Bonding is achieved under a specific pressure and temperature.

[0053] Figure 9 FIG. 1 is a schematic diagram of a method for connecting a chip to a heat dissipation substrate according to an embodiment of the present invention. Figure 9 As shown, the method includes the following steps:

[0054] Step S902 : Disposing a first metal layer structure on the chip and a second metal layer structure on the heat dissipation substrate.

[0055] In an exemplary embodiment, the first metal layer structure is provided on the chip, and the second metal layer structure is provided on the heat dissipation substrate, including: sputtering or evaporating a nano-metal layer, i.e., sputtering or evaporating a bonding layer, on the heat dissipation substrate and the chip surface respectively. The structure of the chip and the heat dissipation substrate after the metal layer is provided can be referred to. Figure 2 .

[0056] In this embodiment, the bonding layer on the chip or the heat dissipation substrate may include one of the following metals: Au, Cu, Ag, and Sn.

[0057] In this embodiment, the thicknesses of the bonding layers of the first metal layer structure and the second metal layer structure are both in the nanometer range.

[0058] In an exemplary embodiment, the first metal layer structure is provided on the chip, and the second metal layer structure is provided on the heat dissipation substrate, including: sputtering or evaporating a nano-metal layer, i.e., a bonding layer, on the surface of the chip, and sequentially sputtering or evaporating two nano-metal layers, i.e., an adhesion layer and a bonding layer, on the surface of the heat dissipation substrate. The structure of the chip and the heat dissipation substrate after the metal layers are provided can be referred to. Figure 3 .

[0059] In this embodiment, the adhesion layer on the heat dissipation substrate may include one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; the bonding layer on the chip or the heat dissipation substrate may include one of the following metals: Au, Cu, Ag and Sn.

[0060] In this embodiment, the thickness of each metal layer of the first metal layer structure and the second metal layer structure is in the nanometer level.

[0061] In an exemplary embodiment, the first metal layer structure is provided on the chip, and the second metal layer structure is provided on the heat dissipation substrate, including: sputtering or evaporating a nano-metal layer, i.e., a bonding layer, on the surface of the heat dissipation substrate, and sequentially sputtering or evaporating two nano-metal layers, i.e., an adhesion layer and a bonding layer, on the surface of the chip. The structure of the chip and the heat dissipation substrate after the metal layers are provided can be referred to. Figure 4 .

[0062] In this embodiment, the adhesion layer on the chip may include one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; the bonding layer on the chip or the heat dissipation substrate may include one of the following metals: Au, Cu, Ag and Sn.

[0063] In this embodiment, the thickness of each metal layer of the first metal layer structure and the second metal layer structure is in the nanometer level.

[0064] In an exemplary embodiment, the first metal layer structure is provided on the chip, and the second metal layer structure is provided on the heat dissipation substrate, including: sputtering or evaporating two nano-metal layers on the heat dissipation substrate and the chip surface respectively, which are an adhesion layer and a bonding layer, that is, the first metal layer structure or the second metal layer structure includes an adhesion layer and a bonding layer. The structure of the chip and the heat dissipation substrate after the metal layers are provided can be referred to. Figure 5 .

[0065] In this embodiment, the adhesion layer may include one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, and Co. The bonding layer may include one of the following metals: Au, Cu, Ag, and Sn. In this embodiment, the thickness of each metal layer in the first metal layer structure and the second metal layer structure is nanometer-scale.

[0066] In an exemplary embodiment, a first metal layer structure is provided on a chip, and a second metal layer structure is provided on a heat dissipation substrate, including: sputtering or evaporating four nano-metal layers on the surface of the chip, wherein the four nano-metal layers are sequentially an adhesion layer, a bonding layer, a barrier layer, and a diffusion layer from a side close to the chip to a side away from the chip; and sputtering or evaporating two nano-metal layers on the surface of the heat dissipation substrate, wherein the two nano-metal layers are sequentially an adhesion layer and a bonding layer from a side close to the heat dissipation substrate to a side away from the heat dissipation substrate; wherein the first metal layer structure includes an adhesion layer, a bonding layer, a barrier layer, and a diffusion layer; and the second metal layer structure includes an adhesion layer and a bonding layer.

[0067] In this embodiment, the chip or heat sink substrate adhesion layer can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co, the chip or heat sink substrate bonding layer can be one of the following metals: Au, Cu, Ag and Al, the chip barrier layer can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co, the chip diffusion layer can be one of the following metals: Au, Cu, Ag and Sn. The structure of the chip and heat sink substrate after the metal layer is set can refer to Figure 6 .

[0068] In this embodiment, the thickness of each metal layer in the first metal layer structure and the second metal layer structure is in the nanometer range.

[0069] In an exemplary embodiment, a first metal layer structure is provided on a chip, and a second metal layer structure is provided on a heat dissipation substrate, including: sputtering or evaporating two nano-metal layers on the surface of the chip, wherein the two nano-metal layers are sequentially an adhesion layer and a bonding layer from a side close to the chip to a side away from the chip; sputtering or evaporating four nano-metal layers on the surface of the heat dissipation substrate, wherein the four nano-metal layers are sequentially an adhesion layer, a bonding layer, a barrier layer and a diffusion layer from a side close to the heat dissipation substrate to a side away from the heat dissipation substrate; wherein the first metal layer structure includes an adhesion layer and a bonding layer; and the second metal layer structure includes an adhesion layer, a bonding layer, a barrier layer and a diffusion layer.

[0070] In this embodiment, the adhesion layer of the chip or heat sink substrate can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; the bonding layer of the chip or heat sink substrate can be one of the following metals: Au, Cu, Ag, and Al; the barrier layer of the heat sink substrate can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; and the diffusion layer of the chip can be one of the following metals: Au, Cu, Ag, and Sn. The structure of the chip and heat sink substrate after the metal layers are set can refer to Figure 7 .

[0071] In this embodiment, the thickness of each metal layer in the first metal layer structure and the second metal layer structure is in the nanometer range.

[0072] In an exemplary embodiment, setting a first metal layer structure on a chip and setting a second metal layer structure on a heat dissipation substrate include: sputtering or evaporating four nano-metal layers on the surface of both the chip and the heat dissipation substrate, namely, an adhesion layer, a bonding layer, a barrier layer and a diffusion layer, that is, the first metal layer structure or the second metal layer structure includes an adhesion layer and a bonding layer, a barrier layer and a diffusion layer.

[0073] In this embodiment, the adhesion layer of the chip or heat sink substrate can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; the bonding layer of the chip or heat sink substrate can be one of the following metals: Au, Cu, Ag, and Al; the barrier layer of the chip or heat sink substrate can be one of the following metals: Ti, Cr, Ni, Al, Mo, Ta, W, Fe, Co; the diffusion layer of the chip or heat sink substrate can be one of the following metals: Au, Cu, Ag, and Sn. The structure of the chip and heat sink substrate after the metal layers are set can refer to Figure 8 .

[0074] In this embodiment, the thickness of each metal layer in the first metal layer structure and the second metal layer structure is in the nanometer range.

[0075] In the embodiment of the present invention, the function of the adhesion layer is to improve the bonding force between the metal layer and the substrate, that is, to improve the bonding force between the chip and the bonding layer, or to improve the bonding force between the heat dissipation substrate and the bonding layer; the function of the second bonding layer is to realize the atomic diffusion between the metal layer and the barrier layer and the diffusion layer under the influence of temperature, so as to avoid the generation of gaps in the bonding interface; the function of the third barrier layer is to avoid rapid diffusion of atoms between the bonding layer and the diffusion layer; the function of the fourth diffusion layer is that it has good wettability, which can ensure good atomic diffusion between the chip and the heat dissipation substrate during the bonding temperature rise stage, thereby forming a reliable bonding interface.

[0076] Before step S902 of this embodiment, the method further includes: cleaning the surface of the chip and the heat dissipation substrate.

[0077] In an exemplary embodiment, the surface of the chip and the heat sink substrate are cleaned, including: rinsing the chip and the heat sink substrate surface with deionized water, then cleaning the chip and the heat sink substrate in a solution of concentrated sulfuric acid: hydrogen peroxide = 4:1, wherein the pickling solution is 150°C and the cleaning time is 15 minutes, and finally rinsing with deionized water and drying with N2 air flow to remove surface contaminants.

[0078] In this embodiment, the chip is a bare chip, which may be made of Si, SiC, GaN, or InP.

[0079] In this embodiment, the heat dissipation substrate is one of bare diamond (including single crystal diamond, polycrystalline diamond, diamond heat sink), silicon-based diamond (including silicon-based single crystal diamond, polysilicon-based crystal diamond and silicon-based diamond heat sink), diamond copper / aluminum metal matrix composite material, Si, SiC, and GaN. Among them, the thermal conductivity of single crystal diamond, polycrystalline diamond, diamond heat sink and silicon-based diamond is greater than 1000W / (mk), the thermal conductivity of diamond copper and diamond aluminum metal composite material is greater than 300W / (mk), and the thermal conductivity of Si, SiC and GaN is greater than 50W / (mk). The thickness of the above heat dissipation sink materials is in the micron level, the surface roughness is in the nanometer level, and the flatness is in the micron level. Furthermore, compared to bare diamond, silicon-based diamond activates the silicon surface when bonding to the chip. Therefore, silicon-based diamond is more likely to activate the bonding surface, giving it more hydroxyl groups, improving the quality and strength of the bonding interface, and meeting the surface roughness required for bonding. Silicon-based diamond polishes the silicon surface, significantly reducing the difficulty and cycle time of polishing the bonding surface, thereby lowering costs. Compared to bare diamond wafers, the surface processing cycle and cost of silicon-based diamond are only 1 / 2 and 1 / 3 of the former, respectively.

[0080] In this embodiment, the nano-metal layer is sputtered or evaporated on the passive surface of the bare chip to prevent the metal layer from affecting the circuit connection of the chip.

[0081] Step S904 : Plasma activation is performed on the chip provided with the first metal layer structure and the heat dissipation substrate provided with the second metal layer structure.

[0082] In one embodiment, the plasma includes, but is not limited to, one of the following: argon, oxygen, hydrogen.

[0083] Step S906 , when the chip and the heat dissipation substrate are plasma activated, the first metal layer structure and the second metal layer structure are arranged adjacent to each other and stacked, so that atomic diffusion occurs between the first metal layer structure and the second metal layer structure to connect the chip and the heat dissipation substrate.

[0084] In step S906 of this embodiment, the first metal layer structure is brought into contact with the second metal layer structure, and pressure and temperature are applied to the chip and the heat dissipation substrate, including: bringing the first metal layer structure into contact with the second metal layer structure, and applying a first pressure for a first duration to the chip and the heat dissipation substrate at a first temperature; and when the first duration has expired, applying a second pressure for a second duration to the chip and the heat dissipation substrate at a second temperature.

[0085] In this embodiment, the first temperature is lower than the second temperature, the first pressure is lower than the second pressure, and the first duration is lower than the second duration.

[0086] In an exemplary embodiment, the first temperature is not lower than 20°C, the second temperature is not higher than 260°C, and the first temperature is lower than the second temperature; the first pressure is lower than the second pressure, the second pressure does not exceed 50MPa, and the first duration is less than or equal to the second duration. Based on the above parameter settings, the process of heating and pressurizing the chip and the heat dissipation substrate is divided into two stages. For example, in the first stage, the first pressure ranges from 0.1 to 30MPa, the first temperature ranges from 20 to 80°C, and the first duration is 60 to 3600s; in the second stage, the second pressure ranges from 1 to 50MPa, the second temperature ranges from 150 to 260°C, and the second duration is 60 to 3600s. Through the above two stages of heating and pressurizing, a reliable connection between the chip and the heat dissipation substrate can be achieved at a temperature not higher than 260°C and a pressure not exceeding 50MPa. The process conditions are simple and easy to implement.

[0087] Through the above-mentioned method embodiment of the present invention, the influence of warping on bonding can be offset by sputtering or evaporating a metal layer, so that the surface of the heat dissipation substrate has better flatness, avoiding defects in the bonding interface between the chip and the heat dissipation substrate, and improving thermal resistance, strength and yield; due to the use of a combination of metal layers, namely the first metal layer and the second metal layer, during the bonding heating and insulation stages, an alloying reaction occurs between the bonding layer, the barrier layer and the diffusion layer, and atomic diffusion between the metal layers in contact with the chip and the heat dissipation substrate can eliminate defects in the bonding interface, improve bonding strength and bonding reliability, and can complete the bonding of the chip and the heat dissipation substrate at a lower temperature while having higher bonding reliability.

[0088] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of various embodiments of the present invention.

[0089] The present invention is further described below with reference to specific embodiments.

[0090] Example 1

[0091] A chip structure is prepared by the following method:

[0092] Step S11, cleaning the surface of the chip and the heat dissipation substrate.

[0093] Specifically, the cleaning process is as follows:

[0094] First, rinse the chip and heat sink substrate surface with deionized water, then clean the chip and heat sink substrate in a solution of concentrated sulfuric acid: hydrogen peroxide = 4:1, where the pickling solution is 150°C and the time is 15 minutes. Finally, rinse with deionized water and blow dry with N2 flow to remove surface contaminants.

[0095] In step S12, four nano-metal layers are sputtered in sequence on the surface of the chip and the heat dissipation substrate, namely a 60nm Ti first metal layer (i.e., adhesion layer), a 310nm Al second metal layer (i.e., bonding layer), a 40nm Ti third metal layer (i.e., barrier layer) and a 300nm Au fourth metal layer (i.e., diffusion layer).

[0096] Step S13: performing argon plasma treatment on the surface of the chip and the heat dissipation substrate.

[0097] Specifically, the processing conditions of the argon plasma treatment are as follows: argon gas flow rate = 400 sccm, pressure = 300 Pa, power = 1000 W, time = 60 s.

[0098] Step S14: placing the plasma-treated chip and the heat dissipation substrate in a bonding machine for bonding.

[0099] Specifically, the overlapping chips and heat dissipation substrate are kept at 20° C. for 60 seconds under a constant pressure of 1 MPa by a bonding machine; then the temperature is raised to 200° C., kept at 200° C. for 60 seconds, and then cooled.

[0100] After the above treatment, the chip containing the metal layer structure and the heat dissipation substrate obtained had an interface thermal resistance of 0.09 (mm2·K) / W, a fracture energy of 2.5J / m-2, a bonding area of ​​100%, and microstructural analysis showed that no defects were observed at the bonding interface.

[0101] Example 2

[0102] A chip structure is prepared by the following method:

[0103] Step S21, cleaning the chip and the surface of the heat dissipation substrate.

[0104] The specific cleaning process can be referred to Example 1, which will not be described in detail in this embodiment.

[0105] In step S22, four nano-metal layers are sequentially sputtered on the surface of the chip and the heat dissipation substrate, namely a first metal layer of 50nm Ti, a second metal layer of 500nm Cu, a third metal layer of 20nm Ti and a fourth metal layer of 500nm Au.

[0106] Step S23: performing oxygen plasma treatment on the surface of the chip and the heat dissipation substrate.

[0107] Specifically, the treatment conditions of the oxygen plasma treatment are as follows: argon gas flow rate = 600 sccm, pressure = 400 Pa, power = 1100 W, time = 300 s.

[0108] Step S24: placing the plasma-treated chip and the heat dissipation substrate in a bonding machine for bonding.

[0109] Specifically, a bonding machine applies a pressure of 0.1 MPa to the overlapping chips and heat dissipation substrate at 80°C and maintains it for 1800 seconds; then the temperature is raised to 260°C, and a pressure of 10 MPa is applied to the overlapping heat sink and chip at 260°C and maintained for 1800 seconds, and then the temperature is lowered.

[0110] After the above treatment, the chip containing the metal layer structure and the heat dissipation substrate obtained had an interface thermal resistance of 0.15 (mm2·K) / W, a fracture energy of 2.4J / m-2, a bonding area of ​​100%, and microstructural analysis showed that no defects were observed at the bonding interface.

[0111] Example 3

[0112] A chip structure is prepared by the following method:

[0113] Step S31, cleaning the chip and the surface of the heat dissipation substrate.

[0114] The specific cleaning process can be referred to Example 1, which will not be described in detail in this embodiment.

[0115] In step S32, four nano-metal layers are sequentially sputtered on the heat dissipation substrate surface: a 100nm Cr first metal layer, a 300nm Al second metal layer, a 10nm Ti third metal layer, and a 100nm Cu fourth metal layer. Two nano-metal layers are sequentially sputtered on the chip surface: a 50nm Cr first metal layer and a 100nm Cu second metal layer.

[0116] Step S33, performing oxygen plasma treatment on the chip and the heat dissipation substrate surface,

[0117] Specifically, the treatment conditions of the oxygen plasma treatment are as follows: oxygen flow rate = 300 sccm, pressure = 200 Pa, power = 800 W, time = 60 s.

[0118] Step S34: placing the plasma-treated chip and the heat dissipation substrate in a bonding machine for bonding.

[0119] Specifically, the overlapping chips and heat dissipation substrate are kept at 20° C. for 120 seconds at a constant pressure of 3 MPa by a bonding machine; then the temperature is raised to 180° C., kept at 180° C. for 300 seconds, and then cooled.

[0120] After the above treatment, the chip containing the metal layer structure and the heat dissipation substrate obtained have an interface thermal resistance of 0.12 (mm2·K) / W, a fracture energy of 2.4 J / m-2, and a bonding area of ​​100%.

[0121] Example 4

[0122] A chip structure is prepared by the following method:

[0123] Step S41, cleaning the surface of the chip and the heat dissipation substrate.

[0124] The specific cleaning process can be referred to Example 1, which will not be described in detail in this embodiment.

[0125] Step S42 , sputtering two nano-metal layers on the surface of the chip and the heat dissipation substrate in sequence, which are a first metal layer of 80nm Ti and a second metal layer of 200nm Ag.

[0126] Step S43, performing argon plasma treatment on the chip and the heat dissipation substrate surface,

[0127] Specifically, the processing conditions of the argon plasma treatment are as follows: hydrogen flow rate = 200 sccm, pressure = 400 Pa, power = 1000 W, time = 120 s.

[0128] Step S44: placing the plasma-treated chip and the heat dissipation substrate in a bonding machine for bonding.

[0129] Specifically, the overlapping chips and heat dissipation substrate are kept at 20° C. for 180 seconds at a constant pressure of 2 MPa by a bonding machine; then the temperature is raised to 240° C., kept at 240° C. for 60 seconds, and then cooled.

[0130] After the above treatment, the chip containing the metal layer structure and the heat dissipation substrate obtained have an interface thermal resistance of 0.082 (mm2·K) / W, a fracture energy of 2.3 J / m-2, and a bonding area of ​​100%.

[0131] The chip structure in each of the above embodiments of the present invention can be applied to a semiconductor packaging structure. Figure 10 Schematic diagram of a semiconductor package structure according to an embodiment of the present invention. Figure 10As shown, the semiconductor packaging structure includes a packaging substrate, a chip, a heat dissipation substrate, a first thermal interface material (TIM1), a heat dissipation cover, a second thermal interface material (TIM2), and a heat sink. The chip is attached to the supporting surface of the packaging substrate with a C4 ball through a bump and an underfill. After the chip and the heat dissipation substrate are connected using the method described in the above embodiment, they are arranged in the semiconductor packaging structure. After the back of the chip and the heat dissipation substrate are connected, they are located between the bump and the TIM1. The TIM1 is arranged on the surface of the heat dissipation substrate, so that the chip after bonding to the heat dissipation substrate is connected to the heat dissipation cover. The heat sink for dissipating the heat generated by the chip is connected to the heat dissipation cover through the TIM2.

[0132] Figure 11 Schematic diagram of a semiconductor package structure according to another embodiment of the present invention. Figure 11 As shown, the semiconductor package structure includes a package substrate, a chip, a heat sink substrate, a thermal interface material (TIM1.5), and a heat sink. The chip is bonded to the supporting surface of the package substrate with a C4 ball via a bump and underfill. After the chip and the heat sink substrate are connected using the method described in the above embodiment, they are placed in the semiconductor package structure. After the back of the chip and the heat sink substrate are connected, they are positioned between the bump and the TIM1.5. The TIM1.5 is placed on the surface of the heat sink substrate, connecting the chip, after bonding to the heat sink substrate, to the heat sink used to dissipate the heat generated by the chip.

[0133] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that: include: A chip and a heat dissipation substrate for dissipating heat from the chip, wherein a first metal layer structure is provided on the upper surface of the chip, and a second metal layer structure is provided on the lower surface of the heat dissipation substrate, the first metal layer structure and the second metal layer structure are adjacent to and stacked with each other, and the chip and the heat dissipation substrate are connected together through the first metal layer structure and the second metal layer structure.

2. The chip structure according to claim 1, characterized in that: in, The first metal layer structure or the second metal layer structure includes one or more metal layers.

3. The chip structure according to claim 2, characterized in that: in, The metal materials of any two adjacent metal layers in the multilayer metal layers of the first metal layer structure or the multilayer metal layers of the second metal layer structure are different, and the metal materials of the two metal layers in contact with the first metal layer structure and the second metal layer structure are the same.

4. The chip structure according to claim 1, wherein: in, The first metal layer structure and the second metal layer structure respectively include a bonding layer, the bonding layer of the first metal layer structure is arranged on the chip, and the bonding layer of the second metal layer structure is arranged on the heat dissipation substrate. The bonding layer of the first metal layer structure is arranged adjacent to the bonding layer of the second metal layer structure, and the bonding layer of the first metal layer structure and the bonding layer of the second metal layer structure are connected together through atomic diffusion.

5. The chip structure according to claim 1, characterized in that: in, The first metal layer structure includes a bonding layer and an adhesion layer. The adhesion layer of the first metal layer structure is arranged on the upper surface of the chip. The bonding layer of the first metal layer structure is arranged on the adhesion layer of the first metal layer structure. The adhesion layer of the first metal layer structure is used to enhance the bonding force between the bonding layer of the first metal layer structure and the chip.

6. The chip structure according to claim 1, characterized in that: in, The second metal layer structure includes a bonding layer and an adhesion layer, the adhesion layer of the second metal layer structure is arranged on the lower surface of the heat dissipation substrate, and the bonding layer of the second metal layer structure is arranged on the adhesion layer of the second metal layer structure; The second metal layer structure adhesion layer is used to enhance the bonding force between the bonding layer of the second metal layer structure and the heat dissipation substrate.

7. The chip structure according to any one of claims 4 to 6, characterized in that: in, The first metal layer structure further includes a barrier layer and a diffusion layer, wherein the barrier layer of the first metal layer structure is arranged on the bonding layer of the first metal layer structure and is used to slow down the atomic diffusion speed between the bonding layer of the first metal layer structure and the diffusion layer of the first metal layer structure; The diffusion layer of the first metal layer structure is arranged on the barrier layer of the first metal layer structure to enhance the atomic diffusion performance between the second metal layer structure and the first metal layer structure. The diffusion layer of the first metal layer structure is arranged adjacent to the second metal layer structure.

8. The chip structure according to any one of claims 4 to 6, characterized in that: in, The second metal layer structure further includes a barrier layer and a diffusion layer, wherein the barrier layer of the second metal layer structure is arranged on the bonding layer of the second metal layer structure and is used to slow down the atomic diffusion rate between the bonding layer of the second metal layer structure and the diffusion layer of the second metal layer structure; The diffusion layer of the second metal layer structure is arranged on the barrier layer of the second metal layer structure to enhance the atomic diffusion performance between the second metal layer structure and the first metal layer structure. The bonding layer of the second metal layer structure is arranged adjacent to the first metal layer structure.

9. The chip structure according to claim 1, wherein: in, The heat dissipation substrate includes one of the following: silicon-based diamond, bare diamond, diamond-copper metal-based composite material, diamond-aluminum metal-based composite material, silicon, silicon carbide, and gallium nitride.

10. The chip structure according to claim 9, characterized in that: in, The silicon-based diamond includes one of the following: silicon-based single crystal diamond, silicon-based multi-crystal diamond and silicon-based diamond heat sink.

11. The chip structure according to claim 9, characterized in that: in, The bare diamond includes one of the following: single crystal diamond, polycrystalline diamond, and diamond heat sink.

12. The chip structure according to claim 8, characterized in that: in, The material of the adhesion layer or the barrier layer in the first metal layer structure or the second metal layer structure includes one of the following: titanium, chromium, nickel, aluminum, molybdenum, tantalum, tungsten, iron or cobalt.

13. The chip structure according to claim 8, characterized in that: in, The material of the bonding layer of the first metal layer structure or the second metal layer structure includes one of the following: gold, copper, silver or aluminum.

14. The chip structure according to claim 8, characterized in that: in, The material of the diffusion layer of the first metal layer structure or the second metal layer structure includes one of the following: gold, copper, silver or tin.

15. The chip structure according to claim 8, characterized in that: in, The thickness of the barrier layer in the first metal layer structure or the second metal layer structure is smaller than the thickness of the adhesion layer.

16. The chip structure according to claim 2, characterized in that: in, The thickness of any metal layer in the first metal layer structure or the second metal layer structure is in the nanometer level.

17. The chip structure according to claim 2, characterized in that: in, Any metal layer in the first metal layer structure or the second metal layer structure is provided by sputtering or evaporation.

18. A method for connecting a chip to a heat dissipation substrate, characterized in that: include: Disposing a first metal layer structure on the upper surface of the chip, and disposing a second metal layer structure on the lower surface of the heat dissipation substrate; Plasma activation of a chip provided with the first metal layer structure and a heat dissipation substrate provided with the second metal layer structure; When the chip and the heat dissipation substrate are activated by the plasma, the first metal layer structure and the second metal layer structure are arranged to be adjacent to and stacked, and pressure and temperature are applied to the chip and the heat dissipation substrate to cause alloying reaction and atomic diffusion between the first metal layer structure and the second metal layer structure to connect the chip and the heat dissipation substrate.

19. The method according to claim 18, characterized in that The method comprises: arranging the first metal layer structure and the second metal layer structure to be adjacent to each other and stacking them, and applying pressure and temperature to the chip and the heat dissipation substrate, comprising: Disposing a first metal layer structure and a second metal layer structure adjacent to each other and stacking them, and applying a first pressure of a first duration to the chip and the heat dissipation substrate at a first temperature; When the first period of time has ended, a second pressure is applied to the chip and the heat dissipation substrate for a second period of time at a second temperature.

20. The method according to claim 19, characterized in that in, The first temperature is lower than the second temperature, the first pressure is lower than the second pressure, and the first duration is lower than the second duration.

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