Lead frame panel, semiconductor package including lead frame, and method of manufacturing same

Abstract

A lead frame panel (10) comprising: a plurality of lead frames (11), where each of the plurality of lead frames (11) comprises a die pad (11A) and a first plurality of leads (11B, 11B. 1), where the leads (11B, 11B. 1) are arranged side by side in a row on a first side of the die pad, where at least a first outermost lead (11B. 1) is connected to the die pad (11A); a first barrier strip (11C) that connects all the leads (11B, 11B. 1) to each other; the first barrier strip (11D) is connected with a first outermost lead, the second barrier strip (11D) is connected with a first outermost lead, the first barrier strip and the second barrier strip are located in the same plane, and the position of the second barrier strip relative to a bare chip bonding pad is different from the position of the first barrier strip relative to the bare chip bonding pad.

Description

Technical Field

[0001] The present disclosure relates to a lead frame panel, a semiconductor package, and a method for manufacturing a semiconductor package. Background Art

[0002] In the manufacture of semiconductor component packages, large-format leadframe panels are often used, which contain a large number of individually interconnected leadframes. Each individual leadframe contains at least one die pad and a large number of leads or other types of external contacts. This large-format leadframe panel is fed one by one into various processing stations, where all the individual leadframes it contains undergo various parallel processing operations. For example, in one processing station, a semiconductor die is applied to the die pads of a leadframe. In a subsequent processing station, connecting wires are attached between the individual connection points. In another subsequent processing station, the individual leadframes are encapsulated by applying molding material.

[0003] It is easy to imagine that a problem may occur in one of these processing stations, making further processing difficult or even impossible.Such a problem has been discovered by the inventors and forms the basis of the present disclosure. Summary of the Invention

[0004] In the past, during the manufacturing process of certain package types, it was increasingly observed that the die pad of the leadframe could warp during application of the semiconductor die to the die pad due to a CTE mismatch between the semiconductor die and the die pad. The semiconductor die is typically applied to the die pad by diffusion bonding. The higher the soldering temperature, the greater the resulting die pad warpage. This die pad warpage can cause the entire leadframe panel to warp, which subsequently renders further processing impossible. This problem is particularly pronounced when a semiconductor die made of SiC is applied to a copper die pad by diffusion bonding due to the difference in CTE between SiC and Cu, but it can also occur with other combinations.

[0005] For these and other reasons, there is a need for the present disclosure.

[0006] Figure 1 The initial problem described above is shown. Figure 1 In its upper section is shown a large frame surrounding a conventional lead frame panel or strip 10 comprising a plurality of individual interconnected lead frames 11, one of which is shown in enlarged section in the small frame on the right, and Figure 1 The warping of the lead frame panel after the semiconductor die is mounted on the die pad by a diffusion soldering process is shown in the lower section.

[0007] from Figure 1As can be seen in the enlarged section of FIG, each lead frame 11 includes a central die pad 11A and a first plurality of leads 11B connected to the die pad 11A and arranged side by side in a row on a first upper side of the die pad 11A. Lateral ridges 11C interconnect all leads 11B in the first plurality of leads 11B. The lead frame 11 also includes a second plurality of leads arranged side by side in a row on a second lower side of the die pad 11A. These second plurality of leads are intended to be connected to contact pads on the upper surface of the semiconductor die via connecting wires for attachment to the die pad 11A in a subsequent process step.

[0008] Figure 1 The lower section of the graph shows measured warpage of the leadframe panel 10 after the semiconductor die is mounted on the die pad. The resulting curves represent measurement data for the leadframe coil assembly after a diffusion soldering process at 410°C. However, it is conceivable that other high-temperature application methods, such as soft soldering with high connection force, could achieve similar results. Warpage is simulated by assuming only a specific CTE value between the semiconductor die and the die pad and neglecting gravity. The resulting curves are assumed to be acquired at room temperature on the top surface of the leadframe panel in the tie-bar area after the die attach process. These curves relate to different types of TOLT packages. The warpage of individual leadframes can be identified in each curve, where the warpage is cumulatively accounted for by the warpage of the entire leadframe panel. The dam bar is a critical structure in the TOLT leadframe panel as it transfers cell-level warpage to strip-level warpage. Maximum warpage occurs in the center of the leadframe panel.

[0009] A first aspect of the present disclosure relates to a lead frame panel comprising: a plurality of lead frames, wherein each of the plurality of lead frames includes a die pad and a first plurality of leads, wherein the leads are arranged side by side in a row on a first side of the die pad, wherein at least a first outermost lead is connected to the die pad; a first dam connecting all the leads to each other; and a second dam connected to the first outermost lead, wherein the first dam and the second dam are located in the same plane, and a position of the second dam relative to the die pad is different from a position of the first dam relative to the die pad.

[0010] According to an embodiment of the lead frame panel of the first aspect, the second dam is located at a position farther away from the die pad than the first dam. Alternatively, the second dam may be located closer to the die pad than the first dam.

[0011] As shown below, this structure can break the inherent stress generated from the die pad level to the lead frame level when the die pad warpage is transferred through the leads to the lead frame tie bars.

[0012] According to one embodiment of the lead frame panel of the first aspect, the lead frame panel further comprises a first auxiliary structure, wherein the second dam is connected between the first outermost lead and the first auxiliary structure. The first auxiliary structure can, in principle, be any supporting component of the lead frame, such as a simple metal piece that connects a single lead frame to another adjacent lead frame. It does not become part of the single lead frame encapsulated in the final semiconductor package.

[0013] According to an embodiment of the lead frame panel of the first aspect, the lead frame panel further comprises: a second outermost lead arranged at the second outermost position of the plurality of leads; and a third barrier connected to the second outermost lead, wherein the first barrier and the third barrier are located in the same plane, and the position of the third barrier relative to the die pad is different from the position of the first barrier relative to the die pad. Otherwise, the same conditions as described above for the second barrier are satisfied.

[0014] Also in combination with the above embodiment, the lead frame panel may further include a second auxiliary structure, wherein the third blocking bar is connected to the second auxiliary structure. The above conditions related to the first auxiliary structure are also applicable to the second auxiliary structure.

[0015] Therefore, this embodiment means that the second and third dams are symmetrically located on opposite sides of the pad, which makes it possible to better break the inherent stress of the lead frame.

[0016] According to one embodiment of the lead frame panel of the first aspect, not only the outermost leads but each lead is connected to the die pad.

[0017] According to an embodiment of the lead frame panel of the first aspect, the lead frame panel further comprises a second plurality of leads, wherein the leads are arranged side by side in a row on a second side of the die pad, the second side being opposite to the first side. According to one example, the lead frame panel further comprises a fourth dam bar interconnecting all of the leads.

[0018] According to an embodiment of the lead frame panel of the first aspect, each lead frame of the lead frame panel is a preform of a TO-Lead Top Side Cooled (TOLT) package.

[0019] According to an embodiment of the lead frame panel of the first aspect, each lead frame of the lead frame panel is made of copper or a copper alloy. According to an example, the lead frame comprises a coating of Ni, Ni / NiP, Ni / NiNiP or any other suitable coating.

[0020] A second aspect of the present disclosure relates to a semiconductor package, comprising: a lead frame including a die pad and a first plurality of leads; and a semiconductor die disposed on the die pad, wherein the leads are arranged side by side in a row on a first side of the semiconductor device package, wherein a first outermost lead arranged at a first outermost position of the first plurality of leads has a structure different from structures of the other leads, wherein at least the first outermost lead is connected to the die pad, and wherein each lead includes a first dam stub located at a first upper level, and the first outermost lead also includes a second dam stub located at a second lower level.

[0021] According to one embodiment of the semiconductor device package of the second aspect, a second lead of the first plurality of leads includes a third dam remnant located at the second lower level. The second lead may be an outermost lead opposite the first outermost lead. In another embodiment, the first outermost lead and the second lead are arranged on the same side of the semiconductor package.

[0022] According to one embodiment of the semiconductor device package of the second aspect, one or both of the second dam remnant portion of the first outermost lead or the third dam remnant portion of the outermost lead include a trapezoidal cross-section.

[0023] According to an embodiment of the semiconductor device package of the second aspect, each lead includes a first upper horizontal portion, a bent portion, and a second lower horizontal portion, wherein the first dam of the lead is located in the first upper horizontal portion, and the second dam of the first outermost lead and the third dam of the second outermost lead are located in the bent portion.

[0024] According to an embodiment of the semiconductor device package of the second aspect, each lead includes a first upper horizontal portion, a bent portion, and a second lower horizontal portion, wherein a first dam remnant of the lead is located in the bent portion, and a second dam remnant of the first outermost lead and a third dam remnant of the second outermost lead are located in the lower horizontal portion or partially overlap with the bent portion.

[0025] It is important to note that in both embodiments described above, the first bar remnant on the one hand and the second and third bar remnants on the other hand are not positioned along the same straight line.

[0026] According to an embodiment of the semiconductor device package of the second aspect, each of the first plurality of leads is connected to the die pad. In one embodiment, "connected" means that the first plurality of leads and the die pad are made of the same piece of metal and there is no manufactured junction between the leads and the die pad.

[0027] According to an embodiment of the semiconductor device package of the second aspect, the package further comprises a second plurality of leads, wherein the leads are arranged side by side in a row on a second side of the semiconductor device package, the second side being opposite to the first side.

[0028] According to an embodiment of the semiconductor device package of the second aspect, the second plurality of leads are identically formed and include dam remnants located at the first upper level.

[0029] According to an embodiment of the semiconductor device package of the second aspect, the semiconductor die includes a semiconductor transistor die.

[0030] According to an embodiment of the semiconductor device package of the second aspect, the semiconductor die includes one or more of a horizontal semiconductor transistor die, a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die (particularly a SiC transistor die or a GaN transistor die).

[0031] According to an embodiment of the semiconductor device package of the second aspect, the package may be any type of SMD package, an example of which is a TO-Lead Top-Side Cooled (TOLT) type package.

[0032] According to an embodiment of the semiconductor package of the second aspect, the lead frame is made of copper or a copper alloy. According to an example, the lead frame includes a coating of Ni, Ni / NiP, Ni / NiNiP or any other suitable coating.

[0033] A third aspect of the present disclosure relates to a method for manufacturing a semiconductor device package, the method comprising providing a lead frame panel according to the first aspect, attaching a semiconductor die to a die pad of the lead frame, encapsulating the lead frame and cutting a first dam bar located between the leads, singulating the lead frame, and bending outer ends of the leads. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily understood as they become better understood by reference to the following detailed description.

[0035] The elements in the drawings are not necessarily drawn to scale relative to each other. Identical or similar reference numbers designate identical or similar parts.

[0036] Figure 1The upper section shows a conventional lead frame panel or strip, and the lower section is a diagram showing the warpage of the lead frame panel after mounting a semiconductor die on a die pad by a diffusion bonding process.

[0037] Figure 2 Shown is a section of a lead frame panel and an enlarged section thereof according to one embodiment.

[0038] Figure 3 Shows a section of a lead frame panel according to one embodiment and an enlarged section thereof, compared to Figure 2 , also showing a semiconductor die pad and an auxiliary structure for connecting with the second dam bar and the third dam bar.

[0039] Figure 4A 、 Figure 4B and Figure 4C A top view (A), a perspective view (B), and an enlarged section of the perspective view (C) on a semiconductor package according to one embodiment are shown.

[0040] Figure 5 A flow chart of a method for manufacturing a semiconductor device package according to one embodiment is included. DETAILED DESCRIPTION

[0041] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which are shown by way of illustration specific embodiments in which the present disclosure may be practiced. In this regard, directional terms such as "top," "bottom," "front," "rear," "leading," and "trailing" are used with reference to the orientation of the figures being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be taken as limiting, and the scope of the present disclosure is defined by the appended claims.

[0042] It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0043] As used in this specification, the terms "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" do not mean that elements or layers must be directly in contact with each other; intervening elements or layers may be provided between the elements being "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively. However, according to the present disclosure, the above-mentioned terms may optionally also have the specific meaning that the elements or layers are directly in contact with each other, i.e., no intervening elements or layers are provided between the elements being "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled," respectively.

[0044] In addition, the term "on" as used in reference to a component, element, or material layer formed or located "on" a surface may be used herein to mean that the component, element, or material layer is "indirectly" located (e.g., placed, formed, deposited, etc.) on the surface, wherein one or more additional components, elements, or layers are disposed between the surface and the component, element, or material layer. However, the term "on" as used in reference to a component, element, or material layer formed or located "on" a surface may alternatively have a specific meaning whereby the component, element, or material layer is "directly" located (e.g., placed, formed, deposited, etc.) on the surface, such as in direct contact with the surface.

[0045] In addition, the word "exemplary" is used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. On the contrary, the use of the word "exemplary" is intended to present concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the aforementioned instances. In addition, unless otherwise specified or clear from the context that it is for a singular form, the articles "a" and "an" used in this application and the appended claims may generally be interpreted to mean "one or more". In addition, at least one of A and B or similar expressions generally refer to A or B or both A and B.

[0046] Figure 2 Shown is a section of a lead frame panel and an enlarged section thereof according to one embodiment.

[0047] Figure 2The illustrated leadframe panel 10 includes a plurality of leadframes 11, each of which includes a die pad 11A and a first plurality of leads 11B, 11B.1. The first plurality of leads 11B, 11B.1 are arranged side by side in a row on a first upper side of the die pad 11A and are connected to the die pad 11A. The first plurality of leads 11B, 11B.1 includes a first outermost lead 11B.1 located on the right-hand side. A first dam 11C interconnects all of the leads 11B, 11B.1. The leadframe panel 10 also includes a second dam 11D connected to the first outermost lead 11B.1. A third dam 11F is shown on the opposite side of the leadframe 11 and is connected to the second outermost lead 11B.2. The leadframe 11 also includes a second plurality of leads 11G arranged side by side in a row on a second lower side of the die pad 11A.

[0048] Figure 3 Shows a section of a lead frame panel according to one embodiment and an enlarged section thereof, compared to Figure 2 , also showing a semiconductor die pad and an auxiliary structure for connecting with the second dam bar and the third dam bar.

[0049] Figure 3 The lead frame panel 10 shown can be used with Figure 2 The leadframe 11 is identical to the leadframe 11, and therefore retains most of the reference numerals. Furthermore, a semiconductor die 12 is attached to the die pad 11. Furthermore, a first auxiliary structure 11E is provided, with a second dam 11D connected between the first outermost lead 11B.1 and the first auxiliary structure 11E. A third dam 11F is shown on the opposite side of the leadframe 11, connected between the second outermost lead 11B.2 and a second auxiliary structure (not shown).

[0050] As indicated by the arrows in the enlarged section, the second dam 11D is moved to a position relative to the die pad 11A that is different from the position of the first dam 11C relative to the die pad 11A. More specifically, the second dam 11D is located farther from the die pad 11A than the first dam 11C. The distance between the first dam 11C and the second dam 11D can be, for example, in the range of 1 mm to 2 mm. The first auxiliary structure 11E forms a mechanical connection between the lead frame 11 and the adjacent lead frame to the right.

[0051] Leadframe 11 may further include a second-outermost lead 11B.2, arranged at the second-outermost position of leads 11B, 11B.1, and 11B.2, a third bar 11F, and a second auxiliary structure (not shown). Third bar 11F connects second-outermost lead 11B.2 to the second auxiliary structure. The structure and connection between second-outermost lead 11B.2 and the second auxiliary structure may be similar to the structure and connection between first-outermost lead 11B.1 and first auxiliary structure 11E, except that they are arranged in a mirror-symmetrical manner.

[0052] The lead frame 11 may further include a second plurality of leads 11G, where the leads 11G are arranged side by side in a row on a second side of the die pad 11A, the second side being opposite the first side. The second plurality of leads 11G are intended to connect to contact pads on the upper surface of a semiconductor die in the manufactured semiconductor package. According to one example, the lead frame 11 may further include a fourth bar 11H that interconnects all of the leads 11G.

[0053] Each of the plurality of lead frames 11 may be designed in such a manner that Figure 2 and Figure 3 In this way, for each lead frame, the inherent stress generated from the die pad level to the lead frame level can be broken down and processing of the lead frame panel can continue.

[0054] Reference again Figure 1 , the lead frame panel 10 moves from left to right as indicated by the arrow. At this stage of the process, in order to correctly move the lead frame panel to the next device, it may only be necessary to lift the rightmost lead of the first lead frame, and for all subsequent lead frames, only the rightmost leads need to be lifted. However, it may also be necessary to lift the rightmost and leftmost leads of the lead frame. In the above embodiment, additional dam bars 11D / 11F are described only for the top row leads 11B, 11B.1, and 11B.2. For the bottom row leads that are not physically connected to the die pad, the dam bars can be arranged in a conventional manner because the bottom row leads are not physically connected to the die pad, and therefore the warpage of the die pad will not be transmitted to the bottom row leads. However, in some embodiments, it is also possible to have a similar arrangement of different dam bars for the bottom row leads similar to the top row leads. This will facilitate the manufacture of the lead frame panel.

[0055] The semiconductor transistor die 12 may be, for example, one or more of a vertical transistor die, a power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a SiCMOS die, or a wide-bandgap semiconductor transistor die (particularly a SiC transistor die or a GaN transistor die). The semiconductor transistor die 12 further includes a drain pad on its lower main surface, which is electrically connected to the die pad 11A. The semiconductor transistor die 12 also includes a source pad, a gate pad, and possibly a source / sense pad (pad not shown), all of which are disposed on the upper main surface of the semiconductor transistor die 12.

[0056] Figure 4A 、 Figure 4B and Figure 4C A top view (A), a perspective view (B), and an enlarged section (C) of the perspective view on a semiconductor device package according to one embodiment are shown.

[0057] Figure 4A 、 Figure 4B and Figure 4C The semiconductor device package 20 includes a lead frame 21, which includes a die pad 21A and a first plurality of leads 21B, 21B.1, and a semiconductor transistor die (not shown) disposed on the die pad 21A. The leads 21B, 21B.1 are connected to the die pad 21A and are arranged side by side in a row on a first side of the semiconductor device package 20. The structure of the first outermost lead 21B.1 arranged at the first outermost position of the first plurality of leads 21B, 21B.1 is different from the structure of the other leads 21B. In particular, each of the leads 21B, 21B.1 includes a first dam residue 21B.A located at a first upper level A (see FIG. 2 ). Figure 4A ), the first outermost lead 21B.1 further comprises a second bar remnant 21B.1A located at a second lower level B (see Figure 4A ).

[0058] The first bar remnant 21B.A is derived from Figure 2 The first bar 11C shown, the second bar residue 21B.1A is derived from Figure 2 The second dam 11D is shown. The first outermost lead 21B.1 has two dam remnants, one at the same level as its adjacent lead 21B.A and the other at a different level 21B.1A.

[0059] The semiconductor device package 20 further includes a second outermost lead 21B.2 arranged at a second outermost position of the plurality of leads. The second outermost position is opposite to the first outermost position. The second outermost lead 21B.2 includes a first dam residue 21B.A, the first dam residue 21B.A originating from Figure 2 The second outermost lead 21B.2 also includes a third bar remnant 21B.2A located at the second lower level B (see Figure 4A ), the third bar residue 21B.2A originates from Figure 2 and Figure 3 The third bar 11F is shown in FIG.

[0060] One or both of the second dam remnant 21B.1A of the first outermost lead 21B.1 or the third dam remnant 21B.2A of the second outermost lead 21B.2 include a trapezoidal cross section resulting from the bending process of the leads.

[0061] like Figure 4A 、 Figure 4B and Figure 4C As shown, each of the leads 21B, 21B.1 and 21B.2 includes a first upper horizontal portion, a bent portion, and a second lower horizontal portion, wherein the first bar remnant 21B.A of the leads 21B and 21B.1 is located in the first upper horizontal portion, and the second bar remnant 21B.1A of the first outermost lead 21B.1 and the third bar remnant 21B.2A of the second outermost lead 21B.2 are located in the bent portion.

[0062] However, alternatively, it is also possible that the first bar remnant 21B.A of the leads 21B, 21B.1 is located at the bent portion, and the second bar remnant 21B.1A of the first outermost lead 21B.1 and the third bar remnant 21B.2A of the second outermost lead 21B.2 are located at the lower horizontal portion or partially overlap the bent portion.

[0063] The semiconductor device package 20 may further include a second plurality of leads 21G, wherein the leads 21G are arranged side by side in a row on a second side of the semiconductor device package 20, the second side being opposite to the first side. According to one example, the leads 21G are identically formed and include a dam remnant 21G.A located at an upper level A (see FIG. Figure 4A ). The bar residue 21G.A is derived from Figure 2 and Figure 3 The fourth bar 11H is shown.

[0064] The semiconductor transistor die may include one or more of a vertical transistor die, a power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a SiCMOS die, a wide bandgap semiconductor transistor die (particularly a SiC transistor die or a GaN transistor die).

[0065] Figure 4A 、 Figure 4Band Figure 4C The semiconductor package 20 shown is an example of a TOLT package. However, it should be understood that the present disclosure is also applicable to other types of semiconductor device packages.

[0066] Figure 5 A flow chart of a method for manufacturing a semiconductor device package according to one embodiment is included.

[0067] Method 100 includes providing a lead frame panel (110) according to the first aspect, attaching a semiconductor die to a die pad (120) of the lead frame, encapsulating the lead frame and cutting a first dam between the leads (130), singulating the package (140), and bending outer ends of the leads (150).

[0068] The bending of the leads can be performed so that it produces Figure 4A 、 Figure 4B and Figure 4C The semiconductor device package shown in the figure is configured such that each lead includes a first upper horizontal portion, a bent portion, and a second lower horizontal portion.

[0069] Example

[0070] Specific examples of the present disclosure are described below.

[0071] Example 1 is a lead frame panel comprising: a plurality of lead frames, wherein each of the plurality of lead frames comprises a die pad and a first plurality of leads, wherein the leads are arranged side by side along a row on a first side of the die pad, wherein at least a first outermost lead is connected to the die pad; a first dam connecting all the leads to each other; and a second dam connected to the first outermost lead, wherein the first dam and the second dam are located in a same plane, and a position of the second dam relative to the die pad is different from a position of the first dam relative to the die pad.

[0072] Example 2 is the lead frame panel of Example 1, wherein the second dam bar is located farther away from the die pad than the first dam bar.

[0073] Example 3 is the lead frame panel according to Example 1 or 2, further comprising a first auxiliary structure, wherein the second dam is connected between the first outermost lead and the first auxiliary structure.

[0074] Example 4 is a lead frame panel according to any of the preceding examples, the lead frame panel further comprising a second outermost lead arranged at a second outermost position of the plurality of leads, and a third dam connected to the second outermost lead, wherein the first dam and the third dam are located in the same plane, and a position of the third dam relative to the die pad is different from a position of the first dam relative to the die pad.

[0075] Example 5 is the lead frame panel according to Example 4, further comprising a second auxiliary structure, wherein the third dam is connected between the second outermost lead and the second auxiliary structure.

[0076] Example 6 is the lead frame panel of any of the preceding examples, wherein each of the first plurality of leads is connected to a die pad.

[0077] Example 7 is a lead frame panel according to any of the preceding examples, further comprising a second plurality of leads, wherein the leads are arranged side by side in a row on a second side of the die pad, the second side being opposite the first side.

[0078] Example 8 is the lead frame panel of Example 7, further comprising a fourth dam bar connecting all of the leads to each other.

[0079] Example 9 is a semiconductor package comprising: a lead frame comprising: a die pad and a first plurality of leads, and a semiconductor transistor die disposed on the die pad, wherein the leads are arranged side by side along a row on a first side of the semiconductor device package, wherein a first outermost lead arranged at a first outermost position of the first plurality of leads has a structure different from a structure of other leads, wherein at least the first outermost lead is connected to the die pad, and wherein each lead includes a first dam remnant portion located at a first upper level, and the first outermost lead also includes a second dam remnant portion located at a second lower level.

[0080] Example 10 is the semiconductor package of Example 9, wherein a second lead of the first plurality of leads includes a third dam remnant at the second lower level.

[0081] Example 11 is the semiconductor package according to Example 9 or 10, wherein one or both of the second dam bar remnant of the first outermost lead or the third dam bar remnant of the second lead include a trapezoidal cross-section.

[0082] Example 12 is a semiconductor package according to any one of Examples 9 to 11, wherein each of the leads includes a first upper horizontal portion, a bent portion, and a second lower horizontal portion, wherein a first dam remnant of the lead is located in the first upper horizontal portion, and a second dam remnant of the first outermost lead and a third dam remnant of the second outermost lead are located in the bent portion.

[0083] Example 13 is the semiconductor package according to any one of Examples 9 to 11, wherein:

[0084] Each of the leads (21B, 21B.1, 21B.2) comprises a first upper horizontal portion, a curved portion, and a second lower horizontal portion, wherein

[0085] The first bar remnant (21B.A) of the lead (21B, 21B.1) is located at the bent portion, the second bar remnant (21B.1A) of the first outermost lead (21B.1) and the third bar remnant (21B.2A) of the second outermost lead (21B.2) are located at the lower horizontal portion or partially overlap with the bent portion.

[0086] Example 14 is the semiconductor package of any one of Examples 9 to 13, wherein each lead is connected to a die pad.

[0087] Example 15 is a semiconductor package according to any one of Examples 9 to 14, further comprising a second plurality of leads, wherein the leads are arranged side by side in a row on a second side of the semiconductor device package, the second side being opposite to the first side.

[0088] Example 16 is the semiconductor package of Example 15, wherein the leads are identically formed and include a dam remnant at the first upper level.

[0089] Example 17 is a semiconductor package according to any one of Examples 9 to 16, wherein the semiconductor transistor die includes one or more of a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die (particularly a SiC transistor die or a GaN transistor die).

[0090] Example 18 is a method for manufacturing a semiconductor device package, the method comprising: providing a lead frame panel according to any one of Examples 1 to 8, attaching a semiconductor die to a die pad of the lead frame, encapsulating the lead frame and cutting a first dam located between the leads and a second dam located between the outermost leads and the auxiliary structure, singulating the package, and bending the outer ends of the leads.

[0091] In addition, although a particular feature or aspect of an embodiment of the present disclosure may be disclosed with respect to only one of multiple embodiments, this feature or aspect may be combined with one or more other features or aspects of other embodiments, which may be desirable and advantageous for any given or specific application. In addition, to the extent that the terms "comprising," "having," "with," or other variations thereof are used in specific embodiments or claims, these terms are intended to be open-ended inclusions in a manner similar to the term "comprising." In addition, it should be understood that embodiments of the present disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming devices. In addition, the term "exemplary" is meant only as an example, not the best or optimal. It should also be understood that for purposes of simplicity and ease of understanding, the features and / or elements depicted herein are shown as having specific dimensions relative to each other, and the actual dimensions may be significantly different from the dimensions shown herein.

[0092] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. A lead frame panel (10), comprising: A plurality of lead frames (11), each of the plurality of lead frames (11) comprising a die pad (11A) and a first plurality of leads (11B, 11B.1); wherein, The leads (11B, 11B.1) are arranged side by side in a row on a first side of the die pad (11A), with at least the first outermost lead (11B.1) being connected to the die pad (11A); and a first bar (11C) connecting all leads (11B, 11B.1) to one another; a second stopper (11D) connected to the first outermost lead (11B.1), the first stopper (11C) and the second stopper (11D) being located in the same plane, and a position of the second stopper (11D) relative to the die pad (11A) being different from a position of the first stopper (11C) relative to the die pad (11A); It is characterized in that The second dam (11D) is located at a position farther away from the die pad (11A) than the first dam (11C).

2. The lead frame panel (10) according to claim 1, further comprising: A first auxiliary structure (11E), wherein a second blocking bar (11D) is connected between the first outermost lead (11B.1) and the first auxiliary structure (11E).

3. The lead frame panel (10) according to any one of the preceding claims, further comprising: a second outermost lead (11B.2) arranged at the second outermost position of the plurality of leads (11B, 11B.1, 11B.2); and A third bar (11F) is connected to the second outermost lead (11B.2), wherein the first bar (11C) and the third bar (11F) are located in the same plane, and the position of the third bar (11F) relative to the die pad (11A) is different from the position of the first bar (11C) relative to the die pad (11A).

4. The lead frame panel (10) according to claim 3, further comprising: A second auxiliary structure, wherein a third bar (11F) is connected between the second outermost lead (11B.2) and the second auxiliary structure.

5. The lead frame panel (10) according to any one of the preceding claims, wherein Each of the first plurality of leads (11B, 11B.1) is connected to the die pad (11A).

6. The lead frame panel (10) according to any one of the preceding claims, further comprising: A second plurality of leads (11G), wherein the leads (11G) are arranged side by side in a row on a second side of the die pad (11A), the second side being opposite the first side.

7. The lead frame panel (10) according to claim 6, wherein The lead frame panel (10) further comprises: A fourth bar (11H) connects all the leads (11G) to each other.

8. A semiconductor package (20), comprising: a lead frame (21) comprising a die pad (21A) and a first plurality of leads (21B, 21B.1); and A semiconductor transistor die (22) is disposed on a die pad (21A); wherein The leads (21B, 21B.1) are arranged side by side in a row on a first side of a semiconductor device package (20), a first outermost lead (21B.1) arranged at a first outermost position of a first plurality of leads (21B, 21B.1) having a structure different from that of the other leads (21B), At least the first outermost lead (21B.1) is connected to the die pad (21A), and Each of the leads (21B, 21B.1) comprises a first bar remnant (21B.A) at a first upper level, the first outermost lead (21B.1) further comprising a second bar remnant (21B.1A) at a second lower level.

9. The semiconductor package (20) according to claim 8, wherein A second lead (21B.2) of the first plurality of leads (21B, 21B.1, 21B.2) comprises a third bar remnant (21B.2A) located at a second lower level.

10. The semiconductor package (20) according to claim 8 or 9, wherein: One or both of the second bar remnant (21B.1A) of the first outermost lead (21B.1) or the third bar remnant (21B.2A) of the second lead (21B.2) include a trapezoidal cross section.

11. The semiconductor package (20) according to any one of claims 8 to 10, wherein: Each of the leads (21B, 21B.1, 21B.2) comprises a first upper horizontal portion, a curved portion, and a second lower horizontal portion, wherein The first bar remnant (21B.A) of the lead (21B, 21B.1) is located in the first upper horizontal portion, the second bar remnant (21B.1A) of the first outermost lead (21B.1) and the third bar remnant (21B.2A) of the second outermost lead (21B.2) are located in the bent portion.

12. The semiconductor package (20) according to any one of claims 8 to 10, wherein: Each of the leads (21B, 21B.1, 21B.2) comprises a first upper horizontal portion, a curved portion, and a second lower horizontal portion, wherein The first bar remnant (21B.A) of the lead (21B, 21B.1) is located in the bent portion, and the second bar remnant (21B.1A) of the first outermost lead (21B.1) and the third bar remnant (21B.2A) of the second outermost lead (21B.2) are located in the lower horizontal portion or partially overlap with the bent portion.

13. The semiconductor package (20) according to any one of claims 8 to 12, wherein: Each of the leads (21B, 21B.1) is connected to the die pad (21A).

14. The semiconductor package (20) according to any one of claims 8 to 13, further comprising: A second plurality of leads (21C) are arranged side by side in a row on a second side of the semiconductor device package (20), the second side being opposite the first side.

15. The semiconductor package (20) according to claim 14, wherein The leads (21G) are identically formed and include a dam remnant (21G.A) located at a first upper level.

16. The semiconductor package (20) according to any one of claims 8 to 15, wherein: The semiconductor transistor die (22) includes one or more of a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die or a GaN transistor die.

17. A method (100) for manufacturing a semiconductor device package, the method comprising: Providing a lead frame panel (110) according to any one of claims 1 to 7; attaching a semiconductor die to a die pad (120) of a lead frame; Encapsulating the lead frame and cutting a first bar between the leads and a second bar between the outermost leads and the auxiliary structure (130); singulated packages (140); and The outer ends (150) of the leads are bent.

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