Field effect transistor packaging module

Abstract

The embodiment of the invention provides a field effect transistor packaging module. The field effect transistor packaging module comprises a packaging frame; an insulating layer fixed to a surface of the package frame; a resistor fixed to a surface of the insulating layer; one end of the resistor is electrically connected to the first pin of the packaging frame; a capacitor fixed to a surface of the insulating layer; one end of the capacitor is electrically connected to the first pin of the packaging frame; a field effect transistor fixed to a surface of the package frame; the drain electrode of the field effect transistor is grounded; the source electrode of the field effect transistor is electrically connected to the second pin of the packaging frame; the grid electrode of the field effect transistor is electrically connected with the other ends of the resistor and the capacitor. According to the field effect transistor packaging module provided by the embodiment of the invention, the threshold voltage can be improved, so that the defect that mistaken switching-on is easily caused in the dynamic process of zero-bias switching-off due to relatively low threshold voltage is overcome.

Description

Technical Field

[0001] The present application relates to semiconductor packaging technology, and in particular to a field effect transistor packaging module. Background Art

[0002] Silicon carbide (SiC) is one of the primary raw materials for third-generation wide-bandgap semiconductors. Its bandgap is 3.2eV, significantly larger than the 1.1eV bandgap of traditional silicon. Furthermore, SiC's critical breakdown field is an order of magnitude higher than silicon's, making it resistant to high temperatures and high pressures. Furthermore, SiC's high saturation drift velocity makes it suitable for manufacturing fast-response semiconductor devices such as VDMOS (Vertical Double-diffused MOSFET) and JFET (Junction Field-Effect Transistor).

[0003] A Junction Field-Effect Transistor (JFET) is a three-port semiconductor device. Its working principle is to use gate voltage to control the reverse bias of the pn junction between the gate and the channel to achieve the shutdown of the drain and source. When the gate is not pressurized, it is usually a normally-on device, and its conducting channel is within the device body.

[0004] SiC JFET uses a PN junction to control the gate. To prevent the gate PN junction from turning on, the gate bias generally does not exceed 2.6V. SiC JFETs include normally closed and normally on types. Among them, the threshold voltage of the normally closed SiC JFET device is relatively low, usually 0.7V to 1V, which leads to two problems in use and driving. First, the threshold voltage is low, which easily causes false turn-on during the dynamic process of zero-bias shutdown. Second, the 2.6V drive upper limit severely limits the overdrive voltage of the device gate, thereby limiting its performance. When the normally on SiC JFET device is blocked, a large negative bias needs to be applied to completely pinch off the channel region. Therefore, both types of SiC JFET devices are incompatible with the existing MOSFET or IGBT device drive circuits, increasing the difficulty of using SiC JFET devices.

[0005] To solve the above problems, a discrete cascode structure is usually adopted to seal the SiC JFET chip with the MOSFET chip. Figure 1 and Figure 2As shown, SiC JFET 1 is bonded to package leadframe 7 via silver sintering. In a side-by-side configuration, MOSFET 13 is connected to metal-plated ceramic isolator 15 via metal solder, isolating it from the SiC JFET Drain signal. Furthermore, the metal plating of metal-plated ceramic isolator 15 is also used to connect the SiC JFET chip's source pad via aluminum wire 5. Another set of source bond wires runs between the MOSFET source and source pins.

[0006] The above method places strict requirements on the compatibility and matching of the two chips, and multi-chip packaging will bring cost and process complexity issues, dynamic performance matching between the two devices, and loss and reliability problems caused by lead inductance during dynamic switching. Summary of the Invention

[0007] In order to solve one of the above technical defects, a field effect transistor packaging module is provided in an embodiment of the present application.

[0008] According to a first aspect of an embodiment of the present application, a field effect transistor package module is provided, comprising:

[0009] Encapsulation framework;

[0010] an insulating layer fixed to a surface of the packaging frame;

[0011] A resistor is fixed to the surface of the insulating layer; one end of the resistor is electrically connected to the first pin of the package frame;

[0012] A capacitor is fixed to the surface of the insulating layer; one end of the capacitor is electrically connected to the first pin of the package frame;

[0013] The field effect transistor is fixed to the surface of the packaging frame; the drain of the field effect transistor is grounded; the source of the field effect transistor is electrically connected to the second pin of the packaging frame; and the gate of the field effect transistor is electrically connected to the other end of the resistor and the other end of the capacitor.

[0014] The technical solution provided in this embodiment employs an insulating layer fixed to the surface of a package frame; a resistor fixed to the surface of the insulating layer; one end of the resistor electrically connected to a first pin of the package frame; a capacitor fixed to the surface of the insulating layer; one end of the capacitor electrically connected to the first pin of the package frame; a field-effect transistor fixed to the surface of the package frame; the drain of the field-effect transistor is grounded; the source of the field-effect transistor is electrically connected to a second pin of the package frame; and the gate of the field-effect transistor is electrically connected to the other ends of the resistor and capacitor, respectively. This can increase the threshold voltage, thereby resolving the defect of normally closed SiC JFETs being prone to false turn-on during the dynamic process of zero-bias shutdown due to low threshold voltage, and meeting the conventional drive voltage of -5V / 18V. Furthermore, it is no longer necessary to co-encapsulate the SiC JFET with the MOSFET chip, eliminating the technical defects of co-encapsulating the SiC JFET with the MOSFET chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 This is a schematic diagram of the existing SiC JFET chip and MOSFET chip sealed structure;

[0017] Figure 2 for Figure 1 Corresponding circuit diagram;

[0018] Figure 3 A schematic structural diagram of a field effect transistor packaging module provided in an embodiment of the present application;

[0019] Figure 4 for Figure 3 Corresponding circuit diagram;

[0020] Figure 5 A schematic structural diagram of another field effect transistor packaging module provided in an embodiment of the present application;

[0021] Figure 6 A schematic structural diagram of another field effect transistor packaging module provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of the structure of a field effect transistor provided in an embodiment of the present application;

[0023] Figure 8 This is a test curve of the field effect transistor package module provided in an embodiment of the present application;

[0024] Figure 9 For existing solutions D-V D curve chart;

[0025] Figure 10 I corresponding to the technical solution of this embodiment D -V D curve chart;

[0026] Figure 11 is a curve diagram of the breakdown voltage BV in the existing solution;

[0027] Figure 12 This is a curve diagram of the breakdown voltage BV corresponding to the technical solution of this embodiment.

[0028] Reference numerals:

[0029] In the background technology:

[0030] 1-SiC JFET; 5-aluminum wire; 7-package lead frame; 13-MOSFET; 15-metal-plated ceramic isolator;

[0031] In a specific embodiment:

[0032] 1-Package frame; 11-First pin; 12-Second pin; 13-Main frame; 14-Isolation frame; 15-Third pin;

[0033] 2-Insulation layer;

[0034] 3-Resistors;

[0035] 4-Capacitor;

[0036] 5-field effect transistor; 51-source; 52-gate;

[0037] 61-first lead; 62-second lead; 63-third lead. DETAILED DESCRIPTION

[0038] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0039] This embodiment provides a field effect transistor packaging module for securing and packaging field effect transistors. This embodiment uses a SiC JFET chip as an example for illustration. Those skilled in the art can also apply the solution provided in this embodiment to packaging other types of field effect transistors.

[0040] like Figure 3 and Figure 4 As shown, the field effect transistor package module provided in this embodiment includes: a package frame 1, an insulating layer 2, a resistor 3, a capacitor 4 and a field effect transistor 5.

[0041] A plurality of pins are provided on the package frame 1. A metal layer is provided on the surface of the package frame 1. The metal layer can be arranged in a preset pattern and can be electrically connected to the corresponding pins.

[0042] The insulating layer 2 is fixed to the surface of the package frame 1 and is insulated from the metal layer on the surface of the package frame 1 .

[0043] The resistor 3 and the capacitor 4 are respectively fixed to the surface of the insulating layer 2 , for example, they can be bonded to the surface of the insulating layer 2 using insulating glue.

[0044] The field effect transistor 5 is fixed to the surface of the package frame 1. The field effect transistor 5 has a gate, a source and a drain, wherein the drain is grounded and the source is electrically connected to the second pin 12 of the package frame.

[0045] The resistor 3 and the capacitor 4 are connected in parallel. Specifically, one end of the resistor 3 is electrically connected to the first pin 11 of the package frame 1, and the other end of the resistor 3 is electrically connected to the gate of the field effect transistor 5. One end of the capacitor 4 is also electrically connected to the first pin 11 of the package frame 1, and the other end is also electrically connected to the gate of the field effect transistor 5.

[0046] The circuit of the above field effect transistor package module is as follows Figure 4 As shown, the resistor 3 is connected in parallel with the capacitor 4 and is connected to the gate of the field effect transistor 5 .

[0047] In the above scheme, a resistor and capacitor are connected in parallel to the gate of the field-effect transistor, which is equivalent to utilizing a normally-on SiC JFET to achieve the function of a normally-off SiC JFET. This can also increase its threshold voltage to 3V-19V, thus resolving the problem of false turn-on during dynamic zero-bias shutdown caused by a low threshold voltage. Furthermore, the added resistor acts as a voltage divider, reducing the gate voltage, allowing the device to withstand drive voltages above 2.6V and improving device performance.

[0048] Furthermore, by adopting the above embodiment, there is no need to co-package the SiC JFET and MOSFET chips, and the technical defects of co-packaging the SiC JFET and MOSFET chips do not exist.

[0049] The technical solution provided in this embodiment adopts an insulating layer fixed to the surface of the packaging frame; a resistor, fixed to the surface of the insulating layer; one end of the resistor is electrically connected to the first pin of the packaging frame; a capacitor, fixed to the surface of the insulating layer; one end of the capacitor is electrically connected to the first pin of the packaging frame; a field-effect transistor, fixed to the surface of the packaging frame; the drain of the field-effect transistor is grounded; the source of the field-effect transistor is electrically connected to the second pin of the packaging frame; the gate of the field-effect transistor is electrically connected to the other ends of the resistor and the capacitor, respectively, which can increase the threshold voltage, thereby solving the defect of easy false turn-on in the dynamic process of zero-bias shutdown due to low threshold voltage. It is no longer necessary to seal the SiC JFET and MOSFET chip together, and the technical defects of sealing the SiC JFET and MOSFET chip together do not exist.

[0050] A field effect transistor such as Figure 7 As shown, an epitaxial layer 56 is provided above a substrate 57. A gate is provided on the upper portion of the epitaxial layer 56, including a top gate 53 and a bottom gate 52, as well as an ohmic contact region 58, a source region 51, a channel 1 54, and a channel 2 55. A drain is provided below the substrate 57.

[0051] In the above solution, the field effect transistor 5 can be fixed to the insulating area on the surface of the package frame 1 , so that the drain is electrically connected to the ground pin of the package frame 1 .

[0052] Alternatively, the drain electrode on the back side of the field effect transistor 5 is directly soldered to the metal layer surface of the packaging frame 1 through conductive solder, and the metal layer is grounded to achieve grounding of the drain electrode of the field effect transistor 5 .

[0053] The source electrode 51 is provided on the front surface of the field effect transistor 5 , and the source electrode 51 is electrically connected to the second pin 12 of the package frame 1 through a lead (specifically, a first lead 61 ). Figure 3 The first lead 61 is a metal wire. Figure 5 The first lead 61 in the embodiment is a metal strip or a metal sheet. The metal wire can be an aluminum wire, a gold wire or a copper wire, the metal strip can be an aluminum strip or a copper strip, and the metal sheet can be an aluminum sheet or a copper sheet.

[0054] Gate 52 (eg Figure 7 The bottom gate 52 is disposed on the front surface of the field-effect transistor 5 and is electrically connected to the other ends of the resistor 3 and capacitor 4, respectively, via leads. Specifically, the gate 52 is connected to the resistor 3 via a second lead 62 and to the capacitor 4 via a third lead 63. The second and third leads 62, 63 may be gold or aluminum wires, and the thickness of the leads may be set according to the size of the capacitors 3 and 4.

[0055] Insulation layer 2 can also be fixed to the metal surface of package frame 1, maintaining insulation from the metal layer. Insulation layer 2 can be a ceramic sheet bonded to the metal surface of package frame 1 with insulating adhesive. Alternatively, insulation layer 2 can be an insulating adhesive film bonded to the metal surface of package frame 1. Resistor 3 and capacitor 4 can be bonded to the surface of insulation layer 2 with insulating adhesive.

[0056] Resistor 3 can be a device purchased directly, and the electrical connection end of resistor 3 can be electroplated with nickel-palladium-gold. Alternatively, an ordinary resistor 3 can be selected, and the electrical connection end of resistor 3 can be electroplated with nickel-palladium-gold before packaging, which is more conducive to wire bonding, improves welding quality, and thus improves the reliability of the packaged device.

[0057] Capacitor 4 can be a device purchased directly, and the electrical connection end of capacitor 4 can be plated with nickel palladium gold; alternatively, an ordinary capacitor 4 can be selected, and the electrical connection end of capacitor 4 can be plated with nickel palladium gold before packaging, which is more conducive to wire bonding, improves welding quality, and thus improves the reliability of the packaged device.

[0058] The gate of the field effect transistor is also connected to the third pin 15 of the package frame 1 through a lead, thereby reducing the inductance of the source line in the package.

[0059] On the basis of the above technical solution, Figure 6 As shown, this embodiment provides another packaging solution. The packaging frame 1 includes: a main frame 13 and an isolation frame 14 that are independent of each other. The field-effect transistor 5 is fixed to the surface of the main frame 13, and the insulating layer 2, resistor 3, and capacitor 4 are fixed to the surface of the isolation frame 14. The specific arrangement can be referred to above.

[0060] The main frame 13 and the isolation frame 14 are used for isolation, which can prevent the heat generated by the field effect transistor 5 from being transferred to the resistor 3 or the capacitor 4 through the metal layer on the surface of the packaging frame 1, thereby reducing the temperature of the resistor 3 and the capacitor 4, improving the baking of the field effect transistor 5 on the resistor 3 and the capacitor 4, and improving the performance and reliability of the packaged device.

[0061] Compared with the multi-chip packaging solution of SiC JFET and MOSFET, the technical solution provided by this embodiment does not require a metal-plated ceramic isolator and can solve the problem of difficult dynamic matching between the two chips, thereby reducing the wafer production cost.

[0062] In addition, the solution provided by this embodiment can flexibly select different capacitor and resistor values, achieving the advantage of flexible adjustment of resistance and capacitance. In this embodiment, the resistance value used is 100Ω-5000Ω, and the capacitance value is 10nF-1000nF.

[0063] The field effect transistor package module obtained in the above embodiment is subjected to a double pulse test, with an operating voltage VDD of 800V, a gate-source voltage Vgs of -8V-+18V, a series inductor L=50μH, a pull-up tube of 15mohmSiC JFET in the circuit topology, an external resistor of 500Ω, and a capacitor of 80nF. Figure 8 As shown in the figure, the horizontal axis is test time, and the vertical axis is short-circuit saturation current. The curve shows the change in short-circuit saturation current of the device between the two tests. The blue curve in the figure is the channel current. The device short-circuit occurs at a test time of approximately 6.7 microseconds, indicating that the device performance meets the requirements.

[0064] Figure 9 For the traditional solution D -V D curve chart, Figure 10 I corresponding to the solution of this embodiment D -V D curve chart. Figure 9 and Figure 10 In the figure, the horizontal axis is the drain-source voltage V DS , the vertical axis is the source-drain current I GS The curves show that the channel current at different gate voltages changes with V DS The change curve (i.e. I D -V D curve). Figure 9 As shown, the V GS The maximum voltage is 2.5V, which cannot achieve a wider voltage swing. Figure 10 As shown, the V GS The operating voltage can be extended to between 3V and 19V, and a good voltage swing can be obtained. This means that after adopting the solution of this embodiment, a good I D -V D curve, which will not cause SiC-JFET gate breakdown and can obtain better short-circuit withstand capability. Figure 11 is a graph of the breakdown voltage BV in the traditional solution, Figure 12 2 is a curve diagram of the breakdown voltage BV of this embodiment. As can be seen from the figure, the breakdown voltage can reach 1600V, indicating that the technical solution provided by this embodiment does not affect the breakdown voltage of the drain and source.

[0065] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0067] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on specific circumstances.

[0068] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0069] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A field effect transistor packaging module, characterized in that: include: Encapsulation framework; an insulating layer fixed to a surface of the packaging frame; a resistor, fixed to the surface of the insulating layer; One end of the resistor is electrically connected to the first pin of the package frame; a capacitor, fixed to the surface of the insulating layer; One end of the capacitor is electrically connected to the first pin of the package frame; The field effect transistor is fixed to the surface of the packaging frame; the drain of the field effect transistor is grounded; the source of the field effect transistor is electrically connected to the second pin of the packaging frame; and the gate of the field effect transistor is electrically connected to the other end of the resistor and the other end of the capacitor.

2. The field effect transistor package module according to claim 1, wherein: The surface of the packaging frame is provided with a metal layer; the insulating layer is fixed to the metal layer surface of the packaging frame.

3. The field effect transistor package module according to claim 2, characterized in that: The metal layer is grounded; and the drain electrode on the back side of the field effect transistor is soldered to the metal layer surface of the package frame through conductive solder.

4. The field effect transistor package module according to claim 3, characterized in that: The source is arranged on the front side of the field effect transistor and is electrically connected to the second pin of the package frame through a lead.

5. The field effect transistor package module according to claim 3, characterized in that: The gate is arranged on the front side of the field effect transistor and is electrically connected to the other end of the resistor and the other end of the capacitor through leads.

6. The field effect transistor package module according to claim 2, wherein: The insulating layer is a ceramic sheet, which is bonded to the metal layer surface of the packaging frame through insulating glue.

7. The field effect transistor package module according to claim 2, wherein: The insulating layer is an insulating film.

8. The field effect transistor package module according to claim 1, wherein: The electrical connection end of the resistor is electroplated with nickel-palladium-gold; the electrical connection end of the capacitor is electroplated with nickel-palladium-gold.

9. The field effect transistor package module according to claim 1, wherein: The packaging frame includes: a main frame and an isolation frame that are independent of each other; The field effect transistor is fixed to the surface of the main frame; the insulating layer, the resistor and the capacitor are fixed to the surface of the isolation frame.

10. The field effect transistor package module according to claim 4 or 5, characterized in that: The lead is a metal wire, a metal strip or a metal sheet.

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