Integrated circuit assembly and chip packaging structure

Abstract

The embodiment of the invention provides an integrated circuit assembly and a chip packaging structure. The integrated circuit component comprises a first wafer bare chip which is provided with a plurality of arithmetic units, and the arithmetic units are used for executing logic operation in parallel; the second wafer bare chip is overlapped with the first wafer bare chip, and a plurality of access control units are formed in the second wafer bare chip; wherein each arithmetic unit corresponds to the plurality of access control units, and each arithmetic unit sends at least one data access instruction to at least one access control unit, so that each access control unit responds to the corresponding data access instruction to execute data access. According to the embodiment of the invention, the data access efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an integrated circuit component and a chip packaging structure. Background Art

[0002] Neural network models, such as Large Language Models (LLMs), are currently popular AI applications. However, efficient inference in neural network models places extremely high demands on storage bandwidth. This is especially true for the attention mechanism processing during the generation phase of LLMs, which consumes significant storage resources given the available computing resources.

[0003] Accelerator architectures such as graphics processing units (GPUs) offer sufficient computational performance but limited memory access bandwidth, making model inference extremely expensive. In some cases, techniques such as data quantization and model pruning can be used, but this comes at a cost in model performance.

[0004] For example, in existing GPU architectures, computing units (CPUs) such as Streaming Multiprocessors (SMs) and shared cache units (L2 Cache) are interconnected via on-chip wiring such as a crossbar. The on-chip access bandwidth from the CPUs to the shared cache units is several times greater than the off-chip access bandwidth to the memory units. As GPU architectures evolve, the crossbar area cannot be further increased due to technical limitations such as the lithography size of GPU chips, limiting the increase in access bandwidth. Therefore, an integrated circuit solution is needed to further improve data access efficiency. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an integrated circuit component and a chip packaging structure to solve the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present invention, an integrated circuit component is provided, comprising: a first wafer die, on which a plurality of operation units are formed, and the plurality of operation units are used to perform logical operations in parallel; a second wafer die, stacked with the first wafer die, and in which a plurality of access control units are formed; wherein each operation unit corresponds to the plurality of access control units, and each operation unit sends at least one data access instruction to at least one access control unit, so that each access control unit performs data access in response to the corresponding data access instruction.

[0007] In another implementation of the present invention, a first inter-die wiring is formed between the first wafer bare die and the second wafer bare die, and each operation unit sends at least one data access instruction to at least one access control unit via the first inter-die wiring.

[0008] In another embodiment of the present invention, a first unit array is formed in the first wafer bare die, the first unit array includes the multiple operation units, the multiple operation units are connected via a first intra-chip wiring, and the first intra-chip wiring is connected to the multiple access control units via a first inter-chip wiring.

[0009] In another implementation of the present invention, each computing unit is provided with a local cache unit.

[0010] In another implementation of the present invention, the first on-chip wiring includes a plurality of first wiring nodes corresponding to the plurality of operation units, and a first wiring network interconnecting the plurality of first wiring nodes.

[0011] In another implementation of the present invention, a second unit array is formed in the second wafer die, and the second unit array includes the multiple access control units and multiple first shared cache units, each access control unit corresponds to at least one first shared cache unit, and each first shared cache unit is shared by at least two computing units.

[0012] In another implementation of the present invention, each access control unit is connected to the corresponding at least one first shared cache unit via a second intra-chip wiring, and the multiple operation units are connected to the second intra-chip wiring via the first inter-chip wiring.

[0013] In another implementation of the present invention, the second on-chip wiring includes multiple second wiring nodes corresponding to the multiple access control units, and a second wiring network interconnecting the multiple second wiring nodes, and each access control unit is connected to at least one shared cache unit corresponding to the access control unit via the second wiring node corresponding to the access control unit.

[0014] In another implementation of the present invention, the second cell array further includes a plurality of second shared cache units, the cache levels of the plurality of first shared cache units being higher than the cache levels of the plurality of second shared cache units, wherein the plurality of second shared cache units, the plurality of first shared cache units and the plurality of access control units are connected via the second on-chip wiring.

[0015] According to a second aspect of an embodiment of the present invention, a chip packaging structure is provided, comprising: a first wafer die, on which a plurality of operation units are formed, and the plurality of operation units are used to perform logical operations in parallel; a second wafer die, on which a plurality of access control units are formed; a third wafer die, on which a plurality of storage units are formed; and an intermediary layer; wherein the second wafer die is stacked between the intermediary layer and the first wafer die, and the second wafer die and the third wafer die are arranged on the same side surface of the intermediary layer; wherein each operation unit corresponds to the plurality of access control units, each access control unit corresponds to at least one storage unit, and each operation unit sends at least one data access instruction to at least one access control unit, so that each access control unit responds to the corresponding data access instruction and accesses at least one storage unit in the third wafer die via the intermediary layer.

[0016] In another implementation of the present invention, a second inter-chip wiring is provided between the second wafer bare die and the interposer, a third inter-chip wiring is provided between the third wafer bare die and the interposer, the second inter-chip wiring and the third inter-chip wiring are connected in the interposer through a third intra-chip wiring, and each access control unit responds to a corresponding data access instruction to access at least one storage unit corresponding to the access control unit via the second inter-chip wiring, the third inter-chip wiring, and the third intra-chip wiring.

[0017] In another embodiment of the present invention, the second inter-chip wiring is formed by hybrid bonding of the bonding points of the second wafer bare die and the first part of the bonding points of the intermediate layer, and the third inter-chip wiring is formed by hybrid bonding of the bonding points of the third wafer bare die and the second part of the bonding points of the intermediate layer.

[0018] In the solution of the embodiment of the present invention, the first wafer bare die and the second wafer bare die are stacked, which fully utilizes the corresponding surface difference between the first wafer bare die and the second wafer bare die, improves the data transmission bandwidth between the first wafer bare die and the second wafer bare die, and reduces the data transmission delay. Therefore, when each computing unit sends at least one data access instruction to at least one access control unit respectively, the data access efficiency is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0020] Figure 1Schematic diagram of the structure of a GPU chip according to some examples.

[0021] Figure 2 is a schematic structural diagram of an integrated circuit component according to some embodiments of the present invention.

[0022] Figure 3 for Figure 2 A schematic structural diagram of a first wafer die according to an embodiment.

[0023] Figure 4A 、 Figure 4B and Figure 4C for Figure 2 Schematic structural diagram of a second wafer die according to various examples of the embodiments.

[0024] Figure 4D for Figure 2 A schematic block diagram of an integrated circuit assembly according to an embodiment.

[0025] Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D Schematic diagram showing different examples of on-chip wiring.

[0026] Figure 6 Schematic diagram of a chip packaging structure according to some other embodiments of the present invention.

[0027] Figure 7 for Figure 6 A schematic structural diagram of a further example of a chip packaging structure according to an embodiment. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and detailedly described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0029] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof and illustrate exemplary embodiments. Furthermore, it is to be understood that other embodiments may be utilized and that structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used merely to facilitate the description of features in the drawings. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the claimed subject matter is defined solely by the appended claims and their equivalents.

[0030] In the following description, numerous details are set forth. However, it will be apparent to those skilled in the art that the embodiments herein may be practiced without these specific details. In some cases, well-known methods and apparatus are shown in block diagram form rather than in detail to avoid blurring the embodiments herein. References throughout this specification to "an embodiment" or "one embodiment" or "some embodiments" mean that the specific features, structures, functions, or characteristics described in conjunction with the embodiment are included in at least one embodiment herein. Therefore, the phrases "in an embodiment" or "in one embodiment" or "some embodiments" appearing throughout this specification do not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific features, structures, functions, or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment in any case where the specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0031] As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0032] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. On the contrary, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediate elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0033] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is significant. For example, in the context of materials, a material or materials positioned above or below another material may be in direct contact or may have one or more intervening materials. Moreover, a material positioned between two materials or materials may be in direct contact with both layers or may have one or more intervening layers. In contrast, a first material or materials "above" a second material or materials is in direct contact with the second material or materials. Similar distinctions apply in the context of component assembly.

[0034] As used throughout this description and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0035] The term "circuit" or "module" may refer to one or more passive and / or active components that are arranged to cooperate with each other to provide a desired functionality. The term "signal" may refer to at least one current signal, voltage signal, or magnetic signal. The terms "substantially," "close to," "approximately," "close to," and "approximately" generally mean within + / - 10% of a target value.

[0036] The specific implementation of the embodiment of the present invention is further described below with reference to the accompanying drawings of the embodiment of the present invention.

[0037] Figure 1 Schematic diagram of the structure of a GPU chip according to some examples. Figure 1 In modern GPU architectures, computing units (CPUs) such as Streaming Multiprocessors (SMs) and shared memory units such as Level 2 Cache are interconnected via on-chip wiring such as crossbars and located within the logic die. Memory dies such as High Bandwidth Memory (HBM) are connected via an interposer, enabling off-chip memory access from the logic die. Typically, the interposer connecting to the memory die is a passive interposer, and the on-chip access bandwidth from the CPU to the shared cache is several times greater than the off-chip access bandwidth to the memory units. As GPU architectures evolve, the area of ​​on-chip wiring such as crossbars cannot be further increased due to the limited lithographic dimensions of GPU chips, limiting the increase in on-chip access bandwidth.

[0038] To this end, various embodiments of the present invention provide a series of solutions to improve data access efficiency. Figure 2 An integrated circuit assembly according to some embodiments of the present invention is shown. Figure 2 The integrated circuit assembly 200 includes a first wafer die 210 and a second wafer die 220, wherein the first wafer die 210 and the second wafer die 220 are stacked. The first wafer die 210 and the second wafer die 220 can be packaged together to form a chip, or as an integrated circuit assembly, form a chip package structure with other wafer die or substrate.

[0039] Specifically, the first wafer die 210 and the second wafer die 220 may utilize 3D wafer-level packaging. Generally speaking, 3D wafer-level packaging refers to an integrated circuit assembly constructed by packaging two or more wafer layers. 3D wafer-level packaging includes processes such as hybrid bonding (HB), through-silicon vias (TSVs), and redistribution layers (RDLs).

[0040] The wafer layer (wafer) is composed of pure silicon (Si) and includes a front side and a back side. The front side of the wafer layer is the main working surface on the wafer for chip production. The front side usually has a specific orientation and lattice structure for growing or building transistors, circuits, and other semiconductor devices thereon, that is, the front side is provided with a wiring layer. The back side of the wafer layer is also called the back surface or backing, which is opposite to the front side. The back side is usually flat and has no crystal structure. It is used to provide mechanical stability for supporting and handling the wafer. The back side usually does not have circuits or devices and can be specially treated or coated to meet specific needs, such as enhancing adhesion or improving thermal conductivity.

[0041] Specifically, hybrid bonding is a method for achieving denser interconnections between stacked chips. The hybrid bonding process allows wafers to be stacked face-to-face. The primary function of through-silicon vias (TSVs) is to provide electrical extension and interconnection along the Z-axis (the coordinate axis perpendicular to the plane of the wafer layers). The redistribution layer (RDL) provides electrical extension and interconnection along the XY plane (the plane of the wafer layers). In advanced packaging technologies like FIWLP (Fan-In Wafer Level Package) and FOWLP (Fan-Out Wafer Level Package), RDL is a key technology. It is used to fan-in or fan-out IO pads, creating different types of wafer-level packaging.

[0042] Specifically, the first wafer die 210 and the second wafer die 220 may be connected to each other through hybrid bonding via bonding points on corresponding surfaces.

[0043] Furthermore, the first wafer die 210 is formed with a plurality of processing elements (PEs), such as Figure 3 As shown, multiple operation units 211 are used to perform logical operations in parallel. In some examples, the operation units can be stream processors or cores in stream processors. Multiple access control units 221 are formed in the second wafer die 220, such as Figures 4A-4C shown.

[0044] It should be understood that the term "die" in this context refers to a die produced through a specific process within a wafer layer. For example, the first and second dies may be logic dies produced using a logic device process, while the third die may be a memory die produced using a memory device process.

[0045] Each operation unit 211 corresponds to multiple access control units 221 . Each operation unit 211 sends at least one data access instruction to at least one access control unit 221 , so that each access control unit 221 responds to the corresponding data access instruction to perform data access.

[0046] In an embodiment of the present invention, the first wafer die and the second wafer die are stacked, which fully utilizes the corresponding surface difference between the first wafer die and the second wafer die, improves the data transmission bandwidth between the first wafer die and the second wafer die, and reduces the data transmission delay. Therefore, when each operation unit sends at least one data access instruction to at least one access control unit respectively, the data access efficiency is further improved.

[0047] Furthermore, a third wafer die provided with a plurality of storage units may be provided Figure 2 Accordingly, each access control unit can access at least one storage unit in the third wafer die (eg, via the interposer) in response to a corresponding data access instruction.

[0048] Furthermore, a first inter-chip wiring is formed between the first wafer bare die 210 and the second wafer bare die 220, thereby improving the parallel data access bandwidth. Figure 3 In the example, a first unit array is formed in the first wafer bare die 210, and the first unit array includes multiple operation units 211. The multiple operation units 211 are connected via first intra-chip wiring, and each operation unit sends at least one data access instruction to at least one access control unit via first inter-chip wiring.

[0049] Furthermore, the first intra-chip wiring is connected to the multiple access control units via the first inter-chip wiring. Thus, the first intra-chip wiring facilitates parallel data processing between the multiple computing units. The first intra-chip wiring is connected to the multiple access control units via the first inter-chip wiring, thereby balancing parallel data processing efficiency and data access efficiency.

[0050] In addition, each computing unit is provided with a local cache unit, and each computing unit can access the local cache unit through a local connection with the local cache unit. For example, the local cache unit can be a level 1 cache L1.

[0051] Furthermore, the first intra-chip wiring includes a plurality of first wiring nodes corresponding to the plurality of computing units, and a first wiring network interconnecting the plurality of first wiring nodes. Thus, the first intra-chip wiring is formed by the plurality of first wiring nodes and the first wiring network. Connected by the first intra-chip wiring and the first inter-chip wiring, the first unit array is fully utilized to compactly arrange the computing units within the first wafer die, while also improving parallel data processing efficiency.

[0052] Further, in Figure 4A In the example, a second cell array is formed in the second wafer die 220. The second cell array includes multiple access control units 221 and multiple first shared cache units 21. Each access control unit 221 corresponds to at least one first shared cache unit 21, and each first shared cache unit 21 is shared by at least two computing units 211. Therefore, placing each first shared cache unit in the second cell array improves the data transmission bandwidth between each first shared cache unit and each computing unit, greatly improving computing efficiency when each computing unit performs parallel computing processing with the help of each first shared cache unit.

[0053] Furthermore, each access control unit 221 is connected to at least one corresponding first shared cache unit 21 via a second intra-chip wiring 23, and the plurality of computing units 211 are connected to the second intra-chip wiring 23 via a first inter-chip wiring. Thus, in the second wafer die 220, the second intra-chip wiring 23 improves the data transmission efficiency between each first shared cache unit 21 and each access control unit 221.

[0054] Furthermore, the second intra-chip wiring 23 includes a plurality of second wiring nodes corresponding to the plurality of access control units 221, and a second wiring network interconnecting the plurality of second wiring nodes. Each access control unit 221 is connected to at least one shared cache unit 21 corresponding to the access control unit 221 via the second wiring node corresponding to the access control unit. Thus, the plurality of computing units 211 are connected to the second intra-chip wiring 23 via the first inter-chip wiring. The second intra-chip wiring 23 is formed by the plurality of second wiring nodes and the second wiring network, making full use of the second unit array to compactly arrange the various access control units 221 in the second wafer bare die 220, while also improving the parallel access efficiency of the various access control units 221.

[0055] Alternatively, in Figure 4B In the example, the second on-chip wiring 23 including the plurality of second wiring nodes and the second wiring network and the first shared cache unit 21 may be distributed in the second cell array.

[0056] In addition, Figure 4CIn the example, the second unit array also includes a plurality of second shared cache units 22, and the cache level of the plurality of first shared cache units 21 is higher than the cache level of the plurality of second shared cache units 22. For example, the first shared cache unit 21 may be a second-level cache L2, and the second shared cache unit 22 may be a third-level cache L3. That is to say, the first shared cache unit 21 is shared by different computing units, and the local shared cache is dedicated to the corresponding computing unit. Compared with the second shared cache unit 21, the second shared cache unit 22 is shared by a wider range of computing units. For example, the second-level cache L2 can be shared between CUDA cores within the same SM, while the third-level cache L3 can be shared by multiple SMs. As a result, all SMs in the GPU can access shared data through the L2 and L3 caches to improve the overall cache efficiency and memory access performance.

[0057] Furthermore, multiple second shared cache units 22, multiple first shared cache units 21, and multiple access control units 221 are connected via second on-chip wiring 23. Therefore, the efficiency of parallel computing is improved by each first shared cache unit, and the efficiency of parallel access is improved by each second shared cache unit. Based on the combination of the two, both parallel computing efficiency and parallel access efficiency are greatly balanced. In addition, the second shared cache units, each first shared cache unit, and each access control unit for row-parallel data processing are connected via the second on-chip wiring, achieving efficient and reliable data transmission in the second cell array.

[0058] The inter-die wiring between the first wafer die 210 (e.g., the computing unit 211) and the second wafer die 220 (e.g., the first shared cache unit 21) includes wiring nodes and wiring network connections. In some examples, the wiring network can be a network on chip (NoC). NoC can be used in on-chip communication architectures within integrated circuits (ICs), serving as an efficient alternative to the global bus structures used for internal communication within an IC chip, breaking down complex communication tasks into smaller, scalable network structures. For example, based on the principles of network interconnection, NoC interconnects functional modules within a chip or wafer die, such as computing units, access control units, cache units, or storage units. Data is transmitted through communication between network nodes, providing high-bandwidth and low-latency data transmission while also offering high reliability and scalability. Alternatively, as another example of a wiring network, the wiring network can be a crossbar array. A crossbar array is an electronic component structure used to implement interconnection and cross-communication, serving as an efficient alternative to the global bus structures used for internal communication within an IC chip. Crossbar arrays are commonly used to implement multiplexing and crossbar switches. For example, a crosspoint array can connect different components or circuits to enable signal routing, data transmission, and interaction between circuits. The crosspoint array interconnects functional modules within a chip or wafer die, such as the arithmetic unit, access control unit, cache unit, or storage unit, enabling data transmission through communication between network nodes. The crosspoint array provides flexibility and scalability. By controlling the crosspoint switch state, the connection configuration between functional modules such as the arithmetic unit, access control unit, cache unit, or storage unit can be realized. The crosspoint array can be increased or decreased as needed to meet more or less interconnection requirements in the system.

[0059] Further, refer to Figure 4D In an example, each computing unit PE in the first wafer die 210 is provided with a first-level cache L1, and each computing unit or its first-level cache L1 is connected to a second intra-chip wiring in the second wafer die 220 via a three-dimensional interconnect (3D link). The second intra-chip wiring can interconnect the various first shared cache units and the various access control units. The second intra-chip wiring can be connected to an external storage structure, for example, directly connected to or connected via an interposer layer to a wafer die (for example, a third wafer die) provided with multiple storage units.

[0060] The following will be combined Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5DDifferent examples of on-chip routing are described below. The on-chip routing 23 of the present embodiment includes a first on-chip routing and a second on-chip routing. It should be understood that the first on-chip routing includes a first routing node 101 and a first routing network formed therefrom, and the second on-chip routing includes a second routing node 201 and a second routing network formed therefrom.

[0061] like Figure 5A As shown, the first intra-chip wiring is arranged in the first unit array of the first wafer bare die 210. The first intra-chip wiring interconnects each operation unit 211 and each first wiring node 101. In some examples, the first unit array can have two array dimensions for interconnection, so as to achieve reliable wiring while ensuring the compactness of the devices of the first unit array. The first wiring nodes 101 are not adjacent to each other, and while maintaining the transmission efficiency of the first wiring network, they provide arrangement space for the operation units 211. For example, in each array dimension, the first wiring nodes 101 are arranged at intervals (that is, arranged at intervals of one array position, or at intervals of two or more array positions). In addition, the operation units 211 are arranged at other array positions. If the ratio between the number of first wiring nodes 101 and the number of operation units 211 is 1:1, then the first wiring nodes 101 are arranged at intervals of one array position.

[0062] like Figure 5B As shown, the second on-chip wiring is arranged in the second cell array of the second wafer die 220. The second wiring nodes 201 are not adjacent to each other, maintaining the transmission efficiency of the second wiring network while providing space for the arrangement of components such as the access control unit 221 and the shared cache unit 20 (the first shared cache unit 21 and / or the second shared cache unit 22). For example, in each array dimension, the second wiring nodes are spaced apart (i.e., spaced apart by one array position, or spaced apart by two or more array positions). Furthermore, the access control units 221 and the shared cache units 20 (the first shared cache unit 21 and / or the second shared cache unit 22) are arranged at other array positions based on the ratio between the number of access control units 221 and the number of shared cache units 20 (the first shared cache unit 21 and / or the second shared cache unit 22). For example, if the ratio between the number of second wiring nodes, the number of access control units 221 and the number of shared cache units 20 (first shared cache units 21 and / or second shared cache units 22) is 2:1:1, adjacent shared cache units 20 or adjacent access control units 221 can be set at two array positions in each dimension so that adjacent shared cache units 20 are evenly distributed in the second unit array, or adjacent access control units 221 are evenly distributed in the second unit array.

[0063] It should be understood that in order to form the on-chip wiring as shown in the figure, it is necessary to form a second wiring network between each second wiring node 201, which can be achieved by interconnecting each second wiring node 201. In addition, in the first unit array, each first wiring node 101 can be connected by Figure 5B Alternatively, direct interconnection is not necessary, because when different computing units perform parallel processing, the frequency of accessing the shared cache unit is higher than direct access between the various computing units.

[0064] like Figure 5C As shown, if the ratio between the number of first wiring nodes 101 and the number of computing units 211 is 1:1, a second wiring node can be provided in the other array dimension for every other array position in one array dimension. Accordingly, a computing unit can be provided in the other array dimension for every other array position in the other array dimension, so that the ratio between the number of first wiring nodes 101 and the number of computing units 211 is 1:1. Thus, by providing each first wiring node 101 along the other array dimension for every other array position in one array dimension, the distribution of the first wiring nodes 101 is ensured while improving the efficiency of the first wiring nodes 101.

[0065] like Figure 5D As shown, if the ratio between the number of second routing nodes 201, the number of access control units 221, and the number of shared cache units 20 is 2:1:1, each second routing node 201 can be arranged along the other array dimension at every other array position in one array dimension, thereby forming a second routing network formed by each second routing node 201. Accordingly, at every other array position in one array dimension, shared cache units 20 and access control units 221 are alternately arranged along the other array dimension, so that the spacing between adjacent access control units 221 in one array dimension is two array positions, and the spacing between adjacent access control units 221 in the other array dimension is four array positions. Furthermore, the spacing between adjacent shared cache units 20 in one array dimension is two array positions, and the spacing between adjacent shared cache units 20 in the other array dimension is four array positions. Thus, by arranging each second routing node 201 along the other array dimension at every other array position in one array dimension, the distribution of each second routing node 201 is ensured while improving the efficiency of the second routing nodes.

[0066] It should be understood that hybrid bonding points between the first wafer die 210 and the second wafer die 220 can be implemented based on some or all of the wiring nodes. For example, hybrid bonding is performed on at least some of the first wiring nodes 101 that correspond to at least some of the second wiring nodes 201, forming inter-die wiring. In some examples, all of the first wiring nodes 101 are aligned with all of the second wiring nodes 201. In other examples, for example, the number of periodic array positions of the first wiring nodes 101 is less than the number of periodic array positions of the second wiring nodes 201, and some of the first wiring nodes 101 are aligned with all of the second wiring nodes 201. In other examples, the number of periodic array positions of the first wiring nodes 101 is greater than the number of periodic array positions of the second wiring nodes 201, and all of the first wiring nodes 101 are aligned with some of the second wiring nodes 201.

[0067] Further, Figure 6 Chip packaging structures according to other embodiments of the present invention are shown. Figure 6 The chip package structure 600 includes a first die 210, a second die 220, a third die 230, and an interposer 240. The second die is stacked between the interposer and the first die, and the second and third die are disposed on the same side of the interposer. In other words, the integrated circuit assembly 200, consisting of the first die 210 and the second die 220, is disposed on the same side of the interposer as the third die.

[0068] It should be understood that the interposer can be a silicon interposer, either a passive interposer or an active interposer. Passive interposers typically use a 2.5D package with the wafer die, and the interposer serves to electrically connect the wafer die. Active interposers include logic process devices, enabling the basic logic and storage architecture of a SoC (System on Chip).

[0069] In some examples, the interposer can utilize a bump structure, such as microbumps or C4 bumps, for ball grid bonding to electrically interconnect with the die wafers. For example, one side of the interposer can be connected to the second and third die wafers via the bump structure, while the other side of the interposer is connected to the package substrate of the chip package structure. Alternatively, the interposer can utilize hybrid bonding points on its surface for hybrid bonding with the die wafers.

[0070] Generally speaking, when the interposer is an active interposer, hybrid bonding is beneficial to the data transmission bandwidth of the second inter-chip wiring and the third inter-chip wiring, reducing data transmission delay. When the interposer is a passive interposer, ball grid bonding is beneficial to compatibility with the traditional process of the interposer.

[0071] For example, the first wafer die 210 and the second wafer die 220 are connected by a first inter-die wiring. Specifically, the first inter-die wiring can be hybrid bonded through each hybrid bonding point on the corresponding surface between the first wafer die 210 and the second wafer die 220.

[0072] Specifically, the first wafer bare die 210 is formed with a plurality of operation units, and the plurality of operation units are used to perform logical operations in parallel. The second wafer bare die 220 is formed with a plurality of access control units. The integrated circuit component composed of the first wafer bare die 210 and the second wafer bare die 220 can refer to the above-mentioned Figure 2 The third wafer die 230 is formed with a plurality of memory cells (not shown) as external memory devices of the integrated circuit assembly.

[0073] In some examples, at least some of the second wiring nodes 201 may also form various ball grid bonding points on the bonding surface of the second wafer die 210 opposite to the interposer 240, and various bonding points are formed on the bonding surface of the interposer 240 corresponding to the second wafer die 210. Some of the second wiring nodes 201 may be selected from all the second wiring nodes 201 so that the ball grid bonding points derived from some of the second wiring nodes 201 correspond to the ball grid bonding points of the interposer 240 (for example, one-to-one correspondence), thereby being compatible with the middle-level process.

[0074] Furthermore, each operation unit 211 corresponds to multiple access control units 221, each access control unit 221 corresponds to at least one storage unit, and each operation unit 211 sends at least one data access instruction to at least one access control unit 221, so that each access control unit 221 responds to the corresponding data access instruction and accesses at least one storage unit in the third wafer bare die 230 via the intermediate layer.

[0075] In an embodiment of the present invention, the first wafer die and the second wafer die are stacked, which fully utilizes the corresponding surface difference between the first wafer die and the second wafer die, improves the data transmission bandwidth between the first wafer die and the second wafer die, and reduces the data transmission delay. Therefore, when each operation unit sends at least one data access instruction to at least one access control unit respectively, the data access efficiency is further improved.

[0076] It should be understood that Figure 7As shown, the second wafer bare die 220 and the third wafer bare die 230 are arranged on the same side surface of the interposer 240, and the number of third wafer bare die 230 can be flexibly set on the interposer. Since the data access bandwidth between the first wafer bare die 210 and the second wafer bare die 220 is improved, it is conducive to setting a larger number of third wafer bare die 230 to improve data storage efficiency.

[0077] It should also be understood that the stacking of the first wafer die 210 and the second wafer die 220 increases the thickness of the wafer die, and a larger number of third wafer die 230 can be stacked while maintaining the compactness of the chip packaging structure, thereby improving data storage efficiency. Figure 7 As shown, the opposite side surface of the interposer 240 on which the integrated circuit component is provided can be used for chip packaging structure, and the other side surface of each of the integrated circuit component 200 and the third wafer bare die 230 stacked with the interposer 240 can be used for chip packaging structure, thereby maintaining the compactness and packaging efficiency of the chip packaging structure.

[0078] In other examples, a second inter-chip wiring is provided between the second wafer bare die 220 and the interposer 240, and a third inter-chip wiring is provided between the third wafer bare die 230 and the interposer 240. The second inter-chip wiring and the third inter-chip wiring are connected in the interposer 240 via a third intra-chip wiring. Each access control unit responds to a corresponding data access instruction and accesses at least one storage unit corresponding to the access control unit via the second inter-chip wiring, the third inter-chip wiring, and the third intra-chip wiring. Thus, the second inter-chip wiring and the third inter-chip wiring are connected in the interposer via the third intra-chip wiring. Therefore, the thickness of the interposer can be set to be thinner, thereby improving the compactness of the chip packaging structure while maintaining data transmission efficiency.

[0079] In other examples, the second wafer bare die 220 and the interposer 240 are connected by a second inter-chip wiring, and the second inter-chip wiring is formed by hybrid bonding between the various bonding points of the second wafer bare die 220 and the first part of the bonding points of the interposer 240, or by ball grid bonding based on the bump structure of the interposer. In addition, the interposer 240 and the third wafer bare die 230 can be connected by a third inter-chip wiring, and the third inter-chip wiring is formed by hybrid bonding between the various bonding points of the third wafer bare die 230 and the second part of the bonding points of the interposer 240, or by ball grid bonding based on the bump structure of the interposer. Therefore, when the interposer is an active interposer, hybrid bonding is beneficial to the data transmission bandwidth of the second inter-chip wiring and the third inter-chip wiring, reducing data transmission delay. When the interposer is a passive interposer, ball grid bonding is beneficial to compatibility with the traditional process of the interposer.

[0080] More specifically, in the case of a single third wafer die, the third inter-die wiring can be formed by hybrid bonding at various hybrid bonding points on corresponding surfaces between the interposer 240 and the third wafer die 230, using ball grid bonding based on the bump structure of the interposer. In the case of multiple third wafer dies, for adjacently stacked interposers 240 and third wafer dies 230, hybrid bonding at various hybrid bonding points on corresponding surfaces between the interposer 240 and the third wafer die 230 can be formed by ball grid bonding based on the bump structure of the interposer. For non-adjacently stacked interposers 240 and third wafer dies 230, the memory cells in such third wafer die can be connected to the third wafer die 230 stacked adjacent to the interposer 240 through a cross-wafer layer connection technology such as through silicon vias (TVS), and then connected to the interposer 240 through hybrid bonding or ball grid bonding based on the bump structure of the interposer. That is to say, the storage unit in any third wafer die of two adjacently stacked third wafer dies can be connected to the other third wafer die through hybrid bonding, and the two non-adjacently stacked third wafer dies can pass through the middle wafer die of the two third wafer dies through silicon via technology, and then be connected through hybrid bonding at various bonding points on the contrasting surfaces of the two adjacently stacked third wafer dies.

[0081] Thus far, specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0082] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0083] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0084] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. An integrated circuit assembly comprising: A first wafer die is formed with a plurality of operation units, wherein the plurality of operation units are used to perform logic operations in parallel; a second wafer die stacked with the first wafer die, wherein a plurality of access control units are formed in the second wafer die; Each operation unit corresponds to the multiple access control units, and each operation unit sends at least one data access instruction to at least one access control unit, so that each access control unit responds to the corresponding data access instruction to perform data access.

2. The integrated circuit assembly according to claim 1, wherein: A first inter-die wiring is formed between the first wafer bare die and the second wafer bare die, and each operation unit sends at least one data access instruction to at least one access control unit via the first inter-die wiring.

3. The integrated circuit assembly of claim 2, wherein: A first cell array is formed in the first wafer die. The first cell array includes the multiple operation units. The multiple operation units are connected via a first intra-chip wiring. The first intra-chip wiring is connected to the multiple access control units via a first inter-chip wiring.

4. The integrated circuit assembly of claim 3, wherein: Each computing unit is provided with a local cache unit.

5. The integrated circuit assembly according to claim 3, wherein: The first on-chip wiring includes a plurality of first wiring nodes corresponding to the plurality of operation units, and a first wiring network interconnecting the plurality of first wiring nodes.

6. The integrated circuit assembly of claim 2, wherein: A second cell array is formed in the second wafer die, and the second cell array includes the multiple access control units and multiple first shared cache units, each access control unit corresponds to at least one first shared cache unit, and each first shared cache unit is shared by at least two operation units.

7. The integrated circuit assembly of claim 6, wherein: Each access control unit is connected to the corresponding at least one first shared cache unit via a second intra-chip wiring, and the plurality of operation units are connected to the second intra-chip wiring via the first inter-chip wiring.

8. The integrated circuit assembly of claim 7, wherein: The second on-chip wiring includes multiple second wiring nodes corresponding to the multiple access control units, and a second wiring network interconnecting the multiple second wiring nodes. Each access control unit is connected to at least one shared cache unit corresponding to the access control unit via the second wiring node corresponding to the access control unit.

9. The integrated circuit assembly of claim 7, wherein: The second cell array also includes multiple second shared cache units, and the cache level of the multiple first shared cache units is higher than the cache level of the multiple second shared cache units, wherein the multiple second shared cache units, the multiple first shared cache units and the multiple access control units are connected via the second on-chip wiring.

10. A chip packaging structure, comprising: A first wafer die is formed with a plurality of operation units, wherein the plurality of operation units are used to perform logic operations in parallel; A second wafer die is formed with a plurality of access control units; A third wafer bare die is formed with a plurality of memory cells; Intermediary layer; The second wafer die is stacked between the interposer and the first wafer die, and the second wafer die and the third wafer die are arranged on the same side surface of the interposer; Among them, each operation unit corresponds to the multiple access control units, each access control unit corresponds to at least one storage unit, and each operation unit sends at least one data access instruction to at least one access control unit, so that each access control unit responds to the corresponding data access instruction and accesses at least one storage unit in the third wafer bare die via the intermediate layer.

11. The chip packaging structure according to claim 10, wherein: A second inter-chip wiring is provided between the second wafer bare die and the interposer, a third inter-chip wiring is provided between the third wafer bare die and the interposer, the second inter-chip wiring and the third inter-chip wiring are connected in the interposer through a third intra-chip wiring, and each access control unit responds to a corresponding data access instruction and accesses at least one storage unit corresponding to the access control unit via the second inter-chip wiring, the third inter-chip wiring, and the third intra-chip wiring.

12. The chip packaging structure according to claim 11, wherein: The second inter-chip wiring is formed by hybrid bonding of the bonding points of the second wafer die and the first part of the bonding points of the interposer, and the third inter-chip wiring is formed by hybrid bonding of the bonding points of the third wafer die and the second part of the bonding points of the interposer.

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