Novel integrated BUCK voltage stabilizer parallel resonance drive circuit

Abstract

The invention discloses a novel integrated BUCK voltage stabilizer parallel resonance drive circuit which comprises a resonant cavity, a hard switch module and a charge pump like module. The resonant cavity is formed by serially connecting an inductor and a resonant capacitor; the hard switch module is composed of complementary MOS tubes and used for controlling the grid voltage of the first PMOS tube after charging and discharging are completed. The similar charge pump module optimizes the voltage division strategy of the charging and discharging process by dynamically switching the connection path of the resonant cavity; specifically, in the discharge stage, the resonant cavity is grounded to form VDD-GND partial voltage, and the voltage difference between the grid voltage of the first PMOS tube and the resonant capacitor is increased; in the charging stage, the resonant cavity is connected to the 1 / 2VDD, and the voltage of the resonant capacitor is pre-charged to the 1 / 2VDD so as to compensate the energy loss of the RLC loop. According to the invention, the resonant driving circuit is connected to the charge pump-like structure, and the voltage swing when the resonant driving circuit independently drives the grid is effectively improved by means of capacitance voltage division from the input voltage to the ground.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a novel integrated BUCK regulator parallel resonant drive circuit. Background Art

[0002] As processor performance increases and computing power demands surge, power management chips must achieve efficient voltage regulation, low-ripple output, and optimized thermal management under high-frequency dynamic loads. This poses a significant challenge to the power supply architecture for high-density computing scenarios such as multi-core processors and AI chips. The current mainstream power supply architecture is a two-stage architecture. The first-stage, off-chip voltage regulation module (VRM), converts the 12-48V DC voltage into a low-voltage 1-4V DC input for the processor, while the second-stage, on-chip integrated voltage regulator (IVR) directly supplies power. However, the high-frequency development of IVRs faces a bottleneck. While increasing switching frequency can reduce size, the drive loss conflicts with the stacked switch design of advanced process nodes. This results in a significant reduction in efficiency at high frequencies (for example, FIVR efficiency is only 83% at 100MHz), hindering the evolution of IVRs towards higher power density and dynamic performance. Currently, there is a lot of research on reducing IVR drive loss, with resonant gate drive technology being one of the most representative control algorithms.

[0003] Traditional parallel resonant drive circuits consist of a resonant cavity and a hard switch. Resonant gate drive technology has been extensively researched for nearly two decades. It uses a resonant cavity consisting of an inductor and capacitor in series with the switch gate, replacing the traditional inverter hard switch for gate charging and discharging. When the high-side PMOS transistor needs to be discharged, the MOS switch is turned on, allowing the charge stored in the PMOS gate parasitic capacitance to be transferred to the resonant cavity capacitor through the resonant path. After half a resonant cycle, the gate voltage reaches its minimum and the voltage on the resonant capacitor reaches its maximum. At this point, when the current in the resonant drive path is zero, the transistor switch is turned off, completing the resonant drive discharge process. The gate is then clamped to 1 / 2 VDD by a designed hard switch to prevent erroneous gate level flips. When the gate needs to be charged again, the charge from the resonant cavity capacitor is injected back into the gate, and then hard-clamped to VDD, thereby recovering the injected gate charge energy and reducing drive losses.

[0004] However, according to relevant research results, the introduction of parasitic capacitance is inevitable with advanced manufacturing processes, and the imperfect manufacturing process for small-value inductors introduces many error factors. As a result, after half a resonant cycle, when the resonant cavity completes discharge to the gate, only a portion of the energy is successfully collected by the resonant cavity capacitor. At this time, the gate voltage differs significantly from 1 / 2VDD, and Vgs is insufficient to fully drive the high-side PMOS switch to conduct. When the charge collected by the resonant inductor needs to be re-injected into the gate, the PMOS gate potential is also insufficient to completely shut down the PMOS. Therefore, due to the non-ideal effects brought about by advanced processes, the traditional parallel resonant drive circuit has very limited effect in reducing power consumption in low-voltage IVR scenarios. Summary of the Invention

[0005] The present invention aims to provide a novel integrated buck regulator parallel resonant drive circuit, designed to improve the problem of parallel resonance, where the resonant voltage swing cannot fully drive the high-side PMOS switch at low quality factors. By connecting the resonant drive circuit to a charge pump-like structure and utilizing a capacitive voltage divider from the input voltage to ground, the present invention effectively increases the voltage swing of the resonant drive circuit when driving the gate alone. The proposed circuit is typically used in integrated buck converters and is compatible with most existing integrated regulators.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] A novel integrated buck regulator parallel resonant drive circuit includes a resonant cavity, a hard switch module, a charge pump-like module, a first PMOS transistor, and a second PMOS transistor;

[0008] The source of the first PMOS transistor is connected to the first power supply voltage, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the output terminal;

[0009] The resonant cavity is composed of an inductor and a resonant capacitor connected in series, wherein a first end of the inductor not connected to the resonant capacitor is connected to the gate of the first PMOS transistor, and a second end is connected to the charge pump-like module via the resonant capacitor. During a discharge phase, the resonant cavity transfers charge in the parasitic capacitance of the gate of the first PMOS transistor to the resonant capacitor through a resonance process, storing a portion of the energy to reduce the gate voltage Vg of the first PMOS transistor to approach 1 / 2VDD. During a charging phase, the charge stored in the resonant capacitor is reversely injected back into the parasitic capacitance of the gate of the first PMOS transistor to supplement the energy required for gate drive and to restore the gate voltage Vg of the first PMOS transistor to approach VDD. VDD is the voltage value of the first power supply voltage.

[0010] The hard switch module is composed of complementary MOS transistors and is used to control the gate voltage Vg of the first PMOS transistor after charging and discharging. Specifically, after discharging, the hard switch module forcibly clamps the gate voltage Vg of the first PMOS transistor to 1 / 2 VDD; after charging, the hard switch module clamps the gate voltage Vg of the first PMOS transistor to VDD.

[0011] The charge pump-like module optimizes the voltage division strategy of the charging and discharging process by dynamically switching the connection path of the resonant cavity. Specifically, in the discharge phase, the resonant cavity is grounded to form a VDD-GND voltage divider, thereby increasing the voltage difference between the gate voltage of the first PMOS tube and the resonant capacitor. In the charging phase, the resonant cavity is connected to 1 / 2VDD, and the voltage of the resonant capacitor is precharged to 1 / 2VDD to compensate for the energy loss of the RLC circuit.

[0012] Furthermore, the hard switch module includes a third PMOS transistor and a first NMOS transistor;

[0013] The source of the third PMOS tube is connected to the first power supply voltage, and the drain is connected to the drain of the first NMOS tube; the source of the first NMOS tube is connected to the second power supply voltage and the gate of the second PMOS tube respectively; the voltage value of the second power supply voltage is 1 / 2VDD.

[0014] Furthermore, the charge pump-like module includes a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

[0015] The source of the second NMOS tube and the gate of the second NMOS tube are both connected to the gate of the second PMOS tube; the drain of the second NMOS tube and the drain of the third NMOS tube are both connected to the end of the resonant capacitor that is not connected to the inductor; the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded.

[0016] Furthermore, when the resonant circuit is the first PMOS transistor gate parasitic capacitance discharged from VDD to 1 / 2VDD, the precise time domain state of the resonance is obtained by the following second-order equation:

[0017]

[0018] in, Cg represents the parasitic capacitance value of the gate of the first PMOS tube, Cr represents the resonant capacitance value; Vg represents the potential of the parasitic capacitance of the gate of the first PMOS tube, Vr represents the potential of the resonant capacitor connected to the inductor, R represents the DC on-resistance of the switching transistor, and L is the inductance value of the resonant cavity.

[0019] Furthermore, after the first resonant half cycle 1 / 2Tr, the potential Vg of the parasitic capacitance of the gate of the first PMOS tube and the potential Vr of the terminal connected to the inductor of the resonant capacitor are respectively:

[0020]

[0021] Where,

[0022] Compared with the prior art, the novel integrated buck regulator parallel resonant drive circuit of the present invention has the following beneficial effects:

[0023] (1) Driving efficiency is significantly improved: By synergistically optimizing the charging and discharging paths through the resonant cavity and charge pump, the low quality factor (Q value) of the RLC circuit in low-voltage scenarios is compensated. Compared with traditional resonant drive circuits, driving losses are reduced by 25%; compared with hard-switching solutions, losses are further reduced by 53%, significantly improving energy utilization efficiency.

[0024] (2) Precise control of voltage swing: The charge pump-like circuit reduces the gate voltage (Vg) from VDD to approximately 1 / 2VDD during the discharge phase (conventional circuits only reach 5 / 8VDD). During the charge phase, it precharges to 1 / 2VDD and reversely injects charge, raising Vg to approximately 7 / 8VDD (conventional circuits are 3 / 4VDD). The voltage swing is closer to the ideal threshold, reducing the ambiguity of the switching state and improving the on-off reliability of the PMOS.

[0025] (3) Hard switching loss optimization: The hard switch is only activated briefly after the charge and discharge are completed, completing the precise clamping of Vg (1 / 2VDD or VDD), avoiding the additional loss caused by frequent switching of hard switches in traditional solutions, while preventing parasitic oscillations and level errors.

[0026] (4) Overall system performance improvement: Experimental data shows that the overall efficiency of this circuit reaches 87% under 10MHz / 2A operating conditions, which is 1% higher than the traditional resonant drive and 4% higher than the hard switch, meeting the stringent requirements of high-performance processors for high power density and low thermal management. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of a novel integrated BUCK regulator parallel resonant drive circuit of the present invention;

[0028] Figure 2 This is the equivalent schematic diagram of the resonant cavity RL2C;

[0029] Figure 3 The present invention improves the resonant drive working waveform;

[0030] Figure 4It is a schematic diagram of the working process of the improved parallel resonant drive charging process;

[0031] Figure 5 It is a schematic diagram of the working process of the improved parallel resonant drive discharge process;

[0032] Figure 6 This is the waveform of the resonant drive charging output voltage and current;

[0033] Figure 7 It is the waveform of the resonant drive discharge output voltage and current. DETAILED DESCRIPTION

[0034] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0035] See also Figure 1 The present invention discloses a novel integrated BUCK regulator parallel resonant drive circuit, the circuit comprising a resonant cavity, a hard switch module, a charge pump-like module, a first PMOS transistor and a second PMOS transistor;

[0036] The source of the first PMOS transistor is connected to the first power supply voltage, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the output terminal;

[0037] The resonant cavity is composed of an inductor and a resonant capacitor connected in series, wherein a first end of the inductor not connected to the resonant capacitor is connected to the gate of the first PMOS transistor, and a second end is connected to the charge pump-like module via the resonant capacitor. During a discharge phase, the resonant cavity transfers charge in the parasitic capacitance of the gate of the first PMOS transistor to the resonant capacitor through a resonance process, storing a portion of the energy to reduce the gate voltage Vg of the first PMOS transistor to approach 1 / 2VDD. During a charging phase, the charge stored in the resonant capacitor is reversely injected back into the parasitic capacitance of the gate of the first PMOS transistor to supplement the energy required for gate drive and to restore the gate voltage Vg of the first PMOS transistor to approach VDD. VDD is the voltage value of the first power supply voltage.

[0038] The hard switch module is composed of complementary MOS transistors and is used to control the gate voltage Vg of the first PMOS transistor after charging and discharging. Specifically, after discharging, the hard switch module forcibly clamps the gate voltage Vg of the first PMOS transistor to 1 / 2 VDD; after charging, the hard switch module clamps the gate voltage Vg of the first PMOS transistor to VDD.

[0039] The charge pump-like module optimizes the voltage division strategy of the charging and discharging process by dynamically switching the connection path of the resonant cavity. Specifically, in the discharge phase, the resonant cavity is grounded to form a VDD-GND voltage divider, thereby increasing the voltage difference between the gate voltage of the first PMOS tube and the resonant capacitor. In the charging phase, the resonant cavity is connected to 1 / 2VDD, and the voltage of the resonant capacitor is precharged to 1 / 2VDD to compensate for the energy loss of the RLC circuit.

[0040] Since each resonant driving process only occurs within half a resonant cycle after the switch is turned on, the entire resonant driving process of the resonant cavity can be regarded as a process of charging and discharging the two capacitors of the inductor Lr, the resonant capacitor Cr, and the gate capacitor Cg of the first PMOS tube in series resonance. Therefore, the present invention simplifies the resonant gate drive circuit into an RL2C circuit and performs time domain modeling on the resonant drive circuit, as shown in the following example: Figure 2 As shown in Figure 2, when a resonant circuit is required for the gate parasitic capacitance Cg to discharge from VDD to 1 / 2VDD, the precise time domain state of resonance can be obtained by the following second-order equation:

[0041]

[0042] Where Vg and Vr represent the gate capacitance Cg of the first PMOS transistor and the potential at the terminal where the resonant capacitor Cr is connected to the inductor, respectively. R is the DC on-resistance Rmos of the switching transistor. Since the resonant system is in underdamped operation, the time domain solution for the voltage difference across the two capacitors is as follows:

[0043]

[0044] At the same time, if 1 / 2VDD is used as the reference potential, the charge conservation law gives:

[0045]

[0046] After the first resonant half cycle 1 / 2Tr, Vg and Vr are obtained as follows:

[0047]

[0048] Under the existing CMOS process, the on-resistance (Rmos) of the switching transistor is 500mΩ~1.5Ω, and the gate parasitic capacitance (Cg) is 600pF~800pF, while it is difficult for the integrated inductor to achieve a large inductance value (typical value 2nH, quality factor Q≈10). The quality factor Q of the RLC resonant circuit thus formed is only 2~4, resulting in the gate voltage reaching only 5 / 8VDD after discharge (much higher than the 1 / 2VDD required for complete shutdown), and the PMOS gate potential is only 3 / 4VDD after the pre-stored charge (3 / 4VDD×Cr) of the resonant capacitor is injected, and it cannot be completely shut down. The traditional solution has limited effect in suppressing driving losses in low-voltage scenarios, so the design of the present invention is to use a CMOS process to reduce the on-resistance of the switching transistor. Figure 1The integrated voltage regulator parallel resonant driving circuit based on the charge pump shown in the figure adds a circuit structure similar to the charge pump (Charge Bump) to the original resonant driving circuit.

[0049] When discharging the gate and collecting energy in the resonant cavity, the resonant cavity is directly connected to GND through a cascode. Then, when the resonant cavity capacitance needs to be re-injected into the gate, the resonant cavity is connected to 1 / 2VDD to push the charge on the resonant cavity capacitance into the gate. The timing diagram and current distribution of the resonant drive circuit with a charge pump structure are shown in the figure below. Figure 3 、 Figure 4 as well as Figure 5 shown.

[0050] The charge pump-like structure provides a different resonant path for the resonant cavity when charging and discharging the gate. When the gate needs to be discharged, the transistor is turned on and directly connected to ground. Although the quality factor of the resonant circuit is not significantly improved, the voltage divider between VDD and GND can be used between the resonant cavity capacitor and the gate capacitor to compensate for the insufficient gate discharge during the resonance process due to the low-Q, high-loss RLC. Therefore, compared to the original parallel resonant drive circuit, the improved resonant drive circuit can reduce the gate voltage to a lower level during the gate discharge process, and the voltage difference on the resonant capacitor will also be larger.

[0051] When the resonant drive charges the gate, the resonant capacitor is connected to 1 / 2VDD. At this time, the potential of the resonant capacitor connected to the inductor is greater than VDD. Even though a lot of energy will be lost in the switching transistor after the RLC series resonance, the remaining energy is sufficient to charge the gate to a very high voltage. Finally, only part of the clamping charge is provided by the hard switch, and the gate of the PMOS is charged to VDD.

[0052] Similar to the derivation results of the traditional resonant drive RL2C model, the improved circuit still has an underdamped RLC timing process.

[0053]

[0054] Using the same device parameters as traditional resonant drive circuits, we can see that after half a resonant cycle, the gate voltage is discharged to 1 / 2 VDD, which is sufficient to fully turn on the top PMOS transistor (the first PMOS transistor). Similarly, when the resonant cavity needs to recharge the top PMOS transistor, the gate voltage can also be charged to approximately 7 / 8 VDD. At this point, the Vgs voltage of the top PMOS transistor is approximately 400 mV, which is lower than the threshold voltage of the top PMOS transistor and is close to completely shutting down the top transistor. Finally, a simple hard switch can be used to clamp the gate voltage. Compared to traditional resonant drive circuits, this also avoids the switching losses caused by hard switching on the driver side or the inverter chain.

[0055] To more clearly illustrate the present invention, Virtuoso was used to simulate the proposed improved resonant drive circuit under the circuit conditions shown in Table 1. In order to meet the load requirements, the power stage switch needs to connect enough transistors in parallel when designing the high-side switch tube to reduce the on-resistance of the complete switch. The simulation waveforms obtained from the proposed improved resonant drive and the simulation waveforms obtained when the traditional parallel resonant circuit is used to charge and discharge the same high-side PMOS switch are shown in Figure 1. Figure 6 and Figure 7 shown.

[0056] Table 1 High-side switch device parameters

[0057] Parameter Type Numerical Craftsmanship 65nm CMOS Device 2.5V PMOS Gate length 10um Gate width 280nm Gate-source capacitance 6.117fF Gate-drain capacitance 2.316fF Number of gates 32 Parallel quantity 999

[0058] When the circuit operates at 20MHz and 2A output current, the driving loss of the high-side switch tube and the overall system efficiency are shown in Table 2.

[0059] Table 2 Comparison of losses in different drive circuits

[0060] Drive type High-side switch drive losses System peak efficiency Hard switch 74.99mW 83％ Traditional parallel resonant drive 48.16mW 86％ Resonant drive circuit proposed by the present invention 36.96mW 87％

[0061] from Figure 6 and Figure 7 As can be seen in Figure 2, the charge pump-like resonant drive circuit effectively increases the voltage swing when driving the gate alone, reducing the energy required for hard-switching clamping. Table 2 also shows that the charge pump-like resonant drive significantly reduces the drive loss of the high-side transistor compared to hard-switching, and slightly improves energy efficiency compared to traditional parallel resonant drive.

[0062] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0063] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A novel integrated buck regulator parallel resonant drive circuit, characterized in that: The circuit includes a resonant cavity, a hard switch module, a charge pump-like module, a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor is connected to the first power supply voltage, and the drain is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to the output terminal; The resonant cavity is composed of an inductor and a resonant capacitor connected in series, wherein a first end of the inductor not connected to the resonant capacitor is connected to the gate of the first PMOS transistor, and a second end thereof is connected to the charge pump-like module via the resonant capacitor. During a discharge phase, the resonant cavity transfers charge in the parasitic capacitance of the gate of the first PMOS transistor to the resonant capacitor through a resonance process, storing a portion of the energy to reduce the gate voltage Vg of the first PMOS transistor to approximately 1 / 2 VDD. During charging, the charge stored in the resonant capacitor is injected back into the parasitic capacitance of the gate of the first PMOS transistor, replenishing the energy required for gate drive to raise the gate voltage Vg of the first PMOS transistor to approach VDD; VDD is the voltage value of the first power supply voltage; The hard switch module is composed of complementary MOS transistors and is used to control the gate voltage Vg of the first PMOS transistor after charging and discharging. Specifically, after discharging, the hard switch module forcibly clamps the gate voltage Vg of the first PMOS transistor to 1 / 2 VDD; after charging, the hard switch module clamps the gate voltage Vg of the first PMOS transistor to VDD. The charge pump-like module optimizes the voltage division strategy during the charge and discharge process by dynamically switching the connection path of the resonant cavity. Specifically, during the discharge phase, the resonant cavity is grounded to form a VDD-GND voltage division, thereby increasing the voltage difference between the gate voltage of the first PMOS transistor and the resonant capacitor. During the charging phase, the resonant cavity is connected to 1 / 2VDD, and the voltage of the resonant capacitor is precharged to 1 / 2VDD to compensate for the energy loss of the RLC circuit.

2. The novel integrated buck regulator parallel resonant drive circuit according to claim 1, characterized in that: The hard switch module includes a third PMOS transistor and a first NMOS transistor; The source of the third PMOS tube is connected to the first power supply voltage, and the drain is connected to the drain of the first NMOS tube; the source of the first NMOS tube is connected to the second power supply voltage and the gate of the second PMOS tube respectively; the voltage value of the second power supply voltage is 1 / 2VDD.

3. The novel integrated buck regulator parallel resonant drive circuit according to claim 1, characterized in that: The charge pump-like module includes a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The source of the second NMOS tube and the gate of the second NMOS tube are both connected to the gate of the second PMOS tube; the drain of the second NMOS tube and the drain of the third NMOS tube are both connected to the end of the resonant capacitor that is not connected to the inductor; the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the fourth NMOS tube is grounded.

4. The novel integrated buck regulator parallel resonant drive circuit according to claim 1, characterized in that: When the resonant circuit is the first PMOS transistor gate parasitic capacitance discharged from VDD to 1 / 2VDD, the precise time domain state of resonance is obtained by the following second-order equation: in, Cg represents the parasitic capacitance value of the gate of the first PMOS tube, Cr represents the resonant capacitance value; Vg represents the potential of the parasitic capacitance of the gate of the first PMOS tube, Vr represents the potential of the resonant capacitor connected to the inductor, R represents the DC on-resistance of the switching transistor, and L is the inductance value of the resonant cavity.

5. The novel integrated buck regulator parallel resonant drive circuit according to claim 4, characterized in that: After the first resonant half cycle 1 / 2Tr, the potential Vg of the parasitic capacitance of the first PMOS transistor gate and the potential Vr of the resonant capacitor connected to the inductor are obtained respectively: Where,

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