An oscillator circuit for a PWM controller

Abstract

The present application belongs to the technical field of electronic circuit, and particularly relates to an oscillator circuit for a PWM controller. The oscillator circuit comprises an oscillator module, a feedback loop and a current detection circuit; a hiccup module, according to the level of an input PWM logic control signal, a data selector selects the input signal to control the on-off of a transmission gate, and establishes a charging and discharging process, thereby providing a delay start function for the oscillator module; and a frequency jitter module, which combines and selects current sources I'ref and I1-I4 to output different sizes of current sources Iref0, and outputs different sizes of four-way current sources Iref1-Iref4 through a current mirror array, thereby providing charging and discharging currents for the oscillator module and the hiccup module. The present application dynamically adjusts the PWM frequency, matches the switching frequency with the load demand, reduces the number of invalid switching times, and greatly reduces the power consumption.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit for a PWM controller. BACKGROUND

[0002] An oscillator circuit is a key electronic circuit that can generate periodic electrical signals (such as sine waves, square waves, or pulse waves), and is widely used in communication, consumer electronics, industrial control, and instruments and meters. In communication systems, oscillators are used to generate carrier signals to ensure the stability of wireless transmission; in consumer electronics (such as smartphones and Internet of Things devices), they provide reference frequencies for clock circuits to ensure the synchronous operation of processors and sensors; in industrial control, oscillators drive PWM controllers to regulate motor speed and power conversion efficiency; and in precision instruments (such as medical devices and test instruments), high-frequency low-noise oscillators are the core of high-precision measurement.

[0003] The current PWM controller oscillator industry is in a period of technological transformation. Although traditional RC charging and discharging and ring oscillator architectures are still mainstream, they face new challenges of high frequency, low power consumption, and strong anti-interference. International giants maintain their leadership through digital DCO and smart spread spectrum technology, while domestic manufacturers are accelerating the import substitution in the mid-low end market. With the trend of high frequency brought by the popularization of GaN / SiC power devices, and the stringent requirements of automotive electronics and industrial power supplies for high reliability, the industry urgently needs to break through key technical bottlenecks such as high-precision temperature compensation, ultra-low static power consumption (<10 μA), and adaptive EMI suppression while maintaining cost advantages, to promote the evolution of oscillator architecture towards a hybrid signal direction of "analog core + digital calibration + intelligent regulation", to meet the differentiated needs of emerging markets such as 5G power supplies and new energy vehicles.

[0004] In the prior art, the oscillator circuit of the PWM pulse width modulation controller usually adopts a design based on RC charging and discharging or a ring oscillator. The core function is to generate a stable frequency signal to set the switching period of the PWM. The following is a brief description of two mainstream technical solutions: ① The first technical solution adopts an RC charging and discharging oscillator. A triangular wave or a sawtooth wave is generated through the charging and discharging process of the resistor R and the capacitor C, and a clock signal required by the PWM is generated by the comparator. Key components in a typical circuit include a timing resistor RT and a capacitor CT that determine the frequency, and a comparator that compares the triangular wave with a reference voltage to output a square wave clock. In the charging phase, the current source charges the capacitor through the resistor, and the voltage rises linearly. In the discharging phase, when the capacitor voltage reaches the upper threshold, the internal switch such as the MOS tube is turned on, and the capacitor is quickly discharged to the lower threshold, and the cycle is repeated. Advantages of this circuit: simple structure, low cost, and flexible frequency adjustment through RC value; disadvantages: poor frequency stability, affected by temperature / component precision, and significant charging and discharging nonlinearity error in high-frequency scenarios. ② Another technical solution adopts a ring oscillator. A feedback loop is formed by using an odd number of inverters (such as 3 or 5), and a square wave is generated by self-oscillation through gate delay. Key components of a typical circuit include a CMOS inverter chain as the basic oscillation unit and a regulation circuit such as a varactor or a current source for frequency modulation. Each inverter introduces a delay td, and the total period T = 2 x n x td (n is the number of stages), which can be adjusted by the voltage-controlled delay VCD to adjust the frequency, forming a voltage-controlled oscillator VCO. Advantages of this circuit: suitable for integrated circuit IC design, no external RC required, good high-frequency performance (up to MHz level); disadvantages: frequency is greatly affected by process deviation and power supply noise; high area / power consumption for low-frequency applications.

[0005] In summary, the PWM controller in the prior art has the following defects:

[0006] (1) Weak anti-interference ability: both traditional solutions are easily affected by external noise (such as power supply ripple, coupled interference), and high-frequency EMI (such as di / dt noise of switching power supply) may be coupled to the RC circuit through parasitic capacitance, causing distortion of the charging and discharging waveform and destroying the linearity of the PWM duty cycle.

[0007] (2) Slow dynamic adjustment response: when adjusting the frequency in real time (such as variable frequency control), the charging and discharging inertia of the RC circuit or the phase-locked delay of the ring oscillator will cause response lag.

[0008] (3) Poor frequency stability: the values of the resistor and the capacitor in the traditional structure change with temperature (such as the temperature coefficient of ceramic capacitors and the TCR of resistors), causing the oscillation frequency to drift.

[0009] (4) Frequency adjustability is poor: when the traditional structure oscillator is adjusted in a wide range, the frequency change rate is inconsistent, and a table or digital compensation is needed, which increases the cost.

[0010] (5) High power consumption: dynamic power consumption is linearly related to frequency, and the overall power consumption rises sharply when high frequency is applied; switching loss is significant, and short-circuit current in the switching process of MOS tube and gate drive loss increase with the increase of frequency. SUMMARY

[0011] The purpose of the present application is to provide an oscillator circuit and charge pump circuit for a PWM controller, which dynamically adjusts the PWM frequency to match the switching frequency with the load demand, reduces the number of invalid switching times, and greatly reduces power consumption; by using constant current charging and discharging instead of resistance, di / dt noise is reduced, and frequency stability is improved; by frequency dithering or intermittent modulation to achieve spread spectrum function, the EMI energy is dispersed to a wider frequency band by slightly modulating the oscillator frequency, thereby reducing peak noise.

[0012] To solve the above technical problems, the present application provides an oscillator circuit for a PWM controller, comprising:

[0013] An oscillator module comprising a feedback loop and a current detection circuit; the input end of the feedback loop inputs the inverted signal X41_YN output by the output end of the current detection circuit, the output end of the feedback loop outputs the signal N4_G to the input end of the current detection circuit, and after comparison processing with the voltage signal VH and the voltage signal VL, the signal X42_YN is output, and after inversion, the signal X41_YN is output;

[0014] A hiccup module that controls the on-off of the transmission gate by gating the input signal of the data selector according to the level of the input PWM logic control signal X840_SNN, and establishes the charging and discharging process to provide a delay start function for the oscillator module;

[0015] A frequency dithering module that combines and gates the current source I'ref and the current sources I1-I4 to output different sizes of current source Iref0, and mirrors the different sizes of four-way current sources Iref1-Iref4 through a current mirror array to provide charging and discharging current for the oscillator module and the hiccup module;

[0016] When the PWM logic control signal X840_SNN is low, the data selector MUX selects the output signal X1225_Y as the signal R720_MINUS, and the working mode enters the hiccup mode, in which the discharging process is the same as in the normal working mode; when the voltage VN4_G drops below the voltage VL, the current source Iref1 does not immediately start charging the capacitor C1, but waits until the capacitor C2 is charged to a voltage VN1_G greater than the voltage VP45_S, the comparator COM3 outputs a high level, and the R end of the RS flip-flop RS2 inputs a low level, and then the current source Iref1 starts charging the capacitor C1.

[0017] Preferably, the feedback loop comprises: an inverter INV1, a PMOS tube P1, an NMOS tube N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN, the output end of the inverter INV1 outputs a signal X41_YN to the gates of the PMOS tube P1 and the NMOS tube N1, the PMOS tube P1 is connected to the drain of the NMOS tube N1 and the capacitor C1 grounded, and serves as an output end to output a signal N4_G, the source of the PMOS tube P1 is connected to a current source Iref1 connected to a power supply X2_D, and the source of the NMOS tube N1 is connected to a current source Iref2 connected to the ground.

[0018] Preferably, the current detection circuit comprises: comparators COM1-COM2, inverters INV2-INV6 and RS flip-flops RS1-RS2; the non-inverting input end of the comparators COM1-COM2 inputs a signal N4_G, the inverting input end of the comparators COM1-COM2 inputs a voltage signal VH and a voltage signal VL respectively, the output end of the comparator COM1 is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to the S end of the RS flip-flop RS1, the output end of the comparator COM2 is connected to the inverters INV3-INV4 in sequence, the output end of the inverter INV4 is connected to the D end of the RS flip-flop RS1, the Q end of the RS flip-flop RS1 and the S end of the RS flip-flop RS2 are connected in series with the inverter INV5, the Q end of the RS flip-flop RS2 is connected to the input end of the inverter INV6, and the output end of the inverter INV6 outputs a signal X42_YN.

[0019] Preferably, the burp module comprises a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; the control end of the data selector MUX is connected to the PWM logic control signal X840_SNN, two input ends of the data selector MUX are connected to the signal R720_MINUS and the signal P872_G respectively, the output end of the data selector MUX is connected to the gate of the PMOS tube P2, the source of the PMOS tube P2 is connected to the current source Iref4 of the power supply X2_D and the input end of the transmission gate, the drain of the PMOS tube P2 is grounded, two control ends of the transmission gate are connected to the signal X41_YN and the signal respectively, the output end of the transmission gate is connected to the current source Iref3 of the power supply X2_D, the capacitor C2 grounded and the non-inverting input end of the comparator COM3, the inverting input end of the comparator COM3 is connected to the signal P45_S, the output end of the comparator COM3 is connected to the input end of the inverter INV7, and the output end of the inverter INV7 is connected to the R end of the RS flip-flop RS2.

[0020] Preferably, the transmission gate is composed of a parallel complementary PMOS tube and NMOS tube pair.

[0021] Preferably, the frequency jitter module comprises switch tubes D1-D4; the gates of the switch tubes D1-D4 are connected to control signals X1_Q-X4_Q in sequence, the drains of the switch tubes D1-D4 are connected to current sources I1-I4 of the power supply X2_D in sequence, and the sources of the switch tubes D1-D4 are connected to the current source I'ref of the power supply X2_D and the current source Iref0 grounded.

[0022] Preferably, the ratio relationship of the current sources I1-I4 is I1:I2:I3:I4=8:4:2:1.

[0023] Preferably, it further comprises a charge-discharge constant current source circuit, and the charge-discharge constant current source circuit generates the current source I'ref through current mirror image replication.

[0024] Preferably, the constant current source circuit comprises PMOS tubes P3~P4, NMOS tubes N2~N3, an operational amplifier OP, a temperature compensation resistor r and a resistor RI; the source of the PMOS tube P3 is connected to the power supply X2_D, the gate-drain of the PMOS tube P3 is connected to the source of the PMOS tube P4, the gate-drain of the PMOS tube P4 is connected to the drain of the NMOS tube N2, the gate of the NMOS tube N2 is connected to the output of the operational amplifier OP and the gate of the NMOS tube N3, the source of the NMOS tube N2 is connected to the source of the NMOS tube N3, one end of the temperature compensation resistor r and the inverting input of the operational amplifier OP, the non-inverting input of the operational amplifier OP is connected to the reference voltage Vref, the other end of the temperature compensation resistor r is connected to the resistor RI grounded, and the drain of the NMOS tube N3 is connected to the current source Iref connected to the power supply X2_D.

[0025] Preferably, the gate-drain of the PMOS tube P4 generates a current source Iref5, the ratio of the current source Iref5 and the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

[0026] Compared with the prior art, the present application has the following beneficial effects:

[0027] The present application significantly reduces power consumption through dynamic frequency adjustment, reduces invalid switching through real-time matching of load requirements, improves energy efficiency, and is particularly suitable for battery-powered scenarios; the use of a constant current source optimally replaces traditional resistors, suppresses noise and enhances frequency stability, and solves the problems of temperature drift and process deviation; the intelligent spread spectrum function is realized through frequency jitter or intermittent modulation, which disperses EMI energy while maintaining PWM precision, reduces filtering costs, and easily passes EMI certification; therefore, the present application breaks through the bottleneck of the prior art in low power consumption, high stability and anti-interference through the synergistic effect of three innovations, and is suitable for high-end scenarios such as consumer electronics and automotive power supplies. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a principle block diagram of an oscillator circuit for a PWM controller provided by the present application.

[0029] Figure 2 is a circuit diagram of an oscillator module provided by the present application.

[0030] Figure 3 is a circuit diagram of a hiccup module provided by the present application.

[0031] Figure 4 is a circuit diagram of a frequency jitter module provided by the present application.

[0032] Figure 5It is a circuit diagram of the charge and discharge constant current source circuit provided by the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0034] like Figures 1 to 5 As shown, an embodiment of the present invention specifically provides an oscillator circuit for a PWM controller, including:

[0035] An oscillator module includes a feedback loop and a current detection circuit; the input end of the feedback loop inputs the inverted signal X41_YN output by the output end of the current detection circuit, and the output end of the feedback loop outputs a signal N4_G (a triangular wave signal, which is also output to an external slope compensation) to the input end of the current detection circuit. After comparing the signal with the voltage signal VH and the voltage signal VL, the signal X42_YN (a rectangular wave signal, which is also output to an external frequency divider) is output, and the signal X41_YN is output after being inverted.

[0036] The hiccup module, according to the level of the input PWM logic control signal X840_SNN, the data selector selects and outputs its input signal to control the on and off of the transmission gate, and establishes the charging and discharging process, providing a delayed start function for the oscillator module;

[0037] The frequency jittering module outputs a current source Iref0 of different sizes by combining and selecting the current source I'ref and the current sources I1~I4, and outputs four current sources Iref1~Iref4 of different sizes through a current mirror array to provide charging and discharging current for the oscillator module and the hiccup module.

[0038] As a further explanation of an embodiment of the present invention, the feedback loop includes: an inverter INV1, a PMOS transistor P1, an NMOS transistor N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN, the output end of the inverter INV1 outputs a signal X41_YN to the gates of the PMOS transistor P1 and the NMOS transistor N1, the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and the grounded capacitor C1, and outputs a signal N4_G as an output end, the source of the PMOS transistor P1 is connected to a current source Iref1 connected to a power supply X2_D, and the source of the NMOS transistor N1 is connected to a grounded current source Iref2.

[0039] As a further illustration of the embodiments of the present application, the current detection circuit comprises comparators COM1-COM2, inverters INV2-INV6 and RS flip-flops RS1-RS2; the non-inverting input terminal of the comparator COM1-COM2 inputs a signal N4 G, the inverting input terminal of the comparator COM1-COM2 inputs voltage signals VH and VL respectively, the output terminal of the comparator COM1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the S terminal of the RS flip-flop RS1, the output terminal of the comparator COM2 is connected to the inverters INV3-INV4 in sequence, the output terminal of the inverter INV4 is connected to the D terminal of the RS flip-flop RS1, the Q terminal of the RS flip-flop RS1 and the S terminal of the RS flip-flop RS2 are connected in series with the inverter INV5, the Q terminal of the RS flip-flop RS2 is connected to the input terminal of the inverter INV6, and the output terminal of the inverter INV6 outputs a signal X42 YN.

[0040] As a further illustration of the embodiments of the present application, the hiccup module comprises a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; the control terminal of the data selector MUX is connected to a PWM logic control signal X840 SNN, two input terminals of the data selector MUX are connected to a signal R720 MINUS and a signal P872 G respectively, the output terminal of the data selector MUX is connected to the gate of the PMOS tube P2, the source of the PMOS tube P2 is connected to a current source Iref4 of a power supply X2 D and the input terminal of the transmission gate, the drain of the PMOS tube P2 is grounded, two control terminals of the transmission gate are connected to a signal X41 YN and a signal respectively, the output terminal of the transmission gate is connected to a current source Iref3 of the power supply X2 D, the capacitor C2 grounded and the non-inverting input terminal of the comparator COM3, the inverting input terminal of the comparator COM3 is connected to a signal P45 S, the output terminal of the comparator COM3 is connected to the input terminal of the inverter INV7, and the output terminal of the inverter INV7 is connected to the R terminal of the RS flip-flop RS2.

[0041] As a further illustration of the embodiments of the present application, the transmission gate is composed of a parallel complementary PMOS tube and NMOS tube pair, and the capacitors C1-C2 are MOS capacitors; the proportional relationship of the current sources I1-I4 is I1:I2:I3:I4=8:4:2:1.

[0042] As further elaboration of the embodiment of the application, the frequency jitter module comprises: switch tubes D1-D4; the gates of the switch tubes D1-D4 are sequentially connected to control signals X1_Q-X4_Q, the drains of the switch tubes D1-D4 are sequentially connected to current sources I1-I4 of a power supply X2_D, and the sources of the switch tubes D1-D4 are connected to a current source I'ref of the power supply X2_D and a current source Iref0 connected to ground.

[0043] As further elaboration of the embodiment of the application, the frequency jitter module comprises: switch tubes D1-D4; the gates of the switch tubes D1-D4 are sequentially connected to control signals X1_Q-X4_Q, the drains of the switch tubes D1-D4 are sequentially connected to current sources I1-I4 of a power supply X2_D, and the sources of the switch tubes D1-D4 are connected to a current source I'ref of the power supply X2_D and a current source Iref0 connected to ground.

[0044] The charging and discharging constant current source circuit comprises: PMOS tubes P3-P4, NMOS tubes N2-N3, an operational amplifier OP, a temperature compensation resistor r, and a resistor RI; the source of the PMOS tube P3 is connected to the power supply X2_D, the gate-drain of the PMOS tube P3 is connected to the source of the PMOS tube P4, the gate-drain of the PMOS tube P4 is connected to the drain of the NMOS tube N2, the gate of the NMOS tube N2 is connected to the output of the operational amplifier OP and the gate of the NMOS tube N3, the source of the NMOS tube N2 is connected to the source of the NMOS tube N3, one end of the temperature compensation resistor r, and the inverting input of the operational amplifier OP, the non-inverting input of the operational amplifier OP is connected to a reference voltage Vref, the other end of the temperature compensation resistor r is connected to the resistor RI connected to ground, and the drain of the NMOS tube N3 is connected to the current source Iref of the power supply X2_D.

[0045] The gate-drain of the PMOS tube P4 generates a current source Iref5, the ratio of the current source Iref5 and the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

[0046] Further comprising the following working principle:

[0047] In the above charging and discharging constant current source circuit, the current source Iref is generated by an external LDO circuit, Iref=Vref / (RI+r), the current source Iref is copied by a current mirror to obtain the current source I'ref, and then the current source I'ref and the frequency jitter module are combined to generate the current source Iref0, and the current source Iref0 generates the charging and discharging current through a current mirror.

[0048] The oscillator circuit of the application comprises the following two working modes:

[0049] Normal mode: PWM logic control signal X840_SNN is high, data selector MUX selects output signal X1225_Y as signal P872_G, if signal X41_YN is high, pass-gate is closed, current source Iref3 charges capacitor C2, if signal X41_YN is low, pass-gate is opened, capacitor C2 discharges, until voltage VP44_S is equal to voltage VN1_G, then voltage VN1_G and voltage VP44_S are always greater than voltage VP45_S, so output of comparator COM3 is always high, R input of RS flip-flop RS2 is always low, then output of RS flip-flop RS2 only depends on S input.

[0050] When voltage VL < VN4_G < VH, output of RS flip-flop RS1 is low, S input of RS flip-flop RS2 is high, then output of RS flip-flop RS2 is low, this state will be maintained until voltage VN4_G = VH; when voltage VN4_G > VH, output of RS flip-flop RS1 is high, S input of RS flip-flop RS2 is low, then output of RS flip-flop RS2 is high; this cycle is repeated.

[0051] Burst mode: the main power loss of switching power supply controller comes from switching loss when it is in light load or no load, switching loss is proportional to PWM frequency. In order to meet the green mode requirement, the chip reduces switching frequency or intermittently opens to achieve it.

[0052] In this state, PWM logic control signal X840_SNN is low, data selector MUX selects output signal X1225_Y as signal R720_MINUS, discharge process in burst mode is the same as normal mode, but when voltage VN4_G drops below voltage VL, current source Iref1 will not immediately start charging capacitor C1, but wait until capacitor C2 is charged to voltage VN1_G > VP45_S, comparator COM3 outputs high, R input of RS flip-flop RS2 is low, then current source Iref1 starts charging capacitor C1.

[0053] In order to better achieve EMI characteristics, frequency jitter function is set in the chip to make actual PWM frequency jitter in the set value range, four control signals X1_Q ~ X4_Q from external frequency divider control turn-off of switches D1 ~ D4, so as to periodically change the size of charging and discharging current.

[0054] In summary, the application designs an oscillator module composed of a feedback loop and a current detection circuit to detect load current / voltage in real time and dynamically adjust PWM frequency, and cooperates with a frequency jitter module and a hiccup module to reduce electromagnetic interference (EMI) and improve system efficiency. By using a high-precision (Iref5:Iref=1:14.85) temperature-compensated current mirror charge-discharge constant-current source circuit, the application has the functions of supporting wide-range current regulation such as 1 μA~1 mA and temperature drift accuracy within ±1%.

[0055] The above description is only a description of the preferred embodiments of the application and does not limit the scope of the application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. An oscillator circuit for a PWM controller, characterized by, The application relates to an oscillation module, a burp module and a frequency jitter module. The oscillation module comprises a feedback loop and a current detection circuit; the input end of the feedback loop inputs a NOT signal X41_YN output by the output end of the current detection circuit; the output end of the feedback loop outputs a signal N4_G to the input end of the current detection circuit; and after the signal N4_G is compared with a voltage signal VH and a voltage signal VL, a signal X42_YN is output, and the signal X42_YN is output after being inverted to output the signal X41_YN; The burp module controls the on-off of a transmission gate according to the level of an input PWM logic control signal X840_SNN, and selects and outputs input signals to establish a charge-discharge process, thereby providing a delay start function for the oscillation module; The frequency jitter module combines and selects current sources I'ref and I1-I4 to output different sizes of a current source Iref0, and mirrors and outputs different sizes of four current sources Iref1-Iref4 through a current mirror array, thereby providing charge-discharge currents for the oscillation module and the burp module; The feedback loop comprises an inverter INV1, a PMOS tube P1, an NMOS tube N1 and a capacitor C1; the input end of the inverter INV1 inputs a signal X42_YN; the output end of the inverter INV1 outputs a signal X41_YN to the gate of the PMOS tube P1 and the NMOS tube N1; the PMOS tube P1 is connected to the drain of the NMOS tube N1 and the capacitor C1 grounded, and serves as an output end to output a signal N4_G; the source of the PMOS tube P1 is connected to a current source Iref1 connected to a power supply X2_D; and the source of the NMOS tube N1 is connected to a current source Iref2 grounded; The current detection circuit comprises comparators COM1-COM2, inverters INV2-INV6 and RS flip-flops RS1-RS2; the noninverting input end of the comparators COM1-COM2 inputs a signal N4_G; the inverting input end of the comparators COM1-COM2 inputs a voltage signal VH and a voltage signal VL respectively; the output end of the comparator COM1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the S end of the RS flip-flop RS1; the output end of the comparator COM2 is connected to the inverters INV3-INV4 in sequence; the output end of the inverter INV4 is connected to the D end of the RS flip-flop RS1; the Q end of the RS flip-flop RS1 and the S end of the RS flip-flop RS2 are connected in series with the inverter INV5; the Q end of the RS flip-flop RS2 is connected to the input end of the inverter INV6; and the output end of the inverter INV6 outputs a signal X42_YN. The hiccup module comprises a data selector MUX, a PMOS tube P2, a transmission gate, a capacitor C2, a comparator COM3 and an inverter INV7; a control end of the data selector MUX is connected with a PWM logic control signal X840_SNN, two input ends of the data selector MUX are connected with a signal R720_MINUS and a signal P872_G respectively, an output end of the data selector MUX is connected with a gate of the PMOS tube P2, a source of the PMOS tube P2 is connected with a current source Iref4 of a power supply X2_D and an input end of the transmission gate, a drain of the PMOS tube P2 is grounded, two control ends of the transmission gate are connected with a signal X41_YN and a signal respectively, and an output end of the transmission gate is connected with a current source Iref3 of the power supply X2_D, the capacitor C2 grounded and a non-inverting input end of the comparator COM3, the non-inverting input end of the comparator COM3 is connected with a signal N1_G, an inverting input end of the comparator COM3 is connected with a signal P45_S, an output end of the comparator COM3 is connected with an input end of the inverter INV7, and an output end of the inverter INV7 is connected with an R end of the RS flip-flop RS2. When the PWM logic control signal X840_SNN is low, the data selector MUX selects the output signal X1225_Y as the signal R720_MINUS, and the working mode enters the hiccup mode, in which the discharge process is the same as in the normal working mode; when the voltage VN4_G of the signal N4_G drops below the voltage of the voltage signal VL, the current source Iref1 does not immediately start charging the capacitor C1, but waits until the capacitor C2 is charged to the voltage VN1_G of the signal N1_G is greater than the voltage VP45_S of the signal P45_S, the comparator COM3 outputs a high level, and the R end of the RS flip-flop RS2 inputs a low level, and then the current source Iref1 starts charging the capacitor C1.

2. An oscillator circuit for a PWM controller as defined in claim 1, characterized in that The transmission gate is composed of a parallel complementary PMOS and NMOS tube pair.

3. An oscillator circuit for a PWM controller as defined in claim 1, wherein, The frequency jittering module comprises: switch tubes D1-D4; the gates of the switch tubes D1-D4 are sequentially connected to control signals X1_Q-X4_Q, the drains of the switch tubes D1-D4 are sequentially connected to current sources I1-I4 of a power supply X2_D, and the sources of the switch tubes D1-D4 are connected to a current source I'ref of the power supply X2_D and a current source Iref0 connected to the ground.

4. An oscillator circuit for a PWM controller as defined in claim 3, characterized in that The proportional relationship of the current sources I1-I4 is I1:I2:I3:I4=8:4:2:

1.

5. An oscillator circuit for a PWM controller as defined in claim 1, wherein, The charging and discharging constant current source circuit further comprises a current mirror for mirror copying to generate the current source I'ref.

6. An oscillator circuit for a PWM controller as defined in claim 5, characterized in that The charging and discharging constant current source circuit comprises: PMOS tubes P3-P4, NMOS tubes N2-N3, an operational amplifier OP, a temperature compensation resistor r, and a resistor RI; the source of the PMOS tube P3 is connected to the power supply X2_D, the gate-drain of the PMOS tube P3 is connected to the source of the PMOS tube P4, the gate-drain of the PMOS tube P4 is connected to the drain of the NMOS tube N2, the gate of the NMOS tube N2 is connected to the output of the operational amplifier OP and the gate of the NMOS tube N3, the source of the NMOS tube N2 is connected to the source of the NMOS tube N3, one end of the temperature compensation resistor r, and the inverting input of the operational amplifier OP, the non-inverting input of the operational amplifier OP is connected to a reference voltage Vref, the other end of the temperature compensation resistor r is connected to the resistor RI connected to the ground, and the drain of the NMOS tube N3 is connected to the current source Iref of the power supply X2_D.

7. An oscillator circuit for a PWM controller as defined in claim 6, characterized in that The gate-drain of the PMOS tube P4 generates a current source Iref5, the proportional relationship between the current source Iref5 and the current source Iref is Iref5:Iref=1:14.85, and the resistor RI=56KΩ.

Images