Method for transmitting streaming data through streaming processing bus and transmission system

Abstract

The invention discloses a method for transmitting streaming data through a streaming processing bus and a transmission system, and belongs to the technical field of streaming data transmission. The method comprises the following steps: a sending end obtains to-be-transmitted streaming data; a transmitting end transmits a group of signals in parallel through a stream processing bus, the transmitting end transmits a group of signals in parallel through the stream processing bus, and the method comprises the steps that a data receiving indication signal sent by a receiving end is received, and the data receiving indication signal is used for indicating whether the receiving end can receive stream data or not; a streaming data signal is sent, and the streaming data signal transmits streaming data under the condition that the received data receiving indication signal indicates that the receiving end can receive the streaming data; and transmitting a data valid signal indicating that the streaming data signal is valid when the streaming data signal transmits the streaming data.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of stream data transmission, and in particular to a method and a transmission system for transmitting stream data through a stream processing bus. Background Art

[0002] With the development of information technology, chip integration is becoming increasingly higher, and the bus technology for interconnecting modules within the chip is developing towards high performance and specialization. Especially with the development of multimedia and artificial intelligence, the interconnection between stream processing units and stream processors in the chip is developing towards high performance with large traffic, low latency, transmittable data types, and controllable transmission.

[0003] Therefore, how to achieve high-performance transmission of streaming data, such as high bandwidth, low latency, data type transmission, and flow controllable transmission, is a technical problem that needs to be solved in related technologies. Summary of the Invention

[0004] The embodiments of the present application provide a method and a transmission system for transmitting stream data through a stream processing bus, which at least achieves one of high bandwidth, low latency, data type transmission and flow controllable transmission of the stream data.

[0005] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, a method for transmitting stream data via a stream processing bus is provided, the method comprising: The transmitting end obtains stream data to be transmitted; the transmitting end transmits a group of signals in parallel through a stream processing bus, including: receiving a data reception indication signal sent by a receiving end, wherein the data reception indication signal is used to indicate whether the receiving end can receive the stream data; sending a stream data signal, wherein, when the received data reception indication signal indicates that the receiving end can receive the stream data, the stream data signal transmits the stream data, and when the received data reception indication signal indicates that the receiving end cannot receive the stream data, the stream data signal transmits padding data; sending a data valid signal, wherein, when the stream data signal transmits the stream data, the data valid signal indicates that the stream data signal is valid, and when the stream data signal transmits padding data, the data valid signal indicates that the stream data signal is invalid.

[0006] In a second aspect, a method for transmitting stream data through a stream processing bus is provided, the method comprising: a receiving end determining whether it is currently capable of receiving stream data based on the amount of stream data currently to be processed; the receiving end transmitting a set of signals in parallel through the stream processing bus, comprising: sending a data reception indication signal, wherein the data reception indication signal is used to indicate whether the receiving end can receive stream data; receiving a stream data signal, wherein the stream data signal is used to transmit the stream data or padding data; and receiving a data valid signal, wherein the data valid signal is used to indicate whether the data transmitted by the stream data signal is valid.

[0007] In a third aspect, a transmission system is provided, which includes: an input interface conversion module for executing the method for transmitting stream data through a stream processing bus as described in the first aspect; a stream processing module for executing the method for transmitting stream data through a stream processing bus as described in the first aspect, and the method for transmitting stream data through a stream processing bus as described in the second aspect; and an output interface conversion module for executing the method for transmitting stream data through a stream processing bus as described in the second aspect.

[0008] In an embodiment of the present application, a transmitting end may transmit a set of signals in parallel via a stream processing bus, including: receiving a data reception indication signal sent by a receiving end to indicate whether the receiving end can receive stream data; transmitting a stream data signal transmitting stream data, and if the received data reception indication signal indicates that the receiving end cannot receive stream data, transmitting a stream data signal transmitting padding data; and transmitting a data valid signal indicating that the stream data signal is valid, and if the stream data signal transmits padding data, transmitting a data valid signal indicating that the stream data signal is invalid. Therefore, the transmitting end may determine whether the receiving end can receive stream data based on the data reception indication signal, and further determine whether to transmit a stream data signal transmitting stream data or a stream data signal transmitting padding data. This facilitates management and control of whether the transmitting end transmits stream data during data transmission, thereby implementing flow control for the source end (i.e., the transmitting end).

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0011] Figure 1 A flow chart of a method for transmitting stream data via a stream processing bus provided by an exemplary embodiment of the present application is shown; Figure 2A flow chart of another method for transmitting stream data via a stream processing bus provided by an exemplary embodiment of the present application is shown; Figure 3 A flow chart of another method for transmitting stream data through a stream processing bus provided by an exemplary embodiment of the present application is shown; Figure 4 A flow chart of another method for transmitting stream data through a stream processing bus provided by an exemplary embodiment of the present application is shown; Figure 5 A flow chart of a method for transmitting stream data via a stream processing bus provided by an exemplary embodiment of the present application is shown; Figure 6 A schematic diagram of an SBUS bus timing description provided by an exemplary embodiment of the present application is shown; Figure 7 A schematic diagram of an SBUS bus timing description provided by another exemplary embodiment of the present application is shown; Figure 8 A schematic structural diagram of a transmission system provided by an exemplary embodiment of the present application is shown; Figure 9 A schematic structural diagram of another transmission system provided by an exemplary embodiment of the present application is shown; Figure 10 A flow chart of a SUBS bus system interconnection process according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0012] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0013] Currently, common inter-chip and intra-chip buses include the Advanced Microcontroller Bus Architecture (AMBA) (e.g., Advanced eXtensible Interface (AXI) and Advanced High-performance Bus (AHB)), Ethernet interfaces, and AXI stream interfaces. These buses are not suitable for streaming data transmission. The AMBA bus exhibits periodic burst transmissions, complex bus definitions, inability to transmit data types synchronously, and some signal unavailability, making it unsuitable for transmitting high-volume, uninterrupted streaming data or image data in stream processing units or stream processors. Ethernet-based transmission interfaces can implement streaming data transmission, but the Ethernet protocol is complex to parse, increasing the design complexity of the system bus. Furthermore, they lack efficient flow control and are therefore unsuitable for streaming data transmission. AXI stream interfaces can implement streaming data transmission, but they lack data type transmission, making them incapable of transmitting stream source and destination information, stream data types, or data flow control at the source. The digital video port (DVP) can transmit streaming data, but cannot transmit data types or control data flow at the source.

[0014] Currently, in the relevant technologies, there is no universal stream data transmission bus, which may lead to incompatibility of stream processing units or stream processor interfaces, and secondary development in the interconnection of equipment from different manufacturers.

[0015] In order to solve at least one of the problems in the above-mentioned related technologies, the embodiment of the present application provides a technical solution for transmitting stream data through a stream processing bus. The technical solution provided by the embodiment of the present application is described below with reference to the accompanying drawings.

[0016] See also Figure 1 , Figure 1 The flow chart of a method for transmitting stream data via a stream processing bus provided by an exemplary embodiment of the present application is shown. The method can be executed by a sending end of the stream data, which can also be called a source end or a master device. Figure 1 As shown in FIG. 1 , the method 100 may include the following steps.

[0017] S101: The sending end obtains the stream data to be transmitted.

[0018] In practical applications, stream data is a sequence of data that arrives sequentially, in large quantities, rapidly, and continuously. Generally, stream data can be considered a dynamic data set that grows indefinitely over time. For example, stream data can be log files generated by applications, information on social networking sites, or image and video data. The sender of stream data refers to the component or device in a data stream processing architecture that generates, collects, and sends data to a data processing system or receiver.

[0019] In an embodiment of the present application, the sending end can obtain the streaming data to be transmitted. For example, the camera in the video surveillance system serves as the sending end of the streaming data and can capture the video screen in real time. In the log collection system, the log files on the server continuously generate new log records, which can be read in real time as streaming data by the sending end (such as Logstash).

[0020] S102: The sending end transmits a group of signals in parallel via a stream processing bus.

[0021] In practical applications, stream bus (SUBS) is a system bus architecture for efficiently processing real-time data streams. It combines stream processing technology and bus communication mechanism to achieve low-latency, high-throughput data processing.

[0022] In an embodiment of the present application, the above-mentioned stream processing bus serves as an interface for stream processing chips, stream processing units or stream processors to realize their arbitrary interconnection. Using this bus can not only simplify the interconnection between stream processing chips, stream processing units or stream processors, but also increase transmission bandwidth, reduce latency, and reduce implementation costs.

[0023] In an embodiment of the present application, the sending end can transmit a group of signals in parallel through the stream processing bus. In this way, by transmitting signals in parallel through the stream processing bus, the sending end can transmit multiple data bits at the same time, thereby improving the data transmission rate and meeting the high-speed data processing requirements.

[0024] In some embodiments, as Figure 2 As shown in , the sending end transmits a set of signals in parallel through the stream processing bus, which may include: S1021: The transmitting end receives a data reception indication signal sent by the receiving end.

[0025] The data reception indication signal is used to indicate whether the receiving end can receive stream data.

[0026] In an embodiment of the present application, the transmitting end may receive a data reception indication signal sbus_ack sent by the receiving end to indicate whether the receiving end can receive stream data. The data reception indication signal may indicate that the stream processing bus can receive a flow control signal of upstream data, that is, the purpose of the data reception indication signal is to control and adjust the rate and amount of data transmission to ensure that the receiving end can effectively process the incoming data and implement data flow control for the transmitting end. The data reception indication signal may be used to inform the transmitting end whether the receiving end currently has sufficient resources (such as buffer space and processing power) to receive more data. When the buffer of the receiving end is about to be full or the processing power reaches its limit, the above-mentioned data reception indication signal may be used to notify the transmitting end to suspend data transmission, thereby avoiding data overflow and loss.

[0027] In some embodiments, the data reception indication signal may be a single-bit signal. For example, it may be assumed that a high-level signal indicates that data can be received, and a low-level signal indicates that data cannot be received.

[0028] In some embodiments, the data reception indication signal may be configured via a register, which is defined as a low level indicating valid data and a high level indicating invalid data.

[0029] The sender can learn whether the receiver can receive the stream data through the data reception indication signal, so as to adjust the sending strategy according to the situation, ensure the reliable transmission of data, realize the flow control processing of the sender data, and enhance the adaptability of the hardware to process the stream data.

[0030] S1022: The sending end sends a stream data signal.

[0031] Wherein, when the received data reception indication signal indicates that the receiving end can receive stream data, the stream data signal transmits the stream data; when the received data reception indication signal indicates that the receiving end cannot receive stream data, the stream data signal transmits padding data.

[0032] In an embodiment of the present application, when the received data reception indication signal indicates that the receiving end can receive stream data, the sending end can send a stream data signal sbus_data for transmitting stream data to the receiving end. When the received data reception indication signal indicates that the receiving end cannot receive stream data, the sending end can send a stream data signal for transmitting fill data to the receiving end.

[0033] In practical applications, a stream data signal can be used to transmit stream data. This stream data signal can be a multi-bit signal, with a bit width of 32 bits. It is the core communication data of the stream processing unit or stream processor, and the specific bit width can be selected according to the actual scenario. After the bit width is determined, the data bit width value can be configured through registers. In specific applications, this stream data signal is pixel data in the image processor and specific processing stream data in the stream processing unit or stream processor.

[0034] In some embodiments, the padding data can be the same as the previous data, or 0, or other predefined data, indicating invalid data. By padding the data, the transmitting end can ensure that the length of the data frame meets the protocol requirements, thereby avoiding data transmission errors caused by insufficient data frame length. In this manner, if the receiving end is able to receive streaming data, the transmitting end can send a stream data signal transmitting the streaming data to the receiving end to ensure normal transmission of the streaming data. If the receiving end is unable to receive streaming data, the transmitting end can send a stream data signal transmitting the padding data to the receiving end to avoid data overflow and loss.

[0035] S1023: The sending end sends a data valid signal.

[0036] Wherein, when the stream data signal transmits the stream data, the data valid signal indicates that the stream data signal is valid; when the stream data signal transmits the filling data, the data valid signal indicates that the stream data signal is invalid.

[0037] In an embodiment of the present application, when the above-mentioned stream data signal transmits stream data, the sending end can send a data valid signal sbus_valid indicating that the stream data signal is valid; when the stream data signal transmits padding data, the sending end can send a data valid signal indicating that the stream data signal is invalid.

[0038] In some embodiments, the data valid signal may indicate valid information about the stream data transmission. For example, the data valid signal may be a single-bit signal. A high level by default indicates that the data is valid, i.e., the stream data signal transmits stream data; a low level indicates that the data is invalid, i.e., the stream data signal transmits fill data.

[0039] In some embodiments, this mode can be configured via registers. For example, a low level can indicate valid data, while a high level indicates invalid data. The specific configuration is not limited. The data valid signal can be used to notify the receiving end whether the stream data signal is valid, ensuring that the receiving end processes the data when it is valid. In practical applications, the data valid signal can achieve high-volume streaming data transmission without burst restrictions. This not only increases bus transmission bandwidth but also reduces transmission latency.

[0040] It should be noted that although Figure 2 The above S1021 to S1023 are represented in a certain order, but in actual application, the above S1021 to S1023 are performed in parallel. For example, the sending end can transmit the above signals in parallel through multiple transmission ports of the SBUS bus, wherein the first transmission port is used to receive the above data reception indication signal, the second transmission port is used to send the stream data signal, and the third transmission port is used to send the data valid signal. The three transmission ports are performed in parallel. When it is detected that the content indicated by the data reception indication signal received on the first transmission port indicates that the receiving end can receive stream data, the stream data is sent on the second transmission port, and the data valid signal indicating that the stream data signal is valid is sent on the third transmission port. When it is detected that the content indicated by the data reception indication signal received on the first transmission port is converted to that the receiving end cannot receive stream data, the stream data sent on the second transmission port is immediately changed to padding data, and the content indicated by the data valid signal sent on the third transmission port is changed to indicate that the stream data signal is invalid.

[0041] For example, the data reception indication signal indicates at a high level that the receiving end can receive stream data, and at a low level that the receiving end cannot receive stream data. When it is detected that the data reception indication signal changes from a high level to a low level, the stream data signal changes from transmitting stream data to transmitting filling data, and the data valid signal also changes from a high level (indicating that the stream data signal is valid) to a low level (indicating that the stream data signal is invalid).

[0042] In an embodiment of the present application, a transmitting end receives, via a stream processing bus, a data reception indication signal sent by a receiving end to indicate whether the receiving end can receive stream data, transmits a stream data signal for transmitting stream data, and transmits a data valid signal indicating that the stream data signal is valid. The transmitting end can determine whether the receiving end can receive stream data based on the data reception indication signal, and further determine whether to transmit a stream data signal for transmitting stream data or a stream data signal for transmitting filler data. This facilitates management and control of whether the transmitting end transmits stream data during the data transmission process, implements flow control processing of the transmitting end's data, and enhances the adaptability of hardware processing of stream data.

[0043] In some embodiments, in order to enable the information of the sending end and the receiving end to be transmitted through hardware to transmit data type signals, in these embodiments, the sending end transmitting a group of signals in parallel through the stream processing bus may also include: the sending end sending a data type signal, wherein the data type signal is used to indicate type-related information of the stream data signal.

[0044] In the above embodiment, the sending end can send a data type signal indicating the type of information related to the stream data signal. This data type signal allows information between the sending and receiving ends to be transmitted through hardware, enabling hardware adaptive processing and improving the processing performance of the stream processing unit and stream processor. Through hardware transmission, the sending and receiving ends can achieve rapid data transmission, share resources, and promote collaboration and cooperation between the two ends.

[0045] In some embodiments, the data type signal may include information related to the type of at least one stream data signal. In these embodiments, the data type signal may include at least one of the following: (1) A row parity signal, used to indicate the parity row attribute corresponding to the stream data signal.

[0046] In practical applications, the data type signal is a multi-bit signal. In some embodiments, the data type signal can be 11 bits, where the default bit 0 represents the odd-even row attribute of the signal, for example, a low level represents an even row, and a high level represents an odd row.

[0047] Odd-even row attribute real-time data monitoring and data analysis, for example, in a real-time data monitoring system, the odd-even row attribute can be used to distinguish continuous data streams, helping monitoring personnel to quickly identify data change trends and patterns.

[0048] (2) A source address signal, used to indicate the source address corresponding to the stream data signal.

[0049] In some embodiments, bits 1 through 3 in the data type signal may be used to indicate a source address.

[0050] In these embodiments, the source address signal may indicate the source address corresponding to the stream data signal, thereby enabling the receiving end to accurately identify the source of the stream data signal. On the other hand, the source address may be used to verify the identity of the sending end.

[0051] (3) Destination address signal, used to indicate the target address corresponding to the stream data signal.

[0052] In some embodiments, bits 4 through 6 of the data type signal may be used to indicate a target address.

[0053] In these embodiments, the destination address corresponding to the stream data signal is indicated by the destination address signal, so that the stream data signal can be accurately delivered to the designated receiving end.

[0054] In the above embodiment, the data type signal is used to indicate the source address and / or the destination address, which can increase the source flow control of the stream data of the stream processing unit or stream processor and realize the adaptive transmission of the hardware data signal.

[0055] (4) A data format signal, used to indicate the data format corresponding to the stream data signal.

[0056] In some embodiments, bits 7 to 9 in the data type signal may be used to indicate the data format.

[0057] The data format can be the type of image data, such as RAW, RGB, YUV and other different formats or user-defined.

[0058] Among them, the RAW format is the unprocessed original image data captured by the camera sensor, RGB is a color model that represents various colors by combining different intensities of the three basic colors of red, green, and blue, and YUV is a color encoding method, in which Y represents brightness (Luma) and U and V represent chrominance (Chroma).

[0059] The data format can provide a standardized way to represent stream data, so that the sender and receiver can understand and process the stream data in a consistent manner, ensuring the readability and consistency of the data and supporting data parsing and processing.

[0060] In the above embodiment, by indicating row parity and / or data format through data type signals, the characteristic transmission of stream data of the stream processing unit or stream processor can be increased, the hardware adaptive processing of upstream and downstream stream processing units can be improved, and the transmission delay can be reduced.

[0061] In some embodiments, the data type signal may further include a frame valid data check value. For example, bit 10 of the data type signal may be used to indicate a frame valid data check value. The check value may be odd or even, without limitation. Transmitting the check value via the data type signal may enhance the functional safety of data transmission by the stream processing unit and improve data transmission reliability.

[0062] In some embodiments, the data type signal can be configured through a register. The content included in the specific data type signal, the length of the signal, the location of each content, etc. can be determined according to the actual scenario. For example, the source address, target address, and data format bit width can be expanded without specific limitation.

[0063] In each of the above embodiments, the source address, destination address and data type of the stream data signal are transmitted through the data type signal, which is beneficial to the automatic routing or transmission of the bus hardware level, enhances the interconnection transmission of multiple buses, and reduces design costs.

[0064] In some embodiments, in order to ensure the integrity and consistency of the data, the transmitting end may send a signal indicating whether the transmission is completed during the transmission process. Figure 3As shown, in these embodiments, the transmitting end transmitting a group of signals in parallel through the stream processing bus may further include at least one of the following S1024 and S1025: S1024: The sending end sends an end-of-line indication signal.

[0065] The line end indication signal is used to indicate whether a line of data in the stream data has been transmitted.

[0066] In some embodiments, the transmission data block can be defined as multi-dimensional transmission, first transmitting the first dimension, then the second dimension and the third dimension, etc., and data of different dimensions are transmitted in sequence. The row end indication signal sbus_h_end can be a valid indication of the last transmission data in each row of the same dimension transmission stream data, which can be a pulse signal.

[0067] In some embodiments, the row end indication signal may be a multi-bit signal or a single-bit signal. When the data valid signal is valid, a high level may indicate that the data transmission of one dimension is completed, and a low level may indicate that the data transmission of one dimension is not completed.

[0068] In some embodiments, when a transmission data block is defined as multi-dimensional transmission, the high and low level meanings of the row end indication signals corresponding to each dimension may be consistent.

[0069] In some embodiments, the row end signal bit width can also be configured through registers, and transmission in different dimensions can also be configured through registers, and the specific meaning is not limited.

[0070] One data can be transmitted in each clock cycle, and the effective length of the data in each row can be fixed or variable, without any specific limitation.

[0071] In the above embodiment, the end-of-line indication signal can be used to indicate the end of transmission of one-dimensional data of the multi-dimensional stream data, which helps to save resources.

[0072] S1025, the sending end sends a frame end indication signal.

[0073] The frame end indication signal is used to indicate whether the transmission of a frame of data in the stream data has ended.

[0074] In some embodiments, the frame end indication signal sbus_v_end may be a valid indication of the last transmission data of the transmission stream data, and may be a pulse signal.

[0075] In some embodiments, the frame end indication signal may be a single-bit signal. When the data valid signal is valid, a high level may indicate that a frame of data transmission is complete, and a low level may indicate that a frame of data transmission is not complete.

[0076] In some embodiments, the frame end indication signal can also be configured through a register. The specific meaning is not limited. For example, when the data valid signal is valid, it can be defined as a low level indicating that a frame of data transmission is completed, and a high level indicating that a frame of data transmission is not completed.

[0077] In the above embodiment, the completion of the transmission of the stream data is indicated by a line end indication signal and / or a frame end indication signal, which can mark the end of the data transmission of a line and / or a frame. The receiving end is notified that a line and / or a frame of data has been sent, and the receiving end can confirm whether a line and / or a frame of data has been received based on the above signal, so as to ensure the integrity and consistency of the data. In practical applications, defining bus transmission by a line end indication signal and / or a frame end indication signal is conducive to simplifying the design of the stream module, reducing design costs, realizing the continuous transmission of large flow data, reducing the delay effect of the burst transmission of the stream processing unit or the stream processor, and reducing the delay of the data.

[0078] It should be noted that although Figure 3 The above S1021 to S1025 are not necessarily represented in order, but in actual application, the above S1021 to S1025 are performed in parallel. For example, the sending end can transmit the above signals in parallel through multiple transmission ports of the SBUS bus.

[0079] In some embodiments, in order to ensure the integrity and consistency of the data, the transmitting end may send a signal indicating whether the transmission has started during the transmission process. Figure 4 As shown, the transmitting end transmitting a group of signals in parallel through the stream processing bus may further include at least one of the following S1026 and S1027: S1026: The sending end sends a row start indication signal.

[0080] The row start indication signal is used to indicate whether a row of data in the dimension stream data starts to be transmitted.

[0081] In some embodiments, the transmission data block can be defined as multi-dimensional transmission, first transmitting the first dimension, then the second dimension and the third dimension, etc., and data of different dimensions are transmitted in sequence. The row start indication signal sbus_h_start can be a valid indication of the first transmission data of each row of the same dimension transmission stream data, which can be a pulse signal.

[0082] In some embodiments, the row start indication signal may be a multi-bit signal and may default to a single-bit width. When the data valid signal is valid, a high level may indicate the start of data transmission in one dimension, and a low level may indicate that data transmission in one dimension has not started.

[0083] In some embodiments, when a transmission data block is defined as multi-dimensional transmission, the high and low level meanings of the row start indication signals corresponding to each dimension may be consistent.

[0084] In some embodiments, the row start signal bit width can also be configured through a register, and transmission in different dimensions can also be configured through a register. The specific configuration method is not limited.

[0085] One piece of data is transmitted in each clock cycle, and the effective length of the data in each row can be fixed or variable, without any specific limitation.

[0086] In the above embodiment, the line start indication signal can be used to indicate the start of one-dimensional data transmission of multi-dimensional stream data, which helps save resources and ensures data integrity.

[0087] S1027, the sending end sends a frame start indication signal.

[0088] The frame start indication signal is used to indicate whether a frame of data of the stream data starts to be transmitted.

[0089] In some embodiments, the frame start indication signal sbus_v_start may be a valid indication of the first transmission data of the transmission stream data, and may be a pulse signal.

[0090] In some embodiments, the frame start indication signal may be a single-bit signal. When the data valid signal is valid, a high level may indicate the start of data transmission, and a low level may indicate that data transmission has not started.

[0091] In some embodiments, the frame start indication signal may also be configured through a register. The meaning of the specific level is not limited. For example, it may be defined that a low level indicates that data transmission has started, and a high level indicates that data transmission has not started.

[0092] In the above embodiment, the start of transmission of stream data is indicated by a line start indication signal and / or a frame start indication signal, which can mark the start of a line and / or a frame of data transmission and notify the receiving end that data transmission has begun, helping to ensure that the sending end and the receiving end maintain a consistent pace during the data transmission process. By sending a line start indication signal and / or a frame start indication signal, the receiving end can prepare to receive data, for example, clear the buffer, start the receiving mechanism, etc. The receiving end can also confirm the start position of transmission of a line and / or a frame of data based on the above signals, helping to ensure the integrity and consistency of the data. In practical applications, defining bus transmission through a line start indication signal and / or a frame start indication signal is conducive to simplifying the design of the stream module and reducing design costs.

[0093] In practical applications, the above-mentioned line start indication signal, line end indication signal, frame start indication signal, and frame end indication signal can help simplify the bus design of the stream processing unit or stream processor and improve the transmission bandwidth and efficiency of stream data such as image data.

[0094] It should be noted that although Figure 4 The above S1021 to S1027 are not necessarily represented in order, but in actual application, the above S1021 to S1027 are performed in parallel. For example, the sending end can transmit the above signals in parallel through multiple transmission ports of the SBUS bus.

[0095] See also Figure 5 , Figure 5 A flow chart illustrating another method for transmitting stream data via a stream processing bus, provided by an exemplary embodiment of the present application, is shown. This method can be executed by a receiving end of the stream data, which can also be referred to as a destination end or a slave device. Method 500 is an operation step performed by a receiving end corresponding to method 100, and has the same or corresponding operations as method 100. The following description focuses on the relevant operation steps of the receiving end. For other matters not covered, please refer to the relevant description of method 100.

[0096] like Figure 5 As shown in , the method 500 may include the following steps. S501: The receiving end determines whether it can currently receive streaming data based on the amount of streaming data currently to be processed.

[0097] In an embodiment of the present application, the receiving end can determine whether it can currently receive stream data based on the amount of stream data currently being processed. For example, a threshold can be set based on available resources (such as buffer space and processing power). If the amount of stream data currently being processed does not exceed the threshold, the receiving end determines that the stream data can currently be received. If the amount of stream data currently being processed exceeds the threshold, the receiving end determines that the stream data cannot currently be received. This prevents data overflow or discard.

[0098] S502: The receiving end transmits a group of signals in parallel via a stream processing bus.

[0099] In an embodiment of the present application, the receiving end can transmit a group of signals in parallel through the stream processing bus. In this way, by transmitting signals in parallel through the stream processing bus, the receiving end can transmit multiple data bits at the same time, thereby improving the data transmission rate and meeting the high-speed data processing requirements.

[0100] In some embodiments, reference Figure 3 , the receiving end may include the following steps to transmit a group of signals in parallel through the stream processing bus: S1021: The receiving end sends a data reception indication signal.

[0101] The data reception indication signal is used to indicate whether the receiving end can receive stream data.

[0102] In an embodiment of the present application, the receiving end may send a data reception indication signal sbus_ack to indicate whether the receiving end can receive stream data. The data reception indication signal may be a flow control signal indicating whether the stream processing bus can receive upstream data, that is, the purpose of the data reception indication signal is to control and adjust the rate and amount of data transmission to ensure that the receiving end can effectively process the incoming data, thereby realizing data flow control for the sending end. The data reception indication signal may be used to inform the sending end whether the receiving end currently has sufficient resources (such as buffer space and processing power) to receive more data. When the buffer of the receiving end is about to be full or the processing power reaches its limit, the above-mentioned data reception indication signal may be used to notify the sending end to suspend data transmission, thereby avoiding data overflow and loss.

[0103] In some embodiments, the data reception indication signal can be a single-bit signal. For example, a high-level signal can be assumed to indicate that data can be received, while a low-level signal can indicate that data cannot be received. Alternatively, the data reception indication signal can be configured via a register, with no specific limitations on the specific level. In this way, the receiving end can use the data reception indication signal to inform the sending end whether it can receive stream data, thereby facilitating the sending end to adjust its transmission strategy accordingly, ensuring reliable data transmission, implementing flow control processing of the sending end's data, and enhancing hardware adaptability in processing stream data.

[0104] S1022: The receiving end receives the stream data signal sent by the sending end.

[0105] The stream data signal is used to transmit the stream data or filling data.

[0106] In an embodiment of the present application, a receiving end may receive a stream data signal for transmitting stream data or padding data. If the data reception indication signal indicates that the receiving end can receive stream data, the receiving end may receive the stream data signal sbus_data transmitted by the transmitting end, transmitting the stream data. If the data reception indication signal indicates that the receiving end cannot receive stream data, the receiving end may receive the stream data signal transmitted by the transmitting end, transmitting the padding data.

[0107] In some embodiments, a stream data signal can be used to transmit stream data. This stream data signal can be a multi-bit signal, with a bit width of 32 bits. It is the core communication data of the stream processing unit or stream processor, and the specific bit width can be selected according to the actual scenario. After the bit width is determined, the data bit width value can be configured through a register. In specific applications, the stream data signal is pixel data in the image processor and is specific processing stream data in the stream processing unit or stream processor.

[0108] In some embodiments, the padding data can be the same as the previous data, or 0, or other predefined data, indicating invalid data. By padding the data, the transmitter can ensure that the length of the data frame meets protocol requirements, avoiding data transmission errors caused by insufficient data frame length. In this manner, if the receiver is able to receive streaming data, it can receive the streaming data signal transmitted by the transmitter, ensuring normal transmission of the streaming data. If the receiver is unable to receive streaming data, it can receive the streaming data signal transmitted by the transmitter, transmitting the padding data, avoiding data overflow and loss.

[0109] S1023: The receiving end receives the data valid signal sent by the transmitting end.

[0110] The data valid signal is used to indicate whether the data transmitted by the stream data signal is valid.

[0111] In an embodiment of the present application, a receiving end may receive a data valid signal for indicating whether the data transmitted by the stream data signal is valid. When the stream data signal transmits stream data, the receiving end may receive a data valid signal sbus_valid sent by the transmitting end to indicate that the stream data signal is valid. When the stream data signal transmits padding data, the receiving end may receive a data valid signal sent by the transmitting end to indicate that the stream data signal is invalid.

[0112] In practical applications, the data valid signal can indicate valid information of the stream data transmission. For example, the data valid signal can be a single-bit signal. The default high level indicates that the data is valid, that is, the stream data signal transmits stream data, and the low level indicates that the data is invalid, that is, the stream data signal transmits fill data. In specific scenarios, the mode can be configured through a register. For example, it can be defined as a low level indicating that the data is valid and a high level indicating that the data is invalid. The specific configuration method is not limited. Through the data valid signal, the receiving end can know whether the data transmitted by the stream data signal is valid, and ensure that it is processed when the data is valid. In practical applications, the data valid signal can realize the transmission of large amounts of stream data without burst restrictions. It can not only improve the bus transmission bandwidth, but also reduce the transmission delay.

[0113] In an embodiment of the present application, the receiving end can determine whether it is currently able to receive stream data based on the amount of stream data currently to be processed; and then transmit a set of signals in parallel through the stream processing bus, wherein the parallel transmission of a set of signals through the stream processing bus may include: sending a data reception indication signal for indicating whether the receiving end can receive stream data, receiving a stream data signal for transmitting the above-mentioned stream data or filling data, and receiving a data valid signal for indicating whether the data transmitted by the above-mentioned stream data signal is valid. In this way, the receiving end can notify the sending end whether the receiving end can receive stream data through the data reception indication signal, and then receive the stream data signal for transmitting stream data or filling data, which helps to manage and control whether the sending end sends stream data during the data transmission process, and realize data flow control of the sending end. It can also ensure that the receiving end can process the received stream data in a timely manner to prevent the receiving end buffer from overflowing or losing data due to excessively fast transmission speed.

[0114] In some embodiments, information from a transmitting end and a receiving end is transmitted via a stream processing bus. In these embodiments, the receiving end transmits a set of signals in parallel via the stream processing bus, and further includes: The receiving end receives a data type signal, and acquires type-related information of the stream data signal based on the data type signal.

[0115] In the above embodiment, the receiving end can receive a data type signal indicating the type of information related to the stream data signal. This data type signal allows information between the sending and receiving ends to be transmitted through hardware, enabling hardware adaptive processing and improving the processing performance of the stream processing unit and stream processor. Through hardware transmission, the sending and receiving ends can achieve rapid data transmission, share resources, and promote collaboration and cooperation between the two ends.

[0116] In some embodiments, the data type signal may include information related to the type of at least one stream data signal. In these embodiments, the data type signal includes at least one of the following: (1) A row parity signal, used to indicate the parity row attribute corresponding to the stream data signal.

[0117] In practical applications, the data type signal is a multi-bit signal, generally with 11 bits by default, and the default bit 0 represents the parity row attribute of the signal, a low level represents an even row, and a high level represents an odd row; the parity row attribute is used for real-time data monitoring and data analysis. For example, in a real-time data monitoring system, the parity row attribute can be used to distinguish continuous data streams, helping monitoring personnel to quickly identify data change trends and patterns.

[0118] (2) A source address signal, used to indicate the source address corresponding to the stream data signal.

[0119] In some embodiments, bits 1 to 3 of the data type signal represent a source address. The source address signal ensures that the receiving end can accurately identify the source of the stream data signal, and the source address can be used to verify the identity of the sending end.

[0120] (3) Destination address signal, used to indicate the target address corresponding to the stream data signal.

[0121] In some embodiments, bits 4 through 6 of the data type signal can be used to indicate the destination address. This destination address signal ensures that the stream data signal is accurately delivered to the designated receiving end. In practical applications, using the data type signal to indicate the source and destination addresses can enhance source flow control of the stream data within the stream processing unit or stream processor, enabling adaptive transmission of hardware data signals.

[0122] (4) A data format signal, used to indicate the data format corresponding to the stream data signal.

[0123] In some embodiments, bits 7 through 9 of the data type signal may indicate a data format, which may be an image data type, such as RAW, RGB, YUV, or a user-defined format. Data formats provide a standardized way to represent data, enabling the sender and receiver to understand and process the data in a consistent manner, ensuring data readability and consistency and supporting data parsing and processing.

[0124] In the above embodiment, the data type signal is used to indicate the row parity and data format, which can increase the characteristic transmission of stream data of the stream processing unit or stream processor, improve the hardware adaptive processing of upstream and downstream stream processing units, and reduce transmission delay.

[0125] In actual applications, the data type signal may also include a frame valid data check value, which may be located at bit 10 and may be odd or even, without specific limitation. By transmitting the check value, the functional safety setting of the data transmission of the stream processing unit may be increased, thereby improving the reliability of data transmission. In actual applications, the data type signal may be configured through a register. The content included in the specific data type signal, the length of the signal, the location of each content, etc. may be determined according to the actual scenario. For example, the source address, the destination address, and the data format bit width may be expandable without specific limitation. In the above embodiment, the source address, the destination address, and the data format of the data stream signal are transmitted using the data type signal, which is beneficial to the automatic routing or transmission of the hardware level of the bus, enhances the interconnection transmission of multiple buses, and reduces the design cost.

[0126] In some embodiments, to ensure data integrity and consistency, during the transmission process, the receiving end may receive a signal indicating whether the transmission has ended. In these embodiments, the receiving end transmits a set of signals in parallel via the stream processing bus, and further includes at least one of the following two situations: In a first case, the receiving end receives a line end indication signal, and determines a transmission end position of a line of data in the stream data based on the line end indication signal.

[0127] The end-of-line indication signal is the end-of-line indication signal sent by the transmitting end in the above embodiment. For details, please refer to the above description of the end-of-line indication signal, which will not be repeated here.

[0128] In the above embodiment, the receiving end can receive a line end indication signal, and then determine the transmission end position of a line of data in the stream data based on the above line end indication signal, which can realize the one-dimensional data transmission end indication of multi-dimensional stream data, which helps to save resources.

[0129] In a second case, the receiving end receives a frame end indication signal, and determines a transmission end position of a frame of data in the stream data based on the frame end indication signal.

[0130] The frame end indication signal is the frame end indication signal sent by the transmitting end in the above embodiment. For details, please refer to the above description of the frame end indication signal, which will not be repeated here.

[0131] In the above embodiment, the receiving end may receive a frame end indication signal and then determine the transmission end position of a frame of data in the stream data based on the frame end indication signal. This helps the receiving end to correctly parse the received stream data.

[0132] Figure 6 A schematic diagram showing the timing description of the SBUS bus of an exemplary embodiment of the present application is shown in FIG. Figure 6 As shown, in this embodiment, when the total valid indication is valid, each bus clock clk transmits one bus data data. The last valid data of each row of data is indicated by the row end indication signal h_end, and the last valid data of each frame of data is indicated by the frame end indication signal v_end. The valid data signal valid is toggled or aligned on the rising edge of the clock, and the data reception signal ack is toggled or aligned on the rising edge of the clock.

[0133] In the above embodiment, the completion of the transmission of the stream data is indicated by a line end indication signal and / or a frame end indication signal, thereby marking the end of the data transmission of a line and / or a frame. The receiving end can confirm whether a line and / or a frame of data has been received based on the transmission end position indicated by the above signal, thereby ensuring the integrity and consistency of the data. In practical applications, defining bus transmission by a line end indication signal and / or a frame end indication signal is conducive to simplifying the design of the stream module and reducing design costs. It can also reduce the delay effect of the burst transmission of the stream processing unit or stream processor, thereby reducing data delay.

[0134] In some embodiments, to ensure data integrity and consistency, during the transmission process, the receiving end may receive a signal indicating whether the transmission has started. In these embodiments, the receiving end transmits a set of signals in parallel via the stream processing bus, and may also include at least one of the following two situations: In a first case, the receiving end receives a line start indication signal, and determines a transmission start position of a line of data in the stream data based on the line start indication signal.

[0135] The row start indication signal is the row start indication signal sent by the transmitting end in the above embodiment. For details, please refer to the above description of the row start indication signal, which will not be repeated here.

[0136] In the above embodiment, the receiving end can receive a row start indication signal, and then determine the transmission start position of a row of data in the stream data based on the row start indication signal, which can realize the one-dimensional data transmission start indication of multi-dimensional stream data, help save resources, and ensure data integrity.

[0137] In a second case, the receiving end receives a frame start indication signal, and determines a transmission start position of a frame of the stream data based on the frame start indication signal.

[0138] The frame start indication signal is the frame start indication signal sent by the transmitting end in the above embodiment. For details, please refer to the above description of the frame start indication signal, which will not be repeated here.

[0139] In the above embodiment, the start of transmission of stream data is indicated by a line start indication signal and / or a frame start indication signal, which can mark the start of a line and / or a frame of data transmission. The receiving end data can be informed that the sending end has started sending data, which helps to ensure that the sending end and the receiving end maintain a consistent pace during the data transmission process. By receiving the line start indication signal and / or the frame start indication signal, the receiving end can prepare to receive data, for example, clear the buffer, start the receiving mechanism, etc. The receiving end can also confirm the start position of the transmission of a line and / or a frame of data based on the above signals, which helps to ensure the integrity and consistency of the data. In practical applications, defining bus transmission by a line start indication signal and / or a frame start indication signal is conducive to simplifying the design scheme of the stream module and reducing design costs.

[0140] In practical applications, the above-mentioned line start indication signal, line end indication signal, frame start indication signal, and frame end indication signal can help simplify the bus design of the stream processing unit or stream processor and improve the transmission bandwidth and efficiency of stream data such as image data.

[0141] Figure 7 FIG. 4 shows a schematic diagram of SBUS bus signals and timing in another exemplary embodiment of the present application. Figure 7 As shown, when the bus valid indication is valid, one bus data point is transmitted per bus clock. The first and last valid data points of each row of data are indicated by the row start indication signal h_start and the row end indication signal h_end, respectively. The first and last valid data points of each frame of data are indicated by the frame start indication signal v_start and the frame end indication signal v_end. The valid data indication signal valid, the row start and end indication signal h_start, and the frame start and end indication signal v_start are aligned on the rising edge of the clock clk. The valid data signal valid is toggled or aligned on the rising edge of the clock. The data reception signal ack and the data type signal type are toggled or aligned on the rising edge of the clock. The bit width of the stream data signal data is 32 bits. The first bit of the data type signal type, namely type[0:0], is the row parity signal. The second to fourth bits of the data type signal type, namely type[3:1], are the source address signal. The fifth to seventh bits of the data type signal type, namely type[6:4], are the destination address signal. The eighth to tenth bits of the data type signal type, namely type[9:7], are the data format signal. The eleventh bit of the data type signal type, namely type

[10] , is the frame valid data check value.

[0142] Figure 8A schematic structural diagram of a transmission system according to an exemplary embodiment of the present application is shown. The transmission system 800 includes an input interface conversion module 801 , a stream processing module 802 , and an output interface conversion module 803 .

[0143] In the embodiment of the present application, the input interface conversion module 801 can be configured as described above. Figures 1 to 4 The method for transmitting stream data through the stream processing bus shown in FIG. 1 transmits a set of signals in parallel to the stream processing module 802 through the stream processing bus; the stream processing module 802 can be configured as described above. Figure 5 The method for transmitting stream data through the stream processing bus shown in FIG. 8 transmits a set of signals in parallel with the access interface conversion module 801, and according to the above Figures 1 to 4 The method for transmitting stream data through the stream processing bus shown in FIG. 1 transmits a set of signals in parallel to the output interface conversion module 803 through the stream processing bus; the output interface conversion module 803 can be configured as described above. Figure 5 The illustrated method of transmitting streaming data via the streaming bus transmits a set of signals in parallel with the streaming module 802 .

[0144] In an embodiment of the present application, the transmission system can be an interconnection device of an SBUS bus. The input interface conversion module 801 can serve as the input interface of the SBUS bus, receive external input data, and convert the received data into a set of signals for the above-mentioned parallel transmission. The output interface conversion module 803 can serve as an output interface, converting the above-mentioned set of parallel transmission signals into data for external output. The solution proposed in the embodiment of the present application is applicable to image processing systems and stream data transmission and processing systems, and is also applicable to the interconnection between stream processing modules, and is particularly applicable to the interconnection between stream processing units, the interconnection between stream processing units and stream processors, and the interconnection between stream processors in multimedia or artificial intelligence field chips.

[0145] The stream processing module 802 can be used to process data streams. For example, the stream processing module 802 can be an image processor, an algorithm function of a video processor, a bus delay or bus interconnection function module, a stream processing unit or a stream processor, etc. It can be not only a specific algorithm processing module, but also a timing delay module, etc.

[0146] In practical applications, a set of signals transmitted in parallel on the SBUS bus may include at least one of a clock signal sbus_clk, a data signal sbus_data, a data valid indication signal sbus_valid, a line start indication signal sbus_h_start, a line end indication signal sbus_h_end, a frame start indication signal sbus_v_start, a frame end indication signal sbus_v_end, a data type signal sbus_type, and a data reception indication signal sbus_ack. In practical applications, a bus valid indication signal may also be included, which can be used to indicate whether the data on the bus is valid.

[0147] In practical applications, a clock signal ensures synchronization between the transmitter and receiver during data transmission. This is the bus clock signal, which transmits a valid data stream signal during each clock cycle. That is, the data signal is transmitted once during each clock cycle. Typically, the transmitter sends data on the rising or falling edge of the clock signal, while the receiver samples the data on the same clock edge. Data transmitted during each clock cycle is considered valid data—data that the receiver can trust and use. The validity of the data signal is typically indicated by a data valid indicator, ensuring that the receiver processes the data only when it is valid.

[0148] In practical applications, when the bus valid indicator signal indicates valid, the data on the bus is valid. One bus data point is transmitted per bus clock. The first and last valid data points of each row of data can be indicated by the row start indicator signal and row end indicator signal, and the first and last valid data points of each frame of data can be indicated by the frame start indicator signal and frame end indicator signal. The bus valid indicator signal, row start and end indicator signal, and frame start and end indicator signal are validly aligned on the rising edge of the clock. The data valid indicator signal is toggled or aligned on the rising edge of the clock. The data received indicator signal and data type signal are toggled or aligned on the rising edge of the clock.

[0149] In practical applications, the input interface conversion module 801 can convert a common interface to an SBUS bus interface. Common interfaces, i.e., interfaces in related technologies, include AXI, AHB, AXI stream, and Ethernet interfaces. During the interface conversion, valid data in the AXI, AHB, and Ethernet interfaces can be used as valid data from the SBUS bus. By converting the data valid indication signals of the aforementioned buses, the data valid indication signal, line start indication signal, line end indication signal, frame start indication signal, and frame end indication signal of the SBUS bus can be obtained. Furthermore, the handshake signals of the aforementioned buses can be used to generate a frame receive signal for the SBUS bus.

[0150] In practical applications, the stream processing module 802 may include at least one input SBUS bus interface and at least one output SBUS bus interface. If the stream processing module 802 is a master device (i.e., the transmitter of stream data), for example, when the stream processing module 802 transmits stream data to the output interface conversion module 803, a bus slave mode may be used. In this case, the data reception indication signal is an input signal, and all other signals except the data reception indication signal are output signals. If the stream processing module 802 is a slave device (i.e., the receiver of stream data), for example, when the stream processing module 802 receives stream data transmitted by the input interface conversion module 801, a bus master mode may be used. In this case, the data reception indication signal is an output signal, and all other signals except the data reception indication signal are input signals.

[0151] Figure 9 A schematic diagram showing the interface signals of the stream processing module in an exemplary embodiment of the present application is shown in FIG. Figure 9 When the stream processing module 802 is a bus interconnection module, the source address signal and the destination address signal in the data type signal in the SBUS bus can be used for filtering and selection to realize the cross-connection and interconnection of the SBUS bus.

[0152] In practical applications, the output interface conversion module 803 can implement conversion from an SBUS bus to a commonly used interface bus. Common interfaces, i.e., interfaces in related technologies, include AXI, AHB, AXI stream, and Ethernet interfaces. During the interface conversion, valid data on the SBUS interface is valid data from the AXI, AHB, and Ethernet interfaces. Data valid indication signals for the AXI, AHB, and Ethernet interfaces can be obtained by converting the data valid indication signal, line start indication signal, line end indication signal, frame start indication signal, and frame end indication signal of the SBUS bus. Handshake signals for the aforementioned buses can also be generated from the frame receive signal of the SBUS bus.

[0153] The embodiment of the present application proposes a transmission system based on the SBUS bus. The modules in the transmission system can execute the above-mentioned method of transmitting streaming data through the stream processing bus. The SBUS bus has no burst transmission mode and no complex handshake signal definition. It can be defined through multi-dimensional data transmission indication, data type, and data transmission end indication hardware. Through the above-mentioned SBUS bus, streaming data can be continuously transmitted with unlimited length, data types can be transferred, streaming data can be flow-controlled, and the processing power of the stream processing unit or stream processor can be improved, and the interface compatibility of the stream processing unit or stream processor can be improved. In particular, the application of the above-mentioned SBUS bus can realize the continuous transmission of unlimited pixel data of image data, the streaming data type can be transmitted, and the streaming data can be flow-controlled. The above-mentioned transmission system can realize high-bandwidth, low-latency transmission of streaming data, and low cost.

[0154] In addition, it should be noted that although Figure 8 There is only one stream processing module 802 shown in FIG, but it is not limited thereto. In practical applications, there may be multiple stream processing modules 802, which are connected in series between the input interface conversion module 801 and the output interface conversion module 803. For example, Figure 9 In the example, the stream processing module 802 includes a first stream processing module 8021 and a second stream processing module 8022 .

[0155] In the above embodiment, in the input interface conversion module 801, the input stream data is converted to generate the SBUS bus data signal, data valid indication signal, line start indication signal, line end indication signal, frame start indication signal, frame end indication signal, data type signal and data reception indication signal, and can also generate a clock signal.

[0156] In the above embodiment, in the first stream processing module 8021, the input SBUS bus data completes specific stream processing functions in the first stream processing module 8021, such as algorithm processing, delay processing, etc., and generates an output SBUS bus interface signal; in the second stream processing module 8022, the input SBUS bus data completes specific stream processing functions in the second stream processing module 8022, such as algorithm processing, delay processing, etc., and generates an output SBUS bus interface signal.

[0157] In the above embodiment, in the input interface conversion module 803, the clock signal, data signal, data valid indication signal, line start indication signal, line end indication signal, frame start indication signal, frame end indication signal, data type signal and data reception indication signal corresponding to the SBUS bus are converted to generate the bus type required by the corresponding common bus interface and generate output data.

[0158] Figure 10 FIG. 1 shows a flow chart of a SUBS bus system interconnection method according to an exemplary embodiment of the present application. Figure 10 As shown, the method includes the following steps: S1001, determine the SBUS bus mode.

[0159] In the embodiments of the present application, the SBUS bus mode can be determined based on the specific scenario, that is, the implementation plan for the data transmission process can be determined. For example, the transmission dimension of the SBUS bus, whether the number of row data is equal, the definition of the high and low levels of the data valid indicator signal, the stream data bit width, the stream data type bit width, etc. In actual application, the SBUS bus mode can be configured through registers. In this way, an efficient, reliable, and secure data transmission solution can be provided according to the specific scenario to meet complex control requirements.

[0160] S1002, determine the SBUS bus signal.

[0161] In embodiments of the present application, SBUS bus signals may be determined based on specific scenarios. For example, in an image processor, SBUS bus signals may include data signals, data valid indication signals, line end indication signals, frame end indication signals, and data reception indication signals. In stream processing units and stream processors of graphics processing units (GPUs) and neural network processing units (NPUs), SBUS bus signals may include data signals, data valid indication signals, line end indication signals, and frame end indication signals.

[0162] S1003, executing SBUS bus system interconnection.

[0163] In the embodiment of the present application, the input interface conversion module 801, the stream processing module 802, and the output interface conversion module 803 can be interconnected. Stream processing data is input from the input interface conversion module 801, converted to an SBUS bus, and then sequentially connected to at least one stream processing module 802. The output SBUS bus of the last stream processing module is connected to the output interface conversion module 803 for conversion and output.

[0164] Through the technical solution provided by the embodiment of the present application, the data valid indication signal, the row start and end indication signal and the frame start and end indication signal are adopted to realize the continuous transmission of large-volume data of the stream processing unit or stream processor, reduce the delay effect of the burst transmission of the stream processing unit or stream processor, and reduce the data delay. By adopting the data type source address and target address setting, the source flow control of the stream data of the stream processing unit or stream processor is increased, and the adaptive transmission of the hardware data signal is realized. By adopting the data type row parity and data type setting, the characteristic transmission of the stream data of the stream processing unit or stream processor is increased, the hardware adaptive processing of the upstream and downstream stream processing units is improved, and the transmission delay is reduced. By adopting the data type check value transmission setting, the functional safety setting of the data transmission of the stream processing unit is increased, and the data transmission reliability is improved. By adopting the bus setting of the start and end valid indication signal of the row and frame, the bus design of the stream processing unit or stream processor is simplified, the transmission bandwidth and efficiency of stream data such as image data are improved, and the system implementation cost is reduced.

[0165] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0166] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for transmitting stream data via a stream processing bus, characterized in that: include: The sender obtains the stream data to be transmitted; The sending end transmits a set of signals in parallel through the stream processing bus, including: receiving a data reception indication signal sent by a receiving end, wherein the data reception indication signal is used to indicate whether the receiving end can receive stream data; sending a stream data signal, wherein, if the received data reception indication signal indicates that the receiving end can receive stream data, the stream data signal transmits the stream data; if the received data reception indication signal indicates that the receiving end cannot receive stream data, the stream data signal transmits padding data; A data valid signal is sent, wherein when the stream data signal transmits the stream data, the data valid signal indicates that the stream data signal is valid; when the stream data signal transmits the filling data, the data valid signal indicates that the stream data signal is invalid.

2. The method according to claim 1, characterized in that The transmitting end transmitting a group of signals in parallel through the stream processing bus further comprises at least one of the following: The transmitting end sends a line end indication signal, wherein the line end indication signal is used to indicate whether a line of data in the stream data has been transmitted; The transmitting end sends a frame end indication signal, wherein the frame end indication signal is used to indicate whether a frame of data in the stream data has been transmitted.

3. The method according to claim 1, characterized in that The transmitting end transmitting a group of signals in parallel through the stream processing bus further comprises at least one of the following: The transmitting end sends a line start indication signal, wherein the line start indication signal is used to indicate whether a line of data in the stream data starts to be transmitted; The transmitting end sends a frame start indication signal, wherein the frame start indication signal is used to indicate whether a frame of data of the stream data starts to be transmitted.

4. The method according to any one of claims 1 to 3, characterized in that The transmitting end transmits a group of signals in parallel through the stream processing bus, further comprising: The transmitting end sends a data type signal, wherein the data type signal is used to indicate type-related information of the stream data signal.

5. The method according to claim 4, characterized in that The data type signal includes at least one of the following: A row parity signal, used to indicate an even or odd row attribute corresponding to the stream data signal; A source address signal, used to indicate a source address corresponding to the stream data signal; A destination address signal, used to indicate a destination address corresponding to the stream data signal; The data format signal is used to indicate the data format corresponding to the stream data signal.

6. A method for transmitting stream data via a stream processing bus, characterized in that: include: The receiving end determines whether it can currently receive the stream data based on the amount of stream data currently to be processed; The receiving end transmits a set of signals in parallel through a stream processing bus, including: Sending a data reception indication signal, wherein the data reception indication signal is used to indicate whether the receiving end can receive stream data; receiving a stream data signal, wherein the stream data signal is used to transmit the stream data or filling data; A data valid signal is received, wherein the data valid signal is used to indicate whether the data transmitted by the stream data signal is valid.

7. The method according to claim 6, characterized in that The receiving end transmits a set of signals in parallel via a stream processing bus, and further includes at least one of the following: The receiving end receives a line end indication signal, and determines a transmission end position of a line of data in the stream data based on the line end indication signal; The receiving end receives a frame end indication signal, and determines a transmission end position of a frame of data in the stream data based on the frame end indication signal.

8. The method according to claim 6, characterized in that The receiving end transmits a set of signals in parallel via a stream processing bus, and further includes at least one of the following: The receiving end receives a line start indication signal, and determines a transmission start position of a line of data in the stream data based on the line start indication signal; The receiving end receives a frame start indication signal, and determines a transmission start position of a frame of data of the stream data based on the frame start indication signal.

9. The method according to any one of claims 6 to 8, characterized in that The receiving end transmits a set of signals in parallel via a stream processing bus, further comprising: The receiving end receives a data type signal, and acquires type-related information of the stream data signal based on the data type signal.

10. The method according to claim 9, characterized in that The data type signal includes at least one of the following: A row parity signal, used to indicate an even or odd row attribute corresponding to the stream data signal; A source address signal, used to indicate a source address corresponding to the stream data signal; A destination address signal, used to indicate a destination address corresponding to the stream data signal; The data format signal is used to indicate the data format corresponding to the stream data signal.

11. A transmission system, characterized in that: include: an input interface conversion module, configured to execute the method for transmitting stream data through a stream processing bus according to any one of claims 1 to 5; A stream processing module, configured to execute the method for transmitting stream data through a stream processing bus according to any one of claims 1 to 5, and the method for transmitting stream data through a stream processing bus according to any one of claims 6 to 10; An output interface conversion module, configured to execute the method for transmitting stream data through a stream processing bus as claimed in any one of claims 6 to 10.

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