Code stream data processing method and device, electronic equipment and storage medium

Abstract

The invention provides a code stream data processing method and device, electronic equipment and a storage medium, and the method comprises the steps: inputting code stream data pre-written into a memory space into at least two cache channels, the code stream data being data contained in a compressed image; and according to the states of at least two decoding units, inputting the code stream data in the cache channel into the at least two decoding units, and decompressing the code stream data in parallel. By determining the state of the decoding unit, inputting the code stream data in the cache channel into the decoding unit and decompressing the code stream data, parallel processing of decompressing is realized, the decoding unit is prevented from being idle, and the decompressing efficiency of the code stream data is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, device, electronic device and storage medium for processing code stream data. Background Art

[0002] With the widespread adoption of explosively traffic-intensive applications such as 5G, large models, ChatGTP, and short video platforms, big data is increasingly challenging computer system performance, power consumption, and bandwidth. The proportion of video and image traffic is increasing year by year, and image compression technology plays a key role in improving system energy efficiency. However, related technologies have low efficiency in the decompression process for compressed images. Summary of the Invention

[0003] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0004] To this end, the present application proposes a method, an apparatus, an electronic device, and a storage medium.

[0005] In one embodiment of the present application, a method for processing code stream data is provided, including:

[0006] Inputting code stream data pre-written into the memory space into at least two cache channels, wherein the code stream data is data contained in the compressed image;

[0007] According to the states of at least two decoding units, the code stream data in the cache channel is input into the at least two decoding units, and the code stream data is decompressed in parallel.

[0008] Optionally, the bitstream data in the cache channel is input into the at least two decoding units to perform decompression processing on the bitstream data in parallel, including:

[0009] The at least two decoding units are scheduled to perform different processing steps in the decompression process in parallel.

[0010] Optionally, the at least two cache channels include a first cache channel and a second cache channel, and inputting the code stream data pre-written in the memory space into the at least two cache channels includes any one of the following:

[0011] In a case where there is no data in the first cache channel, sequentially inputting the code stream data corresponding to the first sub-image block in the compressed image into the first cache channel;

[0012] When there is no data in the second cache channel, the code stream data corresponding to the second sub-image block in the compressed image is sequentially input into the second cache channel.

[0013] Optionally, the at least two decoding units include a first decoding unit and a second decoding unit, the codestream data includes codestream header data and valid codestream data, and inputting the codestream data in the cache channel into the at least two decoding units to perform decompression processing on the codestream data in parallel according to states of the at least two decoding units includes any one of the following:

[0014] When the first decoding unit is in an idle state, inputting the code stream header data in the first cache channel or the second cache channel into the first decoding unit for decoding processing;

[0015] When the first decoding unit has completed processing the code stream header data input by the first cache channel, inputting the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing, and inputting the code stream header data in the second cache channel into the first decoding unit for decoding processing;

[0016] When the first decoding unit has completed processing the code stream header data input by the second cache channel, the valid code stream data corresponding to the code stream header data is input into the second decoding unit for decompression processing, and the code stream header data in the first cache channel is input into the first decoding unit for decoding processing.

[0017] Optionally, when the first decoding unit has completed processing the codestream header data input by the first cache channel, inputting the valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing includes any one of the following:

[0018] When there is no data in the second cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing;

[0019] When there is no data or no valid code stream data in the second cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the first cache channel is input into the second decoding unit for decompression processing.

[0020] Optionally, when the first decoding unit has completed processing the codestream header data input by the second cache channel, inputting the valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing includes any one of the following:

[0021] When there is no data in the first cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing;

[0022] When there is no data or no valid code stream data in the first cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the second cache channel is input into the second decoding unit for decompression processing.

[0023] Optionally, the method further includes any one of the following:

[0024] A first data length corresponding to the processed codestream header data in the first decoding unit is obtained, and codestream data is filled into a cache channel that outputs the processed codestream header data according to the first data length.

[0025] Optionally, filling the first cache channel with code stream data according to the first data length includes any one of the following:

[0026] When the length of the first data is greater than a first length threshold and less than a second length threshold, filling the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold;

[0027] When the first data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

[0028] Optionally, the method further includes:

[0029] A second data length corresponding to the valid code stream data that has been processed in the second decoding unit is obtained, and code stream data is filled into a cache channel that outputs the valid code stream data that has been processed according to the second data length.

[0030] Optionally, the filling of the buffer channel outputting the processed valid stream data with the code stream data according to the second data length includes any one of the following:

[0031] When the second data length is greater than the first length threshold and less than the second length threshold, fill the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold;

[0032] When the second data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

[0033] Optionally, the method further includes:

[0034] determining whether decompression processing of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit;

[0035] For the sub-image block that has completed the decompression process, the data in the cache channel that outputs the sub-image block is cleared.

[0036] Optionally, determining whether decompression of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit includes:

[0037] When the first cache channel receives all the code stream data in the sub-image block, confirming that decompression of the sub-image block is completed;

[0038] In a case where the length of the decoded code stream of the second decoding unit is greater than the length of the valid code stream data in the sub-image block, it is confirmed that the decompression of the sub-image block is completed.

[0039] Another embodiment of the present application provides a device for processing bitstream data, including:

[0040] a cache module, configured to input code stream data pre-written into the memory space into at least two cache channels, wherein the code stream data is data contained in the compressed image;

[0041] The decompression module is configured to input the code stream data in the cache channel into the at least two decoding units according to states of the at least two decoding units and perform decompression processing on the code stream data in parallel.

[0042] Another embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method described in the above aspect is implemented.

[0043] Another aspect of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method described in the aforementioned aspect is implemented.

[0044] Another embodiment of the present application provides a chip, which includes a processing circuit configured to execute the method described in the above aspect.

[0045] Another embodiment of the present application provides a computer program product, which implements the method described in the above aspect when the program is executed by a processor.

[0046] The code stream data processing method, device, electronic device, chip, and storage medium proposed in this application determine the status of a decoding unit, input the code stream data in the cache channel into the decoding unit, and decompress the code stream data in parallel, thereby achieving parallel decompression processing, avoiding idle decoding units, and improving the decompression processing efficiency of the code stream data.

[0047] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0049] Figure 1 A flow chart of a method for processing bitstream data provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of an image compression processing system provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of the structure of a cache channel provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of the structure of a decompression system provided in an embodiment of the present application;

[0053] Figure 5 A schematic structural diagram of a second decoding unit provided in an embodiment of the present application;

[0054] Figure 6 A schematic structural diagram of a bitstream data processing device provided in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0056] Figure 8 This is a schematic diagram of the structure of a chip proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0058] Related technologies propose related image compression and decompression methods. Different technical solutions have different implementation methods. The image compression process and usage scenarios are to divide a frame of image into multiple groups of images, and compress each group of images into N groups of independent code streams. The compression unit sends the compressed code stream to the storage medium. Under certain conditions, the destination device drives the decompression device to initiate a storage medium read request, and restores the compressed code stream to a reconstructed image through decompression.

[0059] The image decompression unit decompresses the code stream in sequence, which has the following disadvantages:

[0060] 1) The next sub-image block code stream cannot be decompressed in advance if the previous sub-image block compression code stream has not been processed yet

[0061] 2) The time for decompressing the code stream header affects the performance of the decompression unit, resulting in a certain delay in the time it takes for the decompression unit to obtain the reconstructed image.

[0062] 3) The decompressed code stream cannot be processed in parallel, and the code stream header information cannot be obtained in advance.

[0063] Figure 1 A schematic diagram of a flow chart of code stream data processing provided in an embodiment of the present application.

[0064] As an implementation manner, the code stream data processing method of the embodiment of the present application can be configured in a code stream data processing device. The code stream data processing device can be applied to any electronic device so that the electronic device can perform the code stream data processing function.

[0065] Among them, the electronic device can be any device with computing capabilities, such as a mobile terminal. The mobile terminal can be, for example, a mobile phone, tablet computer, personal digital assistant, wearable device, or other hardware device with various operating systems, touch screens and / or display screens.

[0066] As another implementation method, the code stream data processing method of the embodiment of the present application can also be executed by a chip with processing capabilities, including an image signal processing chip (Image Signal Processor, ISP), a central processing unit (Central Processing Unit, CPU), an application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC), a microprocessor (Digital Signal Processor, DSP), a field programmable gate array (Field-Programmable Gate Array, FPGA), a system on a chip (System On A Chip, SOC), a reduced instruction set computer RISC (Reduced Instruction Set Computer, reduced instruction set computer), etc., which are not listed one by one this time.

[0067] It should be noted that the collection of user-related data in this application is carried out with the user's authorization and strictly abides by relevant laws and regulations such as privacy and security.

[0068] like Figure 1 As shown, the method may include the following steps:

[0069] Step 101: inputting code stream data pre-written into a memory space into at least two cache channels, wherein the code stream data is data contained in a compressed image;

[0070] Step 102: Input the code stream data in the cache channel into the at least two decoding units according to the states of the at least two decoding units, and decompress the code stream data in parallel.

[0071] Figure 2 This is a structural diagram of an image compression processing system provided by an embodiment of the present application. Figure 2 As shown, the processing flow in the image compression processing system includes:

[0072] The source device initiates a storage request for the image.

[0073] The image compression unit compresses the requested image data, divides the compressed image into N sub-blocks of the same size and compresses them into N code stream data.

[0074] The compressed code stream data is written from the source device to the storage medium through the system routing.

[0075] The destination device initiates a request to read the compressed code stream, and sends the compressed code stream to the image decompression unit in sequence through the system routing.

[0076] The image decompression unit reads each compressed code stream in sequence, decompresses the code stream data, and finally obtains the decompressed image data.

[0077] The following describes the code stream data processing method, device, electronic device, chip and storage medium according to the embodiments of the present application with reference to the accompanying drawings.

[0078] The steps in this embodiment are applied to the above-mentioned image decompression unit. The first step involves the key step of inputting the code stream data pre-written into the memory space into at least two cache channels. The code stream data mentioned here refers to the data contained in the compressed image, that is, this data is the binary data and other information corresponding to the compressed image. By distributing this code stream data to at least two cache channels, it can pave the way for subsequent processing. Next, based on the status of at least two decoding units, the code stream data in the cache channels will be input into these decoding units, allowing the decoding units to decompress the code stream data in parallel, thereby achieving efficient decoding of the compressed image and improving the efficiency and performance of the entire image processing.

[0079] Application scenarios of this embodiment include:

[0080] 1. Ensure that the performance of system-on-chip and other computer devices is not affected under limited bandwidth conditions, such as image processors, video accelerators, etc.

[0081] 2. Image compression technology is used to optimize energy consumption for power-sensitive computer devices, such as AR / VR display devices, camera devices, handheld mobile devices, PC display devices, etc.

[0082] 3. For computer system equipment with limited storage resources and high resolution requirements, image compression technology can be used to reduce storage requirements, such as image and video servers.

[0083] Optionally, the bitstream data in the cache channel is input into the at least two decoding units to perform decompression processing on the bitstream data in parallel, including:

[0084] The at least two decoding units are scheduled to perform different processing steps in the decompression process in parallel.

[0085] In this embodiment, the process of inputting the codestream data in the cache channel into at least two decoding units for parallel decompression processing specifically includes a process of properly scheduling the at least two decoding units. This scheduling operation enables each decoding unit to perform different data processing tasks in the decompression process in parallel. For example, different portions of the codestream data or different types of processing operations can be assigned to different decoding units, allowing them to handle them separately. For example, one decoding unit can process a specific format portion of the codestream data while another decoding unit processes another related portion of data. This fully utilizes the advantages of parallel processing, improves the overall efficiency and speed of the decompression process, and better achieves fast decoding of the codestream data.

[0086] Optionally, the at least two cache channels include a first cache channel and a second cache channel, and inputting the code stream data pre-written in the memory space into the at least two cache channels includes any one of the following:

[0087] In a case where there is no data in the first cache channel, sequentially inputting the code stream data corresponding to the first sub-image block in the compressed image into the first cache channel;

[0088] When there is no data in the second cache channel, the code stream data corresponding to the second sub-image block in the compressed image is sequentially input into the second cache channel.

[0089] In this embodiment, during the decompression process, the compressed image is processed in units of sub-image blocks. The codestream data corresponding to each sub-image block is input into the corresponding cache channel. Simultaneously, the codestream data in the cache channel is input into the decoding unit for decompression processing. Before the codestream data corresponding to a sub-image block is completely processed, the codestream data for other sub-image blocks will not be input into the cache channel. Only after the codestream data corresponding to a sub-image block is processed will the codestream data for the next sub-image block be input into the cache channel.

[0090] A first cache channel and a second cache channel are used to cache the bitstream data of different sub-image blocks. In one possible embodiment, the bitstream data of the 2*i sub-image block is input into the first cache channel, and the bitstream data of the 2*i+1 sub-image block is input into the second cache channel, where (i = [0, 1…(N-1) / 2]) and N is the total number of sub-image blocks. The cache channel can be an integrated circuit memory unit, an FPGA memory unit, or a storage medium allocated in a computer system.

[0091] Figure 3 A schematic diagram of the structure of a cache channel provided in an embodiment of the present application is shown as follows: Figure 3As shown, the cache channel includes an internal cache device and an output cache device. The internal cache device is used to store external input code stream data, and the output cache device is used to store code stream data to be output to the decoding unit, wherein the data in the output cache device comes from the internal cache device.

[0092] Optionally, the at least two decoding units include a first decoding unit and a second decoding unit, the codestream data includes codestream header data and valid codestream data, and inputting the codestream data in the cache channel into the at least two decoding units to perform decompression processing on the codestream data in parallel according to states of the at least two decoding units includes any one of the following:

[0093] When the first decoding unit is in an idle state, inputting the code stream header data in the first cache channel or the second cache channel into the first decoding unit for decoding processing;

[0094] When the first decoding unit has completed processing the code stream header data input by the first cache channel, inputting the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing, and inputting the code stream header data in the second cache channel into the first decoding unit for decoding processing;

[0095] When the first decoding unit has completed processing the code stream header data input by the second cache channel, the valid code stream data corresponding to the code stream header data is input into the second decoding unit for decompression processing, and the code stream header data in the first cache channel is input into the first decoding unit for decoding processing.

[0096] Figure 4 A structural diagram of a decompression system provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the two decoding units include a first decoding unit and a second decoding unit. The first and second cache channels receive bitstream data input from input channel 0. The input channel has a certain cache capacity. The cache device can be an integrated circuit memory unit, an FPGA memory unit, or a storage medium allocated in a computer system. The first decoding unit is used to parse the bitstream header data, and the second decoding unit is a fixed decompression pipeline, which divides the decompression algorithm into several steps, each step is responsible for handling different functions.

[0097] At the beginning, the input channel sends the first code stream of the 2*i-th sub-image block to the first cache channel. The first cache channel caches a certain number of code streams and waits for the output cache device of the first cache channel to be filled with code streams. The length of each code stream can be any length aligned with 8 bits (i = [0, 1...(N-1) / 2]). The cache size of the output cache device is: the number of pixels of the single target decoding * the longest compressed code stream length of a single pixel. The part less than 8 bits is aligned upward by 8 bits.

[0098] At the beginning, the input channel sends the first code stream of the 2*i+1th sub-image block to the first cache channel. The first cache channel caches a certain number of code streams and waits for the output cache device of the first cache channel to be filled with code streams. The length of each code stream can be any length aligned with 8 bits (i = [0, 1...(N-1) / 2]). The cache size of the output cache device is: the number of pixels of the single target decoding * the longest compressed code stream length of a single pixel. The part less than 8 bits is aligned upward by 8 bits.

[0099] The first cache channel sends the codestream header data to the first decoding unit, which parses the codestream header, which includes the codestream length and codestream compression mode information. After parsing the codestream header for the 2*ith sub-image block, the first decoding unit sends the decompressed codestream length information to the first cache channel.

[0100] After the first decoding unit finishes parsing the code stream header data of the first cache channel, the first cache channel switches the output cache device code stream to the second decoding unit. Then the second cache channel inputs the code stream header data into the first decoding unit for parsing.

[0101] Figure 5 A schematic diagram of the structure of a second decoding unit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the second decoding unit includes multiple submodules for processing different steps in decompression.

[0102] Optionally, when the first decoding unit has completed processing the codestream header data input by the first cache channel, inputting the valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing includes any one of the following:

[0103] When there is no data in the second cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing;

[0104] When there is no data or no valid code stream data in the second cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the first cache channel is input into the second decoding unit for decompression processing.

[0105] In this embodiment, decompression processing is performed on a per-block basis within the compressed image. The codestream data corresponding to each sub-block is input into the corresponding cache channel, and the codestream data in the cache channel is simultaneously input into the decoding unit for decompression processing. Until the codestream data corresponding to a sub-block is completely processed, the codestream data for other sub-blocks is not input into the same cache channel. Only after the codestream data corresponding to a sub-block is processed is the data in the cache channel cleared, and the codestream data for the next sub-block is then input into the same cache channel.

[0106] Therefore, if there is no data in the second cache channel, it means that the previous codestream data in the second cache channel has been decompressed and is preparing to input the codestream data of the next sub-image block into the second cache channel. Furthermore, the second decoding unit is in an idle state, indicating that there is no codestream data being processed in the second decoding unit. In this case, the valid codestream data corresponding to the decoded codestream header data in the first cache channel can be input into the second decoding unit for decompression.

[0107] The codestream data contains invalid codestream data that is unrelated to the image. In the codestream data of a sub-image block, the invalid codestream data is located at the end. Therefore, when there is no data or valid codestream data in the second cache channel, it can be determined that all valid codestream data corresponding to the sub-image block has been input into the second decoding unit. Furthermore, the second decoding unit is not in an idle state, indicating that the second decoding unit is processing the last valid codestream data of the sub-image block. After processing the last valid codestream data, the second decoding unit can then process the valid codestream data input from the first cache channel. The second decoding unit contains multiple processing modules, some of which may have already processed the last valid codestream data and are idle, ready to process the valid codestream data input from the first cache channel. In this case, the valid codestream data corresponding to the decoded codestream header data in the first cache channel can be input into the second decoding unit for decompression.

[0108] Optionally, when the first decoding unit has completed processing the codestream header data input by the second cache channel, inputting the valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing includes any one of the following:

[0109] When there is no data in the first cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing;

[0110] When there is no data or no valid code stream data in the first cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the second cache channel is input into the second decoding unit for decompression processing.

[0111] In this embodiment, decompression processing is performed on a per-block basis within the compressed image. The codestream data corresponding to each sub-block is input into the corresponding cache channel, and the codestream data in the cache channel is simultaneously input into the decoding unit for decompression processing. Until the codestream data corresponding to a sub-block is completely processed, the codestream data for other sub-blocks is not input into the same cache channel. Only after the codestream data corresponding to a sub-block is processed is the data in the cache channel cleared, and the codestream data for the next sub-block is then input into the same cache channel.

[0112] Therefore, if there is no data in the first cache channel, it means that the previous codestream data in the first cache channel has been decompressed and is preparing to input the codestream data of the next sub-image block into the second cache channel. Furthermore, the second decoding unit is in an idle state, indicating that the second decoding unit is not processing any codestream data. In this case, the valid codestream data corresponding to the decoded codestream header data in the second cache channel can be input into the second decoding unit for decompression.

[0113] The codestream data contains invalid codestream data that is unrelated to the image. In the codestream data of a sub-image block, the invalid codestream data is located at the end. Therefore, when there is no data or valid codestream data in the first cache channel, it can be determined that all valid codestream data corresponding to the sub-image block has been input into the second decoding unit. Furthermore, the second decoding unit is not in an idle state, indicating that the second decoding unit is processing the last valid codestream data of the sub-image block. After processing the last valid codestream data, the second decoding unit can then process the valid codestream data input from the second cache channel. The second decoding unit contains multiple processing modules, some of which may have already processed the last valid codestream data and are idle, ready to process the valid codestream data input from the second cache channel. In this case, the valid codestream data corresponding to the decoded codestream header data in the second cache channel can be input into the second decoding unit for decompression.

[0114] Optionally, the method further includes any one of the following:

[0115] A first data length corresponding to the processed codestream header data in the first decoding unit is obtained, and codestream data is filled into a cache channel that outputs the processed codestream header data according to the first data length.

[0116] In this embodiment, the second decoding unit sends the single decoding code stream length information to the first cache channel, and the internal cache device of the first cache channel fills the code stream into the output cache device.

[0117] Optionally, filling the first cache channel with code stream data according to the first data length includes any one of the following:

[0118] When the length of the first data is greater than a first length threshold and less than a second length threshold, filling the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold;

[0119] When the first data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

[0120] In this embodiment, after the code stream header data output by the cache channel is processed in the first decoding unit, the cache device inside the cache channel fills the code stream into the output buffer device in an 8-bit aligned manner. The length of the padded code stream is the length of the decoded code stream header. If it is less than 8 bits, it will be rounded down to 8 bits. The padding principle is as follows:

[0121] a) If the single decoding is less than 8 bits, the first buffer channel output buffer device is not filled

[0122] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the first cache channel output buffer device with 8 bits

[0123] c) If a single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the first cache channel output buffer with 8N bits

[0124] Note: The 8(N+1) bit length is less than or equal to the buffer size of the first buffer channel output buffer device

[0125] At the same time, the input channel fills the internal buffer device of the first buffer channel based on the code stream length consumed by the first decoding unit to parse the code stream header information. The buffered code stream length is determined by the output data bit width of the input channel, such as 16, 32, 64, 128, or 256 bits. If the length of a single decoded code stream is less than the input channel output data bit width, the buffering will not be performed until the length of the decoded code stream exceeds the input channel data bit width.

[0126] Optionally, the method further includes:

[0127] A second data length corresponding to the valid code stream data that has been processed in the second decoding unit is obtained, and code stream data is filled into a cache channel that outputs the valid code stream data that has been processed according to the second data length.

[0128] Optionally, the filling of the buffer channel outputting the processed valid stream data with the code stream data according to the second data length includes any one of the following:

[0129] When the second data length is greater than the first length threshold and less than the second length threshold, fill the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold;

[0130] When the second data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

[0131] In this embodiment, after decoding the target number of pixels in a single pass, the first buffer channel output buffer device is padded according to 8-bit alignment. After padded, the length of the bitstream meets the minimum decoding requirement for the next pass. The padded principle is as follows:

[0132] a) If the single decoding is less than 8 bits, the second cache channel output buffer device is not filled

[0133] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the second cache channel output buffer device with 8 bits

[0134] c) If the single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the second cache channel output buffer device with 8N bits

[0135] 8(N+1) bits in length is less than or equal to the cache size of the first cache channel output cache device

[0136] At the same time, the input channel buffers the code stream to the buffer device inside the buffer channel. The length of the buffered code stream is determined according to the output data bit width of the input channel, such as 16, 32, 64, 128, 256 bits, etc.

[0137] Optionally, the method further includes:

[0138] determining whether decompression processing of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit;

[0139] For the sub-image block that has completed the decompression process, the data in the cache channel that outputs the sub-image block is cleared.

[0140] In this embodiment, the completion of decompression processing for a sub-image block is determined based on the status of the code stream data in the cache channel or the second decoding unit. For sub-image blocks that have already been decompressed, the data in the cache channel that outputs the sub-image block must be promptly cleared. This allows for real-time monitoring of the decompression process's progress. Once a sub-image block is processed, the corresponding cache channel data is promptly cleared, freeing up storage space and providing sufficient space resources for subsequent data processing. This ensures that the entire system can continuously and efficiently process and decompress code stream data, avoiding issues such as system performance degradation caused by cache channel data accumulation.

[0141] Optionally, determining whether decompression of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit includes:

[0142] When the first cache channel receives all the code stream data in the sub-image block, confirming that decompression of the sub-image block is completed;

[0143] In a case where the length of the decoded code stream of the second decoding unit is greater than the length of the valid code stream data in the sub-image block, it is confirmed that the decompression of the sub-image block is completed.

[0144] In this embodiment, the cache channel determines whether the current sub-image block code stream of the input channel has been consumed according to one of the following conditions. If it has not been consumed under the following conditions, the unconsumed code stream of the current sub-image block is discarded, the read pointer is updated to the first code stream of the next sub-image block, and the next sub-image block code stream is switched to the second cache channel.

[0145] a) The first cache channel receives the last bitstream of the current sub-image block

[0146] b) The second decoding unit decoding stream length > the sub-image block effective decoding stream length

[0147] In a possible embodiment, the process of image decompression is as follows:

[0148] 1. The source device initiates a request for image storage

[0149] 2. The image compression unit compresses the requested image data.

[0150] 3. The compressed image is divided into N sub-blocks of the same size and compressed into N code stream data

[0151] 4. The compressed stream data is written from the source device to the storage medium

[0152] 5. The target device initiates a request to read the compressed code stream, and sends the compressed code stream to the image decompression unit in sequence through the system routing.

[0153] 6. The image decompression unit starts to read the 0th compressed code stream. Each compressed code stream includes two parts: code stream header and code stream data.

[0154] 7. The decompression unit reads the code stream to the input channel. The input channel has a certain cache capacity. The cache device can be an integrated circuit storage unit, an FPGA storage unit, a storage medium allocated in the computer system, etc.

[0155] 8. The input channel sends the first bitstream of the 2*i-th sub-image block to the first cache channel. The first cache channel caches a certain number of bitstreams and waits for the output cache device of the first cache channel to be filled with bitstreams. The length of each bitstream can be any length aligned with 8 bits (i = [0, 1...(N-1) / 2]). The cache size of the output cache device is: the number of pixels of the single target decoding * the longest compressed bitstream length of a single pixel. The part less than 8 bits is aligned upward by 8 bits. The cache device can be an integrated circuit memory unit, an FPGA memory unit, or a storage medium allocated in a computer system.

[0156] 9. The first cache channel sends the code stream to the first decoding unit, and the first decoding unit parses the code stream header content, which includes the code stream length and code stream compression mode information.

[0157] 10. The first decoding unit completes parsing the 2*i sub-image block stream header and sends the decompressed stream length information to the first cache channel.

[0158] 11. The internal cache device of the first cache channel fills the code stream into the output cache device in an 8-bit aligned manner. The length of the filled code stream is the length of the decoded code stream header. If it is less than 8 bits, it will be rounded down to 8 bits. The filling principle is as follows:

[0159] a) If the single decoding is less than 8 bits, the first buffer channel output buffer device is not filled

[0160] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the first cache channel output buffer device with 8 bits

[0161] c) If a single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the first cache channel output buffer with 8N bits

[0162] Note: The 8(N+1) bit length is less than or equal to the buffer size of the first buffer channel output buffer device

[0163] 12. The input channel fills the cache device inside the first cache channel according to the length of the code stream consumed by the decompression unit 1 decoding the stream header information. The length of the cache code stream is determined by the output data bit width of the input channel, such as 16, 32, 64, 128, 256 bits, etc.

[0164] If the length of a single decoded code stream is less than the input channel output data width, fill it in after the decoded code stream length is greater than the input channel data width.

[0165] 13. The first decoding unit waits to receive the 2*i+1th sub-image block code stream. The first cache channel switches the output cache device code stream to the second decoding unit. The second decoding unit is a fixed decompression pipeline, which divides the decompression algorithm into several steps, each step is responsible for processing different functions.

[0166] 14. If one of the following conditions is met, the second decoding unit starts parsing the code stream payload data.

[0167] a) The second cache channel and the second decoding unit are in idle state

[0168] b) The second cache way is in idle state and the second decoding unit is not in idle state

[0169] c) Neither the second cache channel nor the second decoding unit is in an idle state, and the second cache channel has consumed all valid code streams of the last decompressed sub-image block

[0170] 15. The bitstream payload data is sequentially reconstructed pixel by pixel according to the compressed bitstream sequence within the sub-image block. The reconstruction sequence is based on the order of the bitstream within the sub-image block (which may be raster scan, Z-scan, etc.). The bitstream with the target number of decoded pixels is sent to the second decoding unit through the first cache channel output cache device. The second decoding unit reconstructs the pixels. Each pixel reconstruction consumes a certain number of bits, and the length of the bit consumed by each pixel reconstruction is variable.

[0171] 16. The second decoding unit sends the single decoding code stream length information to the first cache channel, and the internal cache device of the first cache channel fills the code stream into the output cache device

[0172] 17. After decoding the target number of pixels in a single pass, fill the first buffer channel output buffer device according to 8-bit alignment. After filling, the code stream length meets the minimum decoding requirement for the next pass. The filling principle is as follows:

[0173] a) If the single decoding is less than 8 bits, the second cache channel output buffer device is not filled

[0174] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the second cache channel output buffer device with 8 bits

[0175] c) If the single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the second cache channel output buffer device with 8N bits

[0176] 8(N+1) bits in length is less than or equal to the cache size of the first cache channel output cache device

[0177] 18. The input channel buffers the code stream to the internal buffer device of the first buffer channel. The length of the buffered code stream is determined by the output data bit width of the input channel, such as 16, 32, 64, 128, 256 bits, etc.

[0178] 19. Repeat steps 15-18 to continuously parse multiple streams of data and reconstruct the pixels of the sub-image block 2*i according to the compression order of the sub-image block streams.

[0179] 20. The first cache channel determines whether the current sub-image block stream of the input channel has been consumed based on one of the following conditions. If it has not been consumed under the following conditions, the unconsumed stream of the current sub-image block is discarded, the read pointer is updated to the first stream of the next sub-image block, and the stream of the next sub-image block is switched to the second cache channel.

[0180] a) The first cache channel receives the last bitstream of the current sub-image block

[0181] b) The second decoding unit decoding stream length > the sub-image block effective decoding stream length

[0182] 21. The second cache channel receives the first code stream of the 2*i+1th sub-image block, and the internal cache device caches the code stream of the 2*i+1th sub-image block. The internal cache device fills the output cache device. The cache size of the output cache device is: the number of target decoding pixels in a single time * the longest compressed code stream length of a single pixel. Parts less than 8 bits are aligned upward by 8 bits. The cache device can be an integrated circuit memory unit, an FPGA memory unit, or a storage medium allocated in a computer system.

[0183] 22. The second cache channel sends the output cache device data to the first decoding unit, and the first decoding unit parses the stream header content of the 2*i+1th sub-image block. The stream header content includes the stream length and stream compression mode information.

[0184] 23. The first decoding unit completes parsing the 2*i+1th sub-image block code stream header and sends the decompressed code stream length information to the second cache channel.

[0185] 24. The internal buffer device of the second buffer channel fills the output buffer device with a code stream in an 8-bit aligned manner. The length of the padded code stream is the length of the decoded code stream header. If it is less than 8 bits, it is rounded down to 8 bits. The padding principle is as follows:

[0186] a) If the single decoding is less than 8 bits, the second cache channel output buffer device is not filled

[0187] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the second cache channel output buffer device with 8 bits

[0188] c) If the single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the second cache channel output buffer device with 8N bits

[0189] 8(N+1) bits in length is less than or equal to the cache size of the second cache channel output cache device

[0190] 25. The input channel fills the internal cache device of the second cache channel according to the length of the code stream consumed by the decompression unit 1 decoding the stream header information. The length of the cache code stream is determined by the output data bit width of the input channel, such as 16, 32, 64, 128, 256 bits, etc. If the length of the single decoding code stream is less than the output data bit width of the input channel, it will wait until the length of the decoded code stream is greater than the input channel data bit width before filling.

[0191] 26. The first decoding unit waits to receive the 2*i+2th sub-image block code stream, and the second cache channel switches the output cache device code stream to the second decoding unit

[0192] 27. If one of the following conditions is met, the second decoding unit starts parsing the code stream payload data.

[0193] a) The first cache channel and the second decoding unit are in idle state

[0194] b) The first cache channel is in idle state and the second decoding unit is not in idle state

[0195] c) Both the first cache channel and the second decoding unit are not idle, and the first cache channel has consumed all valid code streams of the last decompressed sub-image block

[0196] 28. The bitstream payload data is reconstructed pixel by pixel in the order of the compressed bitstream within the sub-image block. The reconstruction order is based on the order of the bitstream within the sub-image block (which may be raster scan, zigzag scan, etc.). The bitstream with the target number of decoded pixels is sent to the second decoding unit through the second cache channel output cache device. The second decoding unit reconstructs the pixels. Each pixel reconstruction consumes a certain number of bits, and the length of the bit consumption for each pixel reconstruction is variable.

[0197] 29. The second decoding unit sends the single decoding code stream length information to the second cache channel, and the internal cache device of the second cache channel fills the code stream into the output cache device

[0198] 30. After decoding the target number of pixels in a single pass, fill the second buffer channel output buffer device according to 8-bit alignment. After filling, the code stream length meets the minimum decoding requirement for the next pass. The filling principle is as follows:

[0199] a) If the single decoding is less than 8 bits, the second cache channel output buffer device is not filled

[0200] b) If the single decoding is greater than or equal to 8 bits and less than 16, fill the second cache channel output buffer device with 8 bits

[0201] c) If the single decoding is greater than or equal to 8*N bits and less than 8(N+1), fill the second cache channel output buffer device with 8N bits

[0202] 8(N+1) bits in length is less than or equal to the cache size of the first cache channel output cache device

[0203] 31. The input channel buffers the code stream to the internal buffer device of the second buffer channel. The length of the buffered code stream is determined by the output data bit width of the input channel, such as 16, 32, 64, 128, 256 bits, etc.

[0204] 32. Repeat steps 28-31 to continuously parse multiple streams of data and reconstruct the pixels of sub-image block 2*i+1 according to the compression order of the sub-image block streams.

[0205] 33. The second buffer channel determines whether the current sub-image block stream of the input channel has been consumed based on one of the following conditions. If the stream has not been consumed under the following conditions, the unconsumed stream of the current sub-image block is discarded, the read pointer is updated to the first stream of the next sub-image block, and the next sub-image block stream is switched to the first buffer channel.

[0206] a) The second cache channel receives the last bitstream of the current sub-image block

[0207] b) The second decoding unit decoding stream length > the sub-image block effective decoding stream length

[0208] 34. Repeat steps 8-33 until all N sub-image blocks are reconstructed, i.e., one frame of image reconstruction is completed.

[0209] In order to implement the above embodiment, the embodiment of the present application further proposes a code stream data processing device.

[0210] Figure 6 A schematic structural diagram of a bitstream data processing device provided in an embodiment of the present application.

[0211] like Figure 6 As shown, the device may include:

[0212] A cache module 610 is configured to input code stream data pre-written into the memory space into at least two cache channels, wherein the code stream data is data contained in the compressed image;

[0213] The decompression module 620 is configured to input the code stream data in the cache channel into the at least two decoding units according to states of the at least two decoding units, and decompress the code stream data in parallel.

[0214] Optionally, the decompression module includes:

[0215] The scheduling module is used to schedule the at least two decoding units to perform different processing steps in the decompression process in parallel.

[0216] Optionally, the decompression module includes:

[0217] a first input module, configured to input the code stream data corresponding to the first sub-image block in the compressed image into the first cache channel in sequence when there is no data in the first cache channel;

[0218] The second input module is configured to input the code stream data corresponding to the second sub-image block in the compressed image into the second cache channel in sequence when there is no data in the second cache channel.

[0219] Optionally, the at least two decoding units include a first decoding unit and a second decoding unit, the code stream data includes code stream header data and valid code stream data, and the decompression module includes:

[0220] a first decoding module, configured to input the code stream header data in the first cache channel or the second cache channel into the first decoding unit for decoding processing when the first decoding unit is in an idle state;

[0221] a second decoding module configured to, when the first decoding unit has completed processing the codestream header data input by the first cache channel, input valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing, and input the codestream header data in the second cache channel into the first decoding unit for decoding processing;

[0222] The third decoding module is configured to input the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing, and input the code stream header data in the first cache channel into the first decoding unit for decoding processing, when the first decoding unit has completed processing the code stream header data input by the second cache channel.

[0223] Optionally, the second decoding module includes:

[0224] a fourth decoding module, configured to input valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing when there is no data in the second cache channel and the second decoding unit is in an idle state;

[0225] a fifth decoding module, configured to input the valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing, when there is no data or no valid code stream data in the second cache channel and the second decoding unit is not in an idle state.

[0226] Optionally, the third decoding module includes:

[0227] a sixth decoding module, configured to, when there is no data in the first cache channel and the second decoding unit is in an idle state, input valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing;

[0228] a seventh decoding module, configured to input the valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing when there is no data or no valid code stream data in the first cache channel and the second decoding unit is not in an idle state.

[0229] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment and will not be repeated here.

[0230] In order to implement the above embodiments, the present application also proposes a non-transitory computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the method described in the above method embodiments is implemented.

[0231] In order to implement the above embodiments, the present application further proposes a computer program product on which a computer program is stored. When the computer program is executed by a processor, the method described in the above method embodiments is implemented.

[0232] In order to implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the method described in the above method embodiments is implemented.

[0233] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. For example, the electronic device 800 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0234] Reference Figure 7, the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0235] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0236] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0237] The power component 806 provides power to the various components of the electronic device 800. The power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0238] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0239] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0240] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0241] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and temperature changes of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0242] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0243] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0244] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by the processor 820 of the electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0245] In order to implement the above embodiments, the present application further proposes a chip, including: the chip includes a processing circuit, and the processing circuit is configured to execute the method provided in the above embodiments.

[0246] Figure 8 This is a schematic diagram of the structure of a chip proposed in the embodiment of this application. Figure 8 The structure of the chip 1100 is shown, but is not limited thereto.

[0247] The chip 1100 includes a processing circuit 1101 , which is configured to execute any of the above methods.

[0248] In some embodiments, chip 1100 further includes one or more interface circuits 1102. Optionally, interface circuit 1102 is connected to memory 1103. Interface circuit 1102 can be used to receive signals from memory 1103 or other devices, and can be used to send signals to memory 1103 or other devices. For example, interface circuit 1102 can read instructions stored in memory 1103 and send the instructions to processing circuit 1101.

[0249] In some embodiments, the interface circuit 1102 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1101 performs the other steps.

[0250] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0251] In some embodiments, the chip 1100 further includes one or more memories 1103 for storing instructions. Alternatively, all or part of the memories 1103 may be located outside the chip 1100 .

[0252] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0253] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0254] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0255] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0256] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0257] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0258] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0259] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A code stream data processing method, characterized in that: include: Inputting code stream data pre-written into the memory space into at least two cache channels, wherein the code stream data is data contained in the compressed image; According to the states of at least two decoding units, the code stream data in the cache channel is input into the at least two decoding units, and the code stream data is decompressed in parallel.

2. The method according to claim 1, characterized in that The code stream data in the cache channel is input into the at least two decoding units to perform decompression processing on the code stream data in parallel, including: The at least two decoding units are scheduled to perform different processing steps in the decompression process in parallel.

3. The method according to claim 2, characterized in that The at least two cache channels include a first cache channel and a second cache channel, and inputting the code stream data pre-written in the memory space into the at least two cache channels includes any one of the following: In a case where there is no data in the first cache channel, sequentially inputting the code stream data corresponding to the first sub-image block in the compressed image into the first cache channel; When there is no data in the second cache channel, the code stream data corresponding to the second sub-image block in the compressed image is sequentially input into the second cache channel.

4. The method according to claim 3, characterized in that The at least two decoding units include a first decoding unit and a second decoding unit, the code stream data includes code stream header data and valid code stream data, and inputting the code stream data in the cache channel into the at least two decoding units to perform decompression processing on the code stream data in parallel according to states of the at least two decoding units includes any one of the following: When the first decoding unit is in an idle state, inputting the code stream header data in the first cache channel or the second cache channel into the first decoding unit for decoding processing; When the first decoding unit has completed processing the code stream header data input by the first cache channel, inputting the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing, and inputting the code stream header data in the second cache channel into the first decoding unit for decoding processing; When the first decoding unit has completed processing the code stream header data input by the second cache channel, the valid code stream data corresponding to the code stream header data is input into the second decoding unit for decompression processing, and the code stream header data in the first cache channel is input into the first decoding unit for decoding processing.

5. The method according to claim 4, characterized in that The step of inputting the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing after the first decoding unit has processed the code stream header data input by the first cache channel includes any one of the following: When there is no data in the second cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing; When there is no data or no valid code stream data in the second cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the first cache channel is input into the second decoding unit for decompression processing.

6. The method according to claim 4, characterized in that The step of inputting the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing when the first decoding unit has completed processing the code stream header data input by the second cache channel includes any one of the following: When there is no data in the first cache channel and the second decoding unit is in an idle state, inputting the valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing; When there is no data or no valid code stream data in the first cache channel and the second decoding unit is not in an idle state, the valid code stream data corresponding to the decoded code stream header data in the second cache channel is input into the second decoding unit for decompression processing.

7. The method according to claim 4, characterized in that The method further comprises: A first data length corresponding to the processed codestream header data in the first decoding unit is obtained, and codestream data is filled into a cache channel that outputs the processed codestream header data according to the first data length.

8. The method according to claim 7, characterized in that Filling the first cache channel with code stream data according to the first data length includes any one of the following: When the length of the first data is greater than a first length threshold and less than a second length threshold, filling the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold; When the first data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

9. The method according to claim 5 or 6, characterized in that The method further comprises: A second data length corresponding to the valid code stream data that has been processed in the second decoding unit is obtained, and code stream data is filled into a cache channel that outputs the valid code stream data that has been processed according to the second data length.

10. The method according to claim 9, characterized in that Filling the buffer channel outputting the processed valid stream data with the code stream data according to the second data length includes any one of the following: When the second data length is greater than the first length threshold and less than the second length threshold, fill the first cache channel with code stream data, where the length of the filled code stream data is equal to the first length threshold; When the second data length is greater than a second length threshold, the first cache channel is filled with code stream data according to the second length threshold.

11. The method according to claim 5 or 6, characterized in that The method further comprises: determining whether decompression processing of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit; For the sub-image block that has completed the decompression process, the data in the cache channel that outputs the sub-image block is cleared.

12. The method according to claim 11, characterized in that The determining whether the decompression process of the sub-image block is completed according to the code stream data in the cache channel or the second decoding unit includes: When the first cache channel receives all the code stream data in the sub-image block, confirming that decompression of the sub-image block is completed; In a case where the length of the decoded code stream of the second decoding unit is greater than the length of the valid code stream data in the sub-image block, it is confirmed that the decompression of the sub-image block is completed.

13. A code stream data processing device, characterized in that: include: a cache module, configured to input code stream data pre-written into the memory space into at least two cache channels, wherein the code stream data is data contained in the compressed image; The decompression module is configured to input the code stream data in the cache channel into the at least two decoding units according to states of the at least two decoding units and perform decompression processing on the code stream data in parallel.

14. The device according to claim 13, characterized in that The decompression module includes: The scheduling module is used to schedule the at least two decoding units to perform different processing steps in the decompression process in parallel.

15. The device according to claim 14, characterized in that The decompression module includes: a first input module, configured to input the code stream data corresponding to the first sub-image block in the compressed image into the first cache channel in sequence when there is no data in the first cache channel; The second input module is configured to input the code stream data corresponding to the second sub-image block in the compressed image into the second cache channel in sequence when there is no data in the second cache channel.

16. The device according to claim 15, characterized in that The at least two decoding units include a first decoding unit and a second decoding unit, the code stream data includes code stream header data and valid code stream data, and the decompression module includes: a first decoding module, configured to input the code stream header data in the first cache channel or the second cache channel into the first decoding unit for decoding processing when the first decoding unit is in an idle state; a second decoding module configured to, when the first decoding unit has completed processing the codestream header data input by the first cache channel, input valid codestream data corresponding to the codestream header data into the second decoding unit for decompression processing, and input the codestream header data in the second cache channel into the first decoding unit for decoding processing; The third decoding module is configured to input the valid code stream data corresponding to the code stream header data into the second decoding unit for decompression processing, and input the code stream header data in the first cache channel into the first decoding unit for decoding processing, when the first decoding unit has completed processing the code stream header data input by the second cache channel.

17. The device according to claim 16, characterized in that The second decoding module includes: a fourth decoding module, configured to input valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing when there is no data in the second cache channel and the second decoding unit is in an idle state; a fifth decoding module, configured to input the valid code stream data corresponding to the decoded code stream header data in the first cache channel into the second decoding unit for decompression processing, when there is no data or no valid code stream data in the second cache channel and the second decoding unit is not in an idle state.

18. The device according to claim 16, characterized in that The third decoding module includes: a sixth decoding module, configured to, when there is no data in the first cache channel and the second decoding unit is in an idle state, input valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing; a seventh decoding module, configured to input the valid code stream data corresponding to the decoded code stream header data in the second cache channel into the second decoding unit for decompression processing when there is no data or no valid code stream data in the first cache channel and the second decoding unit is not in an idle state.

19. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 12 is implemented.

20. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 12 is implemented.

21. A chip, characterized in that: The chip comprises a processing circuit configured to execute the method according to any one of claims 1 to 12.

22. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 12.

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