A method, apparatus and system for transmitting clock information

Abstract

The application provides a method, device and system for transmitting clock information, which can be applied to an optical transport network. The method comprises: generating first clock information, the first clock information being phase difference information or clock fault information, the first clock information being used for recovering a clock of a first data frame; mapping the first data frame carrying a plurality of first clock information to a second data frame; and transmitting the second data frame. The method for transmitting clock information provided by the application can reduce the bit error rate of the system and improve the transmission quality of the system.

Description

[0001] This application is a divisional application, the original application's application number is 202310273223.4, the original application's original date is 2023-03-13, the original application's entire content is incorporated by reference in this application. TECHNICAL FIELD

[0002] The present application relates to the field of optical transmission technology, more particularly, to a method, device and system for transmitting clock information. BACKGROUND

[0003] Optical transport network (OTN) is based on wavelength division multiplexing technology, which can provide greater transmission rate, higher transmission efficiency and better operations, administration and maintenance (OAM) capability, and has become the mainstream technology of backbone transmission network.

[0004] OTN system transmits clock information corresponding to each service while transmitting various types of service data. However, the clock information may be subject to errors during transmission due to various reasons. Therefore, how to provide accurate clock information transmission and improve the error resistance of the system is a problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a method, device and system for transmitting clock information, which can improve the error resistance of the system, enable the destination device to accurately restore the service layer clock, and thus achieve the purpose of improving user experience.

[0006] In a first aspect, the embodiments of the present application provide a method for transmitting clock information. The method is applied to an optical transmission device and can be executed by an intermediate device or a component (such as a chip or a chip system, etc.) of the intermediate device, which is not limited in the present application. The method comprises: generating first clock information, the first clock information being phase difference information or clock fault information, the first clock information being used for restoring the clock of a first data frame; mapping the first data frame into a second data frame, the first data frame carrying a plurality of first clock information; and transmitting the second data frame.

[0007] In some embodiments, the first data frame is an OSU frame, and the second data frame is an ODU frame.

[0008] The intermediate device carries a plurality of generated first clock information in the first data frame, and transmits the plurality of first clock information in the first data frame to a downstream device through the second data frame. The above scheme increases the accuracy of first clock information transmission, reduces the error rate of the system, improves the transmission quality of the system, and achieves the purpose of improving the reliability of the system.

[0009] With reference to the first aspect, in some implementations of the first aspect, the first data frame is a multi-row and multi-column structure, and the first clock information is carried in a plurality of continuous columns of a same row of the first data frame. By carrying the plurality of clock information in the same row of the data frame, the receiving device can quickly obtain the plurality of clock information, ensuring the reliability and stability of the system without increasing the information processing delay. Meanwhile, since the plurality of same clock information is carried in one row of the data frame, the above scheme can enable a plurality of different clock information to be carried in the plurality of rows of one data frame, i.e., different clock information is carried in each row as a unit, so that the destination device can quickly respond to the clock jitter of the system, thereby improving the response speed of the destination device to the system.

[0010] With reference to the first aspect, in some implementations of the first aspect, the method further includes: receiving a second data frame from an upstream device; demapping the first data frame from the upstream device from the second data frame of the upstream device; obtaining a plurality of clock information in the first data frame of the upstream device, each clock information of the plurality of clock information being phase difference information or clock fault information; determining second clock information generated by the upstream device according to the plurality of clock information; and generating the first clock information according to the second clock information generated by the upstream device. This scheme can improve the reliability of the clock information in the transmission process of the intermediate device, and further improve the error code resistance performance of the system.

[0011] With reference to the first aspect, in some implementations of the first aspect, the first clock information is carried in three adjacent columns of the 1905th column to the 1920th column of any one of the 1st row to the 4th row of the first data frame, or carried in three adjacent columns of the 1st column to the 14th column of any one of the 1st row to the 4th row of the first data frame. When the first data frame is an OSU frame, the overhead area for carrying the first clock information is re-divided in the three adjacent columns of the 1905th column to the 1920th column of the payload area of the data frame, so as to ensure that the original overhead area of the data frame is not affected, thereby ensuring the reliability of the system. Alternatively, the three adjacent columns of the 1st column to the 14th column of the overhead area of the data frame carry the first clock information, so as to save the overhead resources, thereby improving the transmission efficiency of the clock information.

[0012] In some embodiments of the first aspect, the first data frame is a multi-row and multi-column structure, and the plurality of first clock information is carried in a plurality of columns of a plurality of rows of the first data frame.

[0013] In some embodiments of the first aspect, positions of the plurality of columns of the plurality of rows are the same.

[0014] In some embodiments of the first aspect, the plurality of first clock information is carried in three adjacent columns of columns 1905 to 1920 of rows 1 to 4 of the first data frame, or is carried in three adjacent columns of columns 1 to 14 of rows 1 to 4 of the first data frame.

[0015] In some embodiments of the first aspect, positions of the plurality of columns of at least one row of the plurality of rows are different from positions of the plurality of columns of at least one row of the plurality of rows other than the at least one row.

[0016] In some embodiments of the first aspect, the plurality of first clock information is carried in three columns of rows 1 to 4 of the first data frame, the three columns of row 1 of the first data frame are columns 8 to 10 or columns 9 to 11 of the first data frame, and the three columns of rows 2 to 4 of the first data frame are columns 1 to 3 of the first data frame.

[0017] In some embodiments of the first aspect, the first data frame is a multi-row and multi-column structure, and the plurality of first clock information is carried in a same column of a plurality of continuous rows of the first data frame.

[0018] In some embodiments of the first aspect, the plurality of first clock information is carried in any column of columns 1905 to 1920 of rows 1 to 4 of the first data frame, or is carried in any column of columns 1 to 14 of rows 1 to 4 of the first data frame.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the multiple first clock information items carried in the same column of the multiple consecutive rows in the first data frame correspond to the same first data frame. Based on this scheme, by using a single data frame to carry only the same clock information, the destination device can avoid additional positioning of the received clock information and the corresponding data frame, thus simplifying the clock recovery process of the destination device.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the plurality of first clock information is carried in the first column of the second to fourth rows of the first data frame, or carried in the third column of the second to fourth rows of the first data frame.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the first data frame has a row-multiple-column structure, and the plurality of first clock information are carried in the same column of the plurality of first data frames.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the frame structure of the first data frame is 1 row * 960 columns of bytes.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the plurality of first clock information is carried in any one of the first to eighth columns of the three first data frames.

[0024] In conjunction with the first aspect, in some implementations of the first aspect, the number of bytes carrying the first clock information is 1.

[0025] Secondly, embodiments of this application provide a method for transmitting clock information. This method is applied to an optical transmission device and can be executed by a destination device or by a component of the destination device (such as a chip or chip system), and this application does not limit its execution. The method includes: receiving a second data frame from an upstream device; demapping a first data frame from the second data frame from the upstream device; obtaining multiple clock information messages from the first data frame from the upstream device, each of the multiple clock information messages being phase difference information or clock fault information; determining first clock information generated by the upstream device based on the multiple clock information messages; and generating second clock information for the device based on the first clock information generated by the upstream device, the second clock information being used to recover the clock of the first data frame.

[0026] The method of carrying multiple clock information carried in the first data frame of the upstream device can be referred to the relevant description in the first aspect above, and will not be repeated here.

[0027] Based on the above scheme, the target device determines the accurate clock information generated by the upstream device according to the acquired multiple clock information, and uses the accurate clock information to recover the clock of the first data frame. This process can ensure the accuracy of the clock recovery of the target device and achieve the goal of improving system reliability.

[0028] Thirdly, embodiments of this application provide a system for transmitting clock information. The system includes a transmitting device and a destination device. Alternatively, the system includes a transmitting device, a destination device, and at least one first device (also referred to as an intermediate device). The destination device is used to perform the method as described in the second aspect above or any of the possible implementations thereof. The intermediate device is used to perform the method as described in the first aspect above or any of the possible implementations thereof.

[0029] Fourthly, embodiments of this application provide an optical transmission device. This device is used to perform the method provided in either the first or second aspect described above. Specifically, the optical transmission device may include units and / or modules for performing the method provided in either the first aspect or any of the above-described implementations of the first aspect; alternatively, the optical transmission device may include units and / or modules for performing the method provided in either the second aspect or any of the above-described implementations of the second aspect, such as a processing module and a transceiver module.

[0030] In one implementation, the optical transmission device may include units and / or modules for performing the method provided in the first aspect or any of the above implementations of the first aspect, serving as a transmitting end device. The transceiver may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0031] Alternatively, the optical transmission device may be a chip, chip system, or circuit in the transmitting end equipment. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0032] In another implementation, the optical transmission device may include units and / or modules for performing the methods provided in the second aspect or any of the above implementations of the second aspect, serving as a receiving device. The transceiver module may be a transceiver, or an input / output interface. The processing module may be at least one processor. Optionally, the transceiver may be a transceiver circuit. Optionally, the input / output interface may be an input / output circuit.

[0033] Alternatively, the optical transmission device may be a chip, chip system, or circuit in the receiving device. The transceiver module may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit. The processing module may be at least one processor, processing circuit, or logic circuit.

[0034] Fifthly, embodiments of this application provide a processor for executing the methods provided in the above aspects. Unless otherwise specified, or unless contradicted by its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input, etc., or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit these operations.

[0035] Sixthly, embodiments of this application provide a computer-readable storage medium. This computer-readable storage medium stores program code for execution by a device, the program code including methods for performing any implementation of the first or second aspect described above.

[0036] In a seventh aspect, embodiments of this application provide a computer program product containing instructions. When the computer program product is run on a computer, it causes the computer to perform the method provided by any implementation of the first or second aspect described above.

[0037] Eighthly, embodiments of this application provide a chip. The chip includes a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the method provided in any implementation of the first or second aspect described above.

[0038] Optionally, as one implementation, the chip also includes a memory storing computer programs or instructions, and a processor for executing the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the method provided by any of the implementations of the first or second aspect described above.

[0039] The beneficial effects of the third to eighth aspects mentioned above can be specifically referred to in the description of the beneficial effects in the first, second or fifth aspects, and will not be repeated here. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of an OTN optical network system applicable to the embodiments of this application.

[0041] Figure 2 This is a schematic diagram of a possible network device hardware structure.

[0042] Figure 3This is a schematic diagram of a structure that uses one byte to carry clock information, as provided in an embodiment of this application.

[0043] Figure 4 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information in a data frame, as provided in the embodiments of this application.

[0044] Figure 5 The embodiments provided in this application are for Figure 4 A schematic diagram of one possible implementation of carrying clock information.

[0045] Figure 6 As a kind of based Figure 4 The diagram shows the structure of the OSU frame 600 with the shown byte distribution.

[0046] Figure 7 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information in a data frame, as provided in the embodiments of this application.

[0047] Figure 8 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information in a data frame, as provided in the embodiments of this application.

[0048] Figure 9 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information in a data frame, as provided in the embodiments of this application.

[0049] Figure 10 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information in a data frame, as provided in the embodiments of this application.

[0050] Figure 11 As a kind of based Figure 10 The diagram shows the structure of the OSU frame 1100 with the shown byte distribution.

[0051] Figure 12 This is a schematic flowchart of a method 1200 for transmitting clock information provided in an embodiment of this application.

[0052] Figure 13 This is a schematic diagram of the structure of an optical transmission device 1300 provided in an embodiment of this application.

[0053] Figure 14 This is a schematic diagram of another optical transmission device 1400 provided in an embodiment of this application. Detailed Implementation

[0054] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0055] The following description is provided to facilitate understanding of the embodiments of this application.

[0056] First, the terms "first," "second," etc., and various numerical designations in the text descriptions or drawings of the embodiments of this application shown below are merely distinctions for ease of description and are not intended to describe a specific order or sequence, nor are they used to limit the scope of the embodiments of this application. For example, distinguishing different information or different data frames, etc.

[0057] Second, the term "comprising" and any variations thereof in the embodiments of this application shown below are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, products, or devices.

[0058] Third, in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Embodiments or designs described as "exemplary" or "for example" should not be construed as being more preferred or advantageous than other embodiments or designs. The use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner for ease of understanding.

[0059] Fourth, in the embodiments of this application, the mathematical symbol "*" represents the multiplication sign.

[0060] Fifth, in the embodiments of this application shown below, only OTN frames in optical transport network (OTN) are used as examples to illustrate the embodiments. It should be understood that this application also applies to other OTN frames or metro transport network (MTN) frames, or to new types of OTN frames and MTN frames that may be defined as OTN and MTN technologies develop.

[0061] Sixth, in the embodiments of this application, a device can also be called a node or a node device, and a sending device can be called a sending node, a sending end, or a source node. Similarly, a receiving device can be called a receiving end device, a receiving end, a destination device, or a sink node. An intermediate device can be called an intermediate node. It should be understood that an intermediate device can both receive information from an upstream device and send information to a downstream device. Therefore, in the embodiments of this application, whether the sending device is a source node or an intermediate node, and the receiving device is a destination node or an intermediate node, needs to be specifically determined according to the specific embodiment.

[0062] Seventh, in the embodiments of this application, "at least one" means one or more, and "multiple" means two or more. For example, at least one of a, b, and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b, and c, where a, b, and c can be a single or multiple.

[0063] Eighth, in the embodiments of this application, the optical transmission device may also be referred to as an optical transmission equipment, etc.

[0064] Ninth, in this application, "for indicating" includes both direct and indirect indication. When describing information as being used to indicate A, it includes whether the information directly or indirectly indicates A, but does not necessarily mean that the information carries A.

[0065] Tenth, in the embodiments of this application, the preset may include predefined, for example, protocol definition. The "predefined" can be implemented by pre-saving corresponding code, tables, or other means that can be used to indicate relevant information in the device; this application does not limit the specific implementation method.

[0066] Figure 1 This is a schematic diagram of an OTN optical network system applicable to embodiments of this application. Typically, an OTN optical network consists of multiple devices connected by optical fibers, and can be configured into different topologies such as linear, ring, and mesh, depending on specific needs. Figure 1 The OTN 100 shown includes eight OTN devices 101, also known as devices AH. 102 indicates an optical fiber used to connect two devices, and 103 indicates a customer service interface used to receive or send customer service data. Figure 1 As shown, OTN 100 is used to transmit service data for customer equipment 1-3. The customer equipment connects to the OTN equipment through a customer service interface. For example, Figure 1 In the diagram, customer devices 1-3 are connected to OTN devices A, H, and F, respectively. Figure 1 In this example, when client device 1 needs to communicate with client device 3, it can send service data through OTN device AF. For example, OTN device A is the sending device, OTN device BE is the intermediate device, and OTN device F is the receiving device.

[0067] Generally, OTN devices are categorized into optical layer devices, electrical layer devices, and hybrid optoelectronic devices. Optical layer devices refer to those capable of processing optical layer signals, such as optical amplifiers (also known as optical line amplifiers) and optical add-drop multiplexers. Optical amplifiers amplify optical signals to support longer transmission distances while maintaining specific optical signal performance. Optical add-drop multiplexers perform spatial transformations on optical signals, allowing them to be output from different output ports (sometimes referred to as directions). Electrical layer devices refer to those capable of processing electrical layer signals, such as devices capable of processing OTN signals. Hybrid optoelectronic devices refer to devices capable of processing both optical and electrical layer signals. It should be noted that, depending on specific integration needs, an OTN device can integrate multiple different functions. The technical solutions provided in this application are applicable to OTN devices with different forms and integration levels that include electrical layer functions.

[0068] It should be noted that the data frame structure used by the OTN device in this application embodiment is the OTN frame, which is used to carry various service data and provide rich management and monitoring functions. The OTN frame can be an optical data unit frame (ODUk), ODUc n, ODUflex, optical transport unit k (OTUk), OTUc n, or flexible OTN (FlexO) frame, etc. The difference between ODU and OTU frames is that an OTU frame includes both the ODU frame and OTU overhead. k represents different rate levels; for example, k=1 represents 2.5Gbps, k=4 represents 100Gbps; Cn represents a variable rate, specifically a positive integer multiple of 100Gbps. Unless otherwise specified, an ODU frame refers to any one of ODUk, ODUc n, or ODUflex, and an OTU frame refers to any one of OTUk, OTUc n, or FlexO. As OTN technology develops, new types of OTN frames may be defined, which will also apply to this application.

[0069] Figure 2 This is a schematic diagram of a possible network device hardware architecture. For example, Figure 1 Device A in the diagram. Specifically, OTN device 200 includes a tributary board 201, a cross-connect board 202, a circuit board 203, and an optical layer processing board (…). Figure 2 (Not shown) and system control and communication boards 204. The type and number of boards included in a network device may vary depending on the needs. For example, a network device acting as a core node may not have tributary boards 201. Alternatively, a network device acting as an edge node may have multiple tributary boards 201, or no optical cross-connect board 202. Furthermore, a network device that only supports electrical layer functions may not have an optical layer processing board.

[0070] Tributary board 201, cross-connect board 202, and line board 203 are used to process the electrical layer signals of OTN. Tributary board 201 is used to receive and transmit various customer services, such as SDH services, packet services, Ethernet services, and fronthaul services. Further, tributary board 201 can be divided into a customer-side optical transceiver module and a signal processor. The customer-side optical transceiver module, also called an optical transceiver, is used to receive and / or transmit service data. The signal processor is used to perform mapping and demapping processing of service data to data frames. Cross-connect board 202 is used to implement data frame switching, completing the switching of one or more types of data frames. Line board 203 mainly implements the processing of line-side data frames. Specifically, line board 203 can be divided into a line-side optical module and a signal processor. The line-side optical module, also called an optical transceiver, is used to receive and / or transmit data frames. The signal processor is used to perform multiplexing and demultiplexing, or mapping and demapping processing of line-side data frames. System control and communication board 204 is used to implement system control. Specifically, information can be collected from different single boards, or control commands can be sent to the corresponding single boards. It should be noted that, unless otherwise specified, a specific component (e.g., a signal processor) can be one or more, and this application does not impose any limitations. It should also be noted that this application does not impose any limitations on the type of single boards included in the device, or on the functional design and number of the single boards. It should be noted that, in a specific implementation, the two aforementioned single boards may also be designed as a single board. In addition, network devices may also include backup power supplies, fans for heat dissipation, etc.

[0071] With the advent of the fifth-generation fixed network (F5G) era, the demands for leased line services in different scenarios are becoming increasingly refined. For example, industry production networks and high-quality user terminals are experiencing a growing need for high-quality connections. These customer services are characterized by small bandwidth requirements and a large number of connections, necessitating simple and quick bandwidth adjustments. Currently, optical service unit (OSU) frames are used to carry small-granularity services in OTN. This process is based on a flexible tributary unit (TUflex) mapping method, where multiple services are encapsulated into multiple OSUs, with different OSUs corresponding to different TUflexes. These multiple TUflexes are then multiplexed into optical payload unit (OPU) frames.

[0072] To ensure that the destination device in an OTN system can recover the clock of a data frame in a timely and efficient manner, it is necessary to ensure the accuracy of the clock information transmitted by each device in the system. This allows the destination device to receive the correct clock information and restore the clock of the data frame received by the destination device to be consistent with the clock of the data frame sent by the transmitting device, thereby ensuring the reliability of the system. Therefore, how to accurately transmit clock information and reduce the bit error rate in clock information transmission is a technical problem that needs to be solved.

[0073] To address the aforementioned issues, this application proposes a method for transmitting clock information. By repeatedly carrying the same clock information in multiple bytes of a data frame and transmitting it to downstream devices, the receiving device can use multiple clock information to determine the reliable clock information generated by the upstream device, thereby improving the system's error resistance performance and ensuring highly reliable clock recovery.

[0074] It should be noted that, in this embodiment, the clock information is used to recover the clock of the data frame, and is either phase difference information or clock fault information. When the clock information received by the destination device is phase difference information, the destination device adjusts the clock of the received data frame to be consistent with the clock of the data frame sent from the sending end based on the phase difference information. When the clock information received by the destination device is clock fault information, the destination device can determine that the current system has failed or is in an unstable state with abnormal jitter, and waits for the system to stabilize before receiving the phase difference information from the sending end. In this application, the phase difference information is the accumulation of the phase differences generated by each device in the system. For example, for the first device in the system, the phase difference information it receives is the sum of the phase differences of one or more adjacent upstream devices among one or more upstream devices through which the data frame passes, and the phase difference information it sends is the sum of the phase difference generated by the first device and the received phase difference information. For each device in the system, the generated phase difference is an integer multiple of the nominal clock period.

[0075] It should also be noted that, in this application, clock information can be carried by at least one byte of a data frame. For example, Figure 3 This is a schematic diagram illustrating a structure that uses one byte to carry clock information, as provided in an embodiment of this application. Figure 3 In the byte, the highest bit (i.e. Figure 3 The first bit of the byte is used to indicate whether the clock information carried by the byte is phase difference information or clock fault information. Specifically, when the highest bit of the byte is 0, it indicates that the clock information carried by the byte is phase difference information; when the highest bit of the byte is 1, it indicates that the clock information carried by the byte is clock fault information.

[0076] Optionally, when the clock information carried by this byte is clock fault information, the clock information also includes a second, higher bit carrying acknowledgment information. This acknowledgment information is used to instruct downstream devices to confirm that the clock information is clock fault information. For example, when a downstream intermediate device of intermediate device #1, such as intermediate device #2, receives clock information sent by intermediate device #1 that is fault information, intermediate device #2 can reconfirm the current OTN system fault by calculating whether there is a system frequency offset or a sudden frequency offset in the device, and fill the second bit with 1. Through these two acknowledgments, false alarms caused by some recoverable abnormal jitter in the OTN system can be avoided, thereby ensuring the stability of the system performance.

[0077] Optionally, the clock fault information also includes the number of faulty devices, i.e., the number of devices between the faulty device and the destination device. In other words, when the destination device receives this clock fault information, it can determine the location of the faulty device based on the number recorded in the indication field. It should be understood that the number of faulty devices can be indicated by multiple bits from the remaining 7 bits (excluding the most significant bit). Figure 3 In the example structure, it is achieved through the lower 5 bits (such as...) Figure 3 It is indicated by 4-8 bits in the middle.

[0078] For example, when a device (e.g., intermediate device #1) determines that a clock malfunction has occurred, intermediate device #1 generates clock fault information. This clock fault information is generated by setting the highest bit of a byte carrying the clock fault information to 1, and simultaneously recording 1 in the indication fields (bits 4 to 8) that indicate the number of malfunctioning devices, and sending a data frame carrying the clock fault information to downstream devices. When a downstream device receives the data frame and obtains the clock fault information generated by intermediate device #1, if the downstream device also determines that a clock malfunction has occurred, it sets the second bit of the byte carrying the clock information to 1, and modifies the 1s in bits 4 to 8 to 2. Using the same method, downstream devices of intermediate device #1 count sequentially in bits 4 to 8, so that after receiving the clock fault information, the destination device can determine the location of the malfunctioning intermediate device #1 based on the number recorded in the indication field.

[0079] It should be understood that Figure 3 This application only illustrates a possible structure for clock information using a single byte as an example, and is not limited to this. In this application, the number of bytes carrying clock information can also be multiple bytes. When multiple bytes are used to carry clock information, these multiple bytes can also include an indication field indicating that the carried clock information is phase difference information or clock fault information, or include the aforementioned indication field carrying confirmation information and an indication field carrying the number of faulty devices.

[0080] Due to the diversity of OTN frame structures (e.g., multi-row multi-column or single-row multi-column structures), multiple ways of carrying the same clock information may exist within the same OTN frame structure. That is, for the same clock information, the positions of the multiple bytes that can be used within the same data frame can vary. Furthermore, the multiple bytes carrying the same clock information are not necessarily the same for different OTN frame structures. The following detailed illustrations, with reference to the accompanying drawings, illustrate the distribution of several bytes carrying clock information within a data frame, and also list the corresponding possible OTN frame structures.

[0081] It should be noted that the following Figures 4-11 For simplicity, the explanation uses one byte to represent one clock message. Figures 4-11 In the data frame, each column represents one byte.

[0082] Figure 4 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information within a data frame, as provided in the embodiments of this application. (See diagram below.) Figure 4 As shown, multiple bytes carrying multiple clock information are located in the same multiple columns in all rows of the data frame. That is, for a multi-row, multi-column data frame, multiple bytes in the same position in any row of the data frame are used to carry multiple identical clock information.

[0083] In some embodiments, when the system transmits the same clock information three times, Figure 4 This also illustrates a possible implementation for carrying clock information. Figure 4 In the middle, the same three clock messages (i.e. Figure 4 The three 1s, three 2s... three 8s) are carried in three consecutive columns of the same row of the data frame.

[0084] It should be noted that, in Figure 4 In this context, clock information is carried using consecutive columns of all rows in the data frame; that is, for... Figure 4In the 4x4 n-column data frame shown, a single data frame can carry clock information generated by the device at four different times, but this application is not limited to this. For example, at least three columns of one of the four rows can be used to carry the same clock information. Exemplarily, when any one of the four rows is used to carry clock information, this clock information corresponds to a single data frame; that is, the calculation of this clock information is performed on a data frame basis. For example, the device generating the clock information calculates the difference between the nominal clock period corresponding to a data frame of its own device and that of an adjacent upstream device. When four rows are used to carry clock information, this clock information corresponds to one row of a single data frame; that is, the calculation of this clock information is performed on a single row of a data frame. For example, the device generating the clock information calculates the difference between the nominal clock period corresponding to the same row of a data frame of its own device and that of an adjacent upstream device.

[0085] against Figure 4 The diagram showing the distribution of multiple bytes is shown below. Figure 5 This is a schematic diagram illustrating another possible implementation of carrying clock information, provided in an embodiment of this application. Figure 5 In the middle, the same three clock messages (i.e. Figure 5 The three 1s, three 2s, ... three 6s in the text are respectively carried in three different columns of three consecutive rows.

[0086] It should be noted that, in Figure 5 Since the same clock information is repeated 3 times, the number of rows and columns carrying the same clock information is the same as the number of times the clock information is repeated, which is 3.

[0087] Furthermore, for cases where multiple identical clock messages are carried across multiple rows and columns of a data frame, and the number of rows and columns carrying the same clock message is the same as the number of times the clock message is repeated, Figure 5 Only one type of bearing method is shown. For example Figure 5 The three 1s are arranged sequentially from left to right (i.e., from smallest to largest column number) in their respective positions. Alternatively, other methods exist; for example, one could... Figure 5 The three 1s in the middle are arranged in order from right to left (i.e., from largest to smallest column number) and are placed in the first to third rows, etc.

[0088] Figure 6 As a kind of based Figure 4 The diagram shows the structure of an OSU frame 600 with the indicated byte distribution. Figure 6The OSU frame 600 shown is composed of 4*3824 bytes, including a first overhead area, a second overhead area, and a payload area. The first overhead area carries other overheads of the OSU frame 600, including but not limited to: frame alignment signal (FAS), multi-frame alignment signal (MFAS), path monitoring (PM), tandem connection monitoring (TCM) (including TCM1 and TCM2), automatic protection switching, and protection control channel (APS / PCC). The definitions and functions of these overheads can be found in the relevant protocol descriptions and will not be elaborated here. The second overhead area carries multiple clock information. The payload area carries OSU frame service data.

[0089] In some embodiments, such as Figure 6 As shown, the second overhead area is any three adjacent columns from column 1905 to column 1920 of the OSU frame 600. In other embodiments, the second overhead area is any three adjacent columns from column 1 to column 14 of the OSU frame 600.

[0090] It should be understood that, Figure 6 The method of carrying clock information can be referred to above. Figure 4 or Figure 5 This will not be elaborated further here. It should also be noted that clock information is overhead information. When the second overhead area consists of any three adjacent columns from column 1905 to column 1920 of the OSU frame 600, the multiple bytes carrying the clock information constituting the second overhead area of ​​the OSU frame 600 will no longer be contiguous with the first overhead area. Simultaneously, the payload area of ​​the OSU frame 600 will also no longer be contiguous.

[0091] Figure 7 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information within a data frame, as provided in an embodiment of this application. Figure 4 Compared to the diagram showing the distribution of multiple bytes, in Figure 7 In this system, consecutive columns in the first row of each data frame are no longer in the same position as consecutive columns in other rows. That is, the positions of consecutive columns in the first row of each data frame differ from those of columns in the other three rows. When the system uses three repetitions to transmit the same clock information, it can start from the first row of the system's first data frame, grouping the same three clock messages into sets of three (i.e., ...). Figure 7The three 1s, three 2s, ... three 6s in the text should be understood as each of the three identical clock messages being carried in three different consecutive columns of three consecutive rows.

[0092] It should be noted that because the same clock information is repeated three times, therefore, in Figure 7 In this system, the number of rows, columns, and repetitions of the same clock information are all 3. When the system uses a different repetition count, such as 5 times, to transmit the same clock information, the bytes carrying the clock information will come from two adjacent 4-row, n-column data frames, with 5 consecutive columns in each row used to carry the clock information.

[0093] Furthermore, for cases where multiple identical clock messages are carried across multiple rows and columns of a data frame, and the number of rows and columns carrying the same clock message is the same as the number of times the clock message is repeated, Figure 7 Only one carrying method is shown, and it does not limit the scope of protection of this application. For example Figure 7 In this embodiment, only the positions of consecutive columns in the first row differ from those of consecutive columns in other rows. In some embodiments, the positions of consecutive columns in the last row may also differ from those of consecutive columns in other rows; that is, this application is not limited to consecutive columns in the first row having different positions. In other embodiments, there may be two rows where consecutive columns differ from those in other rows, or even more. Furthermore, the data frame used to carry clock information in this application is not limited to... Figure 7 The structure shown is 4 rows and n columns. It should be understood that for a more general multi-row, multi-column data frame structure, the multiple rows include multiple columns of at least one row, which are in different positions than the multiple columns of at least one other row in the multiple rows.

[0094] When based on Figure 7 When the byte distribution method is shown, in Figure 6 In the OSU frame 600 shown, the second overhead is divided into two parts. The first part is columns 8 to 10 of the first row of the OSU frame 600, or columns 9 to 11 of the first row; the second part is columns 1 to 3 of the second to fourth rows of the OSU frame 600.

[0095] It should be understood that, Figure 7 In the middle, is Figure 5 The clock information is shown as an example. Although Figure 7 The position of the bytes used to carry clock information varies in each line of the OSU frame, but for Figure 4 The clock information carrying method shown can still be used Figure 7 The bytes shown are used to carry this information. Figure 7 Each row of the data frame shown is used to carry the same clock information.

[0096] Figure 8 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information within a data frame, as provided in the embodiments of this application. (See diagram below.) Figure 8 As shown, the bytes carrying multiple clock information are located in the same column of all rows of the data frame. That is, for a multi-row, multi-column data frame, the same column in any row of the data frame is used to carry one clock information.

[0097] In some embodiments, when the system transmits the same clock information three times, Figure 8 This also illustrates a possible implementation for carrying clock information. Figure 8 In the middle, the same three clock messages (i.e. Figure 8 The three 1s, three 2s, and two 3s in the data are carried sequentially in eight consecutive rows of the same column in two data frames. It should be understood that the third clock information 3 will be carried in the same column of the first row of the (m+2)th data frame.

[0098] When based on Figure 8 When the clock information is carried out in the way shown, in Figure 6 In the OSU frame 600 shown, the second overhead area is any one of columns 1 to 14. Alternatively, the second overhead area is any one of columns 1905 to 1920.

[0099] Figure 9 This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information within a data frame, as provided in the embodiments of this application. Figure 9 compared to, Figure 9 Each data frame in the data frame carries only three identical clock messages (e.g., ...). Figure 8 Data frame m carries 3 clock information 1; data frame m+1 carries 3 clock information 2).

[0100] It should be noted that, for Figure 9 and Figure 8 Regarding the load-bearing method shown, in Figure 9 In this context, the clock information carried in a single data frame corresponds to different data frames. And... Figure 9 In a data frame, multiple clock messages carried in the same column of consecutive rows correspond to the same data frame.

[0101] When based on Figure 6 When the byte distribution method is shown, in Figure 10 In the OSU frame 600 shown, the second overhead area is the first column of the second to fourth rows, or the second overhead area is the third column of the second to fourth rows.

[0102] Figure 10This is a schematic diagram illustrating the distribution of bytes carrying multiple clock information within a data frame, as provided in the embodiments of this application. (See diagram below.) Figure 11 As shown, the data frame carrying clock information has a 1-row, n-column structure. Therefore, when multiple clock information needs to be transmitted, multiple clock information can be carried in the same column of multiple data frames. That is, for a single-row, multi-column data frame, multiple clock information are carried in the same column of multiple data frames.

[0103] Figure 10 As a kind of based Figure 11 The diagram shows the structure of the OSU frame 1100 with the indicated byte distribution. Figures 4-11 In the OSU frame 1100 shown, the second overhead area is any one of columns 1 to 8.

[0104] It should be noted that the above Figure 4 The examples used here are of the same clock information being transmitted three times, and do not limit the scope of protection of this application. It should be understood that the number of times the same clock information is transmitted repeatedly can be preset by the system. When the number of times the same clock information is transmitted repeatedly increases or decreases, the number of bytes carrying the clock information also increases or decreases accordingly, and the method used to carry the clock information can also be different. Figure 5 , Figures 7-10 and Figure 4 In any of the ways shown, or based on Figure 5 , Figures 7-10 , Figures 4-11 Other load-bearing methods mentioned in any of the methods that can be obtained through simple deformation.

[0105] It should also be noted that the above Figure 11 The distribution of the bytes carrying clock information and the listed OSU frames are merely examples and not limitations. It should be understood that embodiments combining the above embodiments should also be within the scope of protection of this application. For example, the following can be used: Figure 8 The 1*960-byte OSU frame 1100 shown in the figure has any three adjacent columns from column 1 to column 8 carrying the same clock information, etc.

[0106] Furthermore, as explained above, in this embodiment, the clock information transmitted by the data frame is decoupled from the data frame itself. In other words, the clock information transmitted by a data frame is not necessarily only the clock information corresponding to that data frame; specifically, it should be determined by considering the method of carrying the clock information and the structure of the data frame. For example, in Figure 8 In the aforementioned data frame, the clock information carried by data frame m includes two types (such as...). Figure 6The clock information consists of three 1s and one 2, where the second type of clock information is the clock information of data frame m+1 generated by the device. To ensure that all clock information generated by the device can be transmitted, in this embodiment, the period for generating clock information by any device should be greater than the transmission period of the data frame. For example, the period for generating clock information is approximately 4ms, and the transmission period of the data frame is approximately 3ms. In some scenarios, when the device generates clock information, the data frame has not yet been sent. In this case, the device can save the generated clock information and replace the clock information received from the upstream device in the data frame with the newly generated clock information when sending the data frame, and then send the updated clock information to the downstream device through the data frame.

[0107] It should also be noted that the structure of the OSU frames listed in the above embodiments and the position of the bytes carrying clock information within the specific OSU frames (e.g.) Figure 12 The three adjacent columns (columns 1905 to 1920) in OSU frame 600 are for illustrative purposes only and not as a limitation.

[0108] Figure 12 This is a schematic flowchart illustrating a method 1200 for transmitting clock information provided in an embodiment of this application. Figure 12 As shown, method 1200 is a schematic flowchart illustrating the process from the perspective of device interaction. The transmitting device can be an OTN device or a component of an OTN device (such as a chip). The receiving device can be an OTN device or a component of an OTN device (such as a chip or chip system). Specifically, Figure 4 The method 1200 shown includes the following steps.

[0109] S1201, the transmitting device generates first clock information, which is phase difference information or clock fault information, and is used to restore the clock of the first data frame.

[0110] S1202, the transmitting device maps the first data frame into the second data frame, and the first data frame carries multiple first clock signals.

[0111] Specifically, after generating the first clock information, the transmitting device carries multiple pieces of the first clock information in a first data frame and maps the first data frame to a second data frame. The method for carrying multiple pieces of the first clock information can be found in [reference needed]. Figure 5 , Figure 7 , Figure 8 , Figure 9 , Figure 10 or Figure 6In this manner, for example, when the first data frame is an OSU frame, the transmitting device carries multiple first clock information items within the OSU frame and maps the OSU frame carrying the multiple first clock information items to an ODU frame. The OSU frame can be any OSU frame structure corresponding to different distributions of the first clock information, such as those mentioned above, including but not limited to... Figure 11 and Figure 4 Any one of the methods will not be elaborated here. The method for mapping OSU frames to ODU frames can be found in the previous explanations, and will not be repeated here.

[0112] S1203, the transmitting device sends a second data frame to the receiving device.

[0113] Specifically, after the transmitting device maps the first data frame to the second data frame, it sends the second data frame to the receiving device to transmit the first clock information.

[0114] S1204, the receiving device demaps the first data frame from the second data frame.

[0115] S1205, the receiving device acquires multiple clock information from the first data frame.

[0116] Specifically, the receiving device demaps the second data frame sent by the transmitting device to obtain a first data frame carrying multiple clock information, and obtains multiple clock information from the corresponding bytes of the first data frame according to the pre-agreed carrying method.

[0117] S1206, The receiving device determines the first clock information generated by the transmitting device based on multiple clock information.

[0118] Specifically, during the transmission of the second data frame from the sending device to the receiving device, multiple clock information entries in the first data frame may experience bit errors, or bit errors may also occur during the demapping process of the first data frame by the receiving device, resulting in inconsistencies in the multiple clock information entries acquired by the receiving device. Therefore, the receiving device can evaluate the acquired multiple clock information entries. For example, the receiving device can use methods such as the large number decision method to determine the accurate first clock information generated by the sending device from the multiple clock information entries.

[0119] S1207, the receiving device generates third clock information based on the first clock information generated by the transmitting device.

[0120] Specifically, when the receiving device receives the first clock information as phase difference information, it adds the phase difference information to the locally generated phase difference to obtain the updated phase difference information. When the receiving device receives the first clock information as clock fault information, it can determine whether the clock fault information is correct based on the local clock status. For example, the receiving device can wait for a period of time and, based on subsequently received first information, determine whether the upstream transmitting device has indeed experienced a fault or is merely experiencing temporary system jitter, and determine whether to update the fault information or wait for accurate phase difference information based on the judgment result.

[0121] It should be noted that in the above method for transmitting clock information, the sending device can be an intermediate device or a sending end device. The receiving device can be an intermediate device or a destination device. It should be understood that when the receiving device is an intermediate device, the third clock information generated by the intermediate device is phase difference information or fault information. When the receiving device is a destination device, the third clock information generated by the destination device may not include fault information. When the first clock information obtained by the destination device is clock fault information, the destination device can determine that the system is currently in an unstable state based on the clock fault information. If the fault information also includes at least one of the following: acknowledgment information or a number of faulty devices, the destination device will not perform a clock recovery operation.

[0122] It should also be noted that when the sending device is an intermediate device, the method 1200 may also include the following steps.

[0123] S1208, the transmitting device receives the second data frame from the upstream device.

[0124] S1209, the transmitting device demaps the first data frame from the second data frame of the upstream device.

[0125] S1210, the transmitting device acquires multiple clock information from the first data frame, where each clock information is either phase difference information or clock fault information.

[0126] S1211, the transmitting device determines the second clock information generated by the upstream device based on multiple clock information.

[0127] It should be noted that S1208 to S1211 can be applied when bytes carrying multiple clock information are as described above. Figure 13 In the distribution shown, it should be understood that when multiple clock messages are located on the same line of a data frame, the processing delay of the device receiving the multiple clock messages is small, allowing the clock information carried in the first data frame to be corrected at each intermediate device, further improving the system's error tolerance.

[0128] It should be understood that other explanations for S1208 to S1211 can refer to the relevant explanations for the receiving device as an intermediate device in S1204 to S1207 above, and will not be repeated here.

[0129] Figure 14 This is a schematic block diagram of an optical transmission device 1300 provided in an embodiment of this application. The device 1300 includes a receiving module 1301, which can be used to implement corresponding receiving functions. The receiving module 1301 can also be referred to as a receiving unit.

[0130] The device 1300 further includes a processing module 1302, which can be used to implement corresponding processing functions. The device 1300 also includes a sending module 1303, which can be used to implement corresponding sending functions; the sending module 1303 can also be referred to as a sending unit. Optionally, the device 1300 further includes a storage unit, which can be used to store at least one of instructions, data, and other configuration parameters. The processing module 1302 can read the contents stored in the storage unit to enable the device to perform the actions of the relevant devices in the aforementioned method embodiments.

[0131] The device 1300 can be used to perform the actions performed by the target device, transmitting device, or intermediate device in the various method embodiments described above. In this case, the device 1300 can be a component of the target device, transmitting device, or intermediate device. The receiving module 1301 is used to perform receiving-related operations of the target device, transmitting device, or intermediate device in the method embodiments described above; the processing module 1302 is used to perform processing-related operations of the target device, transmitting device, or intermediate device in the method embodiments described above; and the transmitting module 1303 is used to perform transmitting-related operations of the target device, transmitting device, or intermediate device in the method embodiments described above.

[0132] It should be understood that the specific process of each module performing the above-mentioned corresponding steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0133] Figure 14 This is a schematic diagram of a possible optical transmission device 1400, which can be a destination device, a transmitting device, or an intermediate device. Figure 12 As shown, the device 1400 includes a processor 1401, an optical transceiver 1402, and a memory 1403. The memory 1403 is optional. The device 1400 can be applied to both transmitting-side devices (e.g., transmitting equipment) and receiving-side devices (e.g., the aforementioned destination device).

[0134] When applied to the transmitting side device, the processor 1401 and the optical transceiver 1402 are used to implement... Figure 12The method performed by the transmitting device or intermediate device shown is illustrated. In implementation, each step of the processing flow can be accomplished by integrated logic circuitry in the hardware of the processor 1401 or by instructions in software form, fulfilling the method performed by the transmitting device shown in the above figures. The optical transceiver 1402 is used to receive and process transmitted OTN frames for transmission to the peer device (also known as the receiving device).

[0135] When applied to a receiving-side device, the processor 1401 and the optical transceiver 1402 are used to implement... Figure 2 The method is executed by the target device or intermediate device shown. In implementation, each step of the processing flow can be accomplished by integrated logic circuitry in the hardware of the processor 1401 or by instructions in software form, fulfilling the method executed by the receiving device as described in the foregoing figures. The optical transceiver 1402 is used to receive OTN frames sent by the peer device (also known as the transmitting device) and then forward them to the processor 1401 for further processing.

[0136] Memory 1403 is used to store instructions that cause processor 1401 to perform the steps mentioned in the above figure. Alternatively, memory 1403 can also be used to store other instructions to configure parameters of processor 1401 to achieve corresponding functions.

[0137] It should be noted that the processor 1401 and memory 1403 are in Figure 14 In the network device hardware structure diagram, the processor 1401 may be located in a tributary board, or it may be located in a single board that combines tributary and line circuitry. Alternatively, multiple processors 1401 and memory 1403 may be included, located on the tributary board and line circuitry board respectively, with the two boards working together to complete the aforementioned method steps.

[0138] It should be noted that, ​ The device described above can also be used to perform the method steps involved in the variations of the embodiments shown in the foregoing figures, which will not be repeated here.

[0139] Based on the above embodiments, this application also provides a computer-readable storage medium. This storage medium stores a software program, which, when read and executed by one or more processors, can implement the methods provided in any one or more of the above embodiments. The computer-readable storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, magnetic disk, or optical disk.

[0140] Based on the above embodiments, this application also provides a chip. The chip includes a processor for implementing the functions involved in any one or more of the above embodiments, such as acquiring or processing OTN frames involved in the above methods. Optionally, the chip further includes a memory for storing necessary program instructions and data executed by the processor. The chip may be composed of a single chip or may include chips and other discrete devices.

[0141] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0142] It should be understood that the processor mentioned in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0143] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory and / or non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM). For example, RAM can be used as an external cache. By way of example and not limitation, RAM can include various forms such as: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory can be integrated into the processor.

[0144] Those skilled in the art will recognize that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application; such implementations should not be considered beyond the scope of protection of this application.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of apparatus or units may be electrical, mechanical, or other forms.

[0146] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs). For example, the aforementioned available media can include, but are not limited to, various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for transmitting clock information, characterized in that, Applications in optical transmission equipment, including: Generate first clock information, which is phase difference information, and use the first clock information to recover the clock of the first data frame; The first data frame is mapped to the second data frame. The first data frame carries multiple identical first clock information. The first data frame has a multi-row and multi-column structure. The multiple identical first clock information are respectively carried in multiple rows and multiple columns of the first data frame. The multiple rows are consecutive and the multiple columns are consecutive. Send the second data frame.

2. The method according to claim 1, characterized in that, The number of rows and columns of the plurality of rows are the same as the number of identical first clock information items.

3. The method according to claim 1 or 2, characterized in that, The multiple identical first clock information are respectively carried in three consecutive rows and three consecutive columns of the first data frame.

4. The method according to any one of claims 1 to 3, characterized in that, The first clock information is generated based on a line in the first data frame.

5. The method according to any one of claims 1 to 4, characterized in that, The number of bytes carrying each of the first clock information is 1.

6. The method according to any one of claims 1 to 5, characterized in that, The multiple identical first clock information are carried in three adjacent columns from column 1905 to column 1920 of any three rows from row 1 to row 4 of the first data frame.

7. The method according to any one of claims 1 to 6, characterized in that, The first data frame has a frame structure of 4 rows * 3824 columns of bytes.

8. A method for transmitting clock information, characterized in that, Applied to optical transmission equipment, the method includes: Receive the second data frame from the upstream device; Demap the first data frame from the upstream device from the second data frame from the upstream device; Multiple identical clock information is obtained from the first data frame of the upstream device. Each of the multiple identical clock information is phase difference information. The first data frame has a multi-row and multi-column structure. The multiple identical first clock information is respectively carried in multiple rows and multiple columns of the first data frame. The multiple rows are continuous and the multiple columns are continuous. A first phase difference information is determined based on the multiple identical clock information, wherein the first phase difference information is the first clock information generated by the upstream device; Based on the first clock information generated by the upstream device, second clock information is generated.

9. The method according to claim 8, characterized in that, The step of determining the first phase difference information based on the plurality of identical clock information, wherein the first phase difference information is the first clock information generated by the upstream device, includes: The first clock information generated by the upstream device is determined from the multiple identical clock information using a large number decision method.

10. The method according to claim 8 or 9, characterized in that, The step of generating second clock information based on the first clock information generated by the upstream device includes: The first phase difference information is added to the locally generated phase difference to obtain the updated phase difference information, and the second clock information is generated based on the updated phase difference information.

11. The method according to claim 8, characterized in that, The number of rows and columns are the same as the number of identical clock information items.

12. The method according to claim 8 or 11, characterized in that, The multiple identical clock information are respectively carried in three consecutive rows and three consecutive columns of the first data frame.

13. The method according to any one of claims 8 to 12, characterized in that, The first clock information is calculated based on a line in the first data frame.

14. An optical transmission device, characterized in that, The optical transmission device includes an optical transceiver and a processor. The processor is configured to generate first clock information, which is phase difference information, and the first clock information is used to recover the clock of the first data frame; The processor is further configured to map the first data frame into a second data frame, wherein the first data frame carries multiple identical first clock information, the first data frame has a multi-row and multi-column structure, the multiple identical first clock information are respectively carried in multiple rows and multiple columns of the first data frame, the multiple rows are consecutive, and the multiple columns are consecutive; The optical transceiver is used to transmit the second data frame.

15. The apparatus according to claim 14, characterized in that, The number of rows and columns of the plurality of rows are the same as the number of identical first clock information items.

16. The apparatus according to claim 14 or 15, characterized in that, The multiple identical first clock information are respectively carried in three consecutive rows and three consecutive columns of the first data frame.

17. The apparatus according to any one of claims 14 to 16, characterized in that, The first clock information is generated based on a line in the first data frame.

18. The apparatus according to any one of claims 14 to 17, characterized in that, The number of bytes carrying each of the first clock information is 1.

19. The apparatus according to any one of claims 14 to 18, characterized in that, The multiple identical first clock information are carried in three adjacent columns from column 1905 to column 1920 of any three rows from row 1 to row 4 of the first data frame.

20. The apparatus according to any one of claims 14 to 19, characterized in that, The first data frame has a frame structure of 4 rows * 3824 columns of bytes.

21. An optical transmission device, characterized in that, The optical transmission device includes an optical transceiver and a processor. The optical transceiver is used to receive a second data frame from an upstream device; The processor is configured to demap the first data frame from the upstream device from the second data frame of the upstream device; The processor is configured to acquire multiple identical clock information from the first data frame of the upstream device, each of the multiple identical clock information being phase difference information, the first data frame having a multi-row, multi-column structure, the multiple identical first clock information being respectively carried in multiple rows and multiple columns of the first data frame, the multiple rows being consecutive, and the multiple columns being consecutive; The processor is configured to determine a first phase difference information based on the plurality of identical clock information, wherein the first phase difference information is a first clock information generated by the upstream device; The processor is further configured to generate second clock information based on the first clock information generated by the upstream device.

22. The apparatus according to claim 21, characterized in that, The processor is used for: The first clock information generated by the upstream device is determined from the multiple identical clock information using a large number decision method.

23. The apparatus according to claim 21 or 22, characterized in that, The processor is used for: The first phase difference information is added to the locally generated phase difference to obtain the updated phase difference information, and the second clock information is generated based on the updated phase difference information.

24. The apparatus according to claim 21, characterized in that, The number of rows and columns are the same as the number of identical clock information items.

25. The apparatus according to claim 21 or 24, characterized in that, The multiple identical clock information are respectively carried in three consecutive rows and three consecutive columns of the first data frame.

26. The apparatus according to any one of claims 21 to 25, characterized in that, The first clock information is calculated based on a line in the first data frame.

27. A chip, characterized in that, The chip includes a processor. The processor is configured to perform the method as described in any one of claims 1 to 7, or to perform the method as described in any one of claims 8 to 13.

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